Multilayer ceramic electronic components and mounting structures for multilayer ceramic electronic components

Abstract

The present invention provides a multilayer ceramic electronic component that suppresses increases in capacitance and DC resistance, while eliminating the need to design the internal structure for each capacitance level. [Solution] The multilayer ceramic electronic component consists of a multilayer ceramic capacitor 10 and a conductor. The multilayer ceramic capacitor 10 has a laminate 12 including a plurality of stacked dielectric layers 14, a first internal electrode layer 16a exposed on the first end face 12e and the second end face 12f of the laminate 12, a second internal electrode layer 16b exposed on the first side surface 12c and the second side surface 12d, a first external electrode 30a and a second external electrode 30b connected to the first internal electrode layer 16a, and a third external electrode 30c and a fourth external electrode 30d connected to the second internal electrode layer 16b. The conductor is electrically connected to the first external electrode 30a and the second external electrode 30b, and the DC resistance RdcA of the conductor is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component and a mounting structure of the multilayer ceramic electronic component.

Background Art

[0002] For example, a through-hole type three-terminal capacitor is known as a decoupling capacitor used to stabilize the power supply voltage supplied to an integrated circuit component (IC) operating at high speed or as a noise countermeasure component for a power supply line supplied to an integrated circuit component (IC). The through-hole type three-terminal capacitor generally includes a laminate having a first main surface and a second main surface facing each other, a first side surface and a second side surface facing each other, and a first end surface and a second end surface facing each other. Inside the laminate, a plurality of first internal electrode layers and second internal electrode layers are alternately arranged in the stacking direction. Both ends of the first internal electrode layer are led out to the first end surface and the second end surface, and both ends of the second internal electrode layer are led out to the first side surface and the second side surface. The first internal electrode layer is connected to a first external electrode and a second external electrode, and the second internal electrode layer is connected to a third external electrode and a fourth external electrode.

[0003] When a general through-hole type three-terminal capacitor is used as a noise filter, a direct current flows through a signal internal electrode (first internal electrode layer). However, when the capacitance is low, the number of signal internal electrodes (first internal electrode layers) decreases, and the direct current resistance increases, resulting in a problem that the heat generated from the capacitor increases.

[0004] Therefore, as a structure of a low-capacitance through-hole type three-terminal capacitor capable of suppressing an increase in capacitance and suppressing an increase in direct current resistance, a structure such as that of Patent Document 1 is provided. By increasing the number of signal internal electrodes (first internal electrode layers) and opposing the signal internal electrodes (first internal electrode layers) to each other, both the capacitance and the direct current resistance are suppressed.

Prior Art Documents

[0005] [Patent Document 1] Japanese Patent Application Publication No. 9-55335 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, structures like the one described in Patent Document 1 have the following problems. Specifically, there is a limit to how many internal signal electrodes (first internal electrode layers) can be added within the given size constraints, making it difficult to handle even higher currents. Furthermore, the internal structure needs to be designed uniquely for each capacitance, resulting in poor product lineup versatility.

[0007] Therefore, the main objective of the present invention is to provide a multilayer ceramic electronic component that does not require the design of the internal structure for each capacitance value, while suppressing increases in capacitance and DC resistance. [Means for solving the problem]

[0008] The multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of stacked dielectric layers, a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a multilayer ceramic capacitor comprising a first internal electrode layer exposed on the first and second end surfaces, a second internal electrode layer exposed on the first and second side surfaces, a first external electrode and a second external electrode connected to the first internal electrode, and a third external electrode and a fourth external electrode connected to the second internal electrode; and a conductor portion electrically connected to the first and second external electrodes, wherein the DC resistance RdcA of the conductor portion is smaller than the DC resistance RdcB of the multilayer ceramic capacitor. The mounting structure for a multilayer ceramic electronic component according to the present invention comprises a multilayer ceramic electronic component according to the present invention and a mounting substrate on which the multilayer ceramic electronic component is mounted, wherein the multilayer ceramic electronic component is mounted such that the conductive portion does not face the mounting surface.

[0009] In the multilayer ceramic electronic component according to the present invention, the DC resistance RdcA of the conductor connected to the multilayer ceramic capacitor is smaller than the DC resistance RdcB of the multilayer ceramic capacitor. This allows DC current to flow through the conductor and AC current to escape to the multilayer ceramic capacitor. More specifically, DC current tends to flow through the lower DC resistance, so it tends to flow through the conductor, which has a lower DC resistance than the multilayer ceramic capacitor. On the other hand, AC current tends to flow through the lower impedance, so it tends to flow through the multilayer ceramic capacitor, which has a lower impedance. By configuring it in this way, it is possible to suppress an increase in the capacitance and DC resistance of the multilayer ceramic capacitor. Furthermore, it is possible to handle high currents simply by attaching a conductor to an existing multilayer ceramic capacitor, without having to design a new internal structure for each capacitance of the multilayer ceramic capacitor. This also increases the scalability of the product lineup. The mounting structure for multilayer ceramic electronic components according to the present invention mounts the multilayer ceramic electronic components so that the conductive portion does not face the mounting surface. By mounting in this manner, the distance between the multilayer ceramic capacitor and the mounting substrate is not increased, making it easier to achieve a low ESL effect. Furthermore, it is possible to mount the multilayer ceramic electronic component 100 without affecting its mounting on the mounting substrate. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide multilayer ceramic electronic components and mounting structures for multilayer ceramic electronic components that do not require the design of the internal structure for each capacitance, while suppressing an increase in capacitance and DC resistance.

[0011] The above objects, other objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments for carrying out the invention with reference to the drawings.

Brief Description of the Drawings

[0012] [Figure 1] It is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 2] It is a front view of a multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 3] It is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] It is a front view of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 5] It is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 6] It is a cross-sectional view taken along line VI-VI of FIG. 3. [Figure 7] It is a cross-sectional view taken along line VII-VII of FIG. 3. [Figure 8] It is a cross-sectional view taken along line VIII-VIII of FIG. 6. [Figure 9] It is a cross-sectional view taken along line IX-IX of FIG. 6. [Figure 10] It is a cross-sectional view showing an example of a conductor part according to an embodiment of the present invention. [Figure 11a] It is a cross-sectional view showing a first modification example of a conductor part according to an embodiment of the present invention. [Figure 11b] It is a cross-sectional view showing a second modification example of a conductor part according to an embodiment of the present invention. [Figure 11c] It is a cross-sectional view showing a third modification example of a conductor part according to an embodiment of the present invention. [Figure 11d] It is a cross-sectional view showing a fourth modification example of a conductor part according to an embodiment of the present invention. [Figure 12] It is a cross-sectional view in the stacking direction showing the mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 13]It is a cross-sectional view in the width direction showing the mounting structure of the multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 14] It is a cross-sectional view in the stacking direction showing another mounting structure of the multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 15] It is a cross-sectional view in the width direction showing another mounting structure of the multilayer ceramic electronic component according to an embodiment of the present invention. [Figure 16] It is a cross-sectional view showing a first modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 6. [Figure 17] It is a cross-sectional view showing a first modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 7. [Figure 18] It is a cross-sectional view taken along line XVIII-XVIII of FIG. 16. [Figure 19] It is a cross-sectional view taken along line XIX-XIX of FIG. 16. [Figure 20] It is a cross-sectional view showing a second modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 6. [Figure 21] It is a cross-sectional view showing a second modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 7. [Figure 22] It is a cross-sectional view showing a third modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 6. [Figure 23] It is a cross-sectional view showing a third modification example of the multilayer ceramic capacitor according to an embodiment of the present invention, and is a view corresponding to the cross-sectional view of FIG. 7.

Embodiments for Carrying Out the Invention

[0013] 1. Multilayer Ceramic Electronic Component The multilayer ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0014] Figure 1 is an external perspective view showing a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 2 is a front view of a multilayer ceramic electronic component according to an embodiment of the present invention.

[0015] As shown in Figures 1 and 2, the multilayer ceramic electronic component 100 according to an embodiment of the present invention includes a multilayer ceramic capacitor 10 and a conductor portion 40.

[0016] (a) Multilayer ceramic capacitor A multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0017] Figure 3 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 4 is a front view of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 5 is a plan view of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 6 is a cross-sectional view taken along line VI-VI in Figure 3. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 3. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 6. Figure 9 is a cross-sectional view taken along line IX-IX in Figure 6.

[0018] The multilayer ceramic capacitor 10 has a laminated body 12 and external electrodes 30. The following describes the configuration of the laminated body 12 and the external electrodes 30 in that order.

[0019] (Laminated structure) The laminate 12 includes a plurality of stacked dielectric layers 14. Furthermore, the laminate 12 includes a first main surface 12a and a second main surface 12b opposite to the stacking direction x, a first side surface 12c and a second side surface 12d opposite to the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to the length direction z perpendicular to the stacking direction x and the width direction y. The laminate 12 has a rectangular parallelepiped shape. Preferably, the corners and edges of the laminate 12 are rounded. A corner is the part where three adjacent surfaces of the laminate 12 intersect, and an edge is the part where two adjacent surfaces of the laminate 12 intersect. Also, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them.

[0020] As shown in Figures 3 to 9, the laminate 12 has an inner layer portion 15a in which a plurality of internal electrode layers 16 are alternately arranged via dielectric layers 14; a first outer layer portion 15b1 located on the side of the first main surface 12a and formed from a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 15a on the side of the first main surface 12a; and a second outer layer portion 15b2 located on the side of the second main surface 12b and formed from a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 15a on the side of the second main surface 12b.

[0021] Here, the multiple dielectric layers 14 for the inner layer that constitute the inner layer portion 15a are formed so as to be sandwiched between the first inner electrode layer 16a and the second inner electrode layer 16b, which will be described later.

[0022] The number of dielectric layers 14 to be stacked is not particularly limited, but it is preferably 10 to 1000 layers, including the first outer layer 15b1 and the second outer layer 15b2. Furthermore, the thickness of the dielectric layer 14 is preferably 0.5 μm to 15 μm.

[0023] The dielectric layer 14 can be formed from a dielectric material, such as a ceramic material. Such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, and CaZnO3. Furthermore, when the above dielectric material is the main component, depending on the desired properties of the laminate 12, a material with a lower content of minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may be used.

[0024] Furthermore, the dielectric layer 14 may have multiple crystal grains containing a perovskite-type compound with BaTiO3 as its basic structure. The size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer 14. In this embodiment, since a thinner dielectric layer 14 results in a larger capacitance as a capacitor, it is preferable to have a crystal grain size of 1 μm or less.

[0025] Furthermore, the dielectric layers 14 for the outer layers constituting the first outer layer 15b1 and the second outer layer 15b2 are formed from the same dielectric ceramic material as the dielectric layer 14 of the inner layer 15a. Note that the dielectric layers 14 of the first outer layer 15b1 and the second outer layer 15b2 may be formed from different materials than the dielectric layer 14 of the inner layer 15a. Note that each of the dielectric layers 14 of the first outer layer 15b1 and the second outer layer 15b2 may be a single layer or multiple layers. Also, if the dielectric layers 14 of the first outer layer 15b1 and the second outer layer 15b2 each have a multilayer structure, it is preferable that the segregation portions of the dielectric layers of the other outer layers 15b1 and the second outer layer 15b2 are greater than the segregation portions of Si in the dielectric layers 14 of the first outer layer 15b1 and the second outer layer 15b2 that are located closest to the first internal electrode layer 16a and the second internal electrode layer 16b. This makes it possible to improve the flexural strength of the multilayer ceramic capacitor 10 from the stacking direction x side.

[0026] The laminate 12 includes the sides of the laminate 12 (hereinafter referred to as "W gap") 22a and 22b, which are located between the first internal electrode layer 16a and the first side surface 12c, and between the first internal electrode layer 16a and the second side surface 12d.

[0027] Furthermore, the laminate 12 includes ends of the laminate 12 (hereinafter referred to as "L gaps") 24a and 24b located between the second internal electrode layer 16b and the first end face 12e, and between the second internal electrode layer 16b and the second end face 12f.

[0028] (Internal electrode layer) As shown in Figure 9 (not shown in Figure 3), the internal electrode layer 16 has a first internal electrode layer 16a exposed on the first end face 12e and the second end face 12f, and a second internal electrode layer 16b exposed on the first side surface 12c and the second side surface 12d.

[0029] The first internal electrode layer 16a includes a first opposing electrode portion 18a facing the second internal electrode layer 16b, a first leading electrode portion 20a located on one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the first end face 12e of the laminate 12, and a second leading electrode portion 20b located on one end of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the second end face 12f of the laminate 12.

[0030] The second internal electrode layer 16b includes a second opposing electrode portion 18b facing the first internal electrode layer 16a, a third leading electrode portion 20c located on one end of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the first side surface 12c of the laminate 12, and a fourth leading electrode portion 20d located on one end of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the second side surface 12d of the laminate 12.

[0031] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0032] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0033] The shapes of the first and second lead-out electrode portions 20a and 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded or formed at an angle in plan view (tapered). Alternatively, the shape may be tapered in plan view with a slope towards one side.

[0034] The shape of the third and fourth lead-out electrode portions 20c and 20d of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded or formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0035] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the widths of the first extraction electrode portion 20a and the second extraction electrode portion 20b of the first internal electrode layer 16a may be the same width, or one of them may be formed to be narrower.

[0036] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the widths of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b may be the same width, or one of them may be formed to be narrower.

[0037] In this embodiment, the width in the longitudinal direction z of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b is formed to be narrower than the width in the longitudinal direction z of the second opposing electrode portion 18b of the second internal electrode layer 16b.

[0038] Furthermore, while it is preferable that the first internal electrode layer 16a has a uniform thickness, the thickness of the edges of the first internal electrode layer 16a may be thicker than the thickness of the central part. Increasing the thickness of the first internal electrode layer 16a improves coverage. As a result, the current path becomes shorter and the ESL characteristics improve. Alternatively, the thickness of the edges of the first internal electrode layer 16a may be thinner than the thickness of the central part. By making it thinner, the step difference equivalent to the thickness of the first internal electrode layer 16a is mitigated, which helps suppress structural defects.

[0039] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, but are not limited thereto.

[0040] In this embodiment, capacitance is formed when the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, and the characteristics of a capacitor are exhibited.

[0041] The thickness of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably 0.5 μm or more and 1.5 μm or less. The number of layers of the first internal electrode layer 16a and the second internal electrode layer 16b stacked together can be appropriately changed depending on the size and other factors. Increasing the number of layers of the first internal electrode layer 16a can suppress an increase in DC resistance. The total number of layers of the first internal electrode layer 16a and the second internal electrode layer 16b is preferably 10 to 1000.

[0042] The first lead electrode portion 20a and the second lead electrode portion 20b of the first internal electrode layer 16a may be curved. Similarly, the third lead electrode portion 20c and the fourth lead electrode portion 20d of the second internal electrode layer 16b may also be curved. In this case, they may be arranged to curve on either the first main surface 12a or the second main surface 12b. By making the mounting surface a curved surface, the current path can be shortened.

[0043] The distance between the first internal electrode layer 16a on the side closest to the first main surface 12a and the first internal electrode layer 16a on the side closest to the second main surface 12b of the first internal electrode layer 16a drawn out from the first end surface 12e and the second end surface 12f may be shorter than the distance between the first opposing electrode portion 18a of the first internal electrode layer 16a on the side closest to the first main surface 12a and the first opposing electrode portion 18a of the first internal electrode layer 16a on the side closest to the second main surface 12b.

[0044] Furthermore, the distance between the second internal electrode layer 16b on the first main surface 12a side and the second internal electrode layer 16b on the second main surface 12b side of the second internal electrode layer 16b extended from the first side surface 12c and the second side surface 12d may be shorter than the distance between the second opposing electrode portion 18b of the second internal electrode layer 16b on the first main surface 12a side and the second opposing electrode portion 18b of the second internal electrode layer 16b on the second main surface 12b side.

[0045] Furthermore, when increasing the capacitance of the capacitor, it is necessary to increase the area of ​​the internal electrode layer 16, so it is preferable that the LW surface coverage of the internal electrode layer 16 be 90% or more. Here, the LW surface coverage of the internal electrode layer 16 is defined as the ratio obtained by subtracting the area of ​​the void from the area of ​​the inner edge of the internal electrode layer 16 when viewed from the LW surface of the laminate 12. A higher LW surface coverage of the internal electrode layer 16 results in a higher capacitance of the capacitor, but even with a lower LW surface coverage, the dielectric layers 14 are joined to each other via voids, resulting in higher interlayer bonding strength and making delamination less likely.

[0046] (external electrode) The external electrode 30 includes a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0047] The first external electrode 30a is connected to the first internal electrode layer 16a and is formed on the first end face 12e. Preferably, it is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. It may also slightly wrap around to a portion of the first side surface 12c and a portion of the second side surface 12d.

[0048] The second external electrode 30b is connected to the first internal electrode layer 16a and is formed on the second end face 12f. It is also preferable that it is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. It may also slightly wrap around to a portion of the first side surface 12c and a portion of the second side surface 12d.

[0049] The third external electrode 30c is connected to the second internal electrode layer 16b and is formed on the first side surface 12c. It is also preferable that it is located on a portion of the first main surface 12a and a portion of the second main surface 12b. Alternatively, it may be located continuously from the first side surface 12c on either a portion of the first main surface 12a or a portion of the second main surface 12b.

[0050] The fourth external electrode 30d is connected to the second internal electrode layer 16b and is formed on the second side surface 12d. It is also preferable that it is located on a portion of the first main surface 12a and a portion of the second main surface 12b. Alternatively, it may be located continuously from the second side surface 12d on either a portion of the first main surface 12a or a portion of the second main surface 12b.

[0051] The third external electrode 30c and the fourth external electrode 30d may be directly joined together.

[0052] The first external electrode 30a has a first underlay electrode layer 32a containing a conductive metal that is placed on the laminate 12, and a first plating layer 34a that is placed over the first underlay electrode layer 32a. The second external electrode 30b has a second underlay electrode layer 32b containing a conductive metal that is placed on the laminate 12, and a second plating layer 34b that is placed over the second underlay electrode layer 32b. The third external electrode 30c has a third underlay electrode layer 32c containing a conductive metal that is placed on the laminate 12, and a third plating layer 34c that is placed over the third underlay electrode layer 32c. The fourth external electrode 30d has a fourth underlay electrode layer 32d containing a conductive metal, which is placed on the laminate 12, and a fourth plating layer 34d which is placed over the fourth underlay electrode layer 32d.

[0053] The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d. The first base electrode layer 32a, the second base electrode layer 32b, the third base electrode layer 32c, and the fourth base electrode layer 32d each include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0054] The baked layer contains glass components and metal. The baked layer may consist of multiple layers.

[0055] The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc.

[0056] The metal used for the baked layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.

[0057] The baked layer is formed by applying a conductive paste containing glass and metal to the laminate 12 and baking it. It may be baked simultaneously with the internal electrode layer 16, or it may be baked after the internal electrode layer 16 has been baked.

[0058] When baking layers are provided as the first base electrode layer 32a and the second base electrode layer 32b, the thickness of the baking layer in the central part of the stacking direction x of the first base electrode layer 32a and the second base electrode layer 32b located at the first end face 12e and the second end face 12f is preferably, for example, 20 μm or more and 50 μm or less.

[0059] Furthermore, when baking layers are provided as the first base electrode layer 32a and the second base electrode layer 32b on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, it is preferable that the thickness of the baking layer in the central part of the length direction z of the first base electrode layer 32a and the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is, for example, 5 μm or more and 20 μm or less.

[0060] When baking layers are provided as the third base electrode layer 32c and the fourth base electrode layer 32d, the thickness of the baking layer in the central part of the stacking direction x of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first side surface 12c and the second side surface 12d is preferably, for example, 20 μm or more and 50 μm or less.

[0061] Furthermore, when baking layers are provided on the first main surface 12a and the second main surface 12b as a third base electrode layer 32c and a fourth base electrode layer 32d, the thickness of the baking layer in the central part of the length direction z of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first main surface 12a and the second main surface 12b is preferably, for example, 5 μm or more and 20 μm or less.

[0062] Next, we will describe the case where the base electrode layer 32 is formed by a conductive resin layer. The conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a part of the baking layer. In addition, there may be multiple conductive resin layers.

[0063] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0064] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high weather resistance. The reason for using Ag-coated metal is that it allows for the use of a less expensive base metal while maintaining the above-mentioned properties of Ag.

[0065] The metals contained in the conductive resin layer are primarily responsible for the conductive properties of the layer. Specifically, the contact between the metals (conductive fillers) contained in the conductive resin layer forms an electrical pathway within the conductive resin layer.

[0066] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal (conductive filler) contained in the conductive resin layer may be, for example, 0.3 μm to 10 μm.

[0067] Preferably, the metal contained in the conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin.

[0068] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0069] Preferably, the resin contained in the conductive resin layer is present in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0070] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0071] When conductive resin electrode layers are provided as the first base electrode layer 32a and the second base electrode layer 32b, the thickness of the conductive resin electrode layer in the central part of the lamination direction x of the first base electrode layer 32a and the second base electrode layer 32b located at the first end face 12e and the second end face 12f is preferably, for example, 20 μm or more and 70 μm or less.

[0072] Furthermore, when conductive resin electrode layers are provided as the first base electrode layer 32a and the second base electrode layer 32b on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the conductive resin electrode layer at the center of the length direction z of the first base electrode layer 32a and the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is preferably, for example, 5 μm or more and 20 μm or less.

[0073] When conductive resin electrode layers are provided as the third and fourth base electrode layers 32c and 32d respectively, the thickness of the conductive resin electrode layer in the central part of the lamination direction x of the third and fourth base electrode layers 32c and 32d located on the first and second side surfaces 12c and 12d is preferably, for example, 20 μm or more and 70 μm or less.

[0074] Furthermore, when conductive resin electrode layers are provided as a third base electrode layer 32c and a fourth base electrode layer 32d on the first main surface 12a and the second main surface 12b, the thickness of the conductive resin electrode layer at the center of the length direction z of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first main surface 12a and the second main surface 12b is preferably, for example, 5 μm or more and 20 μm or less.

[0075] Furthermore, the first and second base electrode layers 32a and 32b may consist only of conductive resin electrode layers, and the third and fourth base electrode layers 32c and 32d may consist only of conductive resin electrode layers.

[0076] (Plating layer) The plating layer 34 comprises a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0077] The first plating layer 34a is arranged to cover the first base electrode layer 32a. The second plating layer 34b is arranged to cover the second base electrode layer 32b. The third plating layer 34c is arranged to cover the third base electrode layer 32c. The fourth plating layer 34d is arranged to cover the fourth base electrode layer 32d.

[0078] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0079] Furthermore, the plating layer 34 may be formed by multiple layers. Preferably, the plating layer 34 has a two-layer structure consisting of Ni plating followed by Sn plating. The Ni plating layer can prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 10, making mounting easier. If the plating layer 34 has a three-layer structure, it is preferable that the layers be Sn plating, Ni plating, and Sn plating from the laminate 12 side.

[0080] Furthermore, the thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0081] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, or each of them, may have a plating layer directly formed on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure that includes a first internal electrode layer 16a and a plating layer directly electrically connected to the second internal electrode layer 16b. In such a case, a catalyst may be placed on the surface of the laminate 12 as a pretreatment before the plating layer is directly formed.

[0082] The first direct plating layer is positioned on the first end face 12e and formed to be joined to the first internal electrode layer 16a. The second direct plating layer is positioned on the second end face 12f and formed to be joined to the first internal electrode layer 16a. The third direct plating layer is positioned on the first side surface 12c and formed to be joined to the second internal electrode layer 16b. The fourth direct plating layer is positioned on the second side surface 12d and formed to be joined to the second internal electrode layer 16b.

[0083] Each direct plating layer preferably contains at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal.

[0084] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the direct plating layer be formed using Cu, which has good bonding properties with Ni.

[0085] When a plating layer 34 is directly formed on the laminate 12, the thickness of each layer of the plating layer 34 is preferably 1 μm or more and 15 μm or less.

[0086] When a plating layer 34 is directly formed on the laminate 12, it is preferable that the plating layer 34 does not contain glass. Furthermore, it is preferable that the metal content per unit volume of the plating layer 34 is 99% by volume or more.

[0087] The following describes a case where the underlying electrode layer 32 is formed as a thin film layer, and the plating layer 34 is directly formed on the thin film layer.

[0088] A first thin film layer positioned on the first main surface 12a is connected to a first direct plating layer positioned around the first end surface 12e. A second thin film layer positioned on the first main surface 12a is connected to a second direct plating layer positioned around the second end surface 12f. A third thin film layer positioned on the first main surface 12a is connected to a third direct plating layer positioned around the first side surface 12c. A fourth thin film layer positioned on the first main surface 12a is connected to a fourth direct plating layer positioned around the second side surface 12d.

[0089] Similarly, a first thin film layer located on the second main surface 12b is connected to a first direct plating layer located around the first end face 12e. A second thin film layer located on the second main surface 12b is connected to a second direct plating layer located around the second end face 12f. A third thin film layer located on the second main surface 12b is connected to a third direct plating layer located around the first side surface 12c. A fourth thin film layer located on the second main surface 12b is connected to a fourth direct plating layer located around the second side surface 12d.

[0090] The length z dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is defined as dimension L. Dimension L is preferably between 1.0 mm and 3.2 mm. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, which includes the laminated body 12 and the external electrode 30, is defined as dimension T. Dimension T is preferably 0.3 mm or more and 2.5 mm or less. The dimension in the width direction y of the multilayer ceramic capacitor 10, including the laminated body 12 and the external electrodes 30, is defined as the W dimension. The W dimension is preferably 0.5 mm or more and 2.5 mm or less.

[0091] (b) Conductor part Next, the conductor section 40 will be explained. The conductor portion 40 is electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 via the conductive adhesive conductor portion 42.

[0092] The conductive portion 40 is configured, for example, as an interposer substrate.

[0093] Figure 10 is a cross-sectional view showing an example of a conductor portion. The conductor portion 40 is composed of a single-sided substrate. Specifically, the conductor portion 40 includes an insulating substrate 50 and a conductive pattern 52 arranged on one main surface of the insulating substrate 50. A protective layer 54 is placed on the surface of the conductive pattern 52 so as to expose a portion of the conductive pattern 52. The exposed portion of the conductive pattern 52 is a pair of exposed electrode portions 53a and 53b. In addition, the protective layer 54 is placed over the entire surface of the other main surface of the insulating substrate 50. Note that the protective layer 54 does not necessarily have to be formed on the other main surface of the insulating substrate 50. One exposed electrode portion 53a is electrically connected to the first external electrode 30a via the conductive adhesive conductor portion 42. The other exposed electrode portion 53b is electrically connected to the second external electrode 30b via the conductive adhesive conductor portion 42.

[0094] The conductor portion 40 may be rectangular or disc-shaped, and its shape is not limited. However, if the conductor portion 40 is placed on the first main surface 12a or the second main surface 12b, increasing the thickness of the conductor portion 40 in the stacking direction x will increase the dimensions of the multilayer ceramic electronic component 100 in the stacking direction x. Therefore, when the conductor portion 40 is placed on the first main surface 12a or the second main surface 12b of the multilayer ceramic electronic component 100, it is preferable to make the thickness of the conductor portion 40 thinner.

[0095] (c) Modified conductor section As described above, the conductor portion 40 is composed of a single-sided substrate as an interposer substrate, but it may also be composed of a double-sided substrate or a multilayer substrate. The following describes some variations of the conductor portion 40.

[0096] A first modified example of the conductor part 40, conductor part 40A, will now be described. Figure 11a is a cross-sectional view showing a first modified example of the conductor portion. The conductor portion 40A is composed of a double-sided substrate. Specifically, the conductor portion 40A includes an insulating substrate 50, a conductive pattern 52a disposed on one main surface of the insulating substrate 50, and a conductive pattern 52b disposed on the other main surface of the insulating substrate 50. A land electrode portion 56a is placed on the surface of the conductive pattern 52a at one end of the insulating substrate 50, and a land electrode portion 56b is placed on the surface of the conductive pattern 52a at the other end of the insulating substrate 50. On one main surface of the insulating substrate 50, a protective layer 54 is placed in the portion of the conductive pattern 52a where the land electrode portions 56a and 56b are not placed. A land electrode portion 56c is placed on the surface of the conductive pattern 52b at one end of the insulating substrate 50, and a land electrode portion 56d is placed on the surface of the conductive pattern 52b at the other end of the insulating substrate 50. On the other main surface of the insulating substrate 50, a protective layer 54 is placed in the portion of the conductive pattern 52b where land electrode portions 56c and 56d are not arranged. An interlayer connecting conductor (end face through hole) 58a for electrically connecting the land electrode portion 56a and the land electrode portion 56c is provided on one end of the insulating substrate 50. An interlayer connecting conductor (end face through hole) 58b for electrically connecting the land electrode portion 56b and the land electrode portion 56d is provided on the other end of the insulating substrate 50. The land electrode portion 56a is electrically connected to the first external electrode 30a via the conductive adhesive conductor portion 42. The land electrode portion 56b is electrically connected to the second external electrode 30b via the conductive adhesive conductor portion 42.

[0097] Next, we will describe the conductor part 40B, which is a second modified example of the conductor part 40. Figure 11b is a cross-sectional view showing a second modified example of the conductor portion. The conductor portion 40B is composed of a double-sided substrate. Specifically, the conductor portion 40B includes an insulating substrate 50, a conductive pattern 52a disposed on one main surface of the insulating substrate 50, and a conductive pattern 52b disposed on the other main surface of the insulating substrate 50. A protective layer 54 is placed on the surface of the conductive pattern 52a so as to expose a portion of the conductive pattern 52a. The exposed portion of the conductive pattern 52a is a pair of exposed electrode portions 53a and 53b. A protective layer 54 is placed on the surface of the conductive pattern 52b so as to expose a portion of the conductive pattern 52b. The exposed portion of the conductive pattern 52b is a pair of exposed electrode portions 53c and 53d. To provide electrical conductivity between the exposed electrode portion 53a and the exposed electrode portion 53c, an interlayer connecting conductor (through-hole) 60a is placed so as to penetrate the insulating substrate 50 from one main surface to the other main surface. To provide electrical conductivity between the exposed electrode portion 53b and the exposed electrode portion 53d, an interlayer connecting conductor (through-hole) 60b is placed so as to penetrate the insulating substrate 50 from one main surface to the other main surface. The exposed electrode portion 53a is electrically connected to the first external electrode 30a via the conductive adhesive conductor portion 42. The exposed electrode portion 53b is electrically connected to the second external electrode 30b via the conductive adhesive conductor portion 42.

[0098] Next, we will describe the conductor part 40C, which is a third modified example of the conductor part 40. Figure 11c is a cross-sectional view showing a third modified example of the conductor portion. The conductor portion 40C is composed of a multilayer substrate. Specifically, the conductor portion 40C includes a plurality of insulating substrates 50a to 50c and conductive patterns 52a and 52b arranged alternately between the insulating substrates 50a to 50c and the insulating substrates 50a to 50c. The conductive patterns 52a and 52b are arranged to be exposed from both end faces of the insulating substrates 50a to 50c. A land electrode portion 56a is arranged on one end surface of the insulating substrate 50a located on one main surface side of the conductor portion 40C, and a land electrode portion 56b is arranged on the other end surface of the insulating substrate 50c located on the other main surface side of the conductor portion 40C. A protective layer 54 is arranged on the surface of the insulating substrate 50a in areas where the land electrode portions 56a and 56b are not arranged. A land electrode portion 56c is arranged on one end surface of the insulating substrate 50c located on the other main surface side of the conductor portion 40C, and a land electrode portion 56d is arranged on the other end surface of the insulating substrate 50c located on the other main surface side of the conductor portion 40C. A protective layer 54 is arranged on the surface of the insulating substrate 50c in areas where the land electrode portions 56c and 56d are not arranged. An interlayer connecting conductor (end face through-hole) 58a is provided at one end of the insulating substrates 50a to 50c to electrically connect the land electrode portion 56a and the land electrode portion 56c. At this time, the interlayer connecting conductor 58a is electrically connected to both the conductive patterns 52a and 52b. At the other end of the insulating substrates 50a to 50c, an interlayer connecting conductor (end face through-hole) 58b is provided to electrically connect the land electrode portion 56b and the land electrode portion 56d. At this time, the interlayer connecting conductor 58b is electrically connected to both the conductive patterns 52a and 52b. The land electrode portion 56a is electrically connected to the first external electrode 30a via the conductive adhesive conductor portion 42. The land electrode portion 56b is electrically connected to the second external electrode 30b via the conductive adhesive conductor portion 42.

[0099] Next, we will describe the conductor part 40D, which is a fourth modified example of the conductor part 40. Figure 11d is a cross-sectional view showing a fourth modified example of the conductor portion. The conductor portion 40D is composed of a multilayer substrate. Specifically, it includes a plurality of insulating substrates 50a to 50c and conductive patterns 52a and 52b arranged alternately via the insulating substrates 50a to 50c. A protective layer 54 is placed on the surface of the insulating substrate 50a located on one main surface side of the conductor portion 40C, such that a portion of the insulating substrate 50a is exposed. A pair of land electrode portions 56a and 56b are placed on the exposed portion of the insulating substrate 50a. A protective layer 54 is placed on the surface of the insulating substrate 50c located on the other main surface side of the conductor portion 40C, such that a portion of the insulating substrate 50c is exposed. A pair of land electrode portions 56c and 56d are placed on the exposed portion of the insulating substrate 50c. To provide electrical conductivity between the land electrode portion 56a and the land electrode portion 56c, an interlayer connecting conductor (through-hole) 60a is arranged, which is formed to penetrate from the surface of the insulating substrate 50a to the surface of the insulating substrate 50c. At this time, the interlayer connecting conductor 60a is electrically connected to both the conductive patterns 52a and 52b. To provide electrical conductivity between the land electrode portion 56b and the land electrode portion 56d, an interlayer connecting conductor (through-hole) is arranged, which is formed to penetrate from the surface of the insulating substrate 50a to the surface of the insulating substrate 50c. At this time, the interlayer connecting conductor 60b is electrically connected to both the conductive patterns 52a and 52b. The land electrode portion 56a is electrically connected to the first external electrode 30a via the conductive adhesive conductor portion 42. The land electrode portion 56b is electrically connected to the second external electrode 30b via the conductive adhesive conductor portion 42.

[0100] The insulating substrates 50, 50a to 50c are, for example, made of a substrate made by impregnating a base material, which is a mixture of glass cloth and glass nonwoven fabric, with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramics and glass. The insulating substrates 50, 50a to 50c may be single-layer substrates or substrates made by laminating multiple layers. The thickness of the insulating substrates 50, 50a to 50c is not particularly limited, but is preferably, for example, 200 μm or more and 800 μm or less.

[0101] Furthermore, the material of the conductive patterns 52, 52a, and 52b is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. Also, the thickness of the conductive patterns 52, 52a, and 52b, i.e., the dimension in the stacking direction x, is not particularly limited, but it is preferably, for example, 20 μm or more and 200 μm or less.

[0102] Furthermore, the protective layer 54 may be, for example, an etching resist or a solder resist. The material of the protective layer 54 is not particularly limited.

[0103] The conductive adhesive conductor part 42 of the conductive part 40 can be, for example, a high-temperature resistant epoxy adhesive or solder.

[0104] As described above, the conductive adhesive conductor portion 42 is positioned to be electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10. In other words, the conductor portion 40 is electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 via the conductive adhesive conductor portion 42. By positioning the conductor portion 40 in this way to be electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10, a DC current flows through the conductor portion 40, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing temperature rise.

[0105] The DC resistance RdcA of the conductor portion 40 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10. That is, RdcA <RdcBである。

[0106] The DC resistance RdcA of the conductor portion 40 is smaller than the DC resistance RdcB of the multilayer ceramic capacitor 10. As a result, DC current flows more preferentially through the conductor portion 40, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing the temperature rise.

[0107] On the other hand, if the DC resistance RdcA of the conductor portion 40 becomes greater than the DC resistance RdcB of the multilayer ceramic capacitor 10, current will flow more through the multilayer ceramic capacitor 10 than through the conductor portion 40, making it difficult to obtain the effect of handling high currents.

[0108] Furthermore, the conductor portion 40 is not electrically connected to the third external electrode 30c and the fourth external electrode 30d. By arranging the conductor portion 40 so as to be electrically connected only to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10, DC current flows through the conductor portion 40, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing temperature rise.

[0109] The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured after removing the conductive adhesive conductor portion 42 that joins them, and then comparing the DC resistance values ​​of each component. The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured using the four-terminal method with a current of 100 mA, in accordance with JISC2139.

[0110] 2. Mounting structure of multilayer ceramic electronic components Next, a mounting structure 500 for a multilayer ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0111] Figure 12 is a cross-sectional view in the stacking direction showing a mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 13 is a cross-sectional view in the width direction showing a mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 14 is a cross-sectional view in the stacking direction showing another mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention. Figure 15 is a cross-sectional view in the width direction showing another mounting structure of a multilayer ceramic electronic component according to an embodiment of the present invention.

[0112] The mounting structure 500 for multilayer ceramic electronic components according to this embodiment includes a multilayer ceramic electronic component 100 and a mounting substrate 70, as shown in Figures 12 and 13. The mounting substrate 70 includes a substrate core material 72 and connecting conductors (conductor lands) 74.

[0113] The core material 72 of the substrate is, for example, a substrate made of a material impregnated with epoxy resin or polyimide resin on a base material which is a mixture of glass cloth and glass nonwoven fabric, or a ceramic substrate manufactured by firing a sheet which is a mixture of ceramics and glass. The core material 72 of the substrate may be a single-layer substrate or a substrate which is made up of multiple layers. The thickness of the core material 72 of the substrate is not particularly limited, but for example, it is preferably 200 μm or more and 800 μm or less.

[0114] One main surface of the core material 72 of the substrate constitutes a substrate-side mounting surface 72a on which conductive lands 74 are arranged and which serves as the mounting surface for the multilayer ceramic electronic component 100.

[0115] The conductor land 74 includes a first conductor land 74a, a second conductor land 74b, a third conductor land 74c, and a fourth conductor land 74d.

[0116] The first conductor land 74a is electrically connected to and mechanically joined with the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 76. The second conductor land 74b is electrically connected to and mechanically joined with the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 76. The third conductor land 74c is electrically connected to and mechanically joined with the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 76. The fourth conductor land 74d is electrically connected to and mechanically joined with the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 76.

[0117] The conductive land 74 may also be provided on the main surface of the core material 72 of the substrate opposite to the substrate-side mounting surface 72a.

[0118] The material of the conductor land 74 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. The thickness of the conductor land 74, i.e., the dimension in the lamination direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less. For the bonding material 76, for example, a high heat-resistant epoxy adhesive or solder can be used.

[0119] In the above description, the mounting substrate 70 corresponds to the mounting substrate of the present invention. The core material 72 of the substrate corresponds to the core material of the substrate of the present invention. The mounting surface 72a on the substrate side corresponds to the mounting surface of the present invention. The plurality of conductor lands 74 correspond to the plurality of connecting conductors of the present invention. However, the connecting conductor of the present invention is not limited to so-called lands, but is any conductor that is provided between the multilayer ceramic capacitor 10 and the mounting substrate 70 and capable of electrically connecting the two, and is not limited by other uses, functions, shapes, names, etc.

[0120] In the mounting structure 500 for multilayer ceramic electronic components shown in Figures 12 and 13, it is preferable that the multilayer ceramic electronic component 100 is mounted such that the conductive portion 40 of the multilayer ceramic electronic component 100 is positioned opposite to the mounting substrate 70. In other words, it is preferable that the conductive portion 40 of the multilayer ceramic electronic component 100 is positioned on the first main surface side (non-mounted surface side) of the multilayer ceramic capacitor 10, and that the multilayer ceramic capacitor 10 of the multilayer ceramic electronic component 100 is mounted on the mounting substrate 70 side. By mounting in this way, the distance between the multilayer ceramic capacitor 10 and the mounting substrate 70 is not increased, making it easier to obtain the effect of low ESL. In addition, it is possible to mount the multilayer ceramic electronic component 100 without affecting the mounting of the multilayer ceramic electronic component 100 to the mounting substrate.

[0121] Furthermore, as shown in Figures 14 and 15, in the mounting structure 500A for multilayer ceramic electronic components, the conductive portion 40 of the multilayer ceramic electronic component 100 may be arranged on a surface perpendicular to the mounting substrate 70. In other words, with respect to the multilayer ceramic electronic component 100, the conductive portion 40 may be arranged on the first side surface 12c or the second side surface 12d side of the multilayer ceramic capacitor 10. By mounting in this manner, the mounting structure 500A for multilayer ceramic electronic components achieves the same effects as the mounting structure 500 for multilayer ceramic electronic components, and also achieves the following effects. In other words, the length of the conductor portion 40 of the multilayer ceramic electronic component 100 can be determined to match the length T, which is the length x in the stacking direction of the multilayer ceramic capacitor 10, thereby enabling a lower profile design.

[0122] 3. Manufacturing method of multilayer ceramic electronic components The following describes a method for manufacturing a multilayer ceramic capacitor 10, a multilayer ceramic electronic component 100 according to an embodiment of the present invention.

[0123] (a) Manufacturing method of multilayer ceramic capacitors First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. Known binders and solvents can be used.

[0124] Next, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the patterns of the first internal electrode layer 16a and the second internal electrode layer 16b formed on it. More specifically, for example, a screen plate for printing the first internal electrode layer 16a and a screen plate for printing the second internal electrode layer 16b can be prepared separately, and the internal electrode layers 16 of this embodiment can be printed using a printing machine that can print the two types of screen plates separately. Here, to obtain the desired structure, the sheet printed with the first internal electrode layer 16a and the sheet printed with the second internal electrode layer 16b are laminated to form the inner layer portion 15a. In this embodiment, the internal electrode layers 16 were printed by screen printing.

[0125] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer portion 15b1 on the first main surface 12a side. Subsequently, the portion that will become the inner layer portion 15a prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of this inner layer portion 15a to form the second outer layer portion 15b2 on the second main surface 12b side. This completes the production of the laminated sheet.

[0126] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0127] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0128] Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0129] A third base electrode layer 32c for the third external electrode 30c and a fourth base electrode layer 32d for the fourth external electrode 30d are formed on the first side surface 12c and the second side surface 12d of the laminate 12 obtained by firing.

[0130] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the base electrode layer 32. The temperature of this baking process is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed by a baked layer.

[0131] Here, various methods can be used to form the baked layers as the third base electrode layer 32c and the fourth base electrode layer 32d. For example, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed by a method in which conductive paste is extruded from a slit and applied. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0132] Furthermore, the layers can also be formed using a roller transfer method. In the case of the roller transfer method, when forming the third base electrode layer 32c and the fourth base electrode layer 32d not only on the first side surface 12c and the second side surface 12d, but also on a portion of the first main surface 12a and a portion of the second main surface 12b, it is possible to form the third base electrode layer 32c and the fourth base electrode layer 32d on a portion of the first main surface 12a and a portion of the second main surface 12b by increasing the pressing pressure during roller transfer.

[0133] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing. Similar to the third base electrode layer 32c and the fourth base electrode layer 32d, when forming the baked layers as the first base electrode layer 32a and the second base electrode layer 32b, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the first base electrode layer 32a and the second base electrode layer 32b. The temperature of the baking process at this time is preferably 700°C to 900°C.

[0134] Regarding the baking process, the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d may be baked simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d on the side may be baked separately, while the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b on the end face may be baked separately.

[0135] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0136] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0137] The conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, such as a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0138] When forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the desired location using a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of metal particles deposited on it that is less than 1 μm thick.

[0139] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 was formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer were formed on the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0140] As described above, the multilayer ceramic capacitor 10 shown in Figure 1 can be manufactured.

[0141] (b) Method of manufacturing the conductor Next, a method for manufacturing the conductive portion 40 of the multilayer ceramic electronic component 100 according to an embodiment of the present invention will be described.

[0142] The conductor portion 40 can be manufactured by first manufacturing an assembly of conductor portions 40, and then separating the assembly of conductor portions 40 into individual pieces.

[0143] The assembly of the conductive parts 40 is manufactured in the same manner as a typical printed circuit board.

[0144] The single-sided conductive part 40 is manufactured as follows. Specifically, first, a material is prepared with copper foil placed on one main surface of an insulating substrate, and this material is cut to a predetermined size. Next, etching resist is printed on the areas where the copper foil will remain (for example, the conductive pattern). Then, the copper foil other than the areas with etching resist is removed by etching. After that, the etching resist on the remaining areas is peeled off, and the conductive pattern is formed. Next, a solder resist is printed and UV cured to form a protective layer in order to insulate between the conductive patterns and to prevent solder from adhering to unwanted areas during the soldering process. Finally, surface treatments such as solder plating, electroless gold plating, and water-soluble flux treatment are performed on the exposed electrode areas where the conductive pattern is exposed, in order to improve solderability and prevent rust on the copper foil. As a result, an assembly of single-sided conductive parts 40 is manufactured.

[0145] A conductive section 40B, which is an example of a double-sided substrate, is manufactured as follows. Specifically, first, a material with copper foil arranged on both main surfaces of an insulating substrate is prepared, and this material is cut to a predetermined size. Next, holes such as through-holes and via holes are drilled at predetermined positions on the cut material. Next, interlayer connecting conductors (through-holes) are formed by through-hole plating to electrically connect the copper foil surfaces arranged on both main surfaces of the insulating substrate. Next, a dry film (etching resist) is laminated onto both main surfaces of the insulating substrate. Next, it is exposed and developed so that the dry film is baked only onto the inner layer pattern. Next, the dry film in unnecessary parts other than the conductive pattern is removed, and the resist for forming the conductive pattern is completed. Next, the copper foil in parts other than the conductive pattern is removed by etching. Next, the etching resist in the remaining parts is peeled off, and the conductive pattern is formed. Next, after the conductive pattern is formed, a protective layer is formed by forming a solder resist to insulate between the conductive patterns and to prevent solder from adhering to unnecessary parts during the soldering process. Finally, surface treatments such as solder plating, electroless gold plating, and water-soluble flux treatment are performed on the exposed conductive patterns to improve solderability and prevent corrosion of the copper foil. Based on the above, an assembly of conductive parts 40B, which is an example of a double-sided substrate, is manufactured.

[0146] A conductive portion 40D, which is an example of a multilayer substrate, is manufactured as follows. Specifically, first, the inner layer substrate and the outer layer substrate, which has copper foil placed on the surface of the insulating substrate, are cut to predetermined dimensions. Next, a dry film (etching resist) is laminated to both main surfaces of the cut materials. Next, the materials are exposed and developed to bake the dry film only onto the inner layer pattern. Next, unnecessary parts other than the conductive pattern are removed, and the resist for forming the conductive pattern is completed. Next, the copper foil in parts other than the conductive pattern is removed by etching. Next, the etching resist in the remaining parts is peeled off, and the conductive pattern is formed. Next, the inner layer substrate and the outer layer substrate, which already have the conductive pattern formed, are bonded together by pressing using a prepreg (insulating substrate) to manufacture a multilayer substrate. Next, holes such as through-holes and via holes are drilled at predetermined positions on the manufactured multilayer substrate. Next, interlayer connecting conductors (through-holes) are formed by through-hole plating to electrically connect the copper foil surfaces placed on both main surfaces of the multilayer substrate. Next, a dry film (etching resist) is laminated to both main surfaces of the multilayer substrate. Next, the material is exposed and developed to imprint a dry film only on the outer layer pattern. Then, unwanted parts other than the conductive pattern are removed, completing the resist for forming the conductive pattern. Next, the copper foil in parts other than the conductive pattern is removed by etching. Then, the etching resist in the remaining parts is peeled off, forming the conductive pattern. After the conductive pattern is formed, a protective layer is formed by applying solder resist to insulate the conductive patterns and prevent solder from adhering to unwanted parts during the soldering process. Finally, surface treatments such as solder plating, electroless gold plating, and water-soluble flux treatment are performed on the exposed parts of the conductive pattern to improve solderability and prevent corrosion of the copper foil. Based on the above, an assembly of conductive parts 40D, which is an example of a multilayer substrate, is manufactured.

[0147] (c) Manufacturing method of multilayer ceramic electronic components Next, the assembly of conductor parts 40 produced by the above method is separated into individual pieces, and the multilayer ceramic capacitor 10 produced by the above method is mounted on them. The same procedure is followed for conductor parts 40A to 40D.

[0148] More specifically, a cutting support tape is attached to the assembly of conductor parts 40. Next, the assembly of conductor parts 40 is cut to a predetermined size to separate them into individual pieces. Then, the individual pieces of conductor parts 40 are transferred to a heat-resistant plate. Note that heat-resistant tape or adhesive may be placed on the heat-resistant plate during the transfer process. Subsequently, conductive adhesive conductor parts 42 (solder) are printed onto the transferred individual pieces of conductor parts 40, and the multilayer ceramic capacitor 10 is mounted using a mounter. Next, soldering is performed in a reflow oven. Finally, the individual pieces of conductor parts 40 are removed from the heat-resistant plate, and the flux is washed off.

[0149] As described above, the multilayer ceramic electronic component 100 shown in Figure 1 is manufactured.

[0150] 4. Modified example of a multilayer ceramic capacitor according to this embodiment The following describes various modifications (the first to the third modification) of the multilayer ceramic capacitor in the multilayer ceramic electronic component according to this embodiment. Furthermore, for each of these modifications, components corresponding to those in the above embodiment are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0151] (1) First variation The multilayer ceramic capacitor 10A according to the first modified example of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12A of the multilayer ceramic capacitor 10A. Therefore, the same reference numerals are used for parts that are the same as those of the multilayer ceramic capacitor 10, and their descriptions are omitted.

[0152] Figure 16 is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 6. Figure 17 is a cross-sectional view showing a first modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 7. Figure 18 is a cross-sectional view taken along line XVIII-XVIII in Figure 16. Figure 19 is a cross-sectional view taken along line XIX-XIX in Figure 16.

[0153] The multilayer ceramic capacitor 10A has a laminated body 12A and an external electrode 30.

[0154] The laminate 12A includes a plurality of stacked dielectric layers 14. Furthermore, the laminate 12A includes a first main surface 12a and a second main surface 12b opposite to the stacking direction x, a first side surface 12c and a second side surface 12d opposite to the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to the length direction z perpendicular to the stacking direction x and the width direction y.

[0155] At the ends (L gaps) 24a and 24b of the laminate 12A, a first dummy electrode 25a is positioned so as to be exposed to the first end face 12e, and a second dummy electrode 25b is positioned so as to be exposed to the second end face 12f.

[0156] The first dummy electrode 25a and the second dummy electrode 25b are preferably arranged on the same plane as the second internal electrode layer 16b and have the same thickness as the second internal electrode layer 16b.

[0157] Reducing the coverage of the first dummy electrode 25a and the second dummy electrode 25b can shorten the current path.

[0158] The first dummy electrode 25a and the second dummy electrode 25b may be arranged on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, it is preferable that they be arranged on portions corresponding to locations obtained by shifting the ends (L gaps) 24a and 24b of the laminate 212 parallel to the lamination direction x. This arrangement makes it easier to form the plating layer 34 when providing the plating layer 34 without providing the base electrode layer 32.

[0159] Furthermore, if the first dummy electrode 25a and the second dummy electrode 25b are to be placed on the same plane as the second internal electrode layer 16b, the first dummy electrode 25a and the second dummy electrode 25b can be printed together with the second internal electrode layer 16b when printing the second internal electrode layer 16b, thereby arranging the first dummy electrode 25a and the second dummy electrode 25b on the same plane as the second internal electrode layer 16b.

[0160] Furthermore, a third dummy electrode 25c may be positioned on the side portions (W gap) 22a and 22b of the laminate 12A so as to be exposed on the first side surface 12c, and a fourth dummy electrode 25d may be positioned so as to be exposed on the second side surface 12d.

[0161] The third dummy electrode 25c and the fourth dummy electrode 25d are preferably arranged on the same plane as the first internal electrode layer 16a and have the same thickness as the first internal electrode layer 16a.

[0162] Reducing the coverage of the third dummy electrode 25c and the fourth dummy electrode 25d can shorten the current path.

[0163] The third dummy electrode 25c and the fourth dummy electrode 25d may be arranged on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, it is preferable that they be arranged on portions corresponding to the locations obtained by shifting the sides (W gaps) 22a and 22b of the laminate 12A parallel to the lamination direction x. By arranging them in this way, it becomes easier to form the plating layer 34 when the plating layer 34 is to be provided without providing the base electrode layer 32.

[0164] Furthermore, if the third dummy electrode 25c and the fourth dummy electrode 25d are to be placed on the same plane as the first internal electrode layer 16a, the third dummy electrode 25c and the fourth dummy electrode 25d can be placed on the same plane as the first internal electrode layer 16a by printing them together with the second internal electrode layer 16b when printing the first internal electrode layer 16a.

[0165] In the multilayer ceramic capacitor 10A shown in Figures 16 to 19, the first dummy electrode 25a, second dummy electrode 25b, third dummy electrode 25c, and fourth dummy electrode 25d are positioned on the sides (W gap) 22a, 22b and the ends (L gap) 24a, 24b of the laminate 12A, thereby preventing distortion during pressing.

[0166] (2) Second variation The multilayer ceramic capacitor 10B according to the second modification of this embodiment differs from the multilayer ceramic capacitor 10 according to this embodiment only in the structure of the laminate 12B of the multilayer ceramic capacitor 10B. Therefore, the same reference numerals are used for parts that are the same as those in the multilayer ceramic capacitor 10, and their descriptions are omitted.

[0167] Figure 20 is a cross-sectional view showing a second modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 6. Figure 21 is a cross-sectional view showing a second modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 7.

[0168] The laminate 12B includes a plurality of stacked dielectric layers 14. Furthermore, the laminate 12B includes a first main surface 12a and a second main surface 12b opposite to the stacking direction x, a first side surface 12c and a second side surface 12d opposite to the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to the length direction z perpendicular to the stacking direction x and the width direction y.

[0169] The laminate 12B includes an inner layer 15a and a first outer layer 15b1 and a second outer layer 15b2 arranged to sandwich the inner layer 15a in the stacking direction x.

[0170] The dielectric layer 14 of the inner layer 15a may be arranged so as to be sandwiched between the first internal electrode layer 16a and the first internal electrode layer 16a. In this case, the first internal electrode layer 16a and the first internal electrode layer 16a are arranged continuously via the dielectric layer 14 of the inner layer 15a.

[0171] Furthermore, the dielectric layer 14 of the inner layer 15a may be arranged so as to be sandwiched between the second internal electrode layer 16b and the second internal electrode layer 16b. In this case, the second internal electrode layer 16b and the second internal electrode layer 16b are arranged continuously via the dielectric layer 14 of the inner layer 15a. The dielectric layer 14 of the inner layer 15a consists of dielectric ceramic particles having a perovskite structure, mainly composed of a perovskite-type compound containing Ba and Ti. In addition, at least one of Si, Mg and Ba, and Mn may be added as an additive to these main components. The additive is present between the ceramic particles.

[0172] The inner layer portion 15a of the laminate 12B has a capacitance forming portion 26 in which a first internal electrode layer 16a and a second internal electrode layer 16b face each other via a dielectric layer 14 to form capacitance, and an internal electrode laminate portion 28 which is a region in which two or more first internal electrode layers 16a are continuously laminated. The multilayer ceramic capacitor 10B exhibits capacitor characteristics due to this capacitance forming portion 26.

[0173] Furthermore, the internal electrode stacked portion 28 is arranged to be divided into multiple internal electrode stacked portions 28 by the second internal electrode layer 16b. As a result, the aggregate of the first internal electrode layer 16a is dispersed, which enhances the heat dissipation effect and suppresses the temperature rise.

[0174] As shown in Figures 20 and 21, the multilayer ceramic capacitor 10B has an internal electrode laminated portion 28 that is divided by two second internal electrode layers 16b, and the internal electrode laminated portion 28 is divided into a first internal electrode laminated portion 28a, a second internal electrode laminated portion 28b, and a third internal electrode laminated portion 28c.

[0175] Furthermore, the second internal electrode layer 16b, which is arranged to divide the internal electrode stacking portion 28, a region in which two or more first internal electrode layers 16a are stacked consecutively, may be arranged as a single unit. This makes it possible to stack more of the first internal electrode layers 16a, thereby achieving a reduction in DC resistance.

[0176] Furthermore, the second internal electrode layer 16b, which is arranged to divide the internal electrode stacking portion 28, a region in which two or more first internal electrode layers 16a are stacked consecutively, may also be arranged in a manner where two or more layers are stacked consecutively. This makes it possible to achieve more sufficient connectivity between the second internal electrode layer 16b and the external electrode 30, even if the number of second internal electrode layers 16b is reduced.

[0177] The second internal electrode layer 16b may be located in the internal electrode stacking portion 28, which is a region where two or more first internal electrode layers 16a located on the first main surface 12a side of the laminate 12B are stacked in a continuous manner, i.e., between the first internal electrode stacking portion 28a and the first main surface 12a, and in the internal electrode stacking portion 28, which is a region where two or more first internal electrode layers 16a located on the second main surface 12b side of the laminate 12B are stacked in a continuous manner, i.e., between the third internal electrode stacking portion 28c and the second main surface 12b. This allows the capacitance forming portion 26 to be formed near the first outer layer portion 15b1 and the second outer layer portion 15b2, thereby obtaining a portion of the capacitance, shortening the current path to the mounting substrate, and achieving a low ESL effect.

[0178] Furthermore, the second internal electrode layer 16b does not have to be located in the internal electrode stacking section 28, which is the region where two or more first internal electrode layers 16a located on the first main surface 12a side of the laminate 12B are stacked in a continuous manner, i.e., between the first internal electrode stacking section 28a and the first main surface 12a, or in the internal electrode stacking section 28, which is the region where two or more first internal electrode layers 16a located on the second main surface 12b side of the laminate 12B are stacked in a continuous manner, i.e., between the third internal electrode stacking section 28c and the second main surface 12b. This increases the distance from the surface of the laminate 12B to the capacitance forming section 26 where capacitance is formed, and even if cracks occur from the surface of the laminate 12B due to external load, the effect of reducing the deterioration of insulation resistance can be obtained.

[0179] Preferably, the thickness of the dielectric layer 14 adjacent to the second internal electrode layer 16b is greater than the thickness of the dielectric layer 14 sandwiched between the first internal electrode layers 16a. This makes it possible to stack more of the first internal electrode layers 16a, thereby increasing the effect of reducing DC resistance.

[0180] Furthermore, it is preferable that the thickness of the second internal electrode layer 16b be greater than the thickness of the first internal electrode layer 16a. This ensures connectivity between the third lead-out electrode portion 20c of the second internal electrode layer 16b and the third external electrode 30c arranged on the first side surface 12c, even when the capacitance is reduced, and ensures connectivity between the fourth lead-out electrode portion 20d of the second internal electrode layer 16b and the fourth external electrode 30d arranged on the second side surface 12d.

[0181] (3) Third variation The multilayer ceramic capacitor 10C according to the third modified example of this embodiment has the same configuration as the multilayer ceramic capacitor 10 according to this embodiment, except that the laminated body 12C of the multilayer ceramic capacitor 10C is covered with a coating layer 29. Therefore, the same reference numerals are used for parts that are the same as those in the multilayer ceramic capacitor 10, and their descriptions are omitted.

[0182] Figure 22 is a cross-sectional view showing a third modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 6. Figure 23 is a cross-sectional view showing a third modified example of a multilayer ceramic capacitor according to an embodiment of the present invention, and corresponds to the cross-sectional view in Figure 7.

[0183] A coating layer 29 (silane coupling agent layer) is provided on a portion of the surface of the laminate 12C. Furthermore, the coating layer 29 is provided on at least one of the first main surface 12a and the second main surface 12b. More preferably, the coating layer 29 may be provided on both the first main surface 12a and the second main surface 12b. Alternatively, the coating layer 29 may be provided on the first side surface 12c and the second side surface 12d. In this case, it is preferable that the coating layer 29 is provided on part or all of the portion of the first side surface 12c and the second side surface 12d where the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d are not provided.

[0184] By providing a coating layer 29 on the surface of the laminate 12C, it is possible to prevent the intrusion of moisture and flux into the laminate 12C from the outside. Therefore, during flux mounting, corrosion caused by organic acids contained in the flux can be suppressed, thereby suppressing a decrease in moisture resistance reliability.

[0185] The coating layer 29 is preferably composed of a fluorine-based silane coupling agent or a carbon-based silane coupling agent.

[0186] The fluorine-based silane coupling agent contained in the coating layer 29 is CF3-(CF2) n1 -R-Si(O-R')3 (wherein n1 is a non-negative integer, R is a substituent or alkylene group containing Si or O, and R' is an alkyl group.) It is preferable that the silane coupling agent is represented by [formula]. For example, n1 may be an integer between 0 and 7. Also, R' may be a methyl group or an ethyl group.

[0187] The silane coupling agent comprises at least one alkoxy group, which is a reactive group. Furthermore, the silane coupling agent comprises one or more perfluoroalkyl groups.

[0188] Examples of fluorine-based silane coupling agents include, CF3(CF2)5(CH2)2Si(OCH3)3, CF3(CF2)3(CH2)2Si(OCH3)3, CF3(CF2)3(CH2)2Si(OC2H5)3, CF3(CF2)7(CH2)2Si(OCH3)3, CF3CH2O(CH2) 15 Si(OCH3)3, CF3(CH2)2Si(CH3)2(CH2) 15 Si(OCH3)3, CF3(CF2)3(CH2)2Si(CH3)2(CH2)9Si(OCH3)3, CF3COO(CH2) 15 Si(OCH3)3, CF3(CF2)5(CH2)2Si(OC2H5)3, CF3(CF2)7(CH2)2Si(CH3)2(CH2)9Si(OC2H5)3, CF3(CF2)7(CH2)2Si(CH3)2(CH2)6Si(OC2H5)3, CF3(CF2)7(CH2)2Si(OC2H5)3, CF3CH2O(CH2) 15 Si(OC2H5)3, CF3COO(CH2) 15 Si(OC2H5)3, CF3(CF2)4CONH(CH2)3Si(OCH3)3, CF3(CF2)7CONH(CH2)3Si(OCH3)3, CF3(CF2)5CONH(CH2)3Si(OC2H5)3, or, CF3(CF2)7CONH(CH2)3Si(OC2H5)3 You can use it.

[0189] The carbon-based silane coupling agent contained in the coating layer 29 is (RO)3Si-(CH2) n2 -CH3 It is preferable that the silane coupling agent is represented as follows: (where n2 is an integer between 0 and 17, and R is a methyl group or an ethyl group).

[0190] Examples of carbon-based silane coupling agents that can be used include KBM-3103C (decyltrimethoxysilane), KBM-13 (methyltrimethoxysilane), KBE-13 (methyltriethoxysilane), KBM-3033 (n-propyltrimethoxysilane), KBE-3033 (n-propyltriethoxysilane), KBM-3063 (hexyltrimethoxysilane), KBE-3063 (hexyltriethoxysilane), or octadecyltrimethoxysilane manufactured by Tokyo Chemical Industry Co., Ltd. (TCI).

[0191] Other carbon-based silane coupling agents that can be used include, for example, KBM-103 (phenylmethoxysilane), KBM-3066 (1,6-bis(trimethoxysilyl)hexane), and KBM-9659 (tris-(trimethoxysilylpropyl)isocyanurate) manufactured by Shin-Etsu Chemical Co., Ltd.

[0192] The coating layer 29 can be formed after the multilayer ceramic capacitor 10C is manufactured by, for example, immersing the multilayer ceramic capacitor 10C in the above-mentioned fluorine-based silane coupling agent or carbon-based silane coupling agent.

[0193] In the multilayer ceramic capacitor 10C shown in Figures 22 and 23, the coating layer 29 covers all or part of the area where the first external electrode 30a, second external electrode 30b, third external electrode 30c, and fourth external electrode 30d of the laminate 12C are not located. Therefore, in addition to the effects of the multilayer ceramic capacitor 10 of the first embodiment, it is possible to improve the moisture resistance of the multilayer ceramic capacitor 10C.

[0194] As described above, embodiments of the present invention have been disclosed, but the present invention is not limited thereto. In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention.

[0195] <1> A laminate comprising a plurality of stacked dielectric layers, including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, The laminated body is The first internal electrode layer exposed on the first end face and the second end face, The second internal electrode layer exposed on the first and second sides, It has, A first external electrode and a second external electrode connected to the first internal electrode layer, A third external electrode and a fourth external electrode connected to the second internal electrode layer, A multilayer ceramic capacitor equipped with, It has a conductor portion electrically connected to the first external electrode and the second external electrode, A multilayer ceramic electronic component in which the DC resistance RdcA of the conductor portion is smaller than the DC resistance RdcB of the multilayer ceramic capacitor.

[0196] <2> The first internal electrode layer is arranged alternately in the stacking direction with respect to the second internal electrode layer and the dielectric layer. <1> Multilayer ceramic electronic components as described above.

[0197] <3> The first internal electrode layer is arranged alternately with the dielectric layer in the stacking direction, and two or more are arranged consecutively. <1> Multilayer ceramic electronic components as described above.

[0198] <4> The conductor portion is not electrically connected to the third external electrode and the fourth external electrode. <1> or <3> Multilayer ceramic electronic components as described in any one of the items.

[0199] <5> The aforementioned conductor portion consists of an interposer substrate. <1> or <4> Multilayer ceramic electronic components as described in any one of the items.

[0200] <6> The conductor portion is arranged on one of the first main surface side, the first side surface side, and the second side surface side of the laminate. <1> or <5> Multilayer ceramic electronic components as described in any one of the items.

[0201] <7> <1> or <6> A multilayer ceramic electronic component as described in any of the following, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for multilayer ceramic electronic components, wherein the multilayer ceramic electronic component is mounted such that the conductive portion does not face the mounting substrate. [Explanation of Symbols]

[0202] 100 Multilayer Ceramic Electronic Components 10, 10A, 10B, 10C Multilayer Ceramic Capacitors Mounting structure of 500 and 500A multilayer ceramic electronic components 12-layer structure 12a First main surface 12b Second main surface 12c First side 12d Second aspect 12e First end face 12f Second end face 14 Dielectric layer 15a Inner layer 15b1 First outer layer 15b2 Second outer layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First counter electrode portion 18b Second counter electrode section 20a First extraction electrode section 20b Second extraction electrode section 20c Third extraction electrode section 20d Fourth extraction electrode section 22a, 22b Side (W gap) 24a, 24b End (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 32c Third Underlay Electrode Layer 32d Fourth underlay electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 40, 40A~40D Conductor section 42 Conductive adhesive conductor part 50, 50a~50c insulating substrate 52, 52a, 52b conductive patterns 53a~53d Exposed electrode part 54 Protective layer 56a~56d Land electrode section 58a, 58b Interlayer connecting conductors (end face through holes) 60a, 60b Interlayer connecting conductors (through-holes) 70 Implemented circuit boards 71 Core material 71a PCB-side mounting surface 74a, 74b, 74c, 74d Connecting conductors (lands) 76. Bonding material (solder) 25a First dummy electrode 25b Second dummy electrode 25c Third dummy electrode 25d Fourth dummy electrode 26 Capacity forming part 28 Internal electrode stacked section 28a First internal electrode stacked portion 28b Second internal electrode stack 28c Third internal electrode stack 29 Coating layer x stacking direction y width direction z-length direction T Dimensions in the stacking direction W: Dimension in the width direction L: Dimension in the length direction

Claims

1. A laminate comprising a plurality of stacked dielectric layers, including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, The laminated body is The first internal electrode layer exposed on the first end face and the second end face, The second internal electrode layer exposed on the first and second sides, It has, A first external electrode and a second external electrode connected to the first internal electrode layer, The third external electrode and the fourth external electrode are connected to the second internal electrode layer, A multilayer ceramic capacitor equipped with, It has a conductor portion electrically connected to the first external electrode and the second external electrode, A multilayer ceramic electronic component in which the DC resistance RdcA of the conductor portion is smaller than the DC resistance RdcB of the multilayer ceramic capacitor.

2. The multilayer ceramic electronic component according to claim 1, wherein the first internal electrode layer is alternately arranged in the stacking direction with respect to the second internal electrode layer and the dielectric layer.

3. The multilayer ceramic electronic component according to claim 1, wherein the first internal electrode layer is arranged alternately with the dielectric layer in the stacking direction and two or more layers are arranged in a continuous manner.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the conductive portion is not electrically connected to the third external electrode and the fourth external electrode.

5. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the conductive portion is made of an interposer substrate.

6. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the conductive portion is arranged on one of the first main surface side, the first side surface side, and the second side surface side of the laminate.

7. A multilayer ceramic electronic component according to claim 1 or claim 2, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for multilayer ceramic electronic components, wherein the multilayer ceramic electronic component is mounted such that the conductive portion does not face the mounting substrate.

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