Semiconductor device and power conversion device

Abstract

To provide a semiconductor device that can prevent a relationship between resistance and breakdown voltage from being deteriorated even when a narrow mesa structure and a super junction structure are combined.SOLUTION: A semiconductor device 101 comprises: a plurality of trenches 16 that penetrate through a source region 4 and a base region 3; and a mesa region 15 that is a region among the plurality of trenches 16. A gate electrode 6 that faces the base region 3 through a gate insulation film 5 is formed within the trench 16. A field relaxation layer 8 is provided just under the trench 16. A super junction structure, in which a first pillar layer 13 and a second pillar layer 14 are alternately arranged, is formed between the base region 3 and a drift layer 2. Width of the first pillar layer 13 is less than or equal to width of the field relaxation layer 8.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] BACKGROUND ART In power electronics devices, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used as switching elements that control the power supply to loads such as motors.

[0003] Meanwhile, MOSFETs and IGBTs using wide bandgap semiconductors such as silicon carbide (SiC) are attracting attention as next-generation switching elements, and are expected to be applied to technical fields handling high voltages of around 1 kV or higher. In addition to SiC, other wide bandgap semiconductors include gallium nitride (GaN)-based materials and diamond.

[0004] The resistance components of a MOSFET include the channel resistance, which is the resistance component of the inversion layer called the channel, the drift resistance, which is the resistance component of the drift layer, and the contact resistance between the metal electrode (main electrode) and the semiconductor layer. MOSFETs are broadly divided into planar and trench types. In planar types, the gate structure is placed on the surface of the semiconductor layer, while in trench types, the gate structure is placed in a trench formed in the semiconductor layer. Typically, trench types can achieve higher channel density than planar types, thereby reducing channel resistance.

[0005] However, trench transistors have the problem that the electric field concentrates at the bottom of the trench where the gate structure is formed, which can easily deteriorate the reliability of the gate oxide film. To solve this problem, a technology has been proposed in which a p-type electric field buffer layer is provided at the bottom of the trench, extending the depletion layer to the bottom of the trench to buffer the electric field at the bottom of the trench. Furthermore, if the electric field buffer layer is grounded, the displacement of the depletion layer during switching can be accelerated, which can also reduce switching losses.

[0006] When a gate voltage is applied to the gate structure, an inversion layer (channel) is formed only in the surface layer of the semiconductor layer facing the gate structure. Therefore, in a trench-type MOSFET, an inversion layer is formed only in the surface layer on both sides of the mesa-shaped semiconductor region (hereinafter referred to as the "mesa region") sandwiched between the trenches of the gate structure. However, if the width of the mesa region is narrowed to the extent that the inversion layers on both sides are connected, an inversion layer can be formed throughout the entire mesa region, further reducing the channel resistance. A structure in which the mesa region is narrowed in this way so that an inversion layer is formed throughout the entire mesa region is called a "narrow mesa structure."

[0007] On the other hand, the drift layer is a semiconductor region provided between the part where the inversion layer is formed and the semiconductor substrate, and the breakdown voltage of the entire MOSFET is maintained by depleting the drift layer. One technology for reducing drift resistance is a structure called a superjunction, in which p-type pillar layers, which are p-type semiconductor regions extending vertically, and n-type pillar layers, which are n-type semiconductor regions, are arranged alternately. In a superjunction structure, the breakdown voltage is maintained by the depletion layer extending between the p-type pillar layers and the n-type pillar layers, and the drift resistance can be reduced by designing the impurity concentration of the n-type pillar layers to be high.

[0008] By applying both the trench structure and the superjunction structure, the channel resistance and drift resistance can be reduced, thereby making it possible to reduce the resistance of the MOSFET. For example, Patent Document 1 below discloses a semiconductor device that applies both the trench structure and the superjunction structure. Furthermore, Patent Document 2 discloses a silicon carbide semiconductor device in which an electric field buffer layer is provided directly below the trench of the gate structure and a p-type pillar layer of the superjunction structure is disposed directly below the electric field buffer layer. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-66708 [Patent Document 2] Patent Publication No. 2021-27138 Summary of the Invention [Problem to be solved by the invention]

[0010] As mentioned above, combining a trench structure with a superjunction structure can reduce the resistance of a semiconductor device. However, considering the processing technology used in semiconductor device manufacturing, there is a limit to how narrow the trench can be, even if the mesa region can be narrowed. Therefore, in semiconductor devices with narrow mesa structures, the proportion of the trench is larger than the proportion of the mesa region. In this case, if p-type pillar layers are placed directly under all of the trenches, the ratio of the p-type pillar layers to the n-type pillar layers deviates from the ideal, and it has been found that this degrades the relationship between the resistance and breakdown voltage of the semiconductor device.

[0011] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can prevent the relationship between resistance and breakdown voltage from deteriorating even when a narrow mesa structure and a superjunction structure are combined. [Means for solving the problem]

[0012] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, a first conductivity type drift layer formed between the first main surface and the second main surface of the semiconductor substrate, a second conductivity type base region formed in a surface layer portion of the semiconductor substrate on the first main surface side, a first conductivity type source region formed in a surface layer portion of the base region, a contact region in the surface layer portion of the base region where the source region is not formed, a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region, and a front surface of the semiconductor substrate. a mesa region between the plurality of trenches, the mesa region including the base region and the source region; a gate electrode formed in the trench and facing the base region via a gate insulating film; a field relaxation layer of a second conductivity type provided directly below the trench; and a superjunction structure provided between the base region and the drift layer, in which first pillar layers of the second conductivity type and second pillar layers of the first conductivity type are alternately arranged, wherein a width of the first pillar layer is equal to or less than a width of the field relaxation layer. The width of the second pillar layer is wider than the width of the mesa region. . [Effects of the Invention]

[0013] According to the present disclosure, by making the width of the first pillar layer of the superjunction structure narrower than the width of the electric field relaxation layer below the trench of the gate structure, it is possible to maintain a good relationship between the resistance and breakdown voltage of the semiconductor device. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a schematic diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a schematic diagram of a semiconductor device according to a second embodiment. [Figure 3] FIG. 10 is a schematic diagram of a semiconductor device according to a third embodiment. [Figure 4] FIG. 10 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE INVENTION

[0015] <First Embodiment> 1 is a schematic diagram of a semiconductor device 101 according to a first embodiment. Here, an example is shown in which the semiconductor device 101 is a MOSFET, but the semiconductor device 101 may be another switching element such as an IGBT. In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0016] The semiconductor device 101 is formed using a semiconductor substrate 1 made of silicon carbide (SiC). The upper surface of the semiconductor substrate 1 in Fig. 1 is defined as the "first main surface" and the lower surface is defined as the "second main surface." The material of the semiconductor substrate 1 is not limited to silicon carbide, and it may be silicon (Si), or may be formed from other wide bandgap semiconductors such as gallium nitride (GaN)-based materials or diamond.

[0017] A drift layer 2 of a first conductivity type (n-type) is formed between the first and second main surfaces of the semiconductor substrate 1. A base region 3 of a second conductivity type (p-type) is formed in a surface layer portion on the first main surface side of the semiconductor substrate 1. Source regions 4 of the first conductivity type are formed discretely in the surface layer portion of the base region 3, and regions in the surface layer portion of the base region 3 where the source regions 4 are not formed become contact regions 31.

[0018] A source electrode 10 connected to the source region 4 and the contact region 31 is formed on the first main surface of the semiconductor substrate 1. A drain electrode 11 is formed on the second main surface of the semiconductor substrate 1.

[0019] A plurality of trenches 16 are formed on the first main surface side of the semiconductor substrate 1, penetrating the source region 4 and the base region 3. The regions between the plurality of trenches 16 are mesa regions 15, and the base region 3 and source region 4 are formed in the mesa regions 15. On the surface of the mesa region 15, the area of ​​the contact region 31 is preferably smaller than the area of ​​the source region 4.

[0020] A gate insulating film 5, a gate electrode 6, and an interlayer insulating film 7 are buried in the trench 16. The gate insulating film 5 is formed on the side and bottom surfaces of the trench 16, and the gate electrode 6 is formed on the gate insulating film 5. Therefore, the gate electrode 6 faces the base region 3 via the gate insulating film 5. The interlayer insulating film 7 covers the gate insulating film 5, and provides insulation between the gate insulating film 5 and the source electrode 10.

[0021] In addition, a second conductivity type electric field relaxation layer 8 is formed directly below the trench 16. The electric field relaxation layer 8 is electrically connected to the source electrode 10 via the base region 3. In this embodiment, a second conductivity type connection layer 9 that connects the electric field relaxation layer 8 and the base region 3 is provided in a part of the mesa region 15. The connection layer 9 is preferably disposed directly below the contact region 31.

[0022] A superjunction structure in which first pillar layers 13 of the second conductivity type and second pillar layers 14 of the first conductivity type are alternately arranged is provided above the drift layer 2 in the semiconductor substrate 1, i.e., between the base region 3 and the drift layer 2. The peak impurity concentration of the first pillar layers 13 is lower than that of the electric field relaxation layer 8, and the peak impurity concentration of the second pillar layers 14 is higher than that of the drift layer 2.

[0023] In the semiconductor device 101 according to the first embodiment, the extending direction of the first pillar layer 13 and the second pillar layer 14 is the same as the extending direction of the trench 16 and the electric field relaxation layer 8, and the first pillar layer 13 is disposed directly below the electric field relaxation layer 8. The width of the first pillar layer 13 is equal to or less than the width of the electric field relaxation layer 8. In addition, the width of the second pillar layer 14 is wider than the width of the mesa region 15.

[0024] Furthermore, the semiconductor device 101 according to the first embodiment employs a narrow mesa structure in which the width of the mesa region 15 is narrowed. In the narrow mesa structure, the narrow mesa region 15 is sandwiched between the gate electrodes 6, allowing an inversion layer to be formed throughout the mesa region 15. To minimize the current path and reduce channel resistance, it is desirable to have a configuration in which current flows vertically through the mesa region 15. Furthermore, it is desirable for the width of the mesa region 15 to be in the range of 0.01 μm to 0.2 μm.

[0025] Here, a method for forming the trench 16 will be described. The trench 16 can be formed by forming an etching mask on the first main surface of the semiconductor substrate 1 and performing dry etching using the etching mask. When the semiconductor substrate 1 is silicon, a resist mask can be used as the etching mask. However, when the semiconductor substrate 1 is silicon carbide, silicon carbide has a large bond energy, so a resist mask cannot provide a sufficient etching selectivity. In that case, therefore, it is preferable to form a silicon oxide film or the like over the entire first main surface of the semiconductor substrate 1, process it with a resist mask to form a hard mask, and use the hard mask as the etching mask.

[0026] To narrow the mesa region 15 to form a narrow mesa structure, it is necessary to improve the processing accuracy of the etching mask, but there is a limit to how much this can be done. Therefore, the etching mask formed by the above method may be further processed. Specifically, the formed etching mask may be thinned by isotropic etching, and the trench 16 may be formed by dry etching using the thinned etching mask. With this method, it is possible to form a mesa region 15 narrower than 0.2 μm, even when the semiconductor substrate 1 is made of silicon carbide.

[0027] When the semiconductor device 101 is in the on state, the second pillar layer 14 serves as a current path, and when the semiconductor device 101 is switched to the off state, a depletion layer extends from the first pillar layer 13 to the second pillar layer 14, thereby blocking the current path. Since the resistance can be reduced by increasing the impurity concentration of the second pillar layer 14, providing a superjunction structure in the drift layer 2 can significantly improve the relationship between the breakdown voltage and drift resistance.

[0028] The length of the first pillar layer 13 and the second pillar layer 14 in the depth direction of the semiconductor substrate 1 is preferably at least half the length from the bottom of the drift layer 2 to the bottom of the electric field relaxation layer 8. The greater the proportion of the superjunction structure in the region from the bottom of the drift layer 2 to the bottom of the electric field relaxation layer 8, the more improved the relationship between the resistance and the breakdown voltage of the semiconductor device 101.

[0029] The first pillar layers 13 are electrically connected to the source electrodes 10. For this reason, it is desirable that the installation period (i.e., installation interval) of the first pillar layers 13 is the same as the installation period of the trenches 16. In this case, the first pillar layers 13 and the source electrodes 10 can be electrically connected through the electric field relaxation layer 8 below the trenches 16.

[0030] Furthermore, since the area directly below the electric field relaxation layer 8 is unlikely to become a current path, the current path can be made shorter by placing the first pillar layer 13 there. That is, it is preferable to place the first pillar layer 13 directly below the trench 16 and the second pillar layer 14 directly below the mesa region 15.

[0031] The superjunction structure made up of the first pillar layer 13 and the second pillar layer 14 can be formed by high-energy ion implantation or by repeating ion implantation and epitaxial growth.

[0032] If the proportion of the trench 16 becomes larger than the proportion of the mesa region 15 due to constraints on the processing accuracy of the mesa region 15, for example, if a first pillar layer 13 of the same width as the trench 16 is provided below the trench 16 and a second pillar layer 14 of the same width as the trench 16 is provided below the mesa region 15, the proportion of the first pillar layer 13 in the superjunction structure will increase, deteriorating the relationship between resistance and breakdown voltage. In this embodiment, this problem is solved by narrowing the first pillar layer 13 and widening the second pillar layer 14, making it possible to maintain a good relationship between resistance and breakdown voltage.

[0033] <Embodiment 2> In the first embodiment, the ratio between the first pillar layer 13 and the second pillar layer 14 is optimized by narrowing the width of the first pillar layer 13, but in the second embodiment, another method for optimizing the ratio is shown.

[0034] 2 is a schematic diagram of a semiconductor device 102 according to the second embodiment. The semiconductor device 102 according to the second embodiment differs from the semiconductor device 101 according to the first embodiment in the installation period of the first pillar layers 13 and the second pillar layers 14. In the first embodiment, the ratio of the installation period of the first pillar layers 13 to the installation period of the trenches 16 (hereinafter also referred to as the "installation period ratio") was 1:1. However, in the semiconductor device 102 of FIG. 2, the installation period of the first pillar layers 13 is made longer than the installation period of the trenches 16, so that the installation period ratio of the first pillar layers 13 to the trenches 16 is 2:1. Even in this case, the relationship between the breakdown voltage and the resistance is optimized.

[0035] The placement period ratio of the first pillar layers 13 to the trenches 16 may be any integer to integer ratio, for example, 3:1 or 3:2. Depending on the placement period ratio, the first pillar layers 13 may be placed directly below the mesa regions 15, but because the channel resistance is sufficiently reduced, the resulting increase in resistance is negligibly small.

[0036] In the second embodiment, the width of the first pillar layer 13 may be narrower or wider than the width of the electric field buffer layer 8 below the trench 16. If the width of the first pillar layer 13 is wider than the width of the electric field buffer layer 8, the resistance may increase slightly, but even in this case, the increase in resistance is negligibly small.

[0037] In the semiconductor device 102 according to the second embodiment, the channel density can be increased by narrowing the trenches 16, thereby further reducing the channel resistance. However, the method of forming the trenches 16 described in the first embodiment can narrow the mesa regions 15, but cannot narrow the trenches 16. In other words, the ratio between the mesa regions 15 and the trenches 16 can be changed, but the arrangement period of the mesa regions 15 and the trenches 16 cannot be changed.

[0038] Therefore, in the second embodiment, the trenches 16 are preferably formed by the following method. First, a first hard mask is formed on the first main surface of the semiconductor substrate 1 and patterned. Next, a second hard mask is formed over the entire first main surface of the semiconductor substrate 1, and anisotropic etching is performed on the second hard mask. As a result, the second hard mask remains on the sidewalls of the first hard mask. After that, the first hard mask is removed by etching, leaving only the second hard mask. Then, the trenches 16 are formed in the first main surface of the semiconductor substrate 1 by dry etching using the remaining second hard mask as an etching mask. With this method, the second hard mask can be formed at twice the density of the first hard mask, allowing narrow trenches 16 to be formed.

[0039] It is desirable that the first and second hard masks be made of materials with a high etching selectivity. For example, it is recommended to use polycrystalline silicon for the first hard mask and silicon oxide for the second hard mask. Furthermore, by repeating the formation of the second hard mask, the density of the hard mask can be increased by four or eight times, thereby forming even narrower trenches 16.

[0040] By using this method, the placement period of the mesa regions 15 and trenches 16 can be reduced, but there are also limitations on the processing of the width of the first pillar layers 13 and the second pillar layers 14. When the first pillar layers 13 and the second pillar layers 14 are formed by high-energy ion implantation, a thick mask material is required, which makes it difficult to process fine lines. When the first pillar layers 13 and the second pillar layers 14 are formed by a combination of ion implantation and epitaxial growth, the influence of mask misalignment is a limitation. In addition, because the implanted ions have a certain degree of spread in the in-plane direction, it is difficult to process the first pillar layers 13 and the second pillar layers 14 to the same fine size as the mesa regions 15.

[0041] In this embodiment, it is not necessary to place the second pillar layer 14 directly below the mesa region 15, so it is possible to maintain a good relationship between resistance and breakdown voltage while avoiding restrictions on the widths of the first pillar layer 13 and the second pillar layer 14.

[0042] <Third Embodiment> 3 is a schematic diagram of a semiconductor device 103 according to a third embodiment. The semiconductor device 103 according to the third embodiment differs from the semiconductor device 101 according to the first embodiment or the semiconductor device 102 according to the second embodiment in the extending direction of the first pillar layer 13 and the second pillar layer 14. In the first and second embodiments, the extending direction of the first pillar layer 13 and the second pillar layer 14 is the same as the extending direction of the trench 16 and the electric field relaxation layer 8. However, in the semiconductor device 103 of FIG. 3, the extending direction of the first pillar layer 13 and the second pillar layer 14 differs by 90 degrees from the extending direction of the trench 16 and the electric field relaxation layer 8. In other words, the extending direction of the first pillar layer 13 and the second pillar layer 14 is perpendicular to the extending direction of the trench 16 and the electric field relaxation layer 8.

[0043] As described in the first and second embodiments, the widths of the first pillar layers 13 and the second pillar layers 14 are important parameters in the superjunction structure. In the first and second embodiments, a method for improving the relationship between resistance and breakdown voltage by optimizing the widths and placement intervals of the first pillar layers 13 and the second pillar layers 14 was described. However, the widths of the first pillar layers 13 and the second pillar layers 14 cannot be designed independently of the placement intervals of the mesa regions 15. This is because, if the widths of the first pillar layers 13 and the second pillar layers 14 were designed independently of the placement intervals of the mesa regions 15, the positional relationship between the mesa regions 15 and the second pillar layers 14 would vary depending on the location, resulting in localized current imbalances. Localized current imbalances must be avoided because they can cause localized breakdown when a large current flows due to an abnormality such as a load short circuit.

[0044] Therefore, in the third embodiment, the bottom surface of the electric field relaxation layer 8 is used as a boundary, and the extending direction of the first pillar layer 13 and the second pillar layer 14 provided below this boundary is offset by 90 degrees from the extending direction of the mesa region 15 and the trench 16 provided above this boundary. This allows the widths of the first pillar layer 13 and the second pillar layer 14 to be designed independently of the installation period of the mesa region 15. This reduces constraints on the design of the widths of the first pillar layer 13 and the second pillar layer 14, allowing the relationship between resistance and breakdown voltage to be closer to an ideal one. Note that even when the extending direction of the first pillar layer 13 and the second pillar layer 14 is offset by 90 degrees from the extending direction of the mesa region 15 and the trench 16 as in the present embodiment, the first pillar layer 13 can be electrically connected to the source electrode 10 through the electric field relaxation layer 8.

[0045] <Fourth Embodiment> In this embodiment, a semiconductor device according to any one of the above-described embodiments 1 to 3 is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, a case in which the present disclosure is applied to a three-phase inverter will be described below as embodiment 4.

[0046] FIG. 4 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0047] The power conversion system shown in Fig. 4 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0048] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 4, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal to the drive circuit 202 to control the drive circuit 202.

[0049] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0050] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements (not shown), which are switched to convert DC power supplied from the power supply 100 into AC power and supply it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements. A semiconductor device according to any of the above-described first to third embodiments is applied to each switching element of the main conversion circuit 201. Two of the six switching elements are connected in series to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0051] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0052] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0053] In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to third embodiments is applied as the switching element of the main conversion circuit 201, and therefore the resistance can be significantly reduced.

[0054] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0055] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0056] It is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0057] Various aspects of the present disclosure are summarized below as appendices.

[0058] (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; a second conductivity type electric field relaxation layer provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with the width of the first pillar layer is equal to or less than the width of the electric field buffer layer; Semiconductor device.

[0059] (Appendix 2) the width of the second pillar layer is wider than the width of the mesa region; 2. The semiconductor device according to claim 1.

[0060] (Appendix 3) a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; a second conductivity type electric field relaxation layer provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with the ratio of the formation period of the first pillar layers to the formation period of the trenches is expressed as an integer-to-integer ratio excluding 1:1; Semiconductor device.

[0061] (Appendix 4) the extending direction of the first pillar layer and the second pillar layer is the same as the extending direction of the trench; the first pillar layer is disposed directly below the electric field relaxation layer; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0062] (Appendix 5) the extending direction of the first pillar layer and the second pillar layer is perpendicular to the extending direction of the trench; 4. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating film.

[0063] (Appendix 6) In the depth direction of the semiconductor substrate, the length of the first pillar layer and the second pillar layer is equal to or greater than half of the length from the bottom of the drift layer to the bottom of the electric field buffer layer. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

[0064] (Appendix 7) The width of the mesa region is 0.2 μm or less. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0065] (Appendix 8) a second conductivity type connection layer formed directly below the contact region in the mesa region and connecting the electric field reduction layer and the base region; 8. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

[0066] (Appendix 9) an area of ​​the contact region on the surface of the mesa region that is smaller than an area of ​​the source region; 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0067] (Appendix 10) The semiconductor substrate is formed of silicon carbide. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

[0068] (Appendix 11) a main conversion circuit including the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising: [Explanation of symbols]

[0069] 101, 102, 103 semiconductor device, 1 semiconductor substrate, 2 drift layer, 3 base region, 4 source region, 5 gate insulating film, 6 gate electrode, 7 interlayer insulating film, 8 electric field relaxation layer, 9 connection layer, 10 source electrode, 11 drain electrode, 13 first pillar layer, 14 second pillar layer, 15 mesa region, 16 trench, 31 contact region, 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with the width of the first pillar layer is equal to or less than the width of the electric field buffer layer, the width of the second pillar layer is wider than the width of the mesa region; Semiconductor device.

2. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with the width of the first pillar layer is equal to or less than the width of the electric field buffer layer, The width of the mesa region is 0.2 μm or less. Semiconductor device.

3. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; a second conductivity type connection layer formed directly below the contact region in the mesa region and connecting the electric field reduction layer and the base region; Equipped with the width of the first pillar layer is equal to or less than the width of the electric field relaxation layer; Semiconductor device.

4. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with a ratio of an installation period of the first pillar layers to an installation period of the trenches is expressed as an integer-to-integer ratio excluding 1:1, The width of the mesa region is 0.2 μm or less. Semiconductor device.

5. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; a second conductivity type connection layer formed directly below the contact region in the mesa region and connecting the electric field reduction layer and the base region; Equipped with the ratio of the formation period of the first pillar layers to the formation period of the trenches is expressed as an integer-to-integer ratio excluding 1:1; Semiconductor device.

6. a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a drift layer of a first conductivity type formed between the first main surface and the second main surface of the semiconductor substrate; a second conductivity type base region formed in a surface layer portion on the first main surface side of the semiconductor substrate; a first conductivity type source region formed in a surface layer portion of the base region; a contact region, which is a region in a surface layer portion of the base region where the source region is not formed; a source electrode formed on the first main surface of the semiconductor substrate and connected to the source region and the contact region; a plurality of trenches formed on the first main surface side of the semiconductor substrate and penetrating the source region and the base region; a mesa region between the plurality of trenches, in which the base region and the source region are provided; a gate electrode formed in the trench and facing the base region via a gate insulating film; an electric field relaxation layer of a second conductivity type provided directly below the trench; a superjunction structure provided between the base region and the drift layer, in which first pillar layers of a second conductivity type and second pillar layers of a first conductivity type are alternately arranged; Equipped with an installation period of the first pillar layers is longer than an installation period of the trenches, and a ratio of the installation period of the first pillar layers to the installation period of the trenches is expressed as an integer-to-integer ratio excluding 1:1; Semiconductor device.

7. an extending direction of the first pillar layer and the second pillar layer is the same as an extending direction of the trench; the first pillar layer is disposed directly below the electric field relaxation layer; The semiconductor device according to claim 1 .

8. an extension direction of the first pillar layer and the second pillar layer perpendicular to an extension direction of the trench; The semiconductor device according to claim 1 .

9. In the depth direction of the semiconductor substrate, the length of the first pillar layer and the second pillar layer is equal to or greater than half of the length from the bottom of the drift layer to the bottom of the electric field relaxation layer. The semiconductor device according to claim 1 .

10. an area of ​​the contact region on the surface of the mesa region that is smaller than an area of ​​the source region; The semiconductor device according to claim 1 .

11. The semiconductor substrate is formed of silicon carbide. The semiconductor device according to claim 1 .

12. a main conversion circuit including the semiconductor device according to any one of claims 1 to 6, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device; a control circuit that outputs a control signal to the drive circuit to control the drive circuit; A power conversion device comprising:

Images