Touch sensor mutual charge cancellation and related systems, methods and apparatus

Abstract

The process includes receiving relevant input signals via receiver electrodes of the sensor array, the relevant input signals indicative of the relevant mutual capacitance of the receiver electrodes; adding a balanced signal to the relevant input signals to generate a balanced input signal, at least in part responsive to the number of sensor nodes in the receiver electrodes; generating a voltage signal indicative of the relevant mutual capacitance of the receiver electrodes, at least in part responsive to the balanced input signal; and generating a digital value representing the voltage signal.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This patent application claims priority to U.S. Provisional Patent Application No. 63 / 198,877, filed November 19, 2020, and entitled "FREE-FORM TOUCH SENSOR MUTUAL CHARGE CANCELLATION," the entire disclosure of which is incorporated herein by reference.

[0002] FIELD OF THE INVENTION FIELD OF THE DISCLOSURE This disclosure relates generally to capacitive sensors and mutual capacitive touch sensing. [Background technology]

[0003] Capacitive sensors are utilized in a variety of operating situations, including, but not limited to, touch screens, touch pads, and capacitive buttons. [Brief explanation of the drawings]

[0004] To easily identify the discussion of any particular element or function, the most significant digit(s) of a reference number refers to the figure number in which that element is first introduced. [Figure 1] 1 is a schematic diagram illustrating an apparatus according to one or more embodiments. [Figure 2] 1 is a schematic diagram illustrating a portion of a touch sensing device utilizing differential signal processing in accordance with one or more embodiments. [Figure 3] 1 is a schematic diagram illustrating a portion of a touch sensing device utilizing differential signal processing in accordance with one or more embodiments. [Figure 4] 1 is a schematic diagram illustrating a portion of a touch sensing device utilizing differential signal processing in accordance with one or more embodiments. [Figure 5] FIG. 1 illustrates a system for mutual touch sensing, according to one or more embodiments. [Figure 6] FIG. 1 is a flow diagram illustrating a process according to one or more embodiments. [Figure 7]FIG. 1 is a circuit block diagram that, in some embodiments, can be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. [Figure 8A] FIG. 1 is a schematic diagram of an exemplary arrangement of a sensor layout. [Figure 8B] FIG. 1 is a schematic diagram of an exemplary arrangement of a sensor layout. [Figure 8C] FIG. 1 is a schematic diagram of an exemplary arrangement of a sensor layout. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made, as enabled herein, without departing from the scope of the present disclosure.

[0006] The figures presented herein are not meant to be actual illustrations of any particular method, system, device, or structure, but are merely idealized representations used to explain embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is illustrative, and the scope of the present disclosure is intended to encompass examples and legal equivalents. The use of such terms is not intended to limit the examples or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the examples, as generally described herein and illustrated in the figures, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the examples may be presented in figures, the figures are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic among various blocks are exemplary specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (sometimes referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when the general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0012] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structure, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another.

[0013] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient way to distinguish between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, e.g., within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0015] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers present. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers present. The terms "on" and "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly stated otherwise or the context indicates otherwise to one of ordinary skill in the art.

[0016] Mutual capacitance is the capacitive coupling between objects, and in the case of a touch sensor, it is the capacitive coupling between the intersections of electrodes acting as transmitters (transmitter electrodes) and receivers (receiver electrodes), sometimes referred to as "X electrodes" and "Y electrodes," respectively. In a typical arrangement for mutual capacitance sensing, the transmitter electrodes and receiver electrodes are arranged in a grid of rows and columns, and each intersection of a transmitter electrode and a receiver electrode is referred to as a "sensor node." The transmitter electrodes are connected to the mutual capacitance (C M The sensor node is driven with a pulse that injects current into the capacitance of the receiver electrode through the capacitively coupled ground path. A grounded object in suitable proximity to the sensor node shunts some of the charge through the capacitively coupled ground path, thus appearing to an observer (i.e., measurement circuitry) to change (e.g., decrease) the mutual capacitance between the transmitter and receiver electrodes that intersect at that sensor node. Mutual capacitance sensing involves detecting such changes in mutual capacitance.

[0017] A typical two-dimensional (2D) arrangement of a sensor array for mutual capacitance sensing has a rectangular shape, and a typical touch controller is pre-configured to detect changes in capacitive load on a sensor array having a rectangular shape. Sometimes, multiple arrangements, each having a rectangular shape, are combined and individually coupled to multiple touch controllers pre-configured to detect changes in capacitive load on a sensor array having a rectangular shape. In a rectangular arrangement of a sensor array, each row (and column) of the sensor array typically has the same number of sensor nodes. The number of sensor nodes per row may be the same or different from the number of sensor nodes per column. Such symmetry is convenient for mutual capacitance sensing because the effect of capacitive load on the sensor array is balanced (i.e., equalized), and therefore, by utilizing differential signal processing of adjacent lines, such capacitive load does not limit the operating gain range of the touch controller.

[0018] Sometimes, it may be desirable to have a sensor array, for example, a touchscreen or touchpad, in an arrangement having a non-rectangular shape (e.g., but not limited to, trapezoidal or elliptical, and regular or irregular shapes). In a non-rectangular arrangement of a sensor array, some rows (or columns) of the sensor array may have a different number of sensor nodes than other rows (or columns) of the sensor array, and the inventors of the present application understand that for certain types of capacitive loads (e.g., but not limited to, inter-connector capacitance or mutual capacitance), the effect on touch sensing measurements will differ based on the number of sensor nodes, and the use of differential signaling of adjacent lines will be limited in certain areas.

[0019] The inventors of the present disclosure appreciate that it would be advantageous to condition the measurement circuit or associated input signal to its capacitance-to-voltage converter so that the conditioned associated input signal corresponds (e.g., without limitation, in terms of magnitude or frequency) to the input signal expected if each row (or column) of the sensor array had the same number of sensor nodes (as in the case of a rectangular-shaped sensor array), in other words, to reduce at least some of the charge imbalance due to capacitance imbalance. Stated differently, the input signal is altered to more closely resemble the input signal associated with a balanced layout.

[0020] One or more embodiments generally relate to an apparatus (e.g., without limitation, a touch controller) that includes a connector, a capacitance-voltage converter, a signal balancing circuit, and an analog-to-digital converter. The connector may be operable to be coupled to receiver electrodes of a sensor array. The capacitance-voltage converter may be coupled to the connector and generate a voltage signal indicative of the associated mutual capacitance of the receiver electrodes. The signal balancing circuit may be coupled to an input path of the capacitance-voltage converter and may sum a balanced signal with an associated input signal to generate a balanced input signal, the balanced input signal being provided to the capacitance-voltage converter to generate a voltage signal, the balanced input signal being in phase or opposite phase to the associated input signal. The analog-to-digital converter may be coupled to the capacitance-voltage converter and generate a digital value representative of the generated voltage signal.

[0021] 1 is a schematic diagram illustrating an apparatus 100 according to one or more embodiments. The apparatus 100 may include a connector 102, a capacitance-to-voltage converter 104, an analog-to-digital converter 106, a signal balancing circuit 108, and an optional logic circuit 122.

[0022] The connector 102 may be operable to couple with an optional receiver electrode 120 of a sensor array (sensor array not shown). The receiver electrode 120 may have multiple associated sensor nodes, although for convenience a single sensor node is shown. The sensor nodes have an associated mutual capacitance C M (The relative mutual capacitance C of the receiver electrodes 120 MConnector 102 may be any suitable structure for providing electrical contact (e.g., with alignment structures of a sensor array, as non-limiting examples), such as, but not limited to, pins or pads.

[0023] A capacitance-to-voltage converter 104 is coupled to the connector 102 and is configured to calculate the associated mutual capacitance C of the receiver electrodes 120 based at least in part on the associated input signal 126. M generates a voltage signal 112 indicative of

[0024] In one or more embodiments, the capacitance-to-voltage converter 104 may calculate the associated mutual capacitance C according to any suitable technique. M The circuitry may include circuitry and logic for generating a voltage signal 112 indicative of the mutual capacitance. A non-limiting example of a suitable technique is the use of a relaxation oscillator that oscillates at a frequency indicative of the associated mutual capacitance. Another non-limiting example of a suitable technique is the use of a circuit that tracks the time to charge the capacitance of a sensor node to a predetermined voltage, or the amount the sensor node is charged to over a predetermined period of time—the time to charge or the amount to which it is charged is indicative of the mutual capacitance. Another non-limiting example of a suitable technique is the use of a capacitive voltage divider circuit, where if the sensor node and connector (such as, but not limited to, connector 102) are each charged to a predetermined voltage and then share charge, the resulting voltages on the associated capacitors are indicative of the change in capacitance at the sensor node. Another non-limiting example of a suitable technique is the use of a charge transfer circuit that stores charge on an integrating capacitor, where the voltage across the integrating capacitor is indicative of the mutual capacitance and is compared to a reference voltage or read by an analog-to-digital converter for comparison to a threshold. Another non-limiting example of a suitable technique is the use of sigma-delta modulation, where the voltage across an external capacitor is modulated around a reference voltage in charging and discharging operations, the duration of which is indicative of the mutual capacitance.

[0025] The signal balancing circuit 108 is coupled to the input path 118 of the capacitance-to-voltage converter 104 and sums a balancing signal 110 with an associated input signal 116 received via the connector 102 and a receiver electrode 120. The associated input signal 116 summed with the balancing signal 110 is utilized by the capacitance-to-voltage converter 104 to calculate the associated mutual capacitance C of the receiver electrode 120. M generates a voltage signal 112 indicative of

[0026] The amount and phase of the balancing signal 110 added to the associated input signal 116 may be proportional to the number of sensor nodes present along the receiver electrode 120. In one or more embodiments, the signal balancing circuit 108 may generate the balancing signal 110 at least in part in response to a setting 128 that represents the number of sensor nodes present at the receiver electrode. If there are more sensor nodes than the equivalent balanced layout (additional sensor nodes), the balancing signal 110 may be in anti-phase (i.e., subtractive / cancellative) with the associated input signal 116, and the magnitude of the balancing signal 110 may be proportional to the number of additional sensor nodes present—the predetermined value of the setting 128 preset in the balancing circuit 108 may reflect such phase offset and magnitude. If there are fewer sensor nodes than in the equivalent balanced layout (missing sensor nodes), the balanced signal 110 may be in phase (i.e., additive / constructive) with the associated input signal 116, and the magnitude of the balanced signal 110 may be proportional to the number of missing sensor nodes - the predetermined value of the setting 128 preset in the signal balancing circuit 108 may reflect such phase offset (in this case, no phase offset or generally in phase) and magnitude.

[0027] In one or more embodiments, the equivalent balanced layout or the number of its sensor nodes is known or predetermined and may be utilized to determine the number of additional or missing sensor nodes. As a non-limiting example, the value of setting 128 may be preset in a touch controller including signal balancing circuit 108 for a sensor array arrangement having a predetermined shape. As a non-limiting example, the value of setting 128 may be preset in a touch controller including signal balancing circuit 108 for a sensor array arrangement integrated with such touch controller. As a non-limiting example, the respective values ​​of multiple setting units 128 (“setting units 128”) may be preset in a touch controller including signal balancing circuit 108 for multiple sensor array arrangements, and the respective values ​​of setting unit 128 may be selectable (or alternatively selectable) for each sensor array arrangement of multiple sensor array arrangements optionally integrated with such touch controller, including device 100.

[0028] In one or more embodiments, the value of setting portion 128 may indicate a predetermined magnitude and phase that is expected to reduce at least some charge imbalance in input path 118 due to, for example, capacitance imbalance caused by a non-rectangular arrangement of the sensor array.

[0029] An analog-to-digital converter 106 is coupled to the capacitance-to-voltage converter 104 to generate a digital value 114 representing the magnitude of the voltage signal 112 , thereby indicating the associated mutual capacitance of the receiver electrodes 120 .

[0030] The mutual capacitance C of the receiver electrodes 120 M may vary, and thus the observed mutual capacitance C of the receiver electrodes 120 M may vary, and the mutual capacitance C of the receiver electrodes 120 M The digital value 114 representing the associated mutual capacitance C of the receiver electrodes 120 may vary. An optional logic circuit 122 is coupled to the analog-to-digital converter 106 and is responsive, at least in part, to the generated digital value 114. Mand generates an indication 124 thereof. As a non-limiting example, the logic circuit 122 may M The receiver electrode 120 may include or have access to a memory that stores a threshold value (e.g., but not limited to, a baseline value that corresponds to the absence of an object in the vicinity of the sensor array, including the receiver electrode 120), and logic (e.g., but not limited to, a comparator or threshold detector) that compares the digital value 114 to the threshold value.

[0031] In one or more embodiments, differential signal processing—for example, where a differential signal constructed from component signals of adjacent sensor electrodes (transmitters or receivers) is measured to determine a value indicative of mutual capacitance—is utilized in mutual touch sensing. As a non-limiting example, differential signaling may be utilized for mutual touch sensing with a touch display to reduce the effects of display noise or to support higher signal path gain.

[0032] When adjacent sensor electrodes have different numbers of sensor nodes, the effect of some capacitive loads on touch sensing measurements may differ accordingly. The undesirable aspects of such effects may increase when differential signal processing is utilized, for example, because sensor signals are not canceled and signal path gain is reduced.

[0033] One or more embodiments generally relate to summing a balanced signal to an associated input signal utilized to generate a differential signal, the summed balanced signal to compensate for different numbers of sensor nodes along various receiver electrodes of a sensor array, and more generally to improve differential signal processing.

[0034] 2 is a schematic diagram illustrating a portion 200 of a touch sensing device utilizing differential signal processing, according to another embodiment. Portion 200 includes an input path 202, an adjacent input path 216, and a charge injection circuit 230. Input path 202 includes a current amplifier 204 and a summing block 208. Adjacent input path 216 includes a current amplifier 218 and a summing block 222. Charge injection circuit 230 includes a voltage driver 232 and a charge compensation capacitor, denoted as "CC" in FIG. 2.

[0035] 2, input path 202 is coupled by connector 246 to a receiver electrode 250 associated with a missing sensor node (such missing sensor node will be referred to herein as a "missing sensor node 214" for convenience and is not intended to imply that a placeholder or inactive sensor node is required by this disclosure). Adjacent input path 216 is coupled by connector 244 to a receiver electrode 252 associated with sensor node 236. Sensor node 236 resides in a sensor array (not shown) that includes receiver electrode 252, which is also characterized herein as "not missing."

[0036] In the adjacent input path 216, a current amplifier 218 amplifies a related input signal 238 (associated with receiver electrode 252) received via a coupled connector 244 to generate a component input signal 220. The component input signal 220 and an adjacent component input signal 224 (e.g., originating from an adjacent sensor electrode not shown) are provided to positive and negative input terminals, respectively, of a summing block 222 to generate a differential related input signal 228. In the input path 202, a current amplifier 204 amplifies a related input signal 212 (associated with receiver electrode 250) received via a coupled connector 246 to generate a component input signal 206. The component input signal 206 and an adjacent component input signal 226 are provided to positive and negative input terminals, respectively, of a summing block 208 to generate a differential related input signal 210. In one or more embodiments, the differential related input signal 210 and the differential related input signal 228 can be utilized to detect mutual capacitance in a sensor array including receiver electrodes 252 and 252.

[0037] The depiction in FIG. 2 of locally generated component input signals (e.g., component input signal 220 and component input signal 206) provided to the positive input terminals of respective summation blocks 208, 222 and remotely generated component input signals (e.g., adjacent component input signal 224 and adjacent component input signal 226) provided to the negative input terminals of respective summation blocks 208, 222 is for convenience of explanation only and is in no way intended to limit the present disclosure, as other arrangements are specifically contemplated.

[0038] Charge injection circuit 230 is coupled to a node at the input of current amplifier 204 and sums charge transfer 240 with associated input signal 212 (which exhibits differences from an equivalent balanced layout due to missing sensor node 214) to generate balanced input signal 248. In charge injection circuit 230, voltage driver 232 generates and applies drive voltage 242 to compensation capacitor CC in response to event signal 234. A first plate of charge compensation capacitor CC is coupled to the output of voltage driver 232, and a second plate of charge compensation capacitor CC is coupled to the input of current amplifier 204 and to a node coupled to connector 246. Compensation capacitor CC injects charge (in phase or out of phase) into the input of current amplifier 204 in response to application of drive voltage 242 to the second plate of compensation capacitor CC, thereby summing charge transfer 240 with associated input signal 212. Charge transfer 240 thereby accounts for any charge differences associated with input signal 212 and input signal 238, respectively. As a non-limiting example, this difference may be affected, at least in part, by differences in capacitive coupling to connectors 244 and 246 .

[0039] In one or more embodiments, charge compensation capacitor CC is optionally programmable to tune to a fixed voltage output by voltage driver 232. The magnitude of the balanced signal generated via charge transfer 240 can be adjusted by changing the size (capacitance) of compensation capacitor CC, by changing the driver voltage swing of drive voltage 242, or by both changing the size of compensation capacitor CC and by changing the driver voltage swing of drive voltage 242.

[0040] 3 is a schematic diagram illustrating a portion 300 of a touch sensing device utilizing differential signal processing, according to another embodiment. Portion 300 includes an input path 302, an adjacent input path 316, and a charge injection circuit 330. Input path 302 includes a current amplifier 304 and a summing block 308. Adjacent input path 316 includes a current amplifier 318 and a summing block 322. Charge injection circuit 330 includes a voltage driver 332 and a compensation capacitor, labeled CC in FIG. 3.

[0041] In one or more embodiments, the number of sensor nodes 336 present on receiver electrode 352 is different from the number of sensor nodes 314 present on receiver electrode 350. In the particular non-limiting arrangement illustrated by Figure 3, input path 302 is coupled to receiver electrode 350 with a greater number of sensor nodes (sensor nodes 314) than the number of sensor nodes (sensor nodes 336) present on receiver electrodes 352 coupled to adjacent input paths 316. In particular non-limiting embodiments, the equivalent balanced layout corresponds to the number of sensor nodes present on receiver electrodes coupled to input paths 316.

[0042] Charge injection circuit 330 is coupled to a node at the input of current amplifier 304 and sums charge transfer 340 with associated input signal 312 to generate a balanced input signal 348, canceling the effect of additional ones of sensor nodes 314 on associated input signal 312 (compared to an equivalent balanced layout). More specifically, voltage driver 332 generates a drive voltage 342 that exhibits a polarity that is the inverse of (i.e., anti-phase with) the event signal 334. In one or more embodiments, the polarity of event signal 334 may be selected (selection not shown) to match the polarity exhibited by a transmitter signal driven at a transmitter electrode of sensor node 314, such that charge transfer 340 is anti-phase with associated input signal 312, and associated input signal 312 is substantially in phase with, and is generated at least partially in response to, such transmitter signal.

[0043] In one or more embodiments, the respective numbers of sensor nodes (e.g., without limitation, sensor nodes 336 and 314) may both be different from the number of sensor nodes in the equivalent balanced layout, and one or more charge injection circuits (e.g., without limitation, charge injection circuit 330) may induce charge transfer into input paths (e.g., without limitation, input paths 316 and 302) to balance associated input signals (e.g., without limitation, input signals 338 and 312 received via connectors 344 and 346, respectively). In such embodiments, the respective amounts of charge transfer induced in the input paths may be the same or different.

[0044] In adjacent input path 316, current amplifier 318 amplifies related input signal 338 to generate component input signal 320. Component input signal 320 and adjacent component input signal 324 are provided to the positive and negative input terminals, respectively, of summing block 322 to generate differential related input signal 328. In input path 302, current amplifier 304 amplifies balanced input signal 348 to generate component input signal 306, and component input signal 306 and adjacent component input signal 326 (including component input signal 320) are provided to the positive and negative terminals, respectively, of summing block 308 to generate differential input signal 310.

[0045] In single-ended implementations, it is desirable for the respective inter-connector capacitances between various adjacent connectors to be substantially matched. Differences in the number of sensor nodes along the receiver electrodes can result in different inter-connector capacitances.

[0046] 4 is a schematic diagram illustrating a portion 400 of a touch sensing device utilizing single-ended signal processing, according to another embodiment. Portion 400 includes an input path 402 coupled to a receiver connector 426, a charge injection circuit 412 coupled to a node between the input path 402 and the receiver connector 426, and a voltage driver 422 coupled to an adjacent transmitter connector 424 (i.e., the transmitter connector 424 is located adjacent to the receiver connector 426). The charge injection circuit 412 includes a voltage driver 414 and a compensation capacitor CC. The input path 402 includes an amplifier 404. The mutual capacitance of a sensor node 428 formed by the intersection of a receiver electrode 430 (coupled to the receiver connector 426) and a driver electrode 432 (coupled to the transmitter connector 424) is the mutual capacitance C M The inter-connector capacitance between the receiver connector 426 and the transmitter connector 424 is expressed as the inter-connector capacitance C P1 is expressed by

[0047] 4, input path 402 is an input path to a touch sensing system that utilizes single-ended signal processing, as contrasted with FIGS. 2 and 3, in which the touch sensing systems utilize differential signal processing. In contemplated operation, voltage driver 414 generates and applies voltage signal 420 to a first plate of compensation capacitor CC at least in part in response to an event 416 (e.g., but not limited to, generated by a clock source or event logic). A second plate of compensation capacitor CC is coupled to receiver connector 426, and a charge transfer 418 is summed with an associated input signal 408 in response to voltage signal 420 applied to charge compensation capacitor CC to generate a balanced input signal 410. Amplifier 404 amplifies balanced input signal 410 to generate input signal 406. In various embodiments, the summation of charge transfer 418 is achieved by a voltage across a connector capacitance C P1 and other inter-connector capacitances (or inter-connector capacitances in an equivalent balanced layout), thereby improving single-ended operation.

[0048] 5 is a diagram illustrating a system 500 for mutual touch sensing in a touch display, according to one or more embodiments. The system 500 may include a measurement circuit 502, a signal balancing circuit 504, and an optional display 512. An arrangement 514 of receiver and transmitter electrodes overlays the display 512. The various intersections of the receiver and transmitter electrodes in the arrangement 514 each form a sensor node. The sensor nodes 516 are connected to the T X a transmitter electrode coupled to a transmitter connector denoted as R X and a receiver electrode coupled to a receiver connector labeled . In various embodiments, the measurement logic 508 of the measurement circuit 502 may perform single-ended or differential signal processing for mutual touch sensing as described herein, and more specifically, the mutual capacitance C of each sensor node 516. M The signal balancing circuit 504 may measure the signal strength of one or more receiver electrodes R of the sensor node 516. X 1 and 2. The signal balance circuit 504 is coupled to the input path of measurement logic 508 of the receiver connector R to provide a balanced signal as discussed herein. The signal balance circuit 504 includes settings 510 that are each configurable or preset with values ​​indicative of the magnitude and phase of the balanced signal to be generated, and signal generation logic 506 that generates the balanced signal in response to the values ​​of the settings 510. The values ​​of each setting 510 are coupled to the input path of receiver connector R. X In various embodiments, each setting portion 510 and its preset value may be based at least in part on the respective number of sensor nodes 516 associated with the receiver electrodes coupled to each receiver connector R. X or a receiver electrode coupled thereto. In one or more embodiments, configuring the value of setting portion 510 may involve configuring a compensation capacitor, such as, but not limited to, compensation capacitor CC of FIGS. 3 and 4, to generate a desired balanced signal.

[0049] In particular, although not shown, the shape exhibited by arrangement 514 may be non-rectangular, such as, but not limited to, trapezoidal, tapered, polygonal, or elliptical. In particular, system 500 may be utilized for mutual touch sensing in a touch display in which arrangement 514 is rectangular, by configuring setting 510 with a value indicating no charge imbalance compensation, as a non-limiting example.

[0050] FIG. 6 is a flow diagram illustrating a process 600 according to one or more embodiments.

[0051] In operation 602, the process 600 receives a relevant input signal via a receiver electrode of the sensor array, the relevant input signal being indicative of the relevant mutual capacitance of the receiver electrodes.

[0052] At operation 604, process 600 sums a balance signal to the associated input signal to generate a balanced input signal at least in part responsive to the number of sensor nodes present at the receiver electrode. In one or more embodiments, a balance signal may be generated having a phase and magnitude that is at least in part responsive to the number of sensor nodes present at the receiver electrode or a setting (value) representative thereof. In one or more embodiments, the magnitude of the balance signal may be set in a charge compensation capacitor that is programmed to generate a charge amount in response to a fixed voltage generated by an associated driver (e.g., without limitation, charge compensation capacitor CC and voltage driver 232, 332, or 414 of FIG. 2, FIG. 3, or FIG. 4). As a non-limiting example, compensation capacitor CC may be a programmable capacitor array controlled by a digital value, which may be preset.

[0053] In optional operation 606, process 600 generates a balanced signal that is in phase with the associated input signal. Such an in-phase balanced signal is assimilated with the associated input signal to compensate for the missing sensor node for an equivalent balanced layout.

[0054] In optional operation 608, process 600 generates a balanced signal that is anti-phase with the associated input signal. Such anti-phase balanced signal is destructive to the associated input signal to compensate for the additional sensor node for an equivalent balanced layout.

[0055] In optional operation 610, process 600 provides charge transfer to or from an input path to add a balancing signal to the associated input signal. Charge transfer to an input path may be understood to be additive, and charge transfer from an input path may be understood to be destructive. When a sensor node is missing in a mutual touch sensing system, typically less charge is transferred from the transmitter electrode to the receiver electrode, and therefore balancing adds charge (in phase). When there is an extra node or extra mutual capacitive coupling (compared to a balanced layout), the balancing signal reduces charge (in antiphase).

[0056] In particular, operation 610 may be understood to provide charge transfer as a result of operations 606 or 608, i.e., by generating in-phase or anti-phase balanced signals applied to the input paths.

[0057] In operation 612, the process 600 generates a voltage signal indicative of the relative mutual capacitance of the receiver electrodes at least in part in response to the balanced input signal, which includes the relative input signal summed with the balanced signal.

[0058] In operation 614, the process 600 generates a digital value that represents the voltage signal.

[0059] In optional operation 616, process 600 determines a value representing the associated mutual capacitance of the receiver electrodes at least in part in response to the generated digital value representing the voltage signal.

[0060] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 7 illustrates a non-limiting example of an implementation of the functional elements disclosed herein. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0061] 7 is a block diagram of a circuit 700 that, in some embodiments, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. The circuit 700 includes one or more processors 702 (sometimes referred to herein as “processors 702”) operably coupled to one or more data storage devices (sometimes referred to herein as “storage devices 704”). The storage devices 704 include machine-executable code 706 stored thereon, and the processors 702 include logic circuitry 708. The machine-executable code 706 includes information describing functional elements that may be implemented (e.g., executed) by the logic circuitry 708. The logic circuitry 708 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 706. The circuitry 700, when executing the functional elements described by the machine-executable code 706, should be considered dedicated hardware configured to execute the functional elements disclosed herein. In some embodiments, processor 702 may be configured to execute the functional elements described by machine-executable code 706 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0062] When implemented by logic circuitry 708 of processor 702, machine-executable code 706 is configured to cause processor 702 to perform operations of embodiments disclosed herein. For example, machine-executable code 706 may be configured to cause processor 702 to perform at least a portion of, or all of, process 600 of FIG. 6. As another example, machine-executable code 706 may be configured to cause processor 702 to perform at least a portion of, or all of, the operations discussed with respect to device 100 of FIG. 1, portion 200 of FIG. 2, portion 300 of FIG. 3, or portion 400 of FIG. 5. As another example, machine-executable code 706 may be configured to cause processor 702 to perform at least a portion of, or all of the operations discussed with respect to system 500 of FIG. 5.

[0063] The processor 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer when the general-purpose computer is configured to execute functional elements corresponding to machine-executable code 706 (e.g., software code, firmware code, hardware descriptions) related to embodiments of the present disclosure. It should be noted that the general-purpose processor (sometimes referred to herein as a host processor or simply host) may be a microprocessor, but alternatively, the processor 702 may include any conventional processor, controller, microcontroller, or state machine. The processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0064] In some embodiments, memory 704 includes volatile data storage (e.g., without limitation, random-access memory (RAM)), non-volatile data storage (e.g., without limitation, flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM)). In some embodiments, processor 702 and memory 704 may be implemented in a single device (e.g., without limitation, a semiconductor device product, system on chip (SOC)). In some embodiments, processor 702 and memory 704 may be implemented in separate devices.

[0065] In some embodiments, machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by storage 704, accessed directly by processor 702, and executed by processor 702 using at least logic circuitry 708. Also, as a non-limiting example, the computer-readable instructions may be stored in storage 704, transferred for execution to a memory device (not shown), and executed by processor 702 using at least logic circuitry 708. Thus, in some embodiments, logic circuitry 708 includes electrically configurable logic circuitry 708.

[0066] In some embodiments, machine-executable code 706 may describe hardware (e.g., circuits) to be implemented in logic circuitry 708 to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, a hardware description language (HDL) such as the IEEE Standard Hardware Description Language (HDL) may be used. As non-limiting examples, VERILOG™, SYSTEMVERILOG™, or very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0067] The HDL description may be converted into a description at any of a number of other levels of abstraction, as desired. As a non-limiting example, the high-level description may be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by hardware logic circuits (e.g., without limitation, gates, flip-flops, registers) of logic circuit 708 may be described in RTL and then converted by a synthesis tool into a GL description, which may be converted by a place-and-route tool into a layout-level description that corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Thus, in some embodiments, machine-executable code 706 may include HDL, RTL, a GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0068] In embodiments in which machine-executable code 706 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 704) may be configured to implement the hardware description described by machine-executable code 706. As a non-limiting example, processor 702 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 708 may be electronically controlled to implement circuitry in logic circuitry 708 that corresponds to the hardware description. Also, as a non-limiting example, logic circuitry 708 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage device 704) according to the hardware description in machine-executable code 706.

[0069] Regardless of whether machine-executable code 706 includes computer-readable instructions or a hardware description, logic circuitry 708, when implementing the functional elements of machine-executable code 706, is adapted to perform the functional elements described by machine-executable code 706. Note that the hardware description may not directly describe the functional elements, but rather the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0070] 8A, 8B, and 8C illustrate non-limiting examples of non-rectangular arrangements of sensor nodes according to one or more embodiments. FIG. 8A illustrates an arrangement 800a having an elliptical shape 806. A first receiver electrode 802 includes several sensor nodes, and a second receiver electrode 804 includes several sensor nodes that are fewer than the number of sensor nodes of the first receiver electrode 802. Examples of missing sensor nodes 808 and 810 are depicted to represent several sensor nodes that would exist in an equivalent balanced layout of sensor nodes having a rectangular shape 812. Similarly, FIG. 8B illustrates an arrangement 800b having a trapezoidal shape 818. A first receiver electrode 814 includes several sensor nodes, and a second receiver electrode 816 includes several sensor nodes that are fewer than the number of sensor nodes of the first receiver electrode 814. Examples of missing sensor nodes 822 and 820 are depicted to represent several sensor nodes that would exist in an equivalent balanced layout of sensor nodes having a rectangular shape 824. 8C shows an arrangement 800c exhibiting a trapezoidal shape 830. A first receiver electrode 826 includes several sensor nodes, and a second receiver electrode 828 includes several sensor nodes that are fewer than the number of sensor nodes of the first receiver electrode 826. In the particular non-limiting example illustrated by FIG. 8C, the equivalent balanced layout exhibits a rectangular shape 836 having an equivalent area that does not include sensor nodes 832 and 834, which are examples of the "additional sensor nodes" discussed above.

[0071] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation configured to perform the actions of a module or component and / or software object or software routine that may be stored on or executed by general-purpose hardware (e.g., without limitation, computer-readable media, processing devices) of a computing system. In some embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) executing on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored and / or executed on general-purpose hardware), specific hardware implementations, or a combination of software and specific hardware implementations, are also possible and contemplated.

[0072] As used in this disclosure, the term "combination," when referring to multiple elements, can include a combination of all elements or any of various different subcombinations of elements. For example, the phrase "A, B, C, D, or combinations thereof" can refer to A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as any one of A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0073] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," and the term "including," without limitation, should be interpreted as "including, but not limited to." As used herein, the term "each" means in part or in whole. As used herein, "any and all" means in whole.

[0074] Additionally, if a specific number of introduced claim recitations is intended, such intention will be explicitly recited in the claim; in the absence of such recitation, no such intention exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as introducing a claim recitation with the indefinite article "a" or "an" limiting any particular claim containing such introduced claim recitation to embodiments containing only one such recitation (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same applies to the use of express articles used to introduce claim recitations, even if the same claim also includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an."

[0075] Additionally, even when a particular number of introduced claim recitations is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "including but not limited to, at least one of A, B, and C" or "including but not limited to, one or more of A, B, and C" are used, such structures are generally intended to include, but are not limited to, A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together.

[0076] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0077] Further non-limiting examples of the present disclosure are as follows: (open)

[0078] Example 1: An apparatus comprising: a connector coupled to receiver electrodes of a sensor array; a capacitance-voltage converter coupled to the connector and generating a voltage signal indicative of the associated mutual capacitance of the receiver electrodes; a signal balancing circuit coupled to an input path of the capacitance-voltage converter and adding the balancing signal to the associated input signal of the receiver electrode to generate a balanced input signal, the signal balancing circuit generating the balancing signal at least in part in response to a setting representative of the number of sensor nodes present at the receiver electrode; and an analog-to-digital converter coupled to the capacitance-voltage converter and generating a digital value representative of the generated voltage signal.

[0079] The apparatus of claim 1, wherein the balanced signal is in phase with the associated input signal.

[0080] Example 3: The apparatus of examples 1 and 2, wherein the balanced signal is in antiphase with the associated input signal.

[0081] Example 4: The apparatus of Examples 1-3, wherein the signal balancing circuit comprises a charge injection circuit coupled to provide charge transfer in the input path of the capacitance-voltage converter and generating a balanced signal for summing with an associated input signal.

[0082] Example 5: The apparatus of any one of Examples 1 to 4, wherein the charge injection circuit comprises a capacitor and a voltage driver coupled to inject charge for charge transfer in the input path of the capacitance-to-voltage converter.

[0083] Example 6: The apparatus of Examples 1-5, wherein the voltage driver is coupled to apply a voltage to a first plate of the capacitor, and wherein a second plate of the capacitor is coupled to inject charge for charge transfer in the input path of the capacitance-to-voltage converter at least partially in response to the voltage applied to the first plate of the capacitor.

[0084] Example 7: The apparatus of examples 1-6, wherein the charge of the charge transfer is in phase with the associated input signal.

[0085] Example 8: The apparatus of Examples 1-7, wherein the charge of the charge transfer is in antiphase with the associated input signal.

[0086] Example 9: The apparatus of Examples 1-8, wherein the input path comprises a current amplifier coupled to amplify the balanced input signal and an adder block for generating a differential signal at least partially in response to a component input signal and an adjacent component input signal, the component input signal including the amplified balanced input signal, and wherein the capacitance-to-voltage converter generates a voltage signal at least partially in response to the differential signal.

[0087] Example 10: A method comprising: receiving relevant input signals via receiver electrodes of a sensor array, the relevant input signals indicative of the relevant mutual capacitance of the receiver electrodes; summing a balanced signal to the relevant input signals to generate a balanced input signal, at least in part in response to a number of sensor nodes present at the receiver electrodes; generating a voltage signal indicative of the relevant mutual capacitance of the receiver electrodes, at least in part in response to the balanced input signal, the balanced signal including the relevant input signals summed with the balanced signal; and generating a digital value representing the voltage signal.

[0088] Example 11: The method of example 10, including providing a charge transfer to or from the associated input signal to add a balanced signal to the associated input signal.

[0089] Example 12: The method of examples 10 and 11, comprising determining a value representing the associated mutual capacitance of the receiver electrodes at least in part in response to the generated digital value representing the voltage signal.

[0090] Example 13: The method of any of Examples 10-12, including generating a balanced signal that is in phase with an associated input signal.

[0091] Example 14: The method of any one of Examples 10 to 13, including generating a balanced signal that is in antiphase with an associated input signal.

[0092] Example 15: A system comprising: a display; an arrangement of receiver electrodes and transmitter electrodes arranged as capacitive sensor nodes of a sensor array; a measurement circuit coupled to the receiver electrodes and transmitter electrodes and determining the mutual capacitance of sensor nodes formed at intersections of the receiver electrodes and transmitter electrodes; and at least one signal balancing circuit coupled to an input path of the measurement circuit and adding a balancing signal to an associated input signal, the added balancing signal being at least partially responsive to the number of sensor nodes in the receiver electrodes.

[0093] Example 16: The system of example 15, wherein the shape assumed by the arrangement is a non-rectangular shape.

[0094] Example 17: The system of Example 16, wherein the non-rectangular shape is one of a trapezoid, a tapered shape, a polygon, or an ellipse.

[0095] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not so limited. Rather, numerous additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below, along with their legal equivalents. In addition, features of one embodiment can be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. 1. An apparatus comprising: a connector coupled to a receiver electrode of the sensor array; a capacitance-to-voltage converter coupled to the connector for generating a voltage signal indicative of the relative mutual capacitance of the receiver electrodes; a signal balancing circuit coupled to an input path of the capacitance-to-voltage converter for summing a balancing signal with an associated input signal of the receiver electrode to generate a balanced input signal, the signal balancing circuit generating the balancing signal at least in part in response to a setting representative of a number of sensor nodes present at the receiver electrode; an analog-to-digital converter coupled to the capacitance-to-voltage converter to generate a digital value representing the generated voltage signal.

2. 2. The apparatus of claim 1, wherein the balanced signal is in phase with the associated input signal.

3. 2. The apparatus of claim 1, wherein the balanced signal is in antiphase with the associated input signal.

4. The signal balancing circuit 2. The apparatus of claim 1, further comprising: a charge injection circuit coupled to provide charge transfer in the input path of the capacitance-to-voltage converter to generate the balanced signal for summing with the associated input signal.

5. The charge injection circuit 5. The apparatus of claim 4, comprising: a capacitor and a voltage driver coupled to inject charge for the charge transfer in the input path of the capacitance-to-voltage converter.

6. the voltage driver is coupled to apply a voltage to a first plate of the capacitor; 6. The apparatus of claim 5, wherein a second plate of the capacitor is coupled to inject charge of the charge transfer in the input path of the capacitance-to-voltage converter at least in part in response to the voltage applied to the first plate of the capacitor.

7. 5. The apparatus of claim 4, wherein the charge of the charge transfer is in phase with the associated input signal.

8. 5. The apparatus of claim 4, wherein the charge of the charge transfer is in antiphase with the associated input signal.

9. The input path is a current amplifier coupled to amplify the balanced input signal; an adder block for generating a differential signal at least partially responsive to a component input signal and an adjacent component input signal, said component input signal comprising said amplified balanced input signal; The apparatus of claim 1 , wherein the capacitance-to-voltage converter generates the voltage signal at least partially in response to the differential signal.

10. 1. A method comprising: receiving a relevant input signal via receiver electrodes of a sensor array, the relevant input signal being indicative of a relevant mutual capacitance of the receiver electrodes; adding a balanced signal to the associated input signal to generate a balanced input signal, at least in part responsive to a number of sensor nodes present at the receiver electrode; generating a voltage signal indicative of the associated mutual capacitance of the receiver electrodes at least in part in response to a balanced input signal comprising the associated input signal summed with the balanced signal; generating a digital value representing the voltage signal.

11. 11. The method of claim 10, comprising providing a charge transfer to or from the associated input signal to add the balanced signal to the associated input signal.

12. The method of claim 10, comprising determining a value representative of the associated mutual capacitance of the receiver electrodes at least in part in response to the generated digital value representative of the voltage signal.

13. 11. The method of claim 10, including generating the balanced signal in phase with the associated input signal.

14. 11. The method of claim 10, including generating the balanced signal in antiphase with the associated input signal.

15. 1. A system comprising: The display and an arrangement of receiver electrodes and transmitter electrodes arranged as capacitive sensor nodes of a sensor array; a measurement circuit coupled to the receiver electrode and the transmitter electrode for determining the mutual capacitance of a sensor node formed at the intersection of the receiver electrode and the transmitter electrode; at least one signal balancing circuit coupled to an input path of the measurement circuit to sum a balanced signal to an associated input signal, the summed balanced signal being at least partially responsive to a number of sensor nodes in the receiver electrode.

16. The system of claim 15 , wherein the shape assumed by the arrangement is a non-rectangular shape.

17. The system of claim 16 , wherein the non-rectangular shape is one of a trapezoid, a tapered, a polygon, or an ellipse.

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