Distribution circuit

Abstract

Provided is a distribution circuit having satisfactory pass characteristics and isolation characteristics over a wide bandwidth.　In this distribution circuit, Wilkinson type distribution circuits comprising coils, capacitors and resistors are connected in a two-stage cascade between an input terminal and at least three output terminals, and capacitors are connected in parallel with resistors inserted between the output terminals of the latter-stage Wilkinson type distribution circuit.

Description

[Technical Field]

[0001] This technology is applied to a dividing circuit or combining circuit that divides or combines high-frequency signals. minutes Regarding distribution circuits. [Background technology]

[0002] Tuners compatible with 4K / 8K satellite broadcasts are becoming more common in digital television broadcasting. In order to maintain the same sensitivity as a single tuner, multi-tuners that can simultaneously receive multiple channels generally amplify the input signal using an LNA (Low Noise Amplifier), then distribute it using a distribution circuit before inputting the signal into a tuner with an integrated circuit (IC). The tuner outputs a video signal.

[0003] Tuner ICs that are compatible with advanced BS (Broadcasting Satellite) and can receive 4K / 8K satellite broadcasts and can receive both the conventional satellite broadcast band (1032MHz-2053MHz) and the newly added band (2224MHz-3224MHz) with a single terminal are being put into practical use. When supplying signals from the tuner input terminal to two or more tuner ICs for multi-tuner applications, for example, three tuner ICs, a distribution circuit is required to distribute the signal from the input terminal to the three tuner ICs. In this case, the distribution circuit needs to cover a wide band (1032MHz-3224MHz).

[0004] Wilkinson-type divider circuits have been known as divider circuits for some time. For example, Patent Document 1 describes a Wilkinson-type divider circuit configured with a lumped constant circuit. This divider circuit divides an input signal to three output terminals, thereby preventing differences in divided power, frequency characteristics, and phase characteristics. Patent Document 2 describes a divider circuit that ensures reflection characteristics over a wide band by cascading multiple stages of Wilkinson-type divider circuits configured with lumped constant circuits. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2-170625 [Patent Document 2] Japanese Patent Publication No. 2020-136806 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technology described in Patent Document 1 has the problem that it is not possible to achieve isolation characteristics of the output port over a wide band (1032 MHz - 3224 MHz), especially on the low-frequency side. Furthermore, with a configuration in which two-stage divider circuits are cascaded, as in Patent Document 2, it is not possible to achieve the isolation characteristics of the output port required on the low-frequency side, just like Patent Document 1. Furthermore, while it is thought that the isolation characteristics could be improved by increasing the number of stages, the increase in the number of components would increase costs and the component mounting area on the board would also increase.

[0007] Therefore, the objective of this technology is to achieve both broadband pass characteristics and isolation characteristics, and to achieve low cost with a reduced number of components. As much To provide a distribution circuit. [Means for solving the problem]

[0008] This technology uses two cascaded Wilkinson type distribution circuits, each consisting of a coil, a capacitor, and a resistor, connected between an input terminal and at least three output terminals. In the Wilkinson type dividing circuit at the rear stage, a capacitor is connected in parallel with the resistor inserted between the output terminals. R, A resistor is connected in series with one of the multiple resistors inserted between the signal systems corresponding to the multiple output terminals in the Wilkinson type distribution circuit at the previous stage. It is a distribution circuit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1A is a block diagram showing the configuration of a conventional single tuner, and FIG. 1B is a block diagram showing the configuration of a conventional triple tuner. [Figure 2] FIG. 2 is a block diagram showing the configuration of a triple tuner for receiving signals by dividing the band. [Figure 3] FIG. 3 is a block diagram showing the configuration of a triple tuner when receiving without dividing the band. [Figure 4] FIG. 4 is a connection diagram of a conventional distribution circuit. [Figure 5] FIG. 5 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 6] FIG. 6 is a connection diagram of a conventional distribution circuit. [Figure 7] FIG. 7 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 8] FIG. 8 is a connection diagram of a distribution circuit in which the values ​​of the elements in the configuration of FIG. 6 are changed. [Figure 9] FIG. 9 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 10] FIG. 10 is a connection diagram of a configuration in which conventional distribution circuits are connected in cascade. [Figure 11] FIG. 11 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 12] FIG. 12 is a connection diagram of the first embodiment of the present technology. [Figure 13]FIG. 13 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 14] FIG. 14 is a plan view of a substrate on which the distribution circuit of FIG. 12 is mounted on one side. [Figure 15] FIG. 15 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 16] FIG. 16 is a connection diagram of a modified example of an embodiment of the present technology. [Figure 17] FIG. 17 is a plan view of a substrate on which the distribution circuit of FIG. 16 is mounted on one side. [Figure 18] FIG. 18 is a graph showing the simulation results of the distribution circuit of FIG. [Figure 19] FIG. 19 is a graph showing the measurement results of the distribution circuit of FIG. [Figure 20] FIG. 20 is a plan view of one surface of a substrate on both sides of which the distribution circuit of FIG. 16 is mounted. [Figure 21] FIG. 21 is a plan view of the other surface of the substrate on both sides of which the distribution circuits of FIG. 16 are mounted. [Figure 22] FIG. 22 is a connection diagram of a four-way distribution circuit to which the present technology is applied. [Figure 23] FIG. 23 is a connection diagram of a two-way distribution circuit to which the present technology is applied. [Figure 24] FIG. 24 is a connection diagram for explaining the configuration of a two-way distribution circuit using the configuration of a three-way distribution circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present technology will be described with reference to the drawings. Note that the embodiments described below are preferred specific examples of the present technology, and the content of the present technology is not limited to these embodiments. Furthermore, in the following description, in order to prevent the illustrations from becoming complicated, reference symbols may be assigned to only some of the components, or some of the components may be shown in a simplified form. Furthermore, the following description will be given to a case in which the present technology is applied to a distribution circuit.

[0011] To facilitate understanding of one embodiment, a conventional distribution circuit will be described. Tuner ICs compatible with 4K / 8K satellite broadcasting are becoming popular in digital television broadcasting. In the case of a single tuner, as shown in FIG. 1A, a signal from an antenna is input to tuner IC 102 via input terminal 101, such as an F connector or an IEC (International Electrotechnical Commission) connector. In the case of a multi-tuner capable of simultaneously receiving multiple channels, in order to maintain sensitivity performance equivalent to that of a single tuner, a signal input via input terminal 101, such as an F connector or an IEC connector, is generally amplified by LNA 103 as shown in FIG. 1B, and then distributed to tuner ICs 102a, 102b, and 102c using distribution circuit 104. The overall configuration may be a tuner module using a mechanical shield or a substrate, or an on-board configuration using a substrate.

[0012] The tuner ICs 102, 102a, 102b, and 102c are identical in configuration and include a mixer, a variable gain amplifier, and a filter for selecting a specific channel, and output an IF signal. The IF signal is supplied to a demodulation module (not shown). A tuner having a configuration called an IQ detector or a Zero-IF tuner may be used as the tuner ICs 102, 102a, 102b, and 102c. In this case, an I-axis output and a Q-axis output are output.

[0013] In advanced BS tuner ICs compatible with conventional 4K8K satellite broadcasting, there are limitations on the frequency characteristics of the LNA and tuner IC, so as shown in Figure 2, the conventional satellite broadcasting band (1032MHz-2053MHz) and the newly added band (2224MHz-3224MHz) are divided into two bands by splitter 105, and the signals of each band are supplied to distribution circuits 104H and 104L via LNAs 103H and LNAs 103L, and the signals are input to two terminals for each band of tuner ICs 102a, 102b, and 102c by distribution circuits 104H and 104L.

[0014] Recently, LNA 113 and tuner ICs 112a, 112b, and 112c have been developed that can handle these frequency bands in a single band, eliminating the need for a splitter and providing a single distribution circuit 114, as shown in FIG. 3. The IC also has a single signal input terminal. This distribution circuit 114 needs to be a wideband distribution circuit (1032 MHz-3224 MHz) that can be integrated into a single system. This technology provides a distribution circuit that can be used as this wideband distribution circuit 114.

[0015] The Wilkinson-type divider circuit having the configuration of a lumped constant circuit described in Patent Document 1 has the configuration shown in Figure 4. Simulation results of this divider circuit are shown in Figure 5. An impedance Z (e.g., 50 Ω or 75 Ω) is provided as a termination resistor at the input terminal T1 (first signal terminal). An input capacitor C1 is connected between the input terminal T1 and ground.

[0016] A low-pass filter consisting of a coil L9 and a capacitor C11 is inserted between the input terminal T1 and the output terminal T2 (second terminal). A low-pass filter consisting of a coil L8 and a capacitor C10 is inserted between the input terminal T1 and the output terminal T3 (third terminal). A low-pass filter consisting of a coil L3 and a capacitor C9 is inserted between the input terminal T1 and the output terminal T4 (fourth terminal). The output terminals T2, T3, and T4 are each terminated by an impedance Z (e.g., 50 Ω). The output terminals T2, T3, and T4 are commonly connected via resistors R10, R9, and R6.

[0017] In the Wilkinson splitter circuit described above, the signals split into three signal paths do not return to the branch point on the input side, so the impedance at the branch point is maintained. To configure a wideband splitter circuit (1032MHz-3224MHz), the values ​​of each element are selected, for example, as follows:

[0018] Z=50[Ω], C1=0.2[pF], L3,L8,L9=4.7[nH], C9,C10,C11=0.2[pF], R6,R9,R10=220[Ω]

[0019] The simulation was performed in 0.01 GHz steps over a frequency range starting from 0.01 GHz to 3.5 GHz. The simulation results were expressed using S-parameters. Among the S-parameters, the S-parameters S21, S31, and S41, which represent the pass characteristics from input terminal T1 to output terminals T2, T3, and T4, and the S-parameters S23, S24, and S34, which represent the isolation characteristics between the output terminals, are important for evaluating the characteristics of the distribution circuit. Here, lower values ​​for isolation characteristics are better, while higher values ​​for pass characteristics are better. If the isolation characteristics are poor, when tuner ICs in a multi-tuner IC are receiving simultaneously, they may cause interference with other tuner ICs, resulting in reception problems. Furthermore, poor pass characteristics can cause sensitivity degradation.

[0020] FIG. 5 shows S-parameter S21 (pass characteristics from input terminal T1 to output terminal T2) and S-parameter S24 (isolation characteristics between output terminals T2 and T4). In the configuration of FIG. 4, since the values ​​of corresponding circuit elements included in the three signal paths are equal, S-parameters S31 and S41 are the same as S-parameter S21, and S-parameters S23 and S34 are the same as S-parameter S24. In the simulation results described below, when only S-parameter S21 and S-parameter S24 are shown, it means that the other S-parameters are the same. The simulation results of FIG. 5 show that the pass characteristics are good, but the isolation characteristics in the low frequency range are insufficient. For example, the isolation characteristics (target value) of 15 dB at 1 GHz are not achieved.

[0021] Figure 6 shows a circuit configuration in which the connections of resistors R6, R9, and R10 in the circuit configuration in Figure 4 are modified using a star-delta conversion. Figure 7 shows the simulation results for the circuit in Figure 6. The values ​​of each element are the same as those in Figure 4. The simulation results are almost identical to those in Figure 5, indicating that the isolation characteristics in the low frequency range are insufficient.

[0022] One way to improve isolation characteristics is to lower the cutoff frequency of a low-pass filter type divider circuit. Figure 8 shows the configuration of a divider circuit that employs this method. The connections are the same as those in the divider circuit in Figure 6, but the values ​​of each element are as follows:

[0023] Z=50[Ω], C1=0.2[pF], L3,L8,L9=6.8[nH], C9,C10,C11=0.2[pF], R6,R9,R10=220[Ω]

[0024] The value of the coils L3, L8, and L9 in the configurations of Figures 4 and 6 (4.7 nH) has been changed to 6.8 nH. The simulation results in Figure 9 show that the isolation characteristics have been improved, but are still insufficient, and that the pass characteristics in the high frequency range have deteriorated slightly. In other words, there is a trade-off between the isolation characteristics and the pass characteristics, and the desired wideband distribution circuit cannot be constructed with the circuit configuration of Figure 8.

[0025] To further improve the characteristics, a configuration in which the Wilkinson distribution circuit shown in Figure 6 is cascaded in two stages, as shown in Figure 10. The second-stage Wilkinson distribution circuit has the same circuit configuration as the first-stage. A low-pass filter consisting of a coil L9 and a capacitor C11 and a low-pass filter consisting of a coil L6 and a capacitor C16 are cascaded between the input terminal T1 and the output terminal T2 (second terminal). A low-pass filter consisting of a coil L8 and a capacitor C10 and a low-pass filter consisting of a coil L7 and a capacitor C15 are cascaded between the input terminal T1 and the output terminal T3 (third terminal). A low-pass filter consisting of a coil L3 and a capacitor C9 and a low-pass filter consisting of a coil L5 and a capacitor C14 are cascaded between the input terminal T1 and the output terminal T4 (fourth terminal).

[0026] In the first-stage Wilkinson divider circuit, the output of a low-pass filter consisting of coil L9 and capacitor C11 is connected to the output of a low-pass filter consisting of coil L8 and capacitor C10 via resistor R9. The output of the low-pass filter consisting of coil L9 and capacitor C11 is connected to the output of a low-pass filter consisting of coil L3 and capacitor C9 via resistor R10. The output of the low-pass filter consisting of coil L8 and capacitor C10 is connected to the output of a low-pass filter consisting of coil L3 and capacitor C9 via resistor R6. Furthermore, resistors R7 and R8 are inserted between output terminal T2 and output terminals T3 and T4, respectively, and resistor R12 is inserted between output terminal T3 and output terminal T4. These resistors R8, R7, and R12 function as matching resistors, thereby improving isolation characteristics.

[0027] An example of the values ​​of each element in the configuration of FIG. 10 is shown below. Z=50[Ω], C1=0.2[pF], L3,L8,L9=4.7[nH], C9,C10,C11=0.2[pF], R6,R9,R10=220[Ω] L5, L7, L6 = 3.9 [nH], C14,C15,C16=0.2[pF], R12,R7,R8=330[Ω]

[0028] The values ​​of each element are not completely identical between the first-stage Wilkinson divider circuit and the second-stage Wilkinson divider circuit, but are adjusted accordingly. Figure 11 shows the simulation results for the divider circuit configuration in Figure 10. Although the isolation characteristics have been significantly improved, the target value for the low-frequency isolation characteristics (15 dB at 1 GHz) has not been achieved.

[0029] This technology proposes a division circuit that solves the problem of insufficient isolation characteristics on the low-frequency side described above. Figure 12 shows the configuration of an embodiment in which this technology is applied to a division circuit that divides an input signal into three.

[0030] An impedance Z (for example, 50 Ω) is connected as a termination resistor to the input terminal (first terminal) T1, the output terminal (second terminal) T2, the output terminal (third terminal) T3, and the output terminal T4 (fourth terminal). An input capacitor C1 is connected between the input terminal T1 and ground. The input signal from the input terminal T1 is split into three signal systems corresponding to the output terminals T2, T3, and T4, respectively.

[0031] A low-pass filter consisting of a coil L9 and a capacitor C11 and a coil L6 are cascade-connected between the input terminal T1 and the output terminal T2. A low-pass filter consisting of a coil L8 and a capacitor C10 and a coil L7 are cascade-connected between the input terminal T1 and the output terminal T3. A low-pass filter consisting of a coil L3 and a capacitor C9 and a coil L5 are cascade-connected between the input terminal T1 and the output terminal T4.

[0032] A capacitor C15 and a resistor R7 are connected in parallel between the connection point of the coil L6 and the output terminal T2 and the connection point of the coil L7 and the output terminal T3. A capacitor C14 and a resistor R12 are connected in parallel between the connection point of the coil L7 and the output terminal T3 and the connection point of the coil L5 and the output terminal T4. A capacitor C16 and a resistor R8 are connected in parallel between the connection point of the coil L5 and the output terminal T4 and the connection point of the coil L6 and the output terminal T2.

[0033] The first stage Wilkinson divider circuit is made up of coils L9, L8, L3, capacitors C11, C10, C9, and resistors R10, R9, and R6. The second stage Wilkinson divider circuit is made up of coils L6, L7, L5, capacitors C16, C15, and C14, and resistors R8, R7, and R12.

[0034] An example of the values ​​of each element in FIG. 12 is shown below. Z=50[Ω], C1=0.2[pF], L3,L8,L9=4.7[nH], C9,C10,C11=0.2[pF], R6,R9,R10=220[Ω] L5, L7, L6 = 3.9 [nH], C14,C15,C16=0.2[pF], R12,R7,R8=330[Ω]

[0035] In the circuit configuration shown in Figure 12, capacitors C15, C14, and C16 are connected in parallel to isolation resistors R7, R12, and R8, which are inserted between output terminals T2 and T3, between output terminals T3 and T4, and between output terminals T4 and T2, respectively. These capacitors (0.2 pF) and the coils L6, L7, and L5 (3.9 nH) connected in the preceding stage form isolation poles, thereby improving the isolation characteristics in the low frequency range. Furthermore, the isolation characteristics can be improved by shifting the values ​​of the elements in the first and second stages.

[0036] Figure 13 shows the simulation results for the divider circuit with the configuration shown in Figure 12. The simulation results show that the target value for the isolation characteristics on the low frequency side (15 dB at 1 GHz) is slightly not achieved, but as will be described later, the actual measured values ​​show that this target is achieved.

[0037] Figure 14 shows an example of a board on which the circuit shown in Figure 12 is mounted. In this example, elements are mounted on one side of the board (referred to as "side A"), except for the signal line connecting one end of resistor R10 to the junction between coils L3 and L5. Single-sided mounting can reduce manufacturing costs compared to double-sided mounting. However, in the circuit configuration of Figure 12, the signal line connecting one end of resistor R10 to the junction between coils L3 and L5 crosses other signal lines, making it difficult to route it on side A of the board. Instead, it is routed on the other side (referred to as "side B"), as shown by the dashed line in Figure 14. Because this wiring is relatively long, it can be significant for high-frequency signals. In other words, the wiring acts as a stub for the signal line connecting resistors R10, R9, and R6. In the circuit diagram, the wiring portion L between R10 and R6 in Figure 12 corresponds to the stub. In addition, in Figure 14, the hatched circles with a black dot in the center indicate through-holes for signal wiring, while the hatched circles without a black dot in the center indicate through-holes connected to GND on other layers of the board. Wiring portion L is formed between through-holes Ha and Hb. For example, Hc is a through-hole connected to GND. The board layer structure may be a double-sided board, a four-layer board, or another layer structure.

[0038] Figure 15 shows the simulation results for the board with a stub (Figure 14). As shown in Figure 14, there is resistance only on the output terminal T2 side, and the simulation results show that the pass characteristics at frequencies higher than 2 GHz are significantly degraded (particularly the pass characteristics S41 for output terminal T4). This is because there is no resistance on the output terminal T4 side, and if a stub is formed on side B of the board, the out-of-phase signal that has passed through that path returns to output terminal T4 and cancels out the desired signal, resulting in a significant degradation of the pass characteristics at high frequencies for output terminal T4.

[0039] To solve this problem, as shown in Figure 16, the connection point between coils L9 and L6 (the output of the low-pass filter consisting of coil L9 and capacitor C11) is connected to the connection point between coils L3 and L5 (the output of the low-pass filter consisting of coil L3 and capacitor C9) via resistors R10 and R13. An example of the board implementation in this case is shown in Figure 17. By adding resistor R13, the effects of the stub can be suppressed, as can be seen from the simulation results shown in Figure 18. In other words, it is possible to prevent attenuation in the high-frequency range of the pass characteristic S41 for output terminal T4. Furthermore, the characteristics evaluated (measured) on an actual prototype board are shown in Figure 19. We were able to obtain characteristics that roughly matched the simulation results, achieving the target isolation characteristic of 15 dB.

[0040] An example of the values ​​of each element in FIG. 16 is shown below. Z=50[Ω], C1=0.2[pF], L3,L8,L9=4.7[nH], C9,C10,C11=0.2[pF], R6,R9,=220[Ω] R10, R13 = 560 [Ω] L5, L7, L6 = 3.9 [nH], C14,C15,C16=0.2[pF], R12,R7,R8=330[Ω]

[0041] In this technology, the distribution circuit may be mounted on both sides (side A and side B) of the board. FIGS. 20 and 21 show examples of the circuit shown in FIG. 16 mounted on both sides of the board. FIG. 20 shows the pattern on side A, and FIG. 21 shows the pattern on side B. The patterns on sides A and B are connected via through holes. In the case of double-sided mounting, when isolation resistors R10, R9, R6, and R13 are inserted between the output terminals, degradation of the pass characteristics can be prevented by arranging them near the respective signal lines (wiring patterns). In this case, the layer structure of the board may be a double-sided board, a four-layer board, or another layer structure.

[0042] In the above description, an input signal is divided into three outputs, but the present technology is not limited to three divisions and may be divided into other numbers. For example, Fig. 22 shows a configuration in which an input signal is divided into four output terminals T2, T3, T4, and T5. A first-stage Wilkinson division circuit (coil L10, capacitor C18, and resistor R14) is added to the configuration of Fig. 16 above, and a second-stage Wilkinson division circuit consisting of coil L11, capacitor C17, and resistor R15 is also added.

[0043] An example of the values ​​of each element in FIG. 22 is shown below. Z=50[Ω], C1=0.2[pF], L3,L8,L9,L10=4.7[nH], C9,C10,C11,C18=0.2[pF], R9,R6,R14=220[Ω] R10, R13 = 560 [Ω] L5, L7, L6, L11 = 3.9 [nH], C17,C14,C15,C16,=0.2[pF], R15,R12,R7,R8=330 [Ω]

[0044] Figure 23 shows an example of the configuration of a two-way divider circuit. Circuits related to input terminal T1 and output terminals T2 and T3 are provided. Furthermore, as shown in Figure 24, the configuration of a three-way divider circuit is laid out on a board. Here, NM (No mount) indicates that no elements are mounted. A two-way divider circuit can be realized by not mounting any elements. A single-system configuration without distribution can also be realized. Therefore, by simply changing the elements or constants mounted on the same board, various configurations can be realized, allowing for board standardization and cost reduction.

[0045] An example of the values ​​of each element in FIG. 23 is shown below. Z=50[Ω], C1=0.2[pF], L8,L9=4.7[nH], C10, C11 = 0.2 pF, R9 = 220 Ω L7, L6 = 3.9 [nH], C15 = 0.2 pF, R7 = 330 Ω

[0046] As can be seen from the description of the above-mentioned embodiments, the present technology can realize a division circuit that achieves both pass characteristics and isolation characteristics over a wide band (1032 MHz to 3224 MHz). Furthermore, the circuit of the present technology can be mounted on a single-sided board. Furthermore, the present technology can configure a division circuit with a desired number of divisions, such as 2-division, 3-division, or 4-division, providing a highly versatile configuration.

[0047] Although the embodiments of the present technology have been specifically described above, the present technology is not limited to the above-described embodiments, and various modifications based on the technical concept of the present technology are possible. For example, the present technology is not limited to the band (1032 MHz to 3224 MHz), and can be applied to other bands by changing the values ​​of the elements. Furthermore, the present technology is not limited to broadcasting, and can be used in the field of communications. Also, a synthesis circuit may be configured by switching the input and output, such that the input terminal becomes the output terminal and the output terminal becomes the input terminal.

[0048] The configurations, methods, steps, shapes, materials, and values ​​described in the above-described embodiments are merely examples, and different configurations, methods, steps, shapes, materials, and values ​​may be used as needed. The above-described embodiments and variations can be combined as appropriate.

[0049] The present technology can also adopt the following configurations. (1) A signal processing circuit in which a second terminal and a third terminal are connected to a first terminal via two coils, and a resistor and a capacitor are connected in parallel between the second terminal and the third terminal. (2) 1. The signal processing circuit according to claim 1, wherein a signal is input to the first terminal and a signal is output from the second terminal and the third terminal. (3) The signal processing circuit according to (1), wherein a signal is input to the second terminal and the third terminal, and a signal is output from the first terminal. (4) Two Wilkinson type dividing circuits each including a coil, a capacitor, and a resistor are connected in cascade between the first terminal, the second terminal, and the third terminal; a signal processing circuit in which a capacitor is connected in parallel to a resistor inserted between the second terminal and the third terminal in one of the Wilkinson type distribution circuits; (5) The signal processing circuit according to (4), wherein a signal is input to the first terminal and a signal is output from the second terminal and the third terminal. (6) The signal processing circuit according to (4), wherein a signal is input to the second terminal and the third terminal, and a signal is output from the first terminal. (7) Between the input terminal and at least three output terminals, two Wilkinson type distribution circuits each consisting of a coil, a capacitor, and a resistor are cascade-connected, A dividing circuit in which a capacitor is connected in parallel with a resistor inserted between the output terminals in the Wilkinson dividing circuit at the subsequent stage. (8) The division circuit according to (7), wherein a resistor is connected in series with one of a plurality of resistors inserted between the signal systems corresponding to the plurality of output terminals in the Wilkinson type division circuit in the preceding stage. (9) The dividing circuit according to (8), wherein the resistor is connected in series with a resistor inserted between signal systems at distant positions in a pattern mounted on one side of a board. (10) (7) A distribution circuit that obtains less output by not mounting elements included in one or more signal systems on a substrate on which a pattern is formed so that the distribution circuit of 7 can be mounted. [Explanation of symbols]

[0050] T1···· input terminal, T2, T3, T4··· output terminal, C1··· input capacitor, 101: Input terminal for signals from an antenna; 102, 102a, 102b, 102c: Tuner IC; 104, 114: Distribution circuit

Claims

1. Between the input terminal and at least three output terminals, two Wilkinson type distribution circuits each composed of a coil, a capacitor, and a resistor are cascaded; a capacitor is connected in parallel with the resistor inserted between the output terminals in the Wilkinson type dividing circuit at the subsequent stage; A dividing circuit in which a resistor is connected in series with one of a plurality of resistors inserted between signal systems corresponding to a plurality of the output terminals in the Wilkinson dividing circuit in the preceding stage.

2. 2. The dividing circuit according to claim 1, wherein the resistor is connected in series with a resistor inserted between signal systems at distant positions in a pattern mounted on one side of a board.

3. A dividing circuit that obtains less output by not mounting elements included in one or more signal systems on a substrate on which a pattern is formed so that the dividing circuit of claim 1 can be mounted.

Images