quantum devices

Abstract

To provide a quantum device capable of avoiding deterioration in signal characteristic by avoiding decrease in yield and connection precision as quantum bits increase.SOLUTION: A quantum device 1 comprises a first quantum chip 10, a second quantum chip 20, and one or a plurality of interposers 30 mounted with the first quantum chip 10 and second quantum chip 20. The first quantum chip 10 and second quantum chip 20 have surfaces where at least some of regions face each other while mounted on a common or different interposers 30, and are electrically connected between connection terminals which are arranged in at least some of regions on the mutually facing surfaces of the first quantum chip 10 and second quantum chip 20, and face each other.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to quantum devices. [Background technology]

[0002] Quantum computing devices manipulate data using quantum bits, which are quantum mechanical phenomena. Here, quantum mechanical phenomena include superposition of multiple states (quantum variables simultaneously taking on multiple different states) and entanglement (a state in which multiple quantum variables are related regardless of space or time). Quantum chips are equipped with quantum bit circuits that write data to quantum bits and perform data readout and calculations.

[0003] As the number of quantum bits in quantum computer devices increases, studies are underway to move from two-dimensional to three-dimensional arrangements. For example, Patent Document 1 discloses a configuration consisting of a quantum chip equipped with a quantum bit circuit and an interposer that receives it. The interposer is a substrate with through vias that connect wiring (circuits, electrodes) on the front and back surfaces of the substrate.

[0004] In quantum chips and interposers, an increase in the number of quantum bits is inevitable in order to address more complex problems. Generally, an increase in the number of quantum bits requires an increase in the size (area) of the quantum chip or interposer. However, as the area of ​​the quantum chip or interposer increases, defects in the wiring pattern or insulating layer (mainly open defects) or pattern residues due to particles or resist residues (mainly short defects) may occur during manufacturing. As a result, it becomes difficult to secure a good product.

[0005] Furthermore, as the size of quantum chips and interposers increases, the alignment accuracy of the chip's periphery decreases during device manufacturing. The decrease in alignment accuracy of the chip's periphery can occur due to misalignment in the X and Y directions, as well as misalignment in the θ direction (θ misalignment). Furthermore, as the size of quantum chips and interposers increases and the number of connection terminals (connection area) increases, a high mounting load (contact load) is required, resulting in greater height accuracy and positional variation. This results in a decrease in manufacturing yield.

[0006] To address the issue of reduced yield due to the increase in size of a single quantum chip or interposer, it is known that an appropriate size for the quantum chip or interposer (for example, a size that can be configured as a function and has little performance variation) can be selected, and multiple quantum chips or interposers of that size can be connected.

[0007] As a superconducting qubit device having multiple quantum chips and an interposer, for example, Non-Patent Document 1 discloses a configuration in which multiple quantum bit chips are mounted on a carrier chip (interposer) and the quantum bit chips are connected to the carrier chip by capacitive coupling. That is, Non-Patent Document 1 discloses a configuration in which multiple quantum bit chips 501 and 502 mounted on one carrier chip (interposer) 503 are connected by capacitive coupling, as schematically illustrated in FIG. 9A. Quantum bit chips 501 and 502 are flip-chip mounted, circuit side down, on a carrier chip (interposer) 503 using indium (In) bumps 507 and 508. A terminal (electrode) 504 of the quantum bit of the quantum bit chip 501 is capacitively coupled to a terminal (electrode) 506 disposed on the opposing surface of the carrier chip (interposer) 503, and a terminal (electrode) 505 of the quantum bit of the quantum bit chip 502 is capacitively coupled to a terminal (electrode) 506 disposed on the opposing surface of the carrier chip (interposer) 503. The multiple capacitive coupling terminals 504 (505) of the quantum bit chip 501 (502) are arranged in a row along the edge of the chip. Note that Figure 9(A) is based on Figure 1(a) of Non-Patent Document 1, and the reference numbers are newly assigned in this specification.

[0008] Furthermore, Patent Document 2 discloses a configuration in which multiple quantum chips are arranged side by side on an interposer and connected to the interposer using metal bumps, as illustrated schematically in Figure 9B. In Figure 9B, 601 and 602 are first and second quantum bit substrates, 603 is a base substrate (interposer), 604 and 609 are superconducting wiring, 605 and 610 are superconducting quantum bits, and 606 and 611 are superconducting solder bumps. Figure 9B is based on Figure 2 of Patent Document 2, and reference numbers have been changed.

[0009] Furthermore, Patent Document 3 discloses a configuration in which, as illustrated schematically in Figure 9C, first and second chips 701 and 702 are mounted on an interposer 703 with their first surfaces (circuit surfaces) facing downwards, electrodes 704 on the first surface of the first chip 701 are connected to electrodes 705 on the first surface of the second chip 702 by wiring 706 (lateral wiring: AirBridge). Figure 9C is based on Figure 2 of Patent Document 3, and reference numbers have been changed. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] US Patent Application Publication No. 2020 / 0058702 [Patent Document 2] Patent No. 6757948 [Patent Document 3] U.S. Patent No. 10,380,496 [Non-patent literature]

[0011] [Non-Patent Document 1] Alysson Gold et al., "Entanglement Across Separate Silicon Dies in a Modular Superconducting Qubit Device", Quantum Physics, September 28, 2021 [Non-patent document 2] M. Veldhorst et al., "An addressable quantum dot qubit with fault-tolerant control fidelity", nature nanotechnology 12 October 2014 Summary of the Invention [Problem to be solved by the invention]

[0012] When connecting terminals between chips, whether it is a wireless connection (capacitive coupling, inductive coupling, etc.), a bump connection, or lateral wiring, there are problems such as energy loss due to impedance mismatch at the connection point and the tendency for unnecessary frequency components to be superimposed on the signal (noise), so it is necessary to keep the distance between terminals to the minimum necessary.

[0013] In Non-Patent Document 1, one connection path between two quantum chips has two wireless connection points. That is, in Figure 9A, the connection path between first and second quantum bit chips 501 and 502 has two wireless connections: a capacitive coupling between terminal (electrode) 504 of first quantum bit chip 501 and terminal (electrode) 506 of interposer 503, and a capacitive coupling between terminal (electrode) 506 of interposer 503 and terminal (electrode) 505 of second quantum bit chip 502. In addition to the effect of power loss in each wireless connection (capacitive coupling), there is also the problem that a decrease in the accuracy of alignment of opposing terminals (electrodes) can worsen power loss in wireless connections.

[0014] In Patent Document 2, for example, in Fig. 9B, the direction of the current changes significantly at the connection point between superconducting solder bumps 606 and 611. This causes a problem of degradation of signal characteristics due to the influence of reflection and the like.

[0015] 9C, the lateral wiring (air bridge) 706 has a problem that the direction of current changes significantly at the connection point, causing signal reflection and preventing proper protection of the signal line by the ground, resulting in degradation of signal characteristics.

[0016] As mentioned above, a further increase in the number of quantum bits in a quantum computer device will result in an increase in the area of ​​the quantum chip and interposer, which will result in a decrease in the yield and connection accuracy of quantum device products. On the other hand, if multiple quantum chips and interposers are used in sizes that match the yield and connection accuracy, a problem will arise in which the signal characteristics of the connections between the quantum chips will deteriorate.

[0017] Therefore, an object of the present disclosure is to provide a quantum device that solves the above problems. [Means for solving the problem]

[0018] According to one aspect of the present disclosure, there is provided a quantum device comprising a first quantum chip, a second quantum chip, and one or more interposers on which the first quantum chip and the second quantum chip are mounted, wherein the first quantum chip and the second quantum chip have surfaces in at least a partial area facing each other when mounted on a common or different interposer, and electrical connection is made between connection terminals that are arranged in at least a partial area of ​​the facing surfaces of the first quantum chip and the second quantum chip and that face each other. [Effects of the Invention]

[0019] According to the present disclosure, it is possible to avoid a decrease in yield and connection accuracy and to avoid degradation of signal characteristics when the number of quantum bits in a quantum computer device increases. [Brief explanation of the drawings]

[0020] [Figure 1A] FIG. 1 is a perspective view schematically illustrating an overview of a quantum device according to an embodiment. [Figure 1B] FIG. 1 is a plan view schematically illustrating a quantum device according to an embodiment. [Figure 1C] FIG. 1 is a diagram schematically illustrating a cross-sectional side view of a quantum device according to an embodiment. [Figure 1D] FIG. 1 is a diagram schematically illustrating a cross-sectional side view of a quantum device according to an embodiment. [Figure 1E] FIG. 1 is a diagram schematically illustrating a cross-sectional side view of a quantum device according to an embodiment. [Figure 2A] FIG. 10 is a perspective view schematically illustrating an overview of a modified example of the quantum device according to the embodiment. [Figure 2B] FIG. 10 is a plan view schematically illustrating a modified example of the quantum device according to the embodiment. [Figure 2C]FIG. 10 is a diagram schematically illustrating a cross-sectional side view of a quantum device according to a modified example of an embodiment. [Figure 3A] FIG. 10 is a perspective view schematically illustrating an overview of a quantum device according to another embodiment. [Figure 3B] FIG. 10 is a plan view schematically illustrating a quantum device according to another embodiment. [Figure 3C] FIG. 10 is a diagram schematically illustrating a cross-sectional side view of a quantum device according to another embodiment. [Figure 4A] FIG. 1 is a perspective view schematically illustrating an overview of an example in which an embodiment is applied to a silicon quantum bit chip. [Figure 4B] FIG. 10 is a perspective view schematically illustrating an overview of an example in which another embodiment is applied to a silicon quantum bit chip. [Figure 5A] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 5B] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 5C] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 5D] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6A] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6B] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6C] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6D] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6E] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 6F] 10A to 10C are diagrams illustrating a manufacturing process of another embodiment. [Figure 7A] FIG. 10 is a perspective view schematically illustrating an overview of another example of a quantum chip. [Figure 7B] FIG. 10 is a perspective view schematically illustrating an overview of another example of a quantum chip according to another embodiment. [Figure 7C]FIG. 10 is a plan view schematically showing another example of a quantum chip according to another embodiment. [Figure 7D] FIG. 10 is a diagram schematically illustrating a cross-sectional side view of another example of a quantum chip according to another embodiment. [Figure 7E] FIG. 10 is a plan view schematically showing another example of a quantum chip according to another embodiment. [Figure 7F] FIG. 10 is a plan view schematically showing another example of a quantum chip according to another embodiment. [Figure 7G] FIG. 10 is a plan view schematically showing another example of a quantum chip according to another embodiment. [Figure 8] FIG. 10 is a perspective view schematically illustrating an overview of a quantum device according to another embodiment. [Figure 9A] FIG. 1 is a diagram illustrating a related art. [Figure 9B] FIG. 10 is a diagram illustrating another related art. [Figure 9C] FIG. 10 is a diagram illustrating yet another related art. DETAILED DESCRIPTION OF THE INVENTION

[0021] According to one of several preferred aspects of the present disclosure, a quantum device (1) constituting a quantum computer apparatus includes multiple quantum chips, including at least a first quantum chip (10) and a second quantum chip (20), and at least one interposer (30) on which the first quantum chip (10) and the second quantum chip (20) are mounted. Alternatively, the quantum device may be configured to include interposers (30, 40) on which the first quantum chip (10) and the second quantum chip (20) are mounted, respectively. One interposer (40) may be configured to mount one or more other interposers (30).

[0022] The first quantum chip (10) and the second quantum chip (20) have surfaces in at least a portion thereof facing each other when mounted on a common or different interposer, and are arranged in the portion of the facing surfaces of the first quantum chip and the second quantum chip, and electrical connection is made between the facing connection terminals (11, 21, or 15, 25).

[0023] The first quantum chip (10) has one or more connection terminals (11) in a partial area of ​​the same surface as the first surface (circuit surface) on which at least one quantum bit circuit (12) is arranged. The second quantum chip (20) has one or more connection terminals (21) in a partial area of ​​the same surface as the first surface (circuit surface) on which at least one quantum bit circuit (22) is arranged.

[0024] The first quantum chip (10) is mounted on a first interposer (30) with at least one side of the first quantum chip (10) extending beyond the edge of the interposer, and the first surface (circuit surface) of the first quantum chip (10) faces the first surface (circuit surface) of the second quantum chip (20) in an area (103) extending beyond the edge of the first interposer (30), and one or more connection terminals (11) provided in the area (103) of the first surface of the first quantum chip (10) extending beyond the edge of the first interposer (30) are connected to one or more connection terminals (21) located opposite the first surface of the second quantum chip (20).

[0025] The first quantum chip (10) is mounted on the first interposer (30) with its first surface (circuit surface) on which at least one quantum bit circuit is arranged inverted (facing downwards). The second quantum chip (20) is mounted on the second interposer (40) with its second surface, opposite to the first surface (circuit surface) on which at least one quantum bit circuit is arranged, facing downwards. The connection terminals (11) on the first surface of the first quantum chip (10) and the connection terminals (21) on the first surface (circuit surface) of the second quantum chip (20) connected to the connection terminals (11) may be located at the same position on a plane and may be configured to face each other vertically.

[0026] The first quantum chip (10) may be configured to have a connection terminal (15) on at least a partial area of ​​at least one side surface, and the second quantum chip (20) may be configured to have a connection terminal (25) on at least a partial area of ​​at least one side surface. When the first and second quantum chips (10, 20) are mounted on the first interposer (30), the connection terminals (15, 25) on the respective side surfaces of the first and second quantum chips (10, 20) are at the same height.

[0027] The opposing connection terminals (11, 12 or 15, 25) of the first and second quantum chips (10, 20) may be connected by a conductive member. The opposing connection terminals (11, 12 or 15, 25) of the first and second quantum chips (10, 20) may be solder-bonded or ultrasonically bonded in abutting contact state.

[0028] The connection terminals (11, 12 or 15, 25) of the first and second quantum chips (10, 20) may be arranged facing each other at a distance, and the connection terminals (11, 12 or 15, 25) of the first and second quantum chips (10, 20) may be configured to be capacitively or inductively coupled to each other.

[0029] At least one connection terminal of the first and second quantum chips (10, 20) may be connected to the opposing connection terminal of the interposer (30) by a conductive material or may be electrically connected by capacitive or inductive coupling. The interposer (30) may be configured to include a quantum bit circuit.

[0030] In at least one of the first and second quantum chips (10, 20), the connection terminal (at least one of 15, 25) on the side surface may be configured to consist of superconducting metal formed on the side wall of a trench opened in the surface of a region that will become a scribe line in a direction along the side surface, in a wafer on which at least one of the first and second quantum chips (10, 20) is formed.In at least one of the first and second quantum chips (10, 20), the connection terminal (at least one of 15, 25) on the side surface may be configured to include a portion of superconducting metal (metal via) embedded in a via hole (blind via or through hole) opened in the surface of a region that will become a scribe line in a direction along the side surface, in a wafer on which at least one of the first and second quantum chips (10, 20) is formed.

[0031] Hereinafter, several embodiments will be described with reference to the drawings. FIG. 1A is a diagram illustrating one embodiment (embodiment 1). Referring to FIG. 1A, a quantum device 1 includes a first quantum chip 10, a second quantum chip 20, an interposer 30, and a package substrate 40. The package substrate 40 may also be referred to as an interposer. In this case, for example, the interposer 30 may also be referred to as a first interposer, and the package substrate 40 may also be referred to as a second interposer.

[0032] The first quantum chip 10 has a first surface (circuit surface) on which the quantum bit circuit 12 is arranged and a second surface (back surface) on the opposite side. The first quantum chip 10 is mounted with the first surface facing downward and aligned with the terminals of the opposing interposer 30 (face-down mounting). That is, wiring (not shown) on the first surface of the first quantum chip 10 is electrically connected to wiring (pads) (not shown) of the interposer 30 via protruding terminals (convex electrodes, bumps) 31 arranged on the first surface (front surface) of the interposer 30.

[0033] When the first quantum chip 10 is mounted on the interposer 30 , at least one side of the rectangular shape of the first quantum chip 10 extends beyond the edge of the interposer 30 .

[0034] The second quantum chip 20 has a first surface (circuit surface) on which the quantum bit circuit 22 is arranged and a second surface (back surface) that is the opposite surface, and is mounted by aligning terminals (not shown) on the second surface with terminals (not shown) on the opposing package substrate 40 (face-up mounting). The wiring on the first surface (circuit surface) of the second quantum chip 20 is connected to the terminals on the second surface via through vias or the like (not shown). Of course, the first quantum chip 10 and the second quantum chip 20 may each be configured to have multiple quantum bit circuits on their first surfaces (circuit surfaces).

[0035] Although not particularly limited, the quantum bit circuits 12 and 22 include a resonator, an oscillator, a control circuit, a readout circuit, etc. The resonator includes a SQUID (Superconducting Quantum Interference Device) in which superconducting materials are connected in a ring by Josephson junctions. The control circuit controls the magnetic field applied to the resonator. The readout circuit reads out the resonant state (quantum two-level system) from the quantum bit circuit (resonator).

[0036] The interposer 30 has a first surface (front surface) that connects to the first surface (circuit surface) of the first quantum chip 10, and an opposite second surface (back surface), and the wiring on the first surface (front surface) is connected to the wiring on the second surface (back surface) via a through via or the like not shown, and is connected to the opposing surface (first surface) of the package substrate 40 by a bump or the like.

[0037] The first surface of the first quantum chip 10 protruding from the end (edge) of the interposer 30 faces the first surface of the second quantum chip 20, and is electrically connected by connection terminals 11, 21 provided on each. Of course, a quantum bit circuit may be provided on the interposer 30.

[0038] The wiring on the first surface (circuit surface) of the second quantum chip 20 is connected to the wiring (terminals) on the second surface via through vias or the like (not shown), and is connected to the package substrate 40 via bumps or the like provided on the opposing surface (first surface) of the package substrate 40. The wiring on the first surface of the package substrate 40 is connected to the wiring on the second surface via through vias or the like (not shown).

[0039] The connection between the first quantum chip 10 and the second quantum chip 20 via the connection terminals 11, 21 may be a wireless connection such as capacitive coupling or inductive coupling, or may be a solder connection of a metal (conductive member) such as a convex electrode or bump.

[0040] 1B is a schematic plan view of the first quantum chip 10 as viewed from above. The first quantum chip 10 has a rectangular shape in which an area 103 on at least one side thereof extends beyond the end of the interposer 30.

[0041] Fig. 1C is a diagram illustrating a schematic side cross section taken along line AA in Fig. 1B. Wiring that constitutes quantum bit circuit 12 is provided at predetermined locations in wiring layer 102 on the first surface (circuit surface) of substrate 101 of first quantum chip 10, and is joined to electrodes (bumps) 31 provided on wiring layer 302 of interposer 30 with solder (superconducting solder). Note that wiring layer 102 on the first surface (circuit surface) of substrate 101 of first quantum chip 10 may be wiring consisting of multiple layers, as exemplified in Fig. 4A described below.

[0042] The interposer 30 has wiring layers 302, 303 on a first surface of a substrate 301 and on a second surface thereof opposite thereto, and the wiring (signal wiring / ground wiring (pattern)) of the wiring layer 302 on the first surface is connected to the corresponding wiring (signal wiring / ground wiring (pattern)) of the wiring layer 303 on the second surface by a through via 304. The wiring of the wiring layer 303 on the second surface of the interposer 30 is connected to the corresponding wiring of the wiring layer 402 on the first surface of the substrate 401 of the package substrate 40 by a bump 405 or the like. The wiring layer 403 on the second surface of the substrate 401 of the package substrate 40 may have a wiring pattern or may be a ground plane. That is, the package substrate 40 may be configured such that the wiring layer 403 on the second surface is connected to another substrate (Printed Circuit Board: PCB) (not shown) via bumps or the like, or the wiring layer 403 on the second surface of the package substrate 40 may be used as a ground plane and placed on a base (not shown) made of a conductive material, for example.

[0043] In the example of FIG. 1C, the connection terminal 11 provided on the wiring layer 102 of the first surface (circuit surface) of the first quantum chip 10 and the connection terminal 21 provided on the wiring layer 202 of the first surface (circuit surface) of the second quantum chip 20 are located at the same position on the x-y two-dimensional coordinate plane, but are separated by a predetermined distance in the z-axis direction, and signal transmission and / or reception is performed by, for example, capacitive coupling or inductive coupling. In FIG. 1C, the connection terminals 11 and 21 are schematically illustrated as convex electrodes formed on the wiring of the wiring layers 102 and 202, respectively. However, the connection terminals 11 and 21 are not limited to convex electrodes and may be wiring pads. A through via 203 is provided penetrating the first surface (circuit surface: front surface) and the second surface (back surface) of the second quantum chip 20. The wiring of the wiring layer 202 on the first surface of the second quantum chip 20 is electrically connected to the wiring of the wiring layer 402 on the first surface of the substrate 401 of the package substrate 40 via the through via 203, the via pad 204 (the via pad of the through via 203) on the second surface of the second quantum chip 20, and the bump 405.

[0044] Although not particularly limited, the thickness of the interposer 30 and the second quantum chip 20 is preferably the same or approximately the same.

[0045] The substrates 101, 201, 301, and 401 of the first quantum chip 10, the second quantum chip 20, the interposer 30, and the package substrate 40 are preferably made of materials with the same thermal expansion coefficient. Although not particularly limited, when these substrates are made of silicon (Si), high-resistivity silicon of 10 kΩcm (kiloohm centimeter) or more is preferable, and high-resistivity silicon of 20 kΩcm or more is more preferable. These substrates may be made of other electronic materials other than silicon, such as sapphire or compound semiconductor materials (Group IV (GeSn, etc.), Group III-V (GaAs, GaN, GaP, GaSb, InAs, InP, InS, etc.), Group II-VI (ZnS, ZnSe)). While single crystal is preferable, polycrystalline or amorphous materials are also acceptable.

[0046] The quantum bit circuits 12 and 22, which are superconducting circuits, are made of a superconducting material such as niobium (Nb). Note that the superconducting material is not limited to niobium (Nb), but may also be niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, or an alloy containing at least one of these.

[0047] In the second quantum chip 20, the interposer 30, and the package substrate 40, the wiring on the opposing surfaces respectively has through vias 203, 304, and 404 (through silicon vias: TSVs when the substrates 201, 301, and 401 are made of Si).

[0048] The connections between the first quantum chip 10 and the interposer 30, between the interposer 30 and the package substrate 40, and between the second quantum chip 20 and the package substrate 40 may be wireless (e.g., capacitive coupling, inductive coupling, etc.) or metallic (e.g., convex electrodes, bumps, wire bonding, etc.). However, implementation examples using solder bumps instead of metal bumps are not excluded. In FIG. 1C , several through-hole vias connecting the signal wiring / ground wiring (patterns) on the first surface of the substrate to the signal wiring / ground wiring (patterns) on the second surface are shown as a schematic example for the purpose of explaining the configuration. The number and arrangement of the vias are not intended to limit the embodiments. Similarly, the number and arrangement of the bumps are not intended to limit the embodiments. Furthermore, in the schematic cross-sectional side view of FIG. 1C , the cross-sections of the substrates 101, 201, 301, and 401 are represented as wiring layers instead of individual wirings. This also applies to the other schematic cross-sectional side views referred to below.

[0049] In the example of Figure 1D, the second surface (back surface) of the second quantum chip 20 is adhesively fixed to the first surface of the package substrate 40 with resin (die bond material) 23, and the wiring pads 24 on the first surface (circuit surface) of the second quantum chip 20 are bonded to the wiring pads 407 of the package substrate 40 with superconducting metal wires 25. Note that for simplicity, Figure 1D shows only one wire bonding location as a schematic example, but it goes without saying that there may be multiple bonding locations using metal wires. It also goes without saying that instead of die bond mounting, the second surface (back surface) of the second quantum chip 20 may be mounted to the first surface of the package substrate 40 by bump connection. The wiring pads 24 on the first surface (circuit surface) of the second quantum chip 20 may be connected to pads on the wiring layer of an interposer at approximately the same height as the second quantum chip 20 (for example, pads (not shown) on the first surface of an interposer 30 mounted on a package substrate 40 or an interposer (not shown) mounted at the same height) and wiring layer 302) by superconducting metal wires (bonding wires).

[0050] 1E, the wiring of the quantum bit circuit 22 on the first surface of the second quantum chip 20 is connected to a connection terminal 26 on the second surface via a through via 203. This connection terminal 26 is disposed opposite a connection terminal 41 on the first surface of the package substrate 40 at a predetermined distance, and connection terminals 26 and 41 are capacitively or inductively coupled. Similar to connection terminals 26 and 41, signals may be transmitted wirelessly (capacitively or inductively coupled) between predetermined connection terminals of the first quantum chip 10 and interposer 30, and between predetermined connection terminals of the interposer 30 and package substrate 40, instead of by wired connection such as bump connection.

[0051] As a modification of the embodiment, as shown in FIG. 2A, a lid-shaped chip 50 for protection from external magnetic fields (magnetic shielding) may be mounted on the second quantum chip 20. FIG. 2B is a schematic plan view of FIG. 2A viewed from above. FIG. 2C is a schematic view of a side cross section taken along line AA in FIG. 2B. The chip 50 has a ground plane made of a superconducting material, such as copper (Cu) or Au, for magnetic shielding on the surface facing the first surface (circuit surface) of the second quantum chip 20. The superconducting material is selected from niobium (Nb), niobium nitride, aluminum (Al), indium (In), lead (Pb), tin (Sn), rhenium (Re), palladium (Pd), titanium (Ti), tantalum (Ta), tantalum nitride, and alloys containing at least one of these. It should be noted that the size (area) of the chip 50 may be larger or smaller than that of the second quantum chip 20 as long as the circuit of the second quantum chip 20 is protected.

[0052] In this way, on the circuit surface on which the quantum bits of the first quantum chip 10 and the second quantum chip 20 are provided, regions 103 are provided where parts of the regions 103 face each other and overlap vertically, and the regions 103 are connected wirelessly / metallicly (wired) via the respective connection terminals 11, 21 provided in the vertically opposing regions 103.

[0053] According to this embodiment, by using a stacked configuration using multiple quantum chips, namely, first and second quantum chips 10 and 20, an interposer 30, and a package substrate 40, it is possible to minimize and control characteristic variations due to yield reduction and pseudo errors (thinning or swelling of conductors).

[0054] Fig. 3A is a diagram schematically illustrating another embodiment (embodiment 2). Fig. 3B is a schematic plan view of Fig. 3A viewed from above. Fig. 3C is a diagram schematically illustrating a side cross section (side end surface) taken along line A-A in Fig. 3B.

[0055] According to this embodiment, the terminals of the first and second quantum chips 10 and 20 are connected via connection terminals (side terminals) 15 and 25 provided on the side surfaces of the first and second quantum chips 10 and 20. This makes it possible to improve power loss and superimposed noise.

[0056] 3B and 3C, the side terminals 15, 25 provided on the side surfaces of the first and second quantum chips 10, 20 have the same y-axis coordinate and the same (approximately the same) z-axis coordinate in the xy plane. The connection between the side terminals 15, 25 may be a wireless connection such as capacitive coupling or inductive coupling in which the side terminals 15, 25 are spaced apart from each other, or the metals (superconducting metals) such as the convex electrodes and bumps that make up the side terminals 15, 25 may be joined by soldering. That is, the tips of the convex electrodes and bumps of the side terminals 15, 25 may be abutted and joined by soldering, thermocompression bonding, or the like.

[0057] The first and second quantum chips 10 and 20 are mounted on the interposer 30 with their first surfaces (circuit surfaces) having quantum bit circuits facing downward (flip-chip mounting). That is, each wire in the wiring layers 102 and 202 on the first surfaces (circuit surfaces) of the first and second quantum chips 10 and 20 is solder-bonded at predetermined locations to bumps 31 provided on wiring pads of the wiring layer 302 on the first surface of the interposer 30. The wiring (signal wiring / ground wiring (pattern)) in the wiring layer 302 on the first surface of the interposer 30 is connected to the corresponding wiring (signal wiring / ground wiring (pattern)) in the wiring layer 303 on the second surface (the side opposite the first surface) by through vias 304. The wiring layer 303 on the second surface of the interposer 30 may be configured with bumps for connection to another interposer or a PCB (Printed Circuit Board), not shown. The wiring layer 303 may also be configured as a ground plane.

[0058] The first and second quantum chips 10 and 20 are mounted on a common interposer 30, but there may be one or more interposers 30. When there are multiple interposers 30, a package substrate on which multiple interposers 30 are mounted may be provided, as in the above-described embodiment.

[0059] The first and second quantum chips 10, 20 may be connected to the interposer 30 (package substrate) wirelessly (capacitive coupling, inductive coupling, etc.) or by metal (convex electrodes, bumps, wire bonding, etc.).

[0060] The first and second quantum chips 10 and 20 only need to be able to face each other with the side terminals 15 and 25 having the same (almost the same) height direction (z-axis direction) when mounted face down on the interposer 30. The thicknesses of the first and second quantum chips 10 and 20 may be the same or different.

[0061] As in the above-described embodiment, the first and second quantum chips 10, 20 and the substrate of the interposer 30 preferably have the same thermal expansion coefficient (Si, GaAs, sapphire, glass, etc.).

[0062] The side terminals 15, 25 of the first and second quantum chips 10, 20 preferably have the terminal adjacent to the signal terminal as a ground circuit.

[0063] In order to improve the alignment accuracy of the side terminals 15, 25 of the first and second quantum chips 10, 20, guide holes (position adjustment holes) that determine the mounting position of the first and second quantum chips 10, 20, or processing of the chip's outer periphery (for example, if there are guide members for positioning at the four corners, the four corners of the quantum chip may be cut) may be applied.

[0064] FIG. 4A is a diagram showing a schematic diagram of an example in which the above-described embodiment (embodiment 1) is applied to a silicon quantum bit chip (Figure 1a in Non-Patent Document 2). In FIG. 4A, G1 to G4 are quantum dot constituting electrodes. R is a reservoir electrode. C passes under G2-G4 and confines the quantum dot on all sides except for the reservoir electrode R. In the single quantum dot mode, it is tunnel-coupled to the reservoir electrode R via G3 under G4. ST, RB, and LB are data readout circuits for the single electron transistor (SET), which act as charge detectors to determine whether or not a current flows and read out the quantum bit. An AC current I is applied to the ESR electrode. ESR By passing a current through the silicon qubit chip, writing to the qubit and calculations are performed. The chip is placed in a refrigerator and kept at an extremely low temperature. In the example shown in FIG. 4A, the silicon qubit chip (corresponding to the first quantum chip 10) has connection terminals (electrodes) 11 connected to the wiring of the SET's data readout circuit. For simplicity, the connection terminals (electrodes) 11 are illustrated as convex electrodes with a circular planar shape, but the planar shape may also be rectangular or other. All of the multiple connection terminals (electrodes) 11 may be convex electrodes, bumps, etc., or all may be electrodes for wireless connection, or some may be convex electrodes, bumps, etc. and the rest may be electrodes for wireless connection, etc.

[0065] FIG. 4B is a schematic diagram illustrating an example in which another embodiment (embodiment 2) is applied to a silicon quantum bit chip (Figure 1a in Non-Patent Document 2). The diagram illustrates a configuration in which connection terminals (side terminals) 15 are provided on the side of the silicon quantum bit chip instead of connection terminals 11 on the first surface (circuit surface) of the silicon quantum bit chip in FIG. 4A. In FIG. 4B, the wiring of the SET data readout circuit of the silicon quantum bit chip (first quantum chip 10) is connected to the side terminal of another silicon quantum bit chip (second quantum chip 20) (not shown) via side terminals 15. Side terminals (electrodes) 15 are illustrated as rectangular convex electrodes for simplicity, but they may also be circular or have other shapes. The multiple connection terminals (electrodes) 15 arranged on the side may all be convex electrodes, bumps, or the like, or all may be electrodes for wireless connection, or some may be convex electrodes, bumps, or the like, and the rest may be electrodes for wireless connection, or the like.

[0066] 5A to 5D are diagrams for schematically explaining an example of a manufacturing process for the quantum chip according to the second embodiment.

[0067] The process includes the steps of forming trenches 110 in the surface of a scribe region in the peripheral portion of silicon substrate 101 (wafer) shown in Fig. 5A, which corresponds to the side surface of first quantum chip 10 shown in Fig. 5B, forming connection terminals 112 (corresponding to side terminals 15 shown in Fig. 3C) on the side surface of trench 110 shown in Fig. 5C, and cutting along the scribe region (scribe line) inside trench 110 shown in Fig. 5D. The cut chip shown in Fig. 5D corresponds to the cross section taken along line AA in Fig. 4B.

[0068] In the step of FIG. 5B, a trench 110 is formed on the surface of a silicon substrate 101 (wafer) in a region of a scribe line (the width of the scribe line is, for example, on the order of 100 μm (micrometers), although there is no particular limitation) along the side where the side terminal of the first quantum chip 10 is to be formed. In trench processing, etching for processing usually takes a long time. For this reason, if a resist is used as a mask, it will deteriorate and the dimensions will become non-uniform. For this reason, a silicon oxide film (S i O2) layer is formed and patterned with plaster. i The O2 pattern is used as a mask (hard mask). Since vertical anisotropy is required for processing the trench 110 on the side surface of the first quantum chip 10, dry etching that removes only a specific direction is preferably used.

[0069] 5C, the connection terminal 112 may be formed on the side surface of the trench 110 by depositing a superconducting metal film on the side surface of the trench by sputtering (or plating) or the like, followed by patterning.

[0070] 5C illustrates the wiring layer 102 on the first surface (circuit surface) of the silicon substrate 101 and the connection terminals 112 on the trench side surfaces for simplicity, but the formation of the wiring layer 102 on the first surface (circuit surface) of the silicon substrate 101 and the formation of the connection terminals 112 on the trench side surfaces are typically performed in separate processes. However, for example, if the wiring layer 102 is made up of multiple layers, the formation of the pattern of the wiring on the top layer and the formation of the connection terminals 112 on the trench side surfaces may be performed simultaneously. The pattern formation of the wiring layer 102 on the first surface (circuit surface) of the silicon substrate 101 and the formation of the connection terminals 112 on the trench side surfaces may be performed using a lift-off process in which a photoresist is coated on the silicon substrate 101, a photoresist pattern is formed by exposure and development, a superconducting material is deposited on the entire surface, and the photoresist is subsequently peeled off, or a photoetching process may be performed on the deposited superconducting material. That is, a superconducting metal film is deposited on the silicon substrate 101 by sputtering or the like, a photoresist pattern is formed thereon, a wiring pattern is formed by dry etching or wet etching, and then the photoresist is peeled off and removed.

[0071] 5D may be diced using a dicer method using a dicing blade, a laser method, or an etching method using dry etching. In the dicer method, the silicon substrate 101 is attached to the adhesive surface of a dicing tape (not shown) and cut along the dicing street (a scribe line crossing the trench 110) with a dicing blade (not shown). After dicing, the wafer is washed, and the adhesive of the dicing tape is cured by UV (ultraviolet) light irradiation to reduce its adhesive strength, and the dicing tape is stretched to remove the first quantum chip 10.

[0072] After forming the side terminals 15, the protruding portions 113 (bottom portions of the trenches 110 after dicing) directly below the side terminals 15 of the first quantum chip 10 may be thinned by grinding the entire back surface of the silicon substrate 101 (wafer) to make the side terminals 112 of the first quantum chip 10 the same thickness as the first quantum chip 10. Note that the protruding portions 113 directly below the side terminals 112 may be left as they are or may be machined around the periphery and used as a positioning means for accurately positioning the chip on the opposing side terminal. The second quantum chip 20 is manufactured in the same manner as the first quantum chip 10 described above.

[0073] 6A to 6D are diagrams for schematically explaining another example of the manufacturing process of the quantum chip according to the second embodiment.

[0074] The dicing process includes the steps of forming via holes 114 (blind via holes) on the surface of a scribe region in the peripheral portion of a silicon substrate 101 (wafer) shown in Fig. 6A, filling the via holes 114 with a superconducting metal shown in Fig. 6C, and cutting the silicon substrate 101 (wafer) into first quantum chips 10 along scribe lines on metal vias 115 shown in Fig. 6D. The first quantum chips 10 cut in the dicing process shown in Fig. 6D correspond to the cross section taken along line AA in Fig. 4B.

[0075] 6C shows a filled via (filled plating) in which metal is filled in the via hole 114, but a conformal via with a recessed via surface may also be used. Conformal plating allows for plating to be performed with a uniform thickness on the sidewalls and bottom surface of the via, which cannot be achieved by sputtering.

[0076] 6B, the quantum bit circuit (wiring pattern) may be formed on the first surface (circuit surface) of silicon substrate 101, and then via holes 114 may be opened by dry etching or the like, or via holes 114 may be opened in silicon substrate 101 by dry etching or the like, and then via holes 114 may be filled, and then quantum bit circuits (wiring pattern) may be formed on the first surface (circuit surface) of silicon substrate 101. However, from the viewpoint of maintaining the wiring shape and the like on the first surface (circuit surface) of silicon substrate 101, it is preferable to form wiring and electrodes on the first surface (circuit surface) of silicon substrate 101 after superconducting metal 115 (metal via) is filled in via holes 114.

[0077] 6B and 6C, a bottomed via (blind via) is shown as the via hole 114, but a through via (TSV) may also be used. In the case of a through via (TSV), the protruding portion 113 directly below the side terminal 112 is eliminated, and the height of the side terminal 112 corresponds to the thickness of the first quantum chip 10. Also, as shown in FIG. 6B, the via hole 114 may be a blind via hole, and the back surface of the wafer may be ground before dicing to remove the protruding portion 113, so that the height of the side terminal 112 corresponds to the thickness of the first quantum chip 10.

[0078] In the dicing process shown in FIG. 6D, the first quantum chip 10 is cut along the center (scribe line) of the metal via 115 (FIG. 6C) arranged in the scribe line region. As shown in FIG. 6E, the surface of the connection terminal 112 is flush with the side surface of the first quantum chip 10. However, by further coating the cut surface of FIG. 6E with a superconducting metal film and processing it with a laser or the like, a convex electrode (bump) structure can be formed, as shown in FIG. 6F. The convex electrode side terminal 112 of FIG. 6F is suitable for capacitive or inductive coupling with the opposing side terminal of the second quantum chip 20 (which also has a convex electrode side terminal). In particular, in the via formation configuration shown in FIG. 6C, when the via is filled using conformal plating, the surface of the metal via 115 becomes concave with respect to the side surface of the first quantum chip 10. In this case, a superconducting metal film may be further formed on the surface of the metal via 115 on the side surface of the first quantum chip 10 to form the side terminal 112 of the convex electrode.

[0079] 7A to 7G are diagrams illustrating modifications of the second embodiment. FIG. 7A is a diagram schematically illustrating an example of a flux-type quantum bit circuit. In FIG. 7A, a superconducting circuit made of Al wiring is formed on a first surface (circuit surface) of a silicon substrate 101, and data is written to a flux quantum bit consisting of a SQUID (superconducting quantum interference device) by passing a microwave current through a microwave line. The readout line is a quantum state observation circuit.

[0080] Fig. 7B is a diagram showing the first quantum chip 10 of Fig. 7A provided with side terminals 15 according to the second embodiment. In Fig. 7B, the first quantum chip 10 of Fig. 7A has a coplanar substrate configuration in which a ground (GND) pattern is provided on the first surface (circuit surface) of the silicon substrate 101, and ground side terminals 15G are provided on both sides of the signal side terminal 15S connected to the readout line and microwave line of Fig. 7A. The ground side terminals 15G are arranged at the ends of the protruding portions 104 on the side of the silicon substrate 101, and are arranged to protrude further than the signal side terminals 15S.

[0081] FIG. 7C is a diagram schematically illustrating a trench 110 formed on a silicon substrate 101 in a trench formation process during the manufacturing of the first quantum chip 10 of FIG. 7B, and the planar shape of the first quantum chip 10. FIG. 7D is a diagram schematically illustrating a side cross section taken along line AA in FIG. 7C. Referring to FIGS. 7C and 7D, in the process of forming a trench 110 on the surface of a scribe region (scribe line), a protruding portion 104 corresponding to a ground side terminal is provided on the side surface of the silicon substrate 101 (wafer). That is, the trench 110 is formed by dry etching or the like using a hard mask with a pattern having protrusions and recesses on the side surface of the first quantum chip 10, thereby providing the protruding portion 104 on the side surface. Thereafter, a signal side terminal 15S made of a superconducting metal film may be formed in a recess on the side surface of the first quantum chip 10, and a ground side terminal 15G may be formed at the tip of the protruding portion 104, which is a protruding portion on the side surface of the first quantum chip 10. Although not particularly limited, the superconducting metal film may be provided not only on the tip of the protruding portion 104 of the first quantum chip 10 but also on the side wall facing the signal side terminal 15S.

[0082] 7E is a diagram showing a configuration in which a superconducting metal film is applied to the trench sidewalls and protruding portions 104 of the silicon substrate 101 to form the signal side terminals 15S and the ground side terminals 15G, as viewed from above the first surface of the silicon substrate 101. The signal side terminals 15S and the ground side terminals 15G are provided at the tips of the protruding portions 104 on the sidewalls of the trench 110, and are connected to the signal line and the ground line (pattern), respectively.

[0083] 7F shows a configuration in which a ground side terminal 15G of the first quantum chip 10 is bonded to an opposing ground side terminal 25G of the second quantum chip 20, and a signal side terminal 15S of the first quantum chip 10 and a signal side terminal 25S of the second quantum chip 20 are spaced apart and arranged opposite each other, transmitting and / or receiving signals through capacitive or inductive coupling. In FIG. 7B, on the first surface of the substrate 101, the ground side terminal 15G (electrode) of the first quantum chip 10 and the opposing ground side terminal 25G (electrode) of the second quantum chip 20 may be bonded via a gap on both sides of the signal line by soldering or thermocompression bonding using ultrasonic waves. In FIG. 7B, a coplanar configuration is configured in which ground patterns are arranged on both sides of the signal line on the first surface of the substrate 101 via a gap, and the ground side terminal 15G is wired and connected to the ground pattern on the first surface (circuit surface). However, in FIG. 7A, if the second surface (back surface) of substrate 101 is used as a ground plane, ground side terminal 15G may be configured to be connected to the ground plane on the second surface (back surface).

[0084] In FIG. 7F, the side terminals of the first quantum chip 10 and the second quantum chip 20 are both arranged in a concave-convex configuration. That is, the ground side terminals 15G and 25G are arranged on the protruding portions (convex portions) of the side surfaces, and the signal side terminals 15S and 25S are arranged in the concave portions of the side surfaces. However, the side terminals of either the first quantum chip 10 or the second quantum chip 20 may be arranged in a concave-convex configuration, and the other may be arranged on a flat side surface. For example, in the example of FIG. 7G, the ground side terminal 15G of the first quantum chip 10 is arranged at the tip of the protruding portion 104 protruding from the chip side surface, as in FIG. 7F, while the ground side terminal 25G of the second quantum chip 20 is arranged on the flat surface of the chip side surface together with the signal side terminal 25S.

[0085] Although not particularly limited, the side terminals 15 may be arranged such that for each signal side terminal 15S, a ground side terminal 15G, the signal side terminal 15S, and the ground side terminal 15G are arranged as a pair.

[0086] 8 is a schematic diagram showing a modification of another embodiment. First to fifth quantum chips 210-250 are flip-chip mounted on interposer 30 with their first surfaces (circuit surfaces) facing downward. Second to fifth quantum bits 220-250 are arranged on the four sides of first quantum chip 210.

[0087] Side terminal 215 provided on one side of first quantum chip 210 is arranged to face side terminal 225 of the opposing second quantum chip 220, and signals are transmitted and / or received by metal (convex electrode, bump) connection or wireless connection (capacitive coupling or inductive coupling). Side terminals provided on the remaining three side of first quantum chip 210 are arranged to face side terminals of the opposing third to fifth quantum chips 230-250, and signals are transmitted and / or received by metal (convex electrode, bump) connection or wireless connection (capacitive coupling or inductive coupling).

[0088] According to each of the above-described embodiments, in a quantum computer device having a quantum chip and an interposer, by using a configuration using multiple quantum chips or multiple interposers, it is possible to suppress characteristic variations due to, for example, a decrease in yield, pseudo errors (thinning or swelling of conductors), etc. Furthermore, by connecting multiple quantum chips having quantum bit circuits directly between the quantum chips, it is possible to improve power loss and superimposed noise at the connection points.

[0089] The above-described embodiment is supplemented as follows (however, it goes without saying that the present invention is not limited to the following).

[0090] (Supplementary Note 1) A quantum device comprising: a first quantum chip; a second quantum chip; and one or more interposers on which the first quantum chip and the second quantum chip are mounted, wherein the first quantum chip and the second quantum chip have surfaces in at least partial regions facing each other when mounted on a common or different interposer, and electrical connection is made between connection terminals that are arranged in at least partial regions within the facing surfaces of the first quantum chip and the second quantum chip and that face each other.

[0091] (Supplementary Note 2) The first quantum chip and the second quantum chip each include: 2. The quantum device of claim 1, wherein the connection terminal is provided in the partial region of a surface that is the same as a first surface on which at least one quantum bit circuit is arranged.

[0092] (Supplementary Note 3) The interposer includes a first interposer and a second interposer on which the first quantum chip and the second quantum chip are mounted, respectively; the first quantum chip is mounted on the first interposer in a state in which at least one side of the first quantum chip extends beyond an edge of the first interposer; the first surface of the first quantum chip faces the partial region of the first surface of the second quantum chip at the partial region that protrudes beyond the edge of the first interposer; one or more of the connection terminals provided in the partial region of the first surface of the first quantum chip that protrudes beyond an edge of the first interposer; On the first surface of the second quantum chip, one or more of the connection terminals are arranged in a partial region of the second quantum chip that faces the partial region of the first surface of the first quantum chip; 3. The quantum device of claim 2, wherein an electrical connection is made between:

[0093] (Appendix 4) The quantum device described in Appendix 3, wherein the first quantum chip is mounted on the first interposer with the first surface facing down, and the second quantum chip is mounted on the second interposer with a second surface opposite to the first surface facing down, and the connection terminal of the partial region of the first surface of the first quantum chip and the connection terminal of the partial region of the first surface of the second quantum chip that is electrically connected to the connection terminal are located at the same position on a plane and face each other vertically.

[0094] (Appendix 5) A quantum device according to any one of Appendices 2 to 4, comprising a lid-shaped chip facing the surface of the second quantum chip facing the portion of the first quantum chip and covering part or all of the area of ​​the first quantum chip other than the area facing the portion of the first quantum chip, and the lid-shaped chip has a ground plane on the surface facing the second quantum chip.

[0095] (Supplementary Note 6) The quantum device according to Supplementary Note 1, wherein the first quantum chip and the second quantum chip each have the connection terminal on at least one side surface.

[0096] (Appendix 7) The quantum device described in Appendix 6, wherein, when the first quantum chip and the second quantum chip are mounted on the interposer, the connection terminal on the side surface of the first quantum chip and the connection terminal on the side surface of the second quantum chip are arranged opposite each other.

[0097] (Appendix 8) The quantum device described in Appendix 7, wherein the first quantum chip and the second quantum chip are each mounted on a common interposer with a first surface, on which at least one quantum bit circuit is arranged, facing downward.

[0098] (Supplementary Note 9) At least one of the first quantum chip and the second quantum chip has a recess and a protrusion on the side surface, 9. The quantum device according to any one of claims 6 to 8, wherein the connection terminals are provided in the recessed and protruding portions of the side surface, respectively.

[0099] (Supplementary Note 10) At least one of the first quantum chip and the second quantum chip has at least two protruding portions arranged apart from each other on a side surface of a substrate constituting the quantum chip and protruding in a direction perpendicular to the side surface, 9. A quantum device according to any one of claims 6 to 8, wherein the connection terminal is provided in the region between the at least two protrusions on the side surface and on the protrusions.

[0100] (Supplementary Note 11) The electrical connection of one or more of the connection terminals facing each other of the first and second quantum chips is Wired connection using conductive members, wireless connection by capacitive and / or inductive coupling; Mixing of wired and wireless connections 11. A quantum device according to any one of appendices 1 to 10, comprising any one of the connection topologies.

[0101] (Supplementary Note 12) At least one of the first and second quantum chips is one or more connection terminals facing one or more connection terminals of the interposer on which the quantum chip is mounted, The one or more connection terminals of the interposer Wired connections using conductive materials, wireless connection by capacitive and / or inductive coupling; Mixing of wired and wireless connections 12. The quantum device according to any one of claims 1 to 11, having one or more connection terminals electrically connected in any one of the connection forms.

[0102] (Supplementary Note 13) The quantum device according to any one of Supplementary Notes 1 to 11, wherein at least one of the first and second quantum chips has at least one of its four corners cut.

[0103] (Appendix 14) A quantum device according to any one of Appendices 6 to 8, wherein the connection terminal of at least one of the first and second quantum chips includes a portion of superconducting metal formed on the side wall of a trench opened in the surface of an area that will become a scribe line in the direction along the side surface, or a portion of superconducting metal embedded in a via hole opened in the surface of an area that will become a scribe line in the direction along the side surface, in a wafer on which at least one of the first and second quantum chips is formed.

[0104] The disclosures of the above-mentioned Patent Documents 1-3 and Non-Patent Documents 1 and 2 are incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure of the present invention (including the scope of the claims), and further based on the basic technical ideas thereof. Furthermore, various combinations and selections of the various disclosed elements (including each element of each appendix, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. In other words, the present invention naturally includes various modifications and alterations that would be possible for a person skilled in the art in accordance with the entire disclosure, including the scope of the claims, and the technical ideas thereof. [Explanation of symbols]

[0105] 1. Quantum devices 10 The first quantum chip 20 Second quantum chip 11, 21 Connection terminal (electrode) 12, 22 qubit circuits 15, 25 Side terminal (connection terminal) 15S, 25S signal side terminal 15G, 25G ground side terminal 23 Resin 24 Wiring pad (electrode) 25 Bonding Wire 26 Connection terminal 30 Interposer 31 Bump 40 Package substrate (interposer) 41 Connection terminal 50 Lid Tips 101 Substrate (silicon substrate) 102 Wiring layer (circuit surface wiring) 103 Area (range) (overhang) 104 Protruding part 110 Trench 112 Side terminal (electrode) 113 Protruding parts 114 Beer Hall 115 Metal Vias 201 Substrate (silicon substrate) 202 Wiring layer (circuit surface wiring) 203 Through Via 204 Via Pad 210 First Quantum Chip 215, 225, 235, 245 Side terminal (connection terminal) 220 Second Quantum Chip 230 The Third Quantum Chip 240 The Fourth Quantum Chip 250 The Fifth Quantum Chip 301 Substrate (silicon substrate) 302 Wiring layer (wiring) 303 Wiring layer (wiring) 304 Through-Semiconductor Via (TSV) 305 Bump (electrode) 401 Substrate (silicon substrate) 402 Wiring layer (wiring) 403 Wiring layer (wiring) 404 through via 405 Bump 407 Wiring Pad 501 First Qubit Chip 502 Second Qubit Chip 503 Carrier Chip 504, 505 terminals 506 common terminal 507, 508 Indium bump 601 First qubit substrate 602 Second qubit substrate 603 Interposer 604, 609 Superconducting wiring 605, 610 Superconducting qubits 606, 611 Superconducting solder bumps 701 First Chip 702 Second Chip 703 Interposer 704, 705 electrode 706 Wiring

Claims

1. a first quantum chip; and a second quantum chip; and one or more interposers on which the first quantum chip and the second quantum chip are mounted; Equipped with The first quantum chip and the second quantum chip have side surfaces facing each other while being mounted on a common or different interposer, an electrical connection is made between connection terminals that are disposed in at least a partial region of the side surfaces of the first quantum chip and the second quantum chip that face each other, and that face each other; At least one of the first quantum chip and the second quantum chip has a recess and a protrusion in at least a portion of the side surface, and the connection terminal is provided in each of the recess and the protrusion on the side surface.

2. When the first quantum chip and the second quantum chip are mounted on the common interposer, the connection terminal of the convex portion on the side of one of the first quantum chip and the second quantum chip and the connection terminal of the side of the other quantum chip arranged opposite the connection terminal of the convex portion are connected by a wired connection using a conductive member, and the connection terminal of the concave portion on the side of the one quantum chip and the connection terminal of the concave portion are connected by a wireless connection using capacitive coupling or inductive coupling. The quantum device according to claim 1, characterized in that

3. the first and second quantum chips have recesses and protrusions in at least a portion of the side surfaces, and the connection terminals are provided in the recesses and protrusions of the side surfaces, respectively; When mounted on the common interposer, the connection terminals of the convex portions on the side surfaces of the first quantum chip and the second quantum chip arranged opposite each other are connected by a wired connection using a conductive member, and the connection terminals of the concave portions on the side surfaces of the first quantum chip and the second quantum chip arranged opposite each other are connected by a wireless connection using capacitive coupling or inductive coupling. The quantum device according to claim 1,

4. At least one of the first and second quantum chips is one or more connection terminals facing one or more connection terminals of the interposer on which the quantum chip is mounted, The one or more connection terminals of the interposer Wired connections using conductive materials, wireless connection by capacitive and / or inductive coupling; Mixing of wired and wireless connections 4. The quantum device according to claim 1, further comprising one or more connection terminals electrically connected in any one of the connection forms.

Images