Array substrate, display panel, display device, and method of manufacturing array substrate

Abstract

To provide an array substrate with improved performance, a display panel, a display device, and a manufacturing method for the array substrate.SOLUTION: An array substrate includes a pixel unit group 110, the pixel unit group includes a first pixel and a second pixel which are adjacently arranged in parallel in a first direction D1, and the first pixel includes a first pixel electrode 121, a first switching element 123, and a first connecting portion 122 extending from the first pixel electrode. The second pixel includes a second pixel electrode 131, a second switching element 133, and a second connection portion 132 extending from the second pixel electrode. The first pixel electrode and the first switching element are electrically connected to each other through a first connection portion, the second pixel electrode and the second switching element are electrically connected to each other through a second connection portion, and extension length of the first connection portion is not equal to extension length of the second connection portion.SELECTED DRAWING: Figure 4B

Description

[Technical Field]

[0001] The present disclosure relates to an array substrate, a display panel, a display device, and a method for manufacturing an array substrate. [Background technology]

[0002] With the development of display technology, thin film transistor liquid crystal displays (TFT-LCDs) have gradually become the mainstream in the market due to their advantages such as low power consumption, light weight, thinness, and low radiation. As people's living standards improve and their awareness of display devices increases, the demands on display performance are also increasing, such as high resolution, high contrast, and fast response speed. In addition, the demands on parameters that represent display device screen quality (such as image retention, unevenness, and light leakage) are also increasing. For example, to achieve low-cost, high-resolution displays, many display devices adopt a dual-gate design. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure provides an array substrate including a group of pixel units, the group of pixel units including a first pixel and a second pixel arranged adjacent to each other in a first direction, the first pixel including a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode, the second pixel including a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode, the first pixel electrode and the first switching element being electrically connected to each other via the first connection portion, the second pixel electrode and the second switching element being electrically connected to each other via the second connection portion, and an extension length of the first connection portion not equal to an extension length of the second connection portion.

[0004] For example, in at least one example of the array substrate, the pixel unit group includes a first edge and a second edge facing each other in the first direction, and the first switching element and the second switching element are closer to the first edge of the pixel unit group in the first direction than the second edge.

[0005] For example, in at least one example of the array substrate, the first pixel electrode is located between the first switching element and the second switching element in a second direction intersecting the first direction.

[0006] For example, in at least one example of the array substrate, the first switching element and the second switching element are in the second direction relative to the first pixel electrode and are arranged symmetrically with respect to a center line extending along the first direction.

[0007] For example, in at least one example of the array substrate, the extension direction of the first connection portion is a second direction, the extension direction of the second connection portion is the first direction, and the first direction and the second direction intersect with each other.

[0008] For example, in at least one example of the array substrate, the second connection portion and the first pixel electrode at least partially overlap in a second direction intersecting the first direction.

[0009] For example, in at least one example of the array substrate, the first connection portion and the first pixel electrode are integrally formed of the same material, and the second connection portion and the second pixel electrode are integrally formed of the same material.

[0010] For example, in at least one example of the array substrate, the first switching element includes a first source-drain layer including two first source-drain regions facing each other and spaced apart, the second switching element includes a second source-drain layer including two second source-drain regions facing each other and spaced apart, the first connection portion is directly electrically connected to the first pixel electrode, the first connection portion is further electrically connected to one of the two first source-drain regions through a first via, the second connection portion is directly electrically connected to the second pixel electrode, and the second connection portion is further electrically connected to one of the two second source-drain regions through a second via.

[0011] For example, in at least one example of the array substrate, one of the two first source-drains covers a portion of the opening area of ​​the first via, and the remaining portion of the opening area of ​​the first via is located on the side of the one first source-drain closer to the first pixel electrode, and one of the two second source-drains covers a portion of the opening area of ​​the second via, and the remaining portion of the opening area of ​​the second via is located on the side of the one second source-drain closer to the first pixel electrode.

[0012] For example, in at least one example of the array substrate, the array substrate further includes a first gate line and a second gate line extending in the first direction, the first gate line and the second gate line being located on both sides of the pixel unit group in a second direction intersecting the first direction, and a positive projection of the first gate line on the first source-drain layer overlaps with one of the two first source-drains at at least two different positions.

[0013] For example, in at least one example of the array substrate, the first gate line includes a first gate portion, a first line portion, and a first line connection portion connected in sequence, the first gate portion is arranged as a gate of the first switching element, and a positive projection of the first gate line on the first source-drain layer at least partially overlaps with one of the two first source-drains on both sides of the first direction.

[0014] For example, in at least one example of the array substrate, the orthogonal projection of the first line connection portion of the first gate line on one of the two first source-drains at least partially overlaps with one of the two first source-drains.

[0015] For example, in at least one example of the array substrate, the first line connection portion includes a first protrusion protruding toward the first gate portion, and a positive projection of the first protrusion on one of the two first source-drains at least partially overlaps with one of the two first source-drains.

[0016] For example, in at least one example of the array substrate, an overlapping region between an orthogonal projection of one of the two first source-drains of the first protrusion and one of the two first source-drains is a first overlapping region, and the first overlapping region has a first overlapping edge in a second direction intersecting the first direction, an overlapping region between an orthogonal projection of one of the two first source-drains of the first gate portion and one of the two first source-drains is a second overlapping region, and the second overlapping region has a second overlapping edge in the second direction, and the length of the first overlapping edge and the length of the second overlapping edge are equal.

[0017] For example, in at least one example of the array substrate, the orthogonal projection of the second gate line on the second source-drain layer overlaps one of the two second source-drains at at least two different positions.

[0018] For example, in at least one example of the array substrate, the second gate line includes a second gate portion, a second line portion, and a second line connection portion connected in sequence, the second gate portion is arranged as a gate of the second switching element, and the orthogonal projection of the second gate line on the second source-drain layer at least partially overlaps with one of the two second source-drains on both sides of the first direction.

[0019] For example, in at least one example of the array substrate, the orthogonal projection of the second line connection portion of the second gate line on one of the two second source-drains at least partially overlaps with one of the two second source-drains.

[0020] For example, in at least one example of the array substrate, the second line connection portion includes a second protrusion protruding toward the second gate portion, and a positive projection of the second protrusion on one of the two second source-drains at least partially overlaps with one of the two second source-drains.

[0021] For example, in at least one example of the array substrate, an overlap region between an orthogonal projection of one of the two second source-drains of the second protrusion and one of the two second source-drains is a third overlap region, the third overlap region has a third overlap edge in the second direction, an overlap region between an orthogonal projection of one of the two second source-drains of the second gate portion and one of the two second source-drains is a fourth overlap region, the fourth overlap region has a fourth overlap edge in the second direction, and the length of the third overlap edge and the length of the fourth overlap edge are equal.

[0022] For example, in at least one example of the array substrate, an overlap area between a positive projection of the first gate line on the first source-drain layer and one of the two first source-drains is a first value, an overlap area between a positive projection of the second gate line on the second source-drain layer and one of the two second source-drains is a second value, and the first value is equal to the second value.

[0023] For example, in at least one example of the array substrate, the first connection portion and the second connection portion are located on both sides of the first pixel electrode in a second direction perpendicular to the first direction, both the first connection portion and the second connection portion are located between the first gate line and the second gate line in the second direction, and the first gate line and the second gate line are arranged symmetrically in the second direction with respect to a center line of the pixel unit group extending in the first direction.

[0024] For example, in at least one example of the array substrate, the array substrate includes a plurality of pixel unit groups arranged in an array, and a first gate line for driving each of the pixel unit groups and a second gate line for driving a pixel unit group adjacent to each of the pixel unit groups in the second direction partially overlap in the first direction.

[0025] For example, in at least one example of the array substrate, the array substrate includes a plurality of pixel unit groups arranged in an array, and data lines installed between adjacent pixel unit groups, and the first switching element and the second switching element of each pixel unit group are both connected to the same data line.

[0026] For example, in at least one example of the array substrate, the array substrate further includes a plurality of common electrode patterns arranged in an array, the plurality of common electrode patterns and the plurality of pixel unit groups correspond one-to-one, the plurality of common electrode patterns in the same row are located between a first gate line and a second gate line for driving the pixel unit groups corresponding to the plurality of common electrode patterns in the same row, the common electrode patterns adjacent to each other in the first direction are electrically connected by a first common electrode connection portion in the same layer as the common electrode patterns, the common electrode patterns adjacent to each other in the second direction are electrically connected by a second common electrode connection portion in the same layer as the first connection portion, and the second common electrode connection portion is electrically connected to the corresponding common electrode pattern by a third via.

[0027] For example, in at least one example of the array substrate, each of the common electrode patterns includes a main body portion and a first protrusion extending from a first side of the main body portion, the first protrusion extending in the second direction, and adjacent common electrode patterns in the second direction are electrically connected by the first protrusion of the adjacent common electrode pattern and the third via.

[0028] For example, in at least one example of the array substrate, the lateral spacing between the first pixel electrode and the gate line driving the first pixel is greater than 5 microns, and the lateral spacing between the second pixel electrode and the gate line driving the second pixel is greater than 5 microns.

[0029] For example, in at least one example of the array substrate, the extension length of the first connection portion is smaller than the extension length of the second connection portion, and the second pixel electrode has a recess on a side closer to a gate line that drives the second pixel.

[0030] For example, in at least one example of the array substrate, the first pixel electrode and the gate line that drives the first pixel overlap each other in a second direction that intersects with the first direction, the second pixel electrode and the gate line that drives the second pixel overlap each other in a second direction that intersects with the first direction, and an effective overlap length between the coupling structure of the first pixel electrode and the first connection portion and the gate line that drives the first pixel is equal to an effective overlap length between the coupling structure of the second pixel electrode and the second connection portion and the gate line that drives the second pixel.

[0031] At least one embodiment of the present disclosure further provides a display panel including any of the array substrates according to the embodiments of the present disclosure.

[0032] At least one embodiment of the present disclosure further provides a display device including any of the array substrates according to the embodiments of the present disclosure or any of the display panels according to the embodiments of the present disclosure.

[0033] At least one embodiment of the present disclosure further provides a method for manufacturing an array substrate, the method including forming a pixel unit group, the pixel unit group including a first pixel and a second pixel arranged in parallel in a first direction, the first pixel including a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode, the second pixel including a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode, the first pixel electrode and the first switching element being electrically connected to each other via the first connection portion, the second pixel electrode and the second switching element being electrically connected to each other via the second connection portion, and a length of the first connection portion not equal to a length of the second connection portion.

[0034] For example, in at least one example of the manufacturing method, the step of forming the pixel unit group includes a step of patterning the same film layer using the same patterning process to form the first connection portion, the first pixel electrode, the second connection portion, and the second pixel electrode. [Brief explanation of the drawings]

[0035] In order to more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be apparent that the drawings described below are merely related to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0036] [Figure 1] FIG. 1 is a schematic plan view showing an array substrate. [Figure 2A] FIG. 2A is a schematic plan view illustrating an array substrate according to at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a schematic plan view showing a group of pixel units on the array substrate shown in FIG. 2A. [Figure 2C] FIG. 2C is a schematic diagram of the image observed by the user of the display panel with and without tilting. [Figure 2D] FIG. 2D is a schematic diagram illustrating an exemplary method for calculating spatial frequency. [Figure 2E] FIG. 2E is a schematic diagram showing the optimal viewing distance of the tilting stripes of different types of display panels. [Figure 2F] FIG. 2F is a schematic diagram showing the cause of the occurrence of the swing stripe defect. [Figure 2G] FIG. 2G is a schematic diagram showing the charging and discharging of pixels of a display panel. [Figure 2H] FIG. 2H is a schematic diagram showing capacitances associated with pixels of a display panel. [Figure 3A] FIG. 3A is a schematic diagram showing the array substrate shown in FIG. 2A. [Figure 3B] FIG. 3B is an enlarged view showing the region RC1 of the array substrate shown in FIG. 2A. [Figure 3C] FIG. 3C is an enlarged view showing the region RC2 of the array substrate shown in FIG. 2A. [Figure 3D]FIG. 3D is a schematic diagram showing pixel voltages of pixels in a pixel unit group in odd-numbered columns of the array substrate when the source-drain metal layers shown in FIG. 2A are not offset and when they are offset. [Figure 3E] FIG. 3E is a schematic diagram showing pixel voltages of pixels in a pixel unit group in an even-numbered column of the array substrate shown in FIG. 2A when the source-drain metal layers are not offset and when they are offset. [Figure 3F] FIG. 3F is a schematic diagram showing the effective overlap length and horizontal spacing between the pixel electrodes and the coupling structure of the connection parts of the pixels on the array substrate shown in FIG. 2A and the gate lines that drive the pixels. [Figure 3G] FIG. 3G is a schematic diagram showing a comparison of pixel voltages in a positive display frame and a negative display frame between a short connection pixel and a long connection pixel on the array substrate shown in FIG. 2A. [Figure 3H] FIG. 3H is a schematic diagram showing the region RC1 of the array substrate shown in FIG. 2A. [Figure 3I] FIG. 3I is a schematic diagram showing the region RC3 of the array substrate shown in FIG. 2A. [Figure 3J] FIG. 3J is a schematic diagram showing the influence of the capacitance Cpg' of a pixel on the array substrate shown in FIG. 2A on the pixel voltage of the pixel. [Figure 4A] FIG. 4A is a schematic plan view illustrating another array substrate in accordance with at least one embodiment of the present disclosure. [Figure 4B] FIG. 4B is a schematic plan view showing a group of pixel units on the array substrate shown in FIG. 4A. [Figure 4C] FIG. 4C is a schematic plan view showing the first electrode layer of the array substrate shown in FIG. 4A. [Figure 4D] FIG. 4D is a schematic plan view showing the first gate lines and the second gate lines of the array substrate shown in FIG. 4A. [Figure 4E] FIG. 4E is a schematic plan view showing a portion of the first gate lines and second gate lines of the array substrate shown in FIG. 4A corresponding to one pixel unit group. [Figure 5A]FIG. 5A is a schematic plan view showing the semiconductor layer and the second electrode layer of the array substrate shown in FIG. 4A. [Figure 5B] FIG. 5B is a schematic plan view showing the first switching element of the array substrate shown in FIG. 4A. [Figure 5C] FIG. 5C is a schematic diagram showing a cross section taken along line AA' shown in FIG. 5B. [Figure 5D] FIG. 5D is a schematic plan view showing the second switching element of the array substrate shown in FIG. 4A. [Figure 5E] FIG. 5E is a schematic plan view showing a partial region of the array substrate shown in FIG. 2A. [Figure 5F] FIG. 5F is a schematic plan view showing the region RC4 of the array substrate shown in FIG. 5E. [Figure 5G] FIG. 5G is a first schematic diagram showing an overlapping region between the electrode layer on which the gate lines of the array substrate shown in FIG. 4A are located and the orthogonal projection of the electrode layer on which the source / drain are located on the electrode layer on which the gate lines are located. [Figure 5H] FIG. 5H is a second schematic diagram showing the overlapping area between the electrode layer on which the gate lines of the array substrate shown in FIG. 4A are located and the orthogonal projection of the electrode layer on which the source / drain are located on the electrode layer on which the gate lines are located. [Figure 6] FIG. 6 is a schematic plan view showing the third electrode layer of the array substrate shown in FIG. 4A. [Figure 7] FIG. 7 is a schematic plan view showing the first electrode layer, the semiconductor layer, and the second electrode layer of the array substrate shown in FIG. 4A. [Figure 8] FIG. 8 is a schematic plan view showing the first via, the second via, and the third via of the array substrate shown in FIG. 4A. [Figure 9] FIG. 9 is a schematic diagram showing the interval and overlap length between the pixel electrodes of the array substrate shown in FIG. 4A and the gate lines that drive the pixels where the pixel electrodes are located. [Figure 10] FIG. 10 is a schematic plan view showing a plurality of common electrode patterns of the array substrate shown in FIG. 4A. [Figure 11]FIG. 11 is a schematic plan view showing one of the common electrode patterns of the array substrate shown in FIG. 4A. [Figure 12] FIG. 12 is an exemplary block diagram illustrating a display panel and a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0037] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and are not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments that a person skilled in the art can come up with without any creative efforts fall within the scope of protection of the present disclosure.

[0038] Unless otherwise specified, technical or scientific terms used herein have the common meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote order, quantity, or importance, but merely serve to distinguish different components. Similarly, similar terms such as "comprise" or "include" are intended to cover the element or object appearing after the term and its equivalents, but do not exclude other elements or objects. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," and "right" merely indicate relative positions, and if the absolute positions of the objects described change, the relative positions may also change accordingly.

[0039] The inventors of the present disclosure have conducted research and found that display panels employing a dual gate design, particularly TN (Twist Nematic) display panels, suffer from problems such as poor sway stripes and / or low aperture ratios. Hereinafter, the problem of low aperture ratios of display panels employing a dual gate design will be illustrated with reference to FIG. 1.

[0040] 1 is a schematic plan view of an array substrate 500. As shown in FIG. 1, the array substrate 500 includes a plurality of pixel unit groups 510 arranged in an array, gate lines 542 extending in a first direction D1, and data lines 561 extending in a second direction D2 intersecting (e.g., perpendicular to) the first direction D1, where one data line 561 is provided between two adjacent pixel unit groups 510 in the first direction D1, and two gate lines 542 are provided between two adjacent pixel unit groups 510 in the second direction D2, and each row of pixel unit groups 510 is driven by two gate lines 542 provided on both sides of the pixel unit groups 510 of that row (one gate line 542 located above the pixel unit groups 510 of that row and one gate line 542 located below the pixel unit groups 510 of that row).

[0041] As shown in FIG. 1, each pixel unit group 510 includes a first pixel and a second pixel arranged adjacent to each other in parallel in a first direction D1, the first pixel includes a first pixel electrode 521, a first switching element 523, and a first wiring 522 for connecting the first switching element 523 to a data line 561 for driving the first pixel, and the second pixel includes a second pixel electrode 531, a second switching element 533, and a second wiring 532 for connecting the second switching element 533 to a data line 561 for driving the second pixel.

[0042] As shown in FIG. 1, the first pixel electrode 521 and the first switching element 523 are electrically connected by a first via 524, the second pixel electrode 531 and the second switching element 533 are electrically connected by a second via 534, the orthogonal projection of the first via 524 on the first pixel electrode 521 at least partially overlaps with the first pixel electrode 521, and the orthogonal projection of the second via 534 on the second pixel electrode 531 at least partially overlaps with the second pixel electrode 531.

[0043] As shown in FIG. 1, the first switching element 523 and the second switching element 533 for driving the same pixel unit group 510 are arranged in parallel in the second direction D2, and the first switching element 523 and the second switching element 533 at least partially overlap in the second direction D2, i.e., the orthogonal projections of the first switching element 523 and the second switching element 533 in a plane perpendicular to the second direction D2 at least partially overlap, and the first wiring 522 and the second wiring 532 are disposed between two gate lines 542 between two adjacent pixel unit groups 510 in the second direction D2.

[0044] For example, a display panel including the array substrate 500 includes a black matrix (not shown), and the orthogonal projection of the black matrix on the array substrate 500 covers the gate line 542, the data line 561, the first wiring 522, the second wiring 532, the first switching element 523, the second switching element 533, the first via 524, and the second via 534. For example, the first wiring 522, the second wiring 532, and the data line 561 are made of the same material.

[0045] The inventors of the present disclosure have found through research that the aperture ratio of a display panel including the array substrate shown in Fig. 1 is small. Although the aperture ratio of a display panel including the array substrate shown in Fig. 1 can be slightly improved by reducing the width of the first and second wirings in the second direction, reducing the width of the first and second wirings in the second direction increases the risk of open circuits in the first and second wirings. Furthermore, signals in the first and second wirings may interfere with signals in other wirings on the array substrate.

[0046] At least one embodiment of the present disclosure provides an array substrate, a display panel, a display device, and a manufacturing method of the array substrate. The array substrate includes a group of pixel units. The pixel unit group includes a first pixel and a second pixel arranged adjacent to each other in parallel in a first direction, the first pixel including a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode, the second pixel including a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode, the first pixel electrode and the first switching element being electrically connected to each other via the first connection portion, and the second pixel electrode and the second switching element being electrically connected to each other via the second connection portion, and the extending length of the first connection portion is not equal to the extending length of the second connection portion.

[0047] In some examples, the extension length of the first connection portion is not equal to the extension length of the second connection portion (i.e., the array substrate has long connection pixels and short connection pixels), thereby providing the array substrate and the display panel and display device including the array substrate with the ability or basis for increased aperture ratio.

[0048] In some cases, the lateral capacitance of a long-connected pixel is not equal to the associated capacitance of a short-connected pixel, which may result in display unevenness (e.g., swaying stripes or swaying stripe defects) on an array substrate having the capability or foundation for enhancing aperture ratio. Swaying stripes are alternating light and dark stripes that can only be observed by a user of the display panel when the user sways. The swaying stripes are related to different pixel voltage jump amounts Δp of different pixels. Factors that affect the pixel voltage jump amount Δp of a pixel include the lateral capacitance of the pixel, which includes the capacitance Cgs due to the gate line and source / drain layer, the capacitance Cpg due to the pixel electrode and the gate line corresponding to the pixel electrode, and the capacitance Cpg' due to the pixel electrode and the gate line adjacent to the pixel electrode (which does not drive the pixel where the pixel electrode is located). For example, when the capacitance Cgs of the long-connection pixel and the capacitance Cgs of the short-connection pixel become closer, and / or the capacitance Cpg of the long-connection pixel and the capacitance Cpg of the short-connection pixel become closer, the pixel voltage jump amount Δp of the long-connection pixel and the pixel voltage jump amount Δp of the short-connection pixel become closer, thereby reducing the wobbling stripe phenomenon.For the sake of clarity, the definition of wobbling stripes, the causes of their occurrence, related factors, and experimental methods for observing and studying wobbling stripes will be described in detail later, so they will not be described in detail here.

[0049] In some examples, the orthogonal projection of the portion of the gate line (first gate line and second gate line) corresponding to each pixel (first pixel and second pixel) on the source / drain layer overlaps with one of the two source / drains of the pixel at at least two different positions, thereby reducing the variation range (deviation from the design value) of the capacitance Cgs due to the gate line and source / drain layer, and thereby suppressing display unevenness phenomena (for example, the swaying stripe phenomenon, swaying stripe defects).

[0050] In some examples, the overlap area between the orthogonal projection of the first gate line on the source-drain layer and one of the two first source-drains is equal to the overlap area between the orthogonal projection of the second gate line on the source-drain layer and one of the two second source-drains, so that the capacitance Cgs of the long-connection pixel is equal to the capacitance Cgs of the short-connection pixel, thereby further suppressing display unevenness phenomena (e.g., swaying stripe phenomenon, swaying stripe defect).

[0051] In some examples, when the horizontal spacing between the first pixel electrode and the gate line driving the first pixel is greater than 5 microns, the effect on the capacitance Cpg of the first pixel caused by variations in the horizontal spacing between the first pixel electrode and the gate line driving the first pixel (e.g., variations due to the manufacturing process) and variations in the effective overlap length between the coupling structure of the first pixel electrode and the first connection portion and the gate line driving the first pixel can be reduced; when the horizontal spacing between the second pixel electrode and the gate line driving the second pixel is greater than 5 microns, the effect on the capacitance Cpg of the second pixel caused by variations in the horizontal spacing between the second pixel electrode and the gate line driving the second pixel and variations in the effective overlap length between the coupling structure of the second pixel electrode and the second connection portion and the gate line driving the second pixel can be reduced, thereby reducing the requirements for the manufacturing process without degrading the display uniformity.

[0052] In some examples, by providing a recess in the pixel electrode of a long-connection pixel on the side closer to the gate line that drives the long-connection pixel, the effective overlap length lpg between the pixel electrode and the coupling structure of the connection part of the long-connection pixel and the gate line can be shortened. In this case, the effective overlap length between the pixel electrode and the coupling structure of the connection part of the long-connection pixel and the gate line becomes closer to the effective overlap length between the pixel electrode and the coupling structure of the connection part of the short-connection pixel and the gate line. Therefore, the capacitance Cpg of the long-connection pixel and the capacitance Cpg of the short-connection pixel become closer, thereby further suppressing the head-striping defect.

[0053] The following provides a non-limiting description of the array substrate according to the embodiments of the present disclosure by providing several examples and embodiments. As will be described below, if there is no conflict between them, different features in these specific examples and embodiments can be combined with each other to obtain new examples and embodiments, and these new examples and embodiments also fall within the scope of protection of the present disclosure.

[0054] FIG. 2A is a schematic plan view of an array substrate 100 according to at least one embodiment of the present disclosure. As shown in FIG. 2A, the array substrate 100 includes a plurality of pixel unit groups 110 arranged in an array, a plurality of first gate lines 141, a plurality of second gate lines 142, and a plurality of data lines 161, wherein the plurality of first gate lines 141 and the plurality of second gate lines 142 extend approximately in a first direction D1, and the plurality of data lines 161 extend in a second direction D2 that is approximately intersecting (e.g., perpendicular to) the first direction D1.

[0055] The pixel unit groups 110 in each row are driven by two gate lines (one first gate line 141 and one second gate line 142), which are located on both sides of the pixel unit group 110 in that row in the second direction D2 and adjacent to the pixel unit group 110 in that row. Here, the gate line being adjacent to the pixel unit group 110 means that there is no other gate line between the pixel unit group 110 and the gate line. Two gate lines are installed between two pixel unit groups 110 adjacent to each other in the second direction D2, and one data line is installed between two pixel unit groups 110 adjacent to each other in the first direction D1.

[0056] For clarity, one of the pixel unit groups 110 will be described below as an example.

[0057] 2B is a schematic plan view of the pixel unit group 110 of the array substrate 100 shown in FIG. 2A, and for convenience of explanation, FIG. 2B further shows a first gate line 141, a second gate line 142, and a data line 161. Some or all of the pixel unit groups 110 of the array substrate 100 shown in FIG. 2A can be realized as the pixel unit group 110 shown in FIG. 2B.

[0058] 2B, the pixel unit group 110 includes a first pixel and a second pixel arranged adjacent to each other in a first direction D1, where the first pixel and the second pixel arranged adjacent to each other in a parallel manner means that there is no other pixel between the first pixel and the second pixel.

[0059] As shown in FIG. 2B, the first pixel includes a first pixel electrode 121, a first switching element 123, and a first connection portion 122 extending from the first pixel electrode 121, and the second pixel includes a second pixel electrode 131, a second switching element 133, and a second connection portion 132 extending from the second pixel electrode 131, wherein the first pixel electrode 121 and the first switching element 123 are electrically connected to each other via the first connection portion 122, and the second pixel electrode 131 and the second switching element 133 are electrically connected to each other via the second connection portion 132, and the extension length of the first connection portion 122 is not equal to (for example, less than) the extension length of the second connection portion 132.

[0060] For example, in an example where the extension length of the first connection portion 122 is shorter than the extension length of the second connection portion 132, the first pixel may be referred to as a short-connection pixel, and the second pixel may be referred to as a long-connection pixel. For example, the pixel with the shorter extension length of the connection portion included in each pixel unit group is referred to as a short-connection pixel, and the pixel with the longer extension length of the connection portion included in each pixel unit group is referred to as a long-connection pixel. In some examples, all the short-connection pixels on the array substrate are referred to as first pixels, and all the long-connection pixels on the array substrate are referred to as second pixels.

[0061] For example, the extension length of the first connecting portion 122 is not equal to (for example, less than) the extension length of the second connecting portion 132, so that the first switching element 123 and the second switching element 133 are both installed at the edge of the pixel unit group 110 in the first direction D1, which will be described below as an example with reference to FIG. 2B.

[0062] For example, as shown in FIG. 2B, the pixel unit group 110 includes a first edge 111 and a second edge 112 facing each other in a first direction D1, and the first switching element 123 and the second switching element 133 are closer to the first edge 111 of the pixel unit group 110 in the first direction D1 than the second edge 112.

[0063] 2B , the first switching element 123 and the second switching element 133 of each pixel unit group 110 are connected to the same data line 161. For example, the first switching element 123 and the second switching element 133 of each pixel unit group 110 are the same distance from the same data line 161, and in this case, the length (length in the first direction D1) of the connecting line between the first switching element 123 of each pixel unit group 110 and the data line 161 that drives the pixel unit group 110 may be equal to the length (length in the first direction D1) of the connecting line between the second switching element 133 of each pixel unit group 110 and the data line 161 that drives the pixel unit group 110.

[0064] For example, as shown in FIG. 2A, switching elements connected to the same data line 161 include switching elements located on a first side (e.g., left side) of the same data line 161 and switching elements located on a second side (e.g., right side) of the same data line 161, and the switching elements located on the first side (e.g., left side) of the same data line 161 and the switching elements located on the second side (e.g., right side) of the same data line 161 partially overlap in the first direction D1.

[0065] For example, in at least some embodiments of the present disclosure, when structure A and structure B overlap (or partially overlap) in direction C, it means that the orthogonal projection of structure A on plane D perpendicular to direction C and the orthogonal projection of structure B on plane D overlap (or partially overlap).

[0066] For example, by partially overlapping the switching element located on the first side (e.g., the left side) of the same data line 161 and the switching element located on the second side (e.g., the right side) of the same data line 161 in the first direction D1, the dimension in the second direction D2 of the area occupied by the switching elements (first switching element 123 and second switching element 133) can be reduced, and therefore the dimension in the second direction D2 of the black matrix for shielding the switching elements can be reduced, thereby improving the aperture ratio of the array substrate 100, the display panel including the array substrate 100, and the display device.

[0067] For example, as shown in FIG. 2B, the first connection portion 122 and the second connection portion 132 of the pixel unit group 110 are located on both sides of the first pixel electrode 121 in the second direction D2, and the first connection portion 122 and the second connection portion 132 are located between the first gate line 141 and the second gate line 142 in the second direction D2.

[0068] 2B , the extension direction of the first connecting portion 122 is the second direction D2, and the extension direction of the second connecting portion 132 is the first direction D1. In one example, the extension length of the first connecting portion 122 is the length of the first connecting portion 122 in the second direction D2, and the extension length of the second connecting portion 132 is the length of the second connecting portion 132 in the first direction D1, i.e., the extension length of a connecting portion is the length of the connecting portion in its extension direction. In another example, the extension length of a connecting portion may be the total length or physical length of the connecting portion.

[0069] For example, the second connection portion 132 and the first pixel electrode 121 at least partially overlap in the second direction D2, and the first pixel electrode 121 is located between the first switching element 123 and the second switching element 133 in the second direction D2.

[0070] For example, the first connection portion 122 and the first pixel electrode 121 are integrally formed of the same material, and the second connection portion 132 and the second pixel electrode 131 are integrally formed of the same material.

[0071] For example, as shown in FIG. 2B , the first switching element 123 and the second switching element 133 are both adjacent to the same edge (e.g., the first edge 111) of the pixel unit group 110 in the first direction D1, the first connecting portion 122 and the first pixel electrode 121 are integrally formed of the same material, and the second connecting portion 132 and the second pixel electrode 131 are integrally formed of the same material. As a result, the first connecting portion 122 (a first end 1221 of the first connecting portion 122, see FIG. 6 below) and the first pixel electrode 121 are directly electrically connected, and the second connecting portion 132 (a first end 1321 of the second connecting portion 132, see FIG. 6 below) and the second pixel electrode 131 are directly electrically connected. Therefore, compared to the array substrate shown in FIG. 1 , it is possible to avoid providing vias in the region adjacent to the first pixel electrode 121 and the second pixel electrode 131, and accordingly This increases the area of ​​the display region of the first pixel and the display region of the second pixel, and although the first connection portion 122 (the second end 1222 of the first connection portion 122) is electrically connected to the first switching element 123 by the first via 1223 and the second connection portion 132 (the second end 1322 of the second connection portion 132) is electrically connected to the second switching element 133 by the second via 1323, the first via 1223 is close to the first switching element 123 and the second via 1323 is close to the second switching element 133, and the areas close to the first switching element 123 and the second switching element 133 also correspond to areas that are originally shielded by the black matrix, so it is possible to avoid a reduction in the aperture ratio of the pixel unit group 110 and the array substrate 100 due to the first via 1223 and the second via 1323 shown in Figure 2B.

[0072] For example, both the first pixel electrode 121 and the second pixel electrode 131 are formed of a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO). In an example where the first connecting portion 122 and the first pixel electrode 121 are integrally formed of the same material and the second connecting portion 132 and the second pixel electrode 131 are integrally formed of the same material, both the first connecting portion 122 and the second connecting portion 132 may be formed of a transparent conductive material (e.g., ITO). For example, the processing precision of a transparent conductive material (e.g., ITO) may be higher than that of a metal material, i.e., the width of the wiring made of the transparent conductive material may be smaller than the width of the wiring made of the metal material. In this case, the dimensions of the area occupied by the first connecting portion 122 and the second connecting portion 132 can be reduced, and the dimensions of the area occupied by the first pixel electrode 121 and the second pixel electrode 131 can be increased accordingly, thereby further improving the aperture ratio of the pixel unit group 110 and the array substrate 100.

[0073] 2A and 2B, the first switching element 123 and the second switching element 133 are both U-type TFTs. For example, as shown in FIG. 2A, the opening directions of the U-type TFTs of pixel unit groups in adjacent rows are opposite. For example, as shown in FIG. 2A, the opening direction of the U-type TFTs of the pixel unit group in the first row (odd row) is rightward, and the opening direction of the U-type TFTs of the pixel unit group in the second row (even row) is leftward. Correspondingly, the U-type TFTs of the pixel unit group in the first row (odd row) are disposed on the right side of the data line, and the U-type TFTs of the pixel unit group in the second row (even row) are disposed on the left side of the data line.

[0074] The inventors of the present disclosure have conducted research and found that although including long-connection pixels and short-connection pixels in the pixel unit group of the array substrate shown in Figure 2A can improve the aperture ratio of the array substrate, it may cause brightness unevenness phenomena (e.g., swaying stripe phenomenon, swaying stripe defect) on the array substrate shown in Figure 2A. The swaying stripe defect will be described in detail below with reference to Figures 2C to 2H.

[0075] Oscillating stripes are alternating light and dark stripes that are only visible when a user of a display panel oscillates. The left image in Figure 2C shows an image observed by a user of the display panel when the user is not oscillating, and the right image in Figure 2C shows an image observed by a user of the display panel when the user is oscillating (i.e., an image with the oscillating stripe defect), where the display panel is configured to display an image with a gray value of 127 (i.e., each pixel of the image is gray 127).

[0076] As shown in the right diagram of Figure 2C, the light and dark stripes of the oscillating stripes extend in the column direction of the display panel and alternate in the row direction of the display panel. For example, the oscillating stripes are expressed by a spatial frequency fs, which will be described below with reference to Figure 2D. Figure 2D is a schematic diagram showing an exemplary method for calculating the spatial frequency.

[0077] As shown in Figure 2D, the spatial frequency fs is the number of grid periods that sinusoidally modulate the brightness of an image (or stimulus figure) per degree of visual angle, or the number of periods of the brightness distribution of an image per degree of visual angle. The unit of the spatial frequency fs is periods / degree. The spatial frequency fs is expressed by Equation (1), and the optimal observation distance for the oscillating stripe phenomenon can be expressed by Equation (2).

[0078]

number

[0079]

number

[0080] where r is the observation distance, i.e., the distance from the user's eye 611 to the display panel 612, l is the width of a subpixel of the display panel (width in the row direction), n is the number of pixels per light-dark cycle, θ is the viewing angle, and dθ is one degree of viewing angle.

[0081] Research has shown that the human eye is most sensitive to oscillating stripes of different spatial frequencies and different brightness levels when the spatial frequency is equal to 8 cycles per degree. Therefore, the oscillating stripes of a display panel have an optimal viewing distance, determined by a single related parameter. Figure 2E shows the optimal viewing distances for oscillating stripes of different types of display panels. As shown in Figure 2E, the optimal viewing distance for oscillating stripes of most display panels is between 0.2 meters and 0.5 meters. Note that the "r / m" in Figure 2E represents the viewing distance r on the ordinate of Figure 2E, and the unit of viewing distance r is meters. "HD," "FHD," and "UHD" stand for "high definition," "full high definition," and "ultra high definition," respectively.

[0082] The following describes an example of the cause of the head-shaking stripe defect with reference to FIG. 2F. FIG. 2F illustrates the cause of the head-shaking stripe defect. As shown in FIG. 2F, the display panel displays adjacent first, second, third, fourth, fifth, sixth, seventh, and eighth frame images F1, F2, F3, F4, F5, F6, F7, and F8 frame images at time T. The image seen by the human eye is an averaged image of multiple temporally adjacent images. Therefore, when the user's head is stationary, the user cannot observe the head-shaking stripe phenomenon. However, when the user's head moves (e.g., by head movement), the user may not be able to observe some frame images (e.g., the user may not be able to observe frame images F4 through F6). This may prevent the user's eyes from properly averaging the observed images, resulting in the user seeing the head-shaking stripe phenomenon. For example, the user's eyes may not be able to eliminate the brightness difference between different pixels in the displayed image of the same frame by averaging the observed third and seventh frame images F3 and F7.

[0083] As shown in FIG. 2F, when the first frame image F1, the third frame image F3, the fifth frame image F5, and the seventh frame image F7 are displayed, the first pixel voltage applied to the pixel electrode is greater than the common voltage Vcom; when the second frame image F2, the fourth frame image F4, the sixth frame image F6, and the eighth frame image F8 are displayed, the second pixel voltage applied to the pixel electrode is less than the common voltage Vcom, and the voltage difference between the first pixel voltage and the common voltage Vcom is less than the voltage difference between the common voltage Vcom and the second pixel voltage; that is, the brightness of the second frame image F2, the fourth frame image F4, the sixth frame image F6, and the eighth frame image F8 is greater than the brightness of the first frame image F1, the third frame image F3, the fifth frame image F5, and the seventh frame image F7. For example, even if the common voltage Vcom shown in Figure 2F is adjusted and the voltage difference between the first pixel voltage and the common voltage Vcom is made equal to the voltage difference between the common voltage Vcom and the second pixel voltage, the user's eyes will not be able to properly average the observed third frame image F3 and seventh frame image F7 because the fourth frame image F4 to the sixth frame image F6 cannot be observed, and in this case, the user may also see the shaking stripe phenomenon.

[0084] For example, the main factors affecting the brightness of a pixel in a positive frame and a negative frame include the common electrode voltage (VCOM), the pixel voltage jump (ΔVp), and the voltage holding ratio (VHR). Figure 2G is a schematic diagram of the charging and discharging of a pixel of a display panel, showing the time-dependent changes in the drain voltage Vd, common voltage VCOM, pixel voltage Vp, and gate voltage Vg of the pixel of the display panel. As shown in Figure 2G, each display period of the pixel includes adjacent first and second display frames F1 and F2. The second display frame F2 is, for example, an inverted display frame, and in the second display frame F2, the polarity of the voltage of the pixel electrode of each pixel on the array substrate is opposite to that of the first display frame F1. Both the first and second display frames F1 and F2 include a voltage writing period Tw and a voltage holding period Th.

[0085] As shown in Figure 2G, at the beginning of the voltage write phase Tw, the absolute value of the difference between the drain voltage Vd and the common voltage Vcom jumps, and ΔVp is the jump amount of the absolute value of the difference between the drain voltage Vd and the common voltage Vcom, also known as the jump amount of the pixel voltage. As shown in Figure 2G, during the voltage write phase Tw, the absolute value of the difference between the drain voltage Vd and the common voltage Vcom gradually decreases, and Vh is the holding voltage.

[0086] In theory, for the same pixel, the positive frame luminance can be made equal to the negative frame luminance by adjusting the common voltage Vcom. However, since the optimal common voltage Vcom values ​​of multiple pixels included in a display panel are different, in practice, it may be difficult to completely eliminate the luminance difference between adjacent display frames by adjusting the common voltage Vcom.

[0087] As shown in FIG. 2G, the inventors of the present disclosure have found through research that, if the voltage holding ratio (VHR) is not taken into consideration, the pixel voltage jump amount ΔVp has a large impact on the brightness difference between adjacent display frames and the brightness uniformity of the same display frame (e.g., the wobbling stripe phenomenon), which is particularly evident in the case of a display panel employing a dual gate structure. This is because the structures of adjacent sub-pixels in a display panel employing a dual gate structure may be different, and this is hereinafter explained by way of example with reference to FIG. 2H.

[0088] 2H is a schematic diagram showing capacitances associated with pixels of a display panel. As shown in FIG. 2H, the capacitances associated with the pixels include capacitances Cgs, Cpg, Cpg', Cpd, Cpd', Cst, and Clc, and the jump amount ΔVp of the pixel voltage can be expressed by the following equation (3):

[0089]

number

[0090] Here, the capacitance Cgs is a capacitance formed between one of the source and drain of the switching element and a gate line (and / or gate) for driving the switching element, the capacitance Cpg is a horizontal capacitance formed between the pixel electrode and a gate line (and / or gate) for driving the pixel in which the pixel electrode is located, the capacitance Cpg' is a horizontal capacitance formed between the pixel electrode and a gate line (not for driving the pixel in which the pixel electrode is located) adjacent to the pixel electrode, and the capacitance Cpd is a horizontal capacitance formed between the pixel electrode and a data line for driving the pixel in which the pixel electrode is located. The capacitance Cpd' is a horizontal capacitance formed between the pixel electrode and the data line adjacent to the pixel electrode (not for driving the pixel where the pixel electrode is located), the capacitances Cst and Clc are storage capacitances of the pixel, COM is a common electrode, Vgh and Vgl are the first and second levels of the gate scanning signal received by the gate line, respectively, the voltage value of the first level is greater than the voltage value of the second level, GLn and GLn+1 are the gate lines in the nth row and the n+1th row, respectively, and DLn and DLn+1 are the data lines in the nth column and the n+1th column, respectively.

[0091] Through research, the inventors of the present disclosure have found that the sway stripe defect correlates with the difference in luminance between different sub-pixels of the same frame image (the theoretical gray scales of different sub-pixels are the same), and that the difference in luminance between different sub-pixels of the same frame image correlates with the difference in the jump amount ΔVp of the pixel voltage of different sub-pixels.

[0092] The inventors of the present disclosure have conducted research and found that at least one of the following may cause brightness unevenness problems (e.g., a wobbling stripe problem) in the array substrate shown in FIG. 2A: (1) the source-drain metal layer of the array substrate is offset relative to the gate metal layer; (2) the capacitance Cpg of the long-connection pixel of the array substrate is not equal to the capacitance Cpg of the short-connection pixel; and (3) the capacitance Cpg' of the long-connection pixel of the array substrate is not equal to the capacitance Cpg' of the short-connection pixel.

[0093] Hereinafter, the problem of uneven brightness caused by the source / drain metal layer of the array substrate being offset with respect to the gate metal layer will be described with reference to FIGS. 3A to 3C.

[0094] 3A is a schematic diagram of the array substrate shown in FIG. 2A, FIG. 3B is an enlarged view of a region RC1 of the array substrate shown in FIG. 2A, and FIG. 3C is an enlarged view of a region RC2 of the array substrate shown in FIG. 2A.

[0095] 3A shows a plurality of first gate lines, a plurality of second gate lines, a plurality of data lines, and a group of pixel units arranged in an array. As shown in FIG. 3A, the plurality of first gate lines include gate line GL1_1, gate line GL2_1, gate line GL3_1, and gate line GL4_1, the plurality of second gate lines include gate line GL1_2, gate line GL2_2, gate line GL3_2, and gate line GL4_2, the plurality of data lines include data lines DL1 to DL7, and the group of pixel units arranged in an array includes, for example, pixel P11_1, pixel P11_2, pixel P12_1, pixel P12_2, pixel P21_1, pixel P21_2, pixel P22_1, and pixel P22_2.

[0096] Figure 3B is an enlarged view of region RC1 of the array substrate shown in Figure 2A, i.e., Figure 3B shows the overlap region 201 between one of the source / drain of the switching element of pixel P11_2 and the gate line (and / or gate) for driving the switching element, and Figure 3C is an enlarged view of region RC2 of the array substrate shown in Figure 2A, i.e., Figure 3C shows the overlap region 202 between one of the source / drain of the switching element of pixel P11_1 and the gate line (and / or gate) for driving the switching element.

[0097] As shown in Figures 3B and 3C, when the source drain of the switching element moves to the right relative to the gate of the switching element (i.e., the source drain metal layer of the array substrate is offset to the right relative to the gate metal layer), the areas of overlap region 201 and overlap region 202 decrease, and therefore the capacitance Cgs of pixel P11_2 and the capacitance Cgs of pixel P11_1 both decrease, and the pixel voltage jump amount ΔVp of pixel P11_2 and the pixel voltage jump amount ΔVp of pixel P11_1 both decrease.

[0098] As shown in Figures 2A and 3A, the opening direction of the U-shaped electrodes (i.e., the other of the source and drain of the switching elements) of pixels P12_1 and P12_2 is the same as the opening direction of the U-shaped electrodes of the switching elements of pixels P11_1 and P11_2, so when the source and drain of the switching elements move to the right relative to the gate of the switching element, the capacitance Cgs and the pixel voltage jump amount ΔVp of pixels P12_2 and P12_1 also decrease.

[0099] As shown in Figures 2A and 3A, the opening direction of the U-shaped electrodes of the switching elements of pixels P21_1, P21_2, P22_1, and P22_2 is opposite to the opening direction of the U-shaped electrodes of the switching elements of pixels P11_1 and P11_2, so when the source drain of the switching element moves to the right relative to the gate of the switching element, the capacitance Cgs and the pixel voltage jump amount ΔVp of pixels P21_1, P21_2, P22_1, and P22_2 all increase.

[0100] As shown in FIG. 3A, pixels P11_1 and P11_2 are both connected to the data line DL1 of the first column, pixels P12_1, P12_2, P21_1 and P21_2 are both connected to the data line DL2 of the second column, pixels P22_1 and P22_2 are both connected to the data line DL2 of the third column, and the voltages applied to data lines DL1 and DL2 are opposite, and the voltages applied to data lines DL1 and DL3 are the same.

[0101] As shown in FIG. 3A, in an example where the voltages applied to the data lines DL1, DL2, and DL3 are positive, negative, and positive, respectively (pixels P11_1, P11_2, P22_1, and P222 are all in a positive display frame, and pixels P12_1, P12_2, P21_1, and P21_2 are all in a negative display frame), and the luminance of a pixel is negatively correlated with the absolute value of the difference between the pixel voltage of the pixel and the common voltage, the luminance of the pixel unit group in the odd-numbered columns is low, and the luminance of the pixel unit group in the even-numbered columns is low. A pixel in a positive display frame means that the voltage of the pixel electrode of the pixel is a positive voltage, and a pixel in a negative display frame means that the voltage of the pixel electrode of the pixel is a negative voltage. Hereinafter, an exemplary description will be given with reference to FIGS. 3A, 3D, and 3E.

[0102] Figure 3D is a schematic diagram of the pixel voltages of pixels in the pixel unit group in odd columns when the source-drain metal layer is not offset (dashed line) and when it is offset (solid line) relative to the gate metal layer, and Figure 3E is a schematic diagram of the pixel voltages of pixels in the pixel unit group in even columns when the source-drain metal layer is not offset (dashed line) and when it is offset (solid line) relative to the gate metal layer.

[0103] As shown in FIGS. 3A and 3D, the jump amounts ΔVp of the pixel voltages of the pixels P11_1 and P11_2 both decrease, and the pixels P11_1 and P11_2 are both in the positive display frame. Therefore, the pixel voltages Vp of the pixels P11_1 and P11_2 both increase, and the absolute values ​​|Vp-Vcom| of the differences between the pixel voltages of the pixels P11_1 and P11_2 and the common voltage both increase. 2 are both dark, the pixel voltage jump amounts ΔVp of pixels P21_1 and P21_2 both increase, and pixels P21_1 and P21_2 are both in negative display frames, therefore the pixel voltages Vp of pixels P21_1 and P21_2 both decrease, the absolute values ​​|Vp-Vcom| of the differences between the pixel voltages of pixels P21_1 and P21_2 and the common voltage both increase, and pixels P21_1 and P21_2 are both dark.

[0104] As shown in FIGS. 3A and 3E, the jump amounts ΔVp of the pixel voltages of the pixels P12_1 and P12_2 both decrease, and the pixels P12_1 and P12_2 are both in the negative display frame. Therefore, the pixel voltages Vp of the pixels P12_1 and P12_2 both increase, and the absolute values ​​|Vp-Vcom| of the differences between the pixel voltages of the pixels P12_1 and P12_2 and the common voltage both decrease. are both bright, the jump amounts ΔVp of the pixel voltages of pixels P22_1 and P22_2 both increase, and pixels P22_1 and P22_2 are both in the positive display frame; therefore, the pixel voltages Vp of pixels P22_1 and P22_2 both decrease, and the absolute values ​​|Vp-Vcom| of the differences between the pixel voltages of pixels P12_1 and P12_2 and the common voltage both decrease, and pixels P12_1 and P12_2 are both bright.

[0105] Therefore, in the same image frame, there may be a problem of display unevenness (for example, a problem of wavy stripes) in the image displayed by a display panel including the array substrate shown in FIG. 2A.

[0106] 3F and 3G, the problem of uneven brightness caused by the capacitance Cpg of a long-connected pixel on the array substrate being unequal (larger) than the capacitance Cpg of a short-connected pixel will be described. Parameters that affect the capacitance Cpg of a pixel include the horizontal spacing dpg and the effective overlap length lpg.

[0107] Figure 3F shows the coupling structure of the pixel electrode and connection part of a short-connection pixel (first pixel, P11_1) and the effective overlap length lpg1 and horizontal spacing dpg1 between the pixel electrode and connection part and the gate line that drives the short-connection pixel, and Figure 3F further shows the coupling structure of the pixel electrode and connection part of a long-connection pixel (second pixel, P11_2) and the effective overlap length lpg2 and horizontal spacing dpg2 between the pixel electrode and connection part and the gate line that drives the long-connection pixel.

[0108] As shown in Figure 3F, the horizontal spacing dpg of a pixel is the spacing between the pixel electrode of the pixel (the edge of the pixel electrode closest to the gate line for driving the pixel) and the gate line for driving the pixel (the edge of the gate line closest to the pixel electrode).

[0109] 3F, the effective overlap length lpg1 (lpg1 = lpg1_1 + lpg1_2) of the short-connection pixel (first pixel) is smaller than the effective overlap length lpg2 of the long-connection pixel (second pixel). For example, when the horizontal spacing dpg1 of the short-connection pixel and the horizontal spacing dpg2 of the long-connection pixel are the same or close to each other, the capacitance Cpg of the short-connection pixel is smaller than the capacitance Cpg of the long-connection pixel, and therefore the pixel voltage jump amount ΔVp of the short-connection pixel is smaller than the pixel voltage jump amount ΔVp of the long-connection pixel.

[0110] 2A and 3A, the pixel P21_1 is also a long-connection pixel. Fig. 3G is a schematic diagram showing a comparison of pixel voltages between the short-connection pixel P11_1 and the long-connection pixel P21_1 in a positive display frame and a negative display frame.

[0111] As shown in FIG. 3G, in the first image frame F1, the short connection pixel P11_1 is in a positive display frame and the long connection pixel P21_1 is in a negative display frame, and in the second image frame F2, the short connection pixel P11_1 is in a negative display frame and the long connection pixel P21_1 is in a positive display frame.

[0112] As shown in Figure 3G, since the pixel voltage jump amount ΔVp of the short-connection pixel is smaller than the pixel voltage jump amount ΔVp of the long-connection pixel, in the first image frame F1, the short-connection pixel P11_1 and the long-connection pixel P21_1 are both dark, and in the second image frame F2, the short-connection pixel P11_1 and the long-connection pixel P21_1 are both bright, which is explained below as an example with reference to Figure 3G.

[0113] As shown in FIG. 3G, in the first image frame F1, the pixel voltage Vp of the short-connection pixel P11_1 in the positive display frame increases, and the absolute value |Vp-Vcom| of the difference between the pixel voltage Vp and the common voltage Vcom increases. Meanwhile, the pixel voltage Vp of the long-connection pixel P21_1 in the negative display frame decreases, and the absolute value |Vp-Vcom| of the difference between the pixel voltage Vp and the common voltage Vcom increases. Therefore, in the first image frame F1, the short-connection pixel P11_1 and the long-connection pixel P21_1 are both dark. For the same reason, in the first image frame F1, other pixels in the column in which the short-connection pixel P11_1 and the long-connection pixel P21_1 are located are also dark. For the same reason, in the first image frame F1, all pixels in the column in which the long-connection pixel P11_2 and the short-connection pixel P21_2 are located are bright.

[0114] As shown in FIG. 3G, in the second image frame F2, the pixel voltage Vp of the short-connection pixel P11_1 in the negative display frame increases, and the absolute value |Vp-Vcom| of the difference between the pixel voltage Vp and the common voltage Vcom decreases. Meanwhile, the pixel voltage Vp of the long-connection pixel P21_1 in the positive display frame decreases, and the absolute value |Vp-Vcom| of the difference between the pixel voltage Vp and the common voltage Vcom decreases. Therefore, in the first image frame F1, both the short-connection pixel P11_1 and the long-connection pixel P21_1 are bright. For the same reason, in the second image frame F2, other pixels in the column in which the short-connection pixel P11_1 and the long-connection pixel P21_1 are located are also bright. For the same reason, in the first image frame F1, all pixels in the column in which the long-connection pixel P11_2 and the short-connection pixel P21_2 are located are dark.

[0115] As shown in Figure 3G, when only the short-connection pixel P11_1 is considered, the common voltage should be increased from Vcom to Vcom_S (the optimal common voltage for the short-connection pixel P11_1), whereas when only the long-connection pixel P21_1 is considered, the common voltage should be decreased from Vcom to Vcom_L (the optimal common voltage for the long-connection pixel P21_1). Therefore, by adjusting the common voltage, it is difficult to eliminate the phenomenon of uneven brightness in the image caused by the difference between the Cpg of the long-connection pixel and the Cpg of the short-connection pixel (pixels in the same column are both bright or both dark in the same image frame).

[0116] 3H to 3J, the problem of brightness unevenness caused by the capacitance Cpg′ of a long-connected pixel on the array substrate being unequal (larger) than the capacitance Cpg′ of a short-connected pixel will be described. For example, parameters that affect the capacitance Cpg′ of a pixel include the horizontal spacing dpg′ and the effective overlap length lpg′.

[0117] FIG. 3H is a schematic diagram (obtained by scanning electron microscope) of region RC1 of the array substrate shown in FIG. 2A, and FIG. 3I is a schematic diagram (obtained by scanning electron microscope) of region RC3 of the array substrate shown in FIG. 2A.

[0118] As shown in Figure 3H, the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 (not for driving the first pixel in which the first pixel electrode 121 is located, i.e., the second gate line 142) overlap in the second direction D2, and as shown in Figure 3I, the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 (not for driving the second pixel in which the second pixel electrode 131 is located, i.e., the second gate line 142) overlap in the second direction D2.

[0119] 2A, 3H, and 3I, the second pixel electrode 131 shown in FIG. 3I and the first pixel electrode 121 shown in FIG. 3H are located in two different pixel unit groups (two pixel unit groups adjacent in the second direction D2). (2) As shown in FIG. 2A, 3H, and 3I, the second pixel electrode 131 located in the same pixel unit group as the first pixel electrode 121 shown in FIG. 3H is located below the gate line adjacent thereto. Therefore, before charging the pixel in which the second pixel electrode 131 located in the same pixel unit group as the first pixel electrode 121 shown in FIG. 3H is located, the gate line adjacent thereto has already been scanned. Therefore, the charging process of the second pixel electrode 131 located in the same pixel unit group as the first pixel electrode 121 shown in FIG. 3H is not affected (or is only slightly affected) by the gate line adjacent thereto.

[0120] As shown in Figures 3H and 3I, the distance in the second direction D2 between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 (for example, the second gate line 142) is defined as the horizontal distance dpg1', and the distance in the second direction D2 between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 (for example, the second gate line 142) is defined as the horizontal distance dpg2'.

[0121] As shown in Figures 3H and 3I, the effective overlap length lpg1' between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 is the length in the first direction D1 of the region where the horizontal spacing between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 is equal to or less than a predetermined spacing (for example, equal to or less than the horizontal spacing dpg1'), and the effective overlap length lpg2' between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 is the length in the first direction D1 of the region where the horizontal spacing dpg2' between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 is equal to or less than a predetermined spacing (for example, equal to or less than the horizontal spacing dpg2').

[0122] For example, in the case of an array substrate that employs GOA (row-driven array substrate) to drive gate lines, the array substrate has a precharge function, and the pixel voltage of the pixel (e.g., the pixel driven by the odd-numbered gate line) is further reduced by the capacitance Cpg', which will be described below as an example with reference to Figure 3J.

[0123] FIG. 3J is a schematic diagram of the effect of capacitance Cpg' on pixel voltage Vp. As shown in FIG. 3J, Vgate1 is the gate line of an odd row, Vgate2 is the gate line of an even row, and Vp is the pixel voltage of a pixel in an even row. As shown in FIG. 3J, when the signal on the gate line of an odd row is at a rising edge, the pixel voltage Vp of the pixel has an additional increment due to the effect of capacitance Cpg'. However, since the pixel is in a charging phase at this time, this additional increment is eliminated. As shown in FIG. 3J, when the signal on the gate line of an even row is at a falling edge, the pixel voltage Vp of the pixel has an additional decrement ΔVp' due to the effect of capacitance Cpg'. However, since the pixel is not in a charging phase at this time, this additional increment cannot be eliminated.

[0124] For example, the inventors of the present disclosure have found through research that when the capacitance Cgs of the long-connection pixel and the capacitance Cgs of the short-connection pixel are closer and / or the capacitance Cpg of the long-connection pixel and the capacitance Cpg of the short-connection pixel are closer, the pixel voltage jump amount ΔVp of the long-connection pixel and the pixel voltage jump amount ΔVp of the short-connection pixel are closer, thereby reducing display unevenness (for example, the wobbly stripe phenomenon). Hereinafter, an example will be described with reference to FIG. 4A.

[0125] 4A is a schematic plan view of another array substrate 100 according to at least one embodiment of the present disclosure. The differences between the array substrate 100 shown in FIG. 4A and the array substrate shown in FIG. 2A include: (1) the array substrate 100 shown in FIG. 4A has Cgs compensation capability; (2) the pixel electrodes of the long-connection pixels of the array substrate 100 shown in FIG. 4A have recesses on the sides closer to the gate lines that drive the long-connection pixels; (3) the first and second vias of the array substrate 100 shown in FIG. 4A are different from the first and second vias of the array substrate 100 shown in FIG. 2A; and (4) the common electrode pattern of the array substrate 100 shown in FIG. 4A is different from the common electrode pattern of the array substrate 100 shown in FIG. 2A.

[0126] It should be noted that the differences between the array substrate according to other embodiments of the present disclosure and the array substrate shown in FIG. 2A may include only the above four distinguishing features (e.g., any combination of one or more), and will not be described in detail here.

[0127] The array substrate 100 shown in FIG. 4A will be exemplarily described below with reference to FIGS. 4A to 4E, 5A to 5H, and 6 to 11. FIG.

[0128] As shown in FIG. 4A, the array substrate 100 includes a plurality of pixel unit groups 110 arranged in an array, a plurality of first gate lines 141, a plurality of second gate lines 142, and a plurality of data lines 161, wherein the plurality of first gate lines 141 and the plurality of second gate lines 142 each extend approximately in a first direction D1, and the plurality of data lines 161 extend in a second direction D2 that intersects (e.g., is perpendicular to) the first direction D1.

[0129] Each row of pixel unit groups 110 is driven by two gate lines, and the two gate lines (one first gate line 141 and one second gate line 142) are located on both sides of the pixel unit group 110 of that row in the second direction D2 and are adjacent to the pixel unit group 110 of that row. Here, a gate line being adjacent to the pixel unit group 110 means that there is no other gate line between the pixel unit group 110 and the gate line. Two gate lines are installed between two pixel unit groups 110 adjacent to each other in the second direction D2, and one data line is installed between two pixel unit groups 110 adjacent to each other in the first direction D1. This will be described below with reference to FIG. 4A.

[0130] As shown in FIG. 4A, the pixel unit group 110 in each row corresponds to one of the plurality of first gate lines 141 and one of the plurality of second gate lines 142, and the one of the plurality of first gate lines 141 and the one of the plurality of second gate lines 142 are located on both sides of the pixel unit group 110 in the row in the second direction D2 and are configured to drive the pixel unit group 110 in the row.

[0131] As shown in FIG. 4A, one first gate line 141 and one second gate line 142 are disposed between adjacent pixel unit groups 110 in the column direction (i.e., the second direction D2), and are used to drive the pixel unit groups 110 in adjacent rows, respectively. For example, the plurality of first gate lines 141 and the plurality of second gate lines 142 are configured to drive the pixel unit groups 110 adjacent to them (i.e., there are no other gate lines between the gate line and the pixel unit group 110 driven by the gate line). As shown in FIG. 4A, one data line 161 is disposed between adjacent pixel unit groups 110 in the row direction (i.e., the first direction D1). As shown in FIG. 4A, the plurality of first gate lines 141 and the plurality of second gate lines 142 are alternately arranged in the second direction D2.

[0132] Note that the fact that the first gate lines 141 and the second gate lines 142 extend substantially in the first direction D1 does not mean that the first gate lines 141 and the second gate lines 142 are parallel to the first direction D1, but only limits the direction in which the lengths of the first gate lines 141 and the second gate lines 142 extend. That is, according to actual application needs, the first gate lines 141 and the second gate lines 142 may be parallel to the first direction D1 or may be partially non-parallel to the first direction D1. For example, to further improve the aperture ratio of the array substrate 100, partial regions of the first gate lines 141 and the second gate lines 142 may be designed to be curved. For example, the data line 161 may be parallel to the second direction D2 or may be partially non-parallel to the second direction D2.

[0133] For clarity, one pixel unit group 110 among the plurality of pixel unit groups 110 will be exemplarily described below.

[0134] 4B is a schematic plan view of the pixel unit group 110 of the array substrate 100 shown in FIG. 4A, and for convenience of explanation, FIG. 4B further shows a first gate line 141, a second gate line 142, and a data line 161. Some or all of the pixel unit groups 110 of the array substrate 100 shown in FIG. 4A can be realized as the pixel unit group 110 shown in FIG. 4B.

[0135] 4B, the pixel unit group 110 includes a first pixel and a second pixel arranged adjacent to each other in a first direction D1, where the first pixel and the second pixel arranged adjacent to each other in a parallel manner means that there is no other pixel between the first pixel and the second pixel.

[0136] As shown in FIG. 4B, the first pixel includes a first pixel electrode 121, a first switching element 123, and a first connection portion 122 extending from the first pixel electrode 121, and the second pixel includes a second pixel electrode 131, a second switching element 133, and a second connection portion 132 extending from the second pixel electrode 131, wherein the first pixel electrode 121 and the first switching element 123 are electrically connected to each other via the first connection portion 122, and the second pixel electrode 131 and the second switching element 133 are electrically connected to each other via the second connection portion 132, and the extension length of the first connection portion 122 is not equal to (for example, less than) the extension length of the second connection portion 132.

[0137] For example, the extension length of the first connecting portion 122 is not equal to (for example, less than) the extension length of the second connecting portion 132, so that the first switching element 123 and the second switching element 133 are both installed at the edge of the pixel unit group 110 in the first direction D1, which will be described below as an example with reference to FIG. 4B.

[0138] For example, as shown in FIG. 4B, the pixel unit group 110 includes a first edge 111 and a second edge 112 facing each other in a first direction D1, and the first switching element 123 and the second switching element 133 are closer to the first edge 111 of the pixel unit group 110 in the first direction D1 than the second edge 112.

[0139] 4B , the first switching element 123 and the second switching element 133 of each pixel unit group 110 are connected to the same data line 161. For example, the distances between the first switching element 123 and the second switching element 133 of each pixel unit group 110 and the same data line 161 may be the same, and in this case, the length (length in the first direction D1) of the connection line between the first switching element 123 of each pixel unit group 110 and the data line 161 that drives the pixel unit group 110 may be equal to the length (length in the first direction D1) of the connection line between the second switching element 133 of each pixel unit group 110 and the data line 161 that drives the pixel unit group 110.

[0140] For example, as shown in FIG. 4A, switching elements connected to the same data line 161 include switching elements located on a first side (e.g., left side) of the same data line 161 and switching elements located on a second side (e.g., right side) of the same data line 161, and the switching elements located on the first side (e.g., left side) of the same data line 161 and the switching elements located on the second side (e.g., right side) of the same data line 161 partially overlap in the first direction D1.

[0141] For example, by partially overlapping the switching element located on the first side (e.g., the left side) of the same data line 161 and the switching element located on the second side (e.g., the right side) of the same data line 161 in the first direction D1, the dimension in the second direction D2 of the area occupied by the switching elements (first switching element 123 and second switching element 133) can be reduced, and therefore the dimension in the second direction D2 of the black matrix for shielding the switching elements can be reduced, thereby improving the aperture ratio of the array substrate 100, the display panel including the array substrate 100, and the display device.

[0142] For example, as shown in FIG. 4B, the first connection portion 122 and the second connection portion 132 of the pixel unit group 110 are located on both sides of the first pixel electrode 121 in the second direction D2, and both the first connection portion 122 and the second connection portion 132 are located between the first gate line 141 and the second gate line 142 in the second direction D2.

[0143] For example, as shown in FIG. 4B, the extension direction of the first connection portion 122 is the second direction D2, the extension direction of the second connection portion 132 is the first direction D1, in the second direction D2 the second connection portion 132 and the first pixel electrode 121 at least partially overlap, and in the second direction D2 the first pixel electrode 121 is located between the first switching element 123 and the second switching element 133.

[0144] For example, as shown in FIG. 4B, the first switching element 123 and the second switching element 133 are arranged symmetrically in the second direction D2 with respect to the center line of the first pixel electrode 121 (or the pixel unit group 110) extending along the first direction D1 (you may also refer to FIG. 4D below).

[0145] For example, the first connecting portion 122 and the first pixel electrode 121 are integrally formed from the same material, and the second connecting portion 132 and the second pixel electrode 131 are integrally formed from the same material. For example, the first connecting portion 122, the first pixel electrode 121, the second connecting portion 132, and the second pixel electrode 131 may be formed by patterning the same film layer using the same patterning process.

[0146] For example, as shown in FIG. 4B , the first switching element 123 and the second switching element 133 are adjacent to the same edge (for example, the first edge 111) of the pixel unit group 110 in the first direction D1, the first connecting portion 122 and the first pixel electrode 121 are integrally formed of the same material, and the second connecting portion 132 and the second pixel electrode 131 are integrally formed of the same material. As a result, the first connecting portion 122 (a first end 1221 of the first connecting portion 122, see FIG. 6 below) and the first pixel electrode 121 are directly electrically connected, and the second connecting portion 132 (a first end 1321 of the second connecting portion 132, see FIG. 6 below) and the second pixel electrode 131 are directly electrically connected. Therefore, compared to the array substrate shown in FIG. 1 , it is possible to avoid providing vias in the region adjacent to the first pixel electrode 121 and the second pixel electrode 131, thereby The area of ​​the display region of the first pixel and the display region of the second pixel can be increased, and even though the first connection portion 122 (the second end 1222 of the first connection portion 122) is electrically connected to the first switching element 123 by the first via 1223 and the second connection portion 132 (the second end 1322 of the second connection portion 132) is electrically connected to the second switching element 133 by the second via 1323, the first via 1223 is close to the first switching element 123 and the second via 1323 is close to the second switching element 133, and the areas close to the first switching element 123 and the second switching element 133 also correspond to areas that are originally shielded by the black matrix, so a reduction in the aperture ratio of the pixel unit group 110 and the array substrate 100 due to the first via 1223 and the second via 1323 shown in Figure 4B can be avoided.

[0147] For example, both the first pixel electrode 121 and the second pixel electrode 131 are formed of a transparent conductive material. For example, the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO). In an example where the first connecting portion 122 and the first pixel electrode 121 are integrally formed of the same material and the second connecting portion 132 and the second pixel electrode 131 are integrally formed of the same material, both the first connecting portion 122 and the second connecting portion 132 may be formed of a transparent conductive material (for example, ITO). For example, the processing precision of a transparent conductive material (for example, ITO) may be higher than the processing precision of a metal material, i.e., the width of a wiring made of a transparent conductive material may be smaller than the width of a wiring made of a metal material. In this case, the dimensions of the area occupied by the first connecting portion 122 and the second connecting portion 132 can be reduced, and the dimensions of the area occupied by the first pixel electrode 121 and the second pixel electrode 131 can be increased accordingly, thereby improving the aperture ratio of the pixel unit group 110 and the array substrate 100.

[0148] For example, as shown in FIG. 4A , the switching elements connected to the same data line and located on the right side of the same data line are both used to drive pixel units in odd rows (or even rows), and the switching elements connected to the same data line and located on the left side of the same data line are both used to drive pixel units in even rows (or odd rows).

[0149] For example, as shown in Fig. 4A, the first switching elements 123 and second switching elements 133 for driving each pixel unit group are disposed at the edge where the short-connected pixels of the pixel unit group are disposed in the first direction. For example, as shown in Fig. 4A, the first switching elements 123 and second switching elements 133 of the pixel unit groups in odd-numbered rows (or even-numbered rows) are disposed at the left side of the pixel unit groups, and the first switching elements 123 and second switching elements 133 of the pixel unit groups in even-numbered rows (or odd-numbered rows) are disposed at the right side of the pixel unit groups.

[0150] For example, the first switching element 123 and the second switching element 133 are both thin film transistors (TFTs). For example, as shown in FIGS. 4A and 4B, the first switching element 123 and the second switching element 133 are both U-shaped thin film transistors, i.e., the source (or drain) of the thin film transistor is a U-shaped electrode, at least a portion of the drain (or source) of the thin film transistor is disposed within the opening of the U-shaped electrode, and the source and drain of the U-shaped thin film transistor at least partially overlap in the second direction D2. For example, as shown in FIG. 4A, the opening directions of the U-shaped TFTs for driving adjacent rows are opposite. For example, as shown in FIG. 4A, the opening direction of the U-shaped TFT for driving the first row is rightward, and the opening direction of the U-shaped TFT for driving the second row is leftward.

[0151] For example, the array substrate 100 may include a first electrode layer 172 (see FIG. 4C), a first insulating layer 173 (see FIG. 5C), a semiconductor layer 174 (see FIG. 5A and FIG. 5C), a second electrode layer 175 (see FIG. 5A), a second insulating layer 176 (see FIG. 5C), and a third electrode layer 177 (see FIG. 6), and the first electrode layer 172, the first insulating layer 173, the semiconductor layer 174, the second electrode layer 175, the second insulating layer 176, and the third electrode layer 177 are, for example, sequentially disposed on a base substrate 171.

[0152] 4C is a schematic plan view of the first electrode layer 172 of the array substrate shown in FIG. 4A. As shown in FIG. 4C, the first electrode layer 172 includes a plurality of first gate lines 141, a plurality of second gate lines 142, and a common electrode pattern 150 arranged in an array, where the plurality of first gate lines 141 and the plurality of second gate lines 142 are alternately arranged in the second direction D2, the plurality of common electrode patterns 150 correspond one-to-one to the plurality of pixel unit groups 110, and the plurality of common electrode patterns 150 in the same row are located between the first gate lines 141 and the second gate lines 142 for driving the pixel unit groups 110 corresponding to the plurality of common electrode patterns 150 in the same row. Note that in some examples, the first electrode layer 172 may not include a common electrode pattern.

[0153] For clarity, the specific structure of the common electrode patterns 150 and the connection method between the common electrode patterns 150 will be described in detail later, and the structures of the first gate line 141 and the second gate line 142 will be described below with reference to Figures 4D and 4E.

[0154] FIG. 4D is a schematic plan view showing the first gate line 141 and the second gate line 142 of the array substrate shown in FIG. 4A.

[0155] For example, as shown in Figures 4A and 4D, the first gate line 141 for driving each pixel unit group 110 and the second gate line 142 for driving each pixel unit group 110 and the pixel unit group 110 adjacent to each pixel unit group 110 in the second direction D2 partially overlap in the first direction D1, i.e., the first gate line 141 and the second gate line 142 located between the pixel unit groups 110 adjacent to each other in the second direction D2 partially overlap in the first direction D1, thereby reducing the dimension of the area occupied by the gate line in the second direction D2, and thereby improving the aperture ratio of the array substrate 100 and the aperture ratio of the display panel and display device including the array substrate 100.

[0156] For example, as shown in FIG. 4D, the first gate line 141 and the second gate line 142 are arranged symmetrically in the second direction D2 with respect to the center line 113 of the pixel unit group 110 extending along the first direction D1.

[0157] 4E is a schematic plan view showing portions of the first gate line 141 and the second gate line 142 of the array substrate shown in FIG. 4A corresponding to one pixel unit group 110. For example, as shown in FIG. 4E, the first gate line 141 includes a first gate portion 1411, and the second gate line 142 includes a second gate portion 1421. For example, the first gate portion 1411 is configured as the gate of the first switching element 123, and the second gate portion 1421 is configured as the gate of the second switching element 133. That is, the orthogonal projection of the U-shaped electrode (source or drain) of the first switching element 123 on the first electrode layer 172 at least partially overlaps with the first gate portion 1411, and the orthogonal projection of the U-shaped electrode (source or drain) of the second switching element 133 on the first electrode layer 172 at least partially overlaps with the second gate portion 1421.

[0158] 4E , the first gate portion 1411 of the first gate line 141 for driving each pixel unit group 110 and the second gate portion 1421 of the second gate line 142 for driving the pixel unit group 110 adjacent to each pixel unit group 110 in the second direction D2 partially overlap in the first direction D1, thereby reducing the dimension of the area occupied by the gate line in the second direction D2 and thereby improving the aperture ratio of the array substrate 100 and the aperture ratio of the display panel and display device including the array substrate 100. For example, as shown in FIG. 4E , the corresponding gate portions of two gate lines (the first gate line 141 and the second gate line 142) located between adjacent pixel unit groups 110 in the second direction D2 partially overlap in the first direction D1.

[0159] 4E, the first gate line 141 further includes a first line portion 1412, a first line connection portion 1413, and a third line portion 1414 connected in sequence, and the second gate line 142 further includes a second line portion 1422, a second line connection portion 1423, and a fourth line portion 1424 connected in sequence, with the first line portion 1412 connected to the first gate portion 1411 and the second line portion 1422 connected to the second gate portion 1421. For example, as shown in FIG. 4E, the first line connection portion 1413 includes a first protrusion 143 protruding toward the first gate portion 1411, and the second line connection portion 1423 includes a second protrusion 144 protruding toward the second gate portion 1421.

[0160] For example, as shown in FIGS. 4D and 4E, the first line portion 1412, the second line portion 1422, the third line portion 1414, and the fourth line portion 1424 are each parallel to the first direction D1.

[0161] For example, as shown in FIGS. 4D and 4E , a first recess structure 211 is provided between gate portions and line connecting portions that are located on the same gate line, correspond to different pixel unit groups, and are adjacent to each other, and the line connecting portions of the same gate line and adjacent gate lines are disposed within the first recess structure 211.

[0162] For example, as shown in Figures 4A and 4D, each gate line can drive short-connected pixels and long-connected pixels simultaneously, and therefore, each gate line may simultaneously include a first gate portion 1411, a first line portion 1412, a first line connection portion 1413, a third line portion 1414, a second gate portion 1421, a second line portion 1422, a second line connection portion 1423, and a fourth line portion 1424.

[0163] For example, as shown in Figures 4A to 4D, the gate portions and line connection portions corresponding to the same pixel unit group 110 of the gate line are arranged in parallel in the first direction and form a second recess structure 212, and the vias (e.g., the first via or the second via) of the pixels driven by the gate line are located within the second recess structure 212.

[0164] It should be noted that the array substrate 100 according to at least one embodiment of the present disclosure is not limited to the case where each of the plurality of first gate lines 141 and the plurality of second gate lines 142 adopts the structure shown in FIG. 4D. According to actual application needs, some of the plurality of first gate lines 141 and the plurality of second gate lines 142 may adopt the structure shown in FIG. 4D, and the remaining parts of the plurality of first gate lines 141 and the plurality of second gate lines 142 may adopt other applicable gate line structures (e.g., straight gate lines), which will not be described in detail here.

[0165] In some examples, the first line connection portion 1413 may not include the first protrusion 143 and the second line connection portion 1423 may not include the second protrusion 144 .

[0166] 5A is a schematic plan view of the semiconductor layer 174 and the second electrode layer 175 of the array substrate shown in FIG. 4A. As shown in FIG. 4B and FIG. 5A, the second electrode layer 175 includes a plurality of data lines 161, a plurality of first source-drain layers arranged in parallel, and a plurality of second source-drain layers arranged in parallel, the first source-drain layer including one 1241 of two first source-drains of the first switching element 123 and the other 1243 of the two first source-drains of the first switching element 123 (for example, a U-shaped electrode), and the second source-drain layer including one 1341 of two second source-drains of the second switching element 124 and the other 1343 of the two second source-drains of the second switching element 124 (for example, a U-shaped electrode).

[0167] In addition, the first source / drain layer and the second source / drain layer may be located in different regions of the same layer, the first source / drain layer and the second source / drain layer may be spaced apart in a direction perpendicular to the base substrate, and the first source / drain layer and the second source / drain layer may be formed by patterning the same film layer (e.g., a single film layer) using the same patterning process.

[0168] 5B is a schematic plan view (image obtained from a scanning electron microscope) of the first switching element 123 of the array substrate shown in FIG. 4A. For convenience of explanation, FIG. 5B further shows the first gate line 141, some of the first pixel electrodes 121, and the first via 1223. FIG. 5C is a schematic cross-sectional view of the array substrate 100 taken along line AA′ shown in FIG. 5B. FIG. 5D is a schematic plan view of the second switching element 133 according to at least one embodiment of the present disclosure.

[0169] For example, as shown in Figures 5B and 5C, in a direction perpendicular to the base substrate 171, the first switching element 123 includes a first gate portion 1411 (which is the gate of the first switching element 123), a first insulating layer 173, a semiconductor layer 174 (first semiconductor layer 125), and a first source-drain layer, and the first source-drain layer includes two first source-drains (i.e., one of the two first source-drains 1241 and the other of the two first source-drains 1243) that are individually installed opposite each other; for example, when the first switching element 123 is in an off state, the two first source-drains are insulated from each other).

[0170] For example, the semiconductor layer 174 includes a first semiconductor layer 125 (a region of the semiconductor layer 174 corresponding to the first switching element) and a second semiconductor layer (a region of the semiconductor layer 174 corresponding to the second switching element). Note that the first semiconductor layer 125 and the second semiconductor layer may be located in different regions of the same layer, the first semiconductor layer 125 and the second semiconductor layer may be spaced apart in a direction perpendicular to the base substrate, and the first semiconductor layer 125 and the second semiconductor layer may be formed by patterning the same film layer (for example, a single film layer) using the same patterning process.

[0171] For example, in a direction perpendicular to the base substrate 171, the second switching element 133 includes a second gate portion 1421 (the gate of the second switching element 133), a first insulating layer 173, a semiconductor layer 174 (a second semiconductor layer), and a second source-drain layer. As shown in FIG. 4B , the second source-drain layer includes two second source-drains (i.e., one of the two second source-drains 1341 and the other of the two second source-drains 1343) that are individually disposed opposite each other; for example, when the second switching element 133 is in an off state, the two second source-drains are insulated from each other.

[0172] For example, as shown in FIG. 5C, the array substrate 100 further includes a second insulating layer 176, a third electrode layer 177, and a first via 1223 and a second via 1323 disposed in the second insulating layer 176.

[0173] Fig. 6 is a schematic plan view of the third electrode layer 177 of the array substrate 100 shown in Fig. 4A. Fig. 7 is a schematic plan view of the first electrode layer 172, the semiconductor layer 174, and the second electrode layer 175 of the array substrate 100 shown in Fig. 4A, and Fig. 8 is a schematic plan view of the first via 1223, the second via 1323, and the third via 153 of the array substrate 100 shown in Fig. 4A.

[0174] As shown in Figures 5B, 5C and 6, the third electrode layer 177 includes a first pixel electrode 121, a first connection portion 122, a second pixel electrode 131, a second connection portion 132 and a second common electrode connection portion 152.

[0175] 5B, 5C, and 6, the first connecting portion 122 includes a first end 1221 and a second end 1222, the first end 1221 of the first connecting portion 122 is directly electrically connected to the first pixel electrode 121, and the second end 1222 of the first connecting portion 122 is electrically connected to one of the two first source-drains 1241 through the first via 1223. As shown in FIGS. 5B and 5C, the first via 1223 is a half via, i.e., one of the two first source-drains 1241 covers only a part of the opening area of ​​the first via 1223, and as shown in FIGS. 5B and 5C, the remaining part of the opening area of ​​the first via 1223 is located on the side of one of the two first source-drains 1241 closer to the first pixel electrode 121 and is directly covered by the first pixel electrode 121, i.e., the bottom of the remaining part of the opening area of ​​the first via 1223 directly contacts the first pixel electrode 121.

[0176] As shown in Figures 6 and 4B, the second connection portion 132 includes a first end 1321 and a second end 1322, the first end 1321 of the second connection portion 132 is directly electrically connected to the second pixel electrode 131, and the second end 1322 of the second connection portion 132 is electrically connected to one of the second source-drains 1341 through the second via 1323. As shown in Figure 5D, the one of the second source-drains 1341 covers a portion 1324 of the opening area of ​​the second via 1323, and the remaining portion 1325 of the opening area of ​​the second via 1323 is located on the side of the one of the second source-drains 1341 closer to the first pixel electrode 121 and is directly covered by the second pixel electrode 131, i.e., the bottom of the remaining portion 1325 of the opening area of ​​the second via 1323 directly contacts the second pixel electrode 131.

[0177] 5B and 5C, and other applicable installation forms can be selected for the first via 1223 and the second via 1323 according to actual application needs. Hereinafter, an exemplary description will be given with reference to the array substrate 100 shown in FIG. 2A.

[0178] FIG. 5E is a schematic plan view showing a partial region of the array substrate 100 shown in FIG. 2A, and FIG. 5F is a schematic plan view (obtained by a scanning electron microscope) of a region RC4 of the array substrate 100 shown in FIG. 5E.

[0179] As shown in Figures 5E and 5F, both the first via 1223 and the second via 1323 of the array substrate 100 shown in Figure 2A are half vias, i.e., one 1241 (e.g., the first drain) of the two first source-drains of the first switching element 123 covers only a portion 1224 of the opening area of ​​the first via 1223, and one 1341 (e.g., the second drain) of the two second source-drains of the second switching element 133 covers only a portion 1324 of the opening area of ​​the second via 1323.

[0180] 5E and 5F , the remaining portion 1225 of the opening region of the first via 1223 is located on the side of one of the two first source-drains 1241 that is away from the first pixel electrode 121, and the remaining portion 1325 of the opening region of the second via 1323 is located on the side of one of the second source-drains 1341 that is away from the first pixel electrode 121. In some examples, in the array substrate shown in FIGS. 5E and 5F , the first line connecting portion 1413 may include a first protrusion, and the second line connecting portion 1423 may include a second protrusion. In this case, if the positions of the first protrusion and the second protrusion are offset, the added first protrusion may be electrically connected (short-circuited) to the first pixel electrode through the first via, and the added second protrusion may be electrically connected (short-circuited) to the second pixel electrode through the second via. Therefore, compared to the structure of the first via 1223 shown in Figures 5E and 5F, the remaining portion 1225 of the opening area of ​​the first via 1223 shown in Figures 5B and 5C is located on the side of one of the two first source-drains 1241 away from the first pixel electrode 121, thereby reducing the risk of a short circuit between the first protrusion 143 of the array substrate and the first connection portion 122 shown in Figures 5B and 5C, and the remaining portion 1325 of the opening area of ​​the second via 1323 shown in Figure 5F is located on the side of one of the second source-drains 1341 away from the first pixel electrode 121, thereby reducing the risk of a short circuit between the second protrusion 144 of the array substrate and the second connection portion 132 shown in Figures 5B and 5C.

[0181] Hereinafter, the Cgs compensation function and the head stripe suppression function of the array substrate shown in FIG. 4B will be described with reference to FIGS. 4B and 5B.

[0182] As shown in FIG. 5B, the orthogonal projection of the first gate line 141 on the second conductive layer (first source-drain layer) overlaps with one of the two first source-drains 1241 at at least two different positions, for example, as shown in FIG. 5B, the orthogonal projection of the first gate line 141 on the first source-drain layer at least partially overlaps with one of the two first source-drains 1241 on both sides of the first direction D1.

[0183] For example, when the orthogonal projection of the first gate line 141 on the first source-drain layer at least partially overlaps with one of the two first source-drain regions 1241 on both sides of the first direction D1, the variation range of the capacitance value formed between the first gate line and the first source-drain layer can be reduced, and since the variation range of the capacitance value formed between the first gate line and the first source-drain layer is positively correlated with the oscillating stripes, by reducing the variation range of the capacitance value formed between the first gate line and the first source-drain layer, it is possible to suppress and avoid oscillating stripe defects caused by the offset of the mask for manufacturing the second electrode layer 175 relative to the first electrode layer 172.

[0184] For example, for convenience of explanation, in the following embodiments, the first source-drain and second source-drain connected to the data line 161 are referred to as the first source and the second source, respectively, and the first source-drain and second source-drain connected to the pixel electrode are referred to as the first drain and the second drain, respectively; however, the embodiments of the present disclosure are not limited thereto, and in some other embodiments, the first source-drain and second source-drain connected to the data line 161 may be referred to as the first drain and the second drain, respectively, and the first source-drain and second source-drain connected to the pixel electrode may be referred to as the first source and the second source, respectively.

[0185] Figure 5G is a first schematic diagram (corresponding to the first switching element) of the overlapping area between the electrode layer on which the gate lines of the array substrate shown in Figure 4A are located and the electrode layer on which the source and drain are located, as projected orthogonally on the electrode layer on which the gate lines are located, and Figure 5H is a second schematic diagram (corresponding to the second switching element) of the overlapping area between the electrode layer on which the gate lines of the array substrate shown in Figure 4A are located and the electrode layer on which the source and drain are located, as projected orthogonally on the electrode layer on which the gate lines are located.

[0186] For example, as shown in FIG. 5G, the orthogonal projection of the first gate line 141 (first gate portion 1411 of the first gate line 141) on the first source-drain layer overlaps with the region closer to the first source of the first drain (e.g., the left side), and the orthogonal projection of the first gate line 141 (first line connection portion 1413 of the first gate line 141) on the first source-drain layer overlaps with the region away from the first source of the first drain (e.g., the right side). 5G , an orthogonal projection of the first protrusion 143 at one 1241 (e.g., the first drain) of the two first source-drains at least partially overlaps with the one 1241 (e.g., the first drain) of the two first source-drains, and an overlapping region between the orthogonal projection of the first protrusion 143 at one 1241 (e.g., the first drain) of the two first source-drains and the one 1241 (e.g., the first drain) of the two first source-drains is a first overlapping region 145. For example, as shown in FIG. 5G , an overlapping region between the orthogonal projection of the first gate portion 1411 at the first drain and the first drain is a second overlapping region 146.

[0187] As shown in FIG. 5G, when the first source / drain layer is offset to the right relative to the first electrode layer 172 (e.g., the first gate portion 1411), the size of the first overlap region 145 increases and the size of the second overlap region 146 decreases; when the first source / drain layer is offset to the left relative to the first electrode layer 172 (e.g., the first gate portion 1411), the size of the first overlap region 145 decreases and the size of the second overlap region 146 increases. Therefore, compared to an example in which the first overlap region 145 is not provided, the provision of the first overlap region 145 can reduce the range of change in the capacitance (Cgs1) value formed between the gate line and the first source / drain layer (due to the offset of the first source / drain layer relative to the first electrode layer 172), thereby suppressing the occurrence of streak defects in display panels and display devices including the array substrate 100.

[0188] As shown in FIG. 5G, the first overlap region 145 has a first overlap edge 1451 in a second direction D2 intersecting with the first direction D1, and the second overlap region 146 has a second overlap edge 1461 in the second direction D2 intersecting with the first direction D1, and the length of the first overlap edge 1451 and the length of the second overlap edge 1461 are the same. In this case, the range of change in the value of the capacitance (Cgs1) formed between the gate line and the first source / drain layer (due to the offset of the first source / drain layer relative to the first electrode layer 172) and the range of change in the pixel voltage jump amount of the first pixel can be further reduced.

[0189] For example, as shown in FIG. 5H, the orthogonal projection of the second gate line 142 on the second source-drain layer overlaps with one of the two second source-drain regions 1341 at at least two different positions, and the orthogonal projection of the second gate line 142 on the second source-drain layer at least partially overlaps with one of the two second source-drain regions 1341 on both sides of the first direction D1.

[0190] For example, as shown in FIG. 5H, the orthogonal projection of the second gate line 142 (second gate portion 1421 of the second gate line 142) on the second source-drain layer overlaps with the region of the second drain closer to the second source, and the orthogonal projection of the second gate line 142 (second line connection portion 1423 of the second gate line 142) on the second source-drain layer overlaps with the region of the second drain away from the second source.

[0191] For example, as shown in FIG. 5H , an orthogonal projection of one 1341 (e.g., the second drain) of the second protrusion 144 at least partially overlaps with one 1341 (e.g., the second drain) of the second source-drain, and the overlapping region between the orthogonal projection of one 1341 (e.g., the second drain) of the second protrusion 144 and one 1341 (e.g., the second drain) of the two second source-drains is a third overlapping region 147. For example, as shown in FIG. 5H , an overlapping region between the orthogonal projection of the second drain of the second gate portion 1421 and the second drain is a fourth overlapping region 148. For example, compared to an example in which the third overlapping region 147 is not provided, the provision of the third overlapping region 147 can reduce the width of the change in the capacitance (Cgs2) value formed between the gate line and the second source-drain layer (due to the offset of the second source-drain layer relative to the first electrode layer 172), thereby suppressing the occurrence of streak defects in a display panel and a display device including the array substrate 100.

[0192] For example, the third overlap region 147 has a third overlap edge 1471 in a second direction D2 that intersects with the first direction D1, and the fourth overlap region 148 has a fourth overlap edge 1481 in the second direction D2 that intersects with the first direction D1, and the length of the third overlap edge 1471 and the length of the fourth overlap edge 1481 are the same.In this case, the range of change in the value of the capacitance (Cgs2) formed between the gate line and the second source / drain layer (due to the offset of the second source / drain layer relative to the first electrode layer 172) and the range of change in the pixel voltage jump amount of the second pixel can be further reduced.

[0193] In some examples, the planar shapes of the first overlap region 145, the second overlap region 146, the third overlap region 147, and the fourth overlap region 148 are all substantially rectangular, the dimension of the first overlap region 145 in the second direction D2 is equal to the dimension of the second overlap region 146 in the second direction D2, and the dimension of the third overlap region 147 in the second direction D2 is equal to the dimension of the fourth overlap region 148 in the second direction D2. In some examples, when determining the second overlap region 146, the first semiconductor layer 125 located between the first gate portion 1411 and the first drain may be taken into consideration, i.e., the overlap region between the orthogonal projection of the first gate portion 1411 of the combined structure of the first drain and the first semiconductor layer 125 and the first gate portion 1411 may be defined as the second overlap region 146, and correspondingly, when determining the fourth overlap region 148, the overlap region between the orthogonal projection of the second gate portion 1421 of the combined structure of the second drain and the second semiconductor layer and the second gate portion 1421 may be defined as the fourth overlap region 148.

[0194] For example, the overlapping area between the orthogonal projection of the first gate line 141 on the first source-drain layer and one of the two first source-drain regions 1241 is a first value, the overlapping area between the orthogonal projection of the second gate line 142 on the second source-drain layer and one of the two second source-drain regions 1341 is a second value, and the first value is equal to the second value. In this case, the capacitance (Cgs1) formed between the gate line and the first source-drain layer is equal to the capacitance (Cgs2) formed between the gate line and the second source-drain layer, and the pixel voltage jump amount of the first pixel and the pixel voltage jump amount of the second pixel are relatively close (for example, equal), thereby further suppressing the occurrence of streak defects in display panels and display devices including the array substrate 100.

[0195] Hereinafter, with reference to FIG. 9, another technical solution for improving the display uniformity of a display panel including the array substrate shown in FIG. 4A will be described.

[0196] In one example, the first pixel electrode 121 and the gate line driving the first pixel overlap in the second direction D2, and the second pixel electrode 131 and the gate line driving the second pixel overlap in the second direction D2. Figure 9 is a schematic diagram showing the interval and overlap length between a pixel electrode and a gate line driving the pixel in which the pixel electrode is located, according to at least one embodiment of the present disclosure.

[0197] As shown in Figure 9, the horizontal distance dpg1 between the first pixel electrode 121 and the gate line that drives the first pixel is the distance between the edge of the first pixel electrode 121 that is close to the gate line that drives the first pixel (for example, the first gate line 141 shown in Figure 9) and the gate line that drives the first pixel, and the horizontal distance dpg2 between the second pixel electrode 131 and the gate line that drives the second pixel (for example, the second gate line 142 shown in Figure 9) is the distance between the edge of the second pixel electrode 131 that is close to the gate line that drives the second pixel and the gate line that drives the second pixel. For example, since the distance (the distance in the direction perpendicular to the first electrode layer 172) between the third electrode layer 177 on which the first pixel electrode 121 is located and the first electrode layer 172 on which the gate line for driving the first pixel is located is relatively small, as shown in Figure 9, the distance in the second direction D2 between the first pixel electrode 121 and the gate line for driving the first pixel (e.g., the first gate line 141 shown in Figure 9) can be defined as horizontal distance dpg1, and the distance in the second direction D2 between the second pixel electrode 131 and the gate line for driving the second pixel (e.g., the second gate line 142 shown in Figure 9) can be defined as horizontal distance dpg2. In other embodiments of the present disclosure, the horizontal distances have similar definitions and will not be described in detail.

[0198] As shown in FIG. 9, the effective overlap length between the coupling structure of the first pixel electrode 121 and the first connection portion 122 and the gate line driving the first pixel is the length in the first direction D1 of the gate line driving the first pixel in the region where the horizontal spacing dpg1 is equal to or less than a predetermined spacing (e.g., 6 microns), and the effective overlap length between the coupling structure of the second pixel electrode 131 and the second connection portion 132 and the gate line driving the second pixel is the length in the first direction D1 of the gate line driving the second pixel in the region where the horizontal spacing dpg2 is equal to or less than a predetermined spacing (e.g., 6 microns).

[0199] In one example, the lateral spacing between the first pixel electrode 121 and the gate line driving the first pixel is greater than 5 microns, and the lateral spacing between the second pixel electrode 131 and the gate line driving the second pixel is greater than 5 microns. For example, the inventors of the present disclosure, through repeated testing and analysis, have found that when the horizontal spacing between the first pixel electrode 121 and the gate line driving the first pixel is greater than 5 microns, the effects on the capacitance Cpg of the first pixel caused by changes in the horizontal spacing between the first pixel electrode 121 and the gate line driving the first pixel (for example, changes due to the manufacturing process) and changes in the effective overlap length between the first pixel electrode 121 and the first connecting portion 122 and the gate line driving the first pixel can be reduced; and when the horizontal spacing between the second pixel electrode 131 and the gate line driving the second pixel is greater than 5 microns, the effects on the capacitance Cpg of the second pixel caused by changes in the horizontal spacing between the second pixel electrode 131 and the gate line driving the second pixel and changes in the effective overlap length between the second pixel electrode 131 and the second connecting portion 132 and the gate line driving the second pixel can be reduced, thereby reducing the requirements for the manufacturing process without degrading the wobble stripes.

[0200] In one example, as shown in FIG. 9 , the extension length of the first connection portion 122 is smaller than the extension length of the second connection portion 132, the effective overlap length between the coupling structure of the first pixel electrode and the first connection portion and the first gate line is smaller than the effective overlap length between the coupling structure of the second pixel electrode and the second connection portion and the second gate line, and the second pixel electrode 131 has a recess on the side closer to the gate line that drives the second pixel.

[0201] For example, by providing a recess in the pixel electrode of a long-connection pixel (e.g., the second pixel) on the side closer to the gate line that drives the long-connection pixel, the effective overlap length lpg between the pixel electrode and the coupling structure of the connection part of the long-connection pixel and the gate line can be shortened. In this case, the effective overlap length between the pixel electrode and the coupling structure of the connection part of the long-connection pixel and the gate line becomes closer to the effective overlap length between the pixel electrode and the coupling structure of the connection part of the short-connection pixel (e.g., the first pixel) and the gate line. Therefore, the capacitance Cpg of the long-connection pixel and the capacitance Cpg of the short-connection pixel become closer, thereby further suppressing the occurrence of sway stripe defects.

[0202] In one example, the effective overlap length between the coupling structure of the first pixel electrode 121 and the first connection portion 122 and the gate line driving the first pixel is equal to the effective overlap length between the coupling structure of the second pixel electrode 131 and the second connection portion 132 and the gate line driving the second pixel, thereby further suppressing the occurrence of sway stripe defects.

[0203] In one example, the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121 (not for driving the first pixel in which the first pixel electrode 121 is located) overlap in the second direction D2, and the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131 (not for driving the second pixel in which the second pixel electrode 131 is located) overlap in the second direction D2.

[0204] Furthermore, when the gate line adjacent to the second pixel electrode 131 is located above the second pixel electrode 131, the gate line adjacent to the second pixel electrode 131 has little or no effect on the charging process of the second pixel electrode 131. Therefore, the second pixel electrode 131 of the long-connection pixel described below when explaining the effect of Cpg' on the display uniformity of the display panel is located above the gate line adjacent to it (which does not drive the pixel). In other words, the first pixel electrode 121 and the second pixel electrode 131 referred to below when explaining the effect of Cpg' on the display uniformity of the display panel are in the same column rather than the same pixel unit group.

[0205] In some examples, in order to further reduce the impact of the capacitance Cpg' of the long-connection pixels and the short-connection pixels on the display uniformity of the display panel and suppress the wobbling stripe defect, the horizontal spacing dpg1' (e.g., the spacing in the second direction D2 between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121) and the horizontal spacing dpg2' (e.g., the spacing in the second direction D2 between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131) are made as large as possible, and the effective overlap length lpg1' (e.g., the effective overlap length between the first pixel electrode 121 and the gate line adjacent to the first pixel electrode 121) is made equal to the effective overlap length lpg2' (the effective overlap length between the second pixel electrode 131 and the gate line adjacent to the second pixel electrode 131), or the impact of the capacitance Cpg of the long-connection pixels and the short-connection pixels on the display uniformity of the display panel is made exactly the same or close to it.

[0206] The structure and connection relationship of the plurality of common electrode patterns 150 will be described below with reference to Figures 10 and 11. Figure 10 is a schematic plan view of the common electrode patterns 150 arranged in an array on the array substrate 100 according to at least one embodiment of the present disclosure, and Figure 11 is a schematic plan view of the common electrode patterns 150 on the array substrate 100 according to at least one embodiment of the present disclosure. As shown in FIG. 10, adjacent common electrode patterns 150 in the first direction D1 are electrically connected by first common electrode connection portions 151, which are in the same layer as the common electrode patterns 150, and the common electrode patterns 150 in different rows are installed at intervals.

[0207] As shown in Figure 10, adjacent common electrode patterns 150 in the second direction D2 are electrically connected by a second common electrode connection portion 152, which is located in the same layer as the first connection portion 122, and the second common electrode connection portion 152 is electrically connected to the corresponding common electrode pattern 150 by a third via 153.

[0208] As shown in Figures 10 and 11, at least one (each) common electrode pattern 150 is configured to include a main body portion 154, a first protrusion 155 and two second protrusions 156 extending from a first side of the main body portion 154, the first protrusion 155 and the two second protrusions 156 each extending in the second direction D2, the first protrusion 155 is located between the two second protrusions 156 in the first direction D1, the first common electrode connection portion 151 is located between the second protrusions 156 of two adjacent common electrode patterns 150 in the first direction D1, and both ends of the first common electrode connection portion 151 are directly electrically connected to the second protrusions 156 of the two adjacent common electrode patterns 150 in the first direction D1.

[0209] 10 , adjacent common electrode patterns 150 in the second direction D2 are electrically connected to the first protrusion 155 and the third via 153 of the adjacent common electrode patterns 150. For example, one end of the first protrusion 155 that is not connected to the main body 154 includes an enlarged portion 158, and adjacent common electrode patterns 150 in the second direction D2 are electrically connected to the enlarged portion 158, the third via 153, and the second common electrode connection portion 152 of the adjacent common electrode patterns 150. For example, by including the enlarged portion 158 at the one end of the first protrusion 155 that is not connected to the main body 154, the design freedom of the second common electrode connection portion 152 can be improved.

[0210] 10 schematically illustrates a connection method for the common electrode patterns 150 in different rows, the shape and structure of the second common electrode connection portion 152 are not limited thereto. For example, the second common electrode connection portion 152 may have the shape and structure of the second common electrode connection portion 152 illustrated in FIG. 6, and detailed description thereof will be omitted.

[0211] 10 , the planar shape of at least one (each) common electrode pattern 150 is “E” shaped, and the opening direction of the at least one (each) common electrode pattern 150 (i.e., the opening direction of the “E” shape) is opposite to the opening direction of an adjacent common electrode pattern 150 in the column direction. For example, the main body 154 of each common electrode pattern 150 faces the main body 154 of one common electrode pattern 150 adjacent to the common electrode pattern 150 in the second direction, and the opening of each common electrode pattern 150 faces the opening of the other common electrode pattern 150 adjacent to the common electrode pattern 150 in the second direction.

[0212] In one example, as shown in FIG. 10, for common electrode patterns in the same column, the opening directions of the common electrode patterns 150 in odd-numbered columns are the same, the opening directions of the common electrode patterns 150 in even-numbered columns are the same, and the opening directions of two adjacent common electrode patterns 150 in the second direction are different.

[0213] As shown in FIG. 10, the main body portion 154 of at least one (each) common electrode pattern 150 has a recess on the side away from the first protrusion 155 of the common electrode pattern 150, and as shown in FIG. 4B, the recess of the main body portion 154 of the at least one (each) common electrode pattern 150 corresponds to (e.g., at least partially overlaps with) the recess of the corresponding common electrode pattern 150.

[0214] For example, as shown in Figures 4B, 6 and 10, the main body 154 of each common electrode pattern 150 is located on the side where the second connection portion 132 of the pixel unit group 110 corresponding to the common electrode pattern 150 is located in the second direction, and the opening of each common electrode pattern 150 is located on the side where the first connection portion 122 of the pixel unit group 110 corresponding to the common electrode pattern 150 is located in the second direction.

[0215] It should be noted that in some examples, the common electrode pattern 150 may also be referred to as a common electrode line or a common data line.

[0216] In some examples (in the case of a TN mode display panel), the opposing substrate of the display panel further includes a common electrode layer (e.g., made of a transparent conductive material such as ITO), and the common electrode layer and the common electrode pattern 150 are electrically connected by a conductive portion (e.g., a conductive gold ball).

[0217] In some other examples (such as display panels based on Advanced Super Dimension Switch technology), the array substrate further includes a common electrode layer (e.g., a patterned common electrode layer insulated from the gate lines), and the common electrode pattern 150 and the common electrode layer are electrically connected. For example, the common electrode pattern 150 and the common electrode layer are directly electrically connected or connected by a via. For example, when the common electrode pattern 150 and the common electrode layer are directly electrically connected, the common electrode layer may be located on the side of the common electrode pattern 150 away from the data line.

[0218] At least one embodiment of the present disclosure further provides an experimental analysis method for wobble stripes, and experimental data analysis shows that when a display panel displays an image with 127 gray levels and the gray scale difference between pixels is 6 gray levels, obvious wobble stripes will appear. The following describes the experimental analysis method for wobble stripes and an experimental design scheme for studying wobble stripes.

[0219] For example, experimental equipment for studying wobble fringes includes an igniter, a detector (eg, model CA310), and a DC power supply.

[0220] The experiment for studying the wobble stripes includes the following steps S501 to S505.

[0221] In step S501, a common voltage Vcom is applied to the sample (display panel) from the outside, that is, the common voltage Vcom is applied to the common electrode or common electrode pattern in the display panel from a DC power source (DC voltage) outside the display panel.

[0222] In step S502, a pattern is constructed using a lighting device, and pixels of the same structure and polarity are lit (127 gray scale), and the remaining pixels are not lit (0 gray scale).

[0223] In step S503, the measurement probe of the detector (for example, model number CA310) is placed vertically at the center of the sample, and the degree of blinking (blinking value) is detected.

[0224] In step S504, the common voltage Vcom is adjusted until the blinking value is minimized, and the common voltage Vcom at this time is the optimal common voltage Vcom for this pixel structure.

[0225] In step S505, steps S501 to S504 are repeated for all sub-pixels in one period until the optimum common voltages Vcom for all sub-pixels (12 pixels) in one period are detected.

[0226] Next, a head-shaking stripe analysis is performed based on the above detection results.

[0227] According to the flashing mechanism, when the flashing value is minimum, it can be considered that the positive and negative frame luminance of the pixel at this time is the same. Therefore, when the flashing value is minimum, the relationship between the common voltage Vcom and the jump amount ΔVp of the pixel voltage is: It is expressed as Vcom=Vcenter-△Vp.

[0228] Therefore, when the blinking value is minimum, the common voltage Vcom and the jump amount ΔVp of the pixel voltage are inversely proportional, so that the difference in the jump amount ΔVp of the pixel voltage between different pixels can be estimated based on the difference in Vcom.

[0229] Table 1 shows the optimum common voltages Vcom of the pixels (pixels P1-P6) in one period of a 21.5-inch twisted nematic display panel (full high definition), where the pixels P1-P6 are, for example, red, green, blue, red, green and blue sub-pixels, respectively.

[0230] [Table 1]

[0231] As shown in Table 1, when the display panel has a swaying stripe defect, the difference between the optimum common voltages Vcom of different sub-pixels is 0.05 V, and when the display panel does not have a swaying stripe defect, the difference between the optimum common voltages Vcom of different sub-pixels is 0.02 V. For example, based on the data in Table 1, a VT curve (i.e., the curve between voltage and transmittance of the display panel) can be fitted around 127 gray scales, and combined with the gamma curve, it can be seen that when the pixel voltage difference is 0.05 V and the gray scale difference is 6 gray scales, swaying stripes are relatively obvious.

[0232] At least one embodiment of the present disclosure further provides a display panel including any of the array substrates according to the embodiments of the present disclosure. At least one embodiment of the present disclosure further provides a display device including any of the array substrates according to the embodiments of the present disclosure or any of the display panels according to the embodiments of the present disclosure.

[0233] 12 is an exemplary block diagram of a display panel and an exemplary block diagram of a display device. As shown in FIG. 12, the display panel 10 includes an array substrate 100, and the display device includes the display panel 10.

[0234] The display substrate 10 and the display device 20 have the capability or foundation for improving the aperture ratio.

[0235] At least one embodiment of the present disclosure further provides a method for manufacturing an array substrate, including forming a pixel unit group, the pixel unit group including a first pixel and a second pixel arranged in parallel in a first direction, the first pixel including a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode, the second pixel including a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode, the first pixel electrode and the first switching element being electrically connected to each other via the first connection portion, the second pixel electrode and the second switching element being electrically connected to each other via the second connection portion, and a length of the first connection portion not equal to a length of the second connection portion.

[0236] For example, forming the pixel unit group includes patterning the same film layer using the same patterning process to form the first connecting portion, the first pixel electrode, the second connecting portion and the second pixel electrode.

[0237] For example, the method for manufacturing the array substrate may include the following steps S101 to S108.

[0238] In step S101, a base substrate is provided.

[0239] In step S102, a first electrode layer is formed on a base substrate.

[0240] In step S103, a first insulating layer is formed on the base substrate on which the first electrode layer is formed.

[0241] In step S104, a semiconductor layer is formed on the base substrate on which the first insulating layer is formed.

[0242] In step S105, a second electrode layer is formed on the base substrate on which the semiconductor layer is formed.

[0243] In step S106, a second insulating layer is formed on the base substrate on which the second electrode layer is formed.

[0244] In step S107, the first via, the second via, and the third via are formed in the second insulating layer.

[0245] In step S108, a third electrode layer is formed on the base substrate in which the first via, the second via, and the third via are formed.

[0246] Hereinafter, a method for manufacturing an array substrate according to at least one embodiment of the present disclosure will be exemplarily described using the array substrate shown in FIG. 4A as an example.

[0247] For example, the base substrate can be a glass substrate, a quartz substrate, a plastic substrate (eg, a polyethylene terephthalate (PET) substrate), or a substrate made of other suitable materials.

[0248] For example, the first electrode layer (see FIG. 4C ) includes a plurality of first gate lines, a plurality of second gate lines, a common electrode pattern arranged in an array, and a plurality of first common electrode connections. For example, step S102 includes forming a first electrode film on a base substrate, and patterning the first electrode film using the same patterning process to form a plurality of first gate lines, a plurality of second gate lines, the common electrode pattern arranged in an array, and a plurality of first common electrode connections, i.e., forming a first electrode layer. For example, the first electrode layer is formed of a metal material (e.g., copper, aluminum, or aluminum alloy) or other applicable material.

[0249] For example, the material of the first insulating layer (see FIG. 5C) can be silicon oxide (SiOx), silicon oxynitride (SiNxOy), silicon nitride (SiNx), or other suitable materials.

[0250] For example, the semiconductor layer (see FIGS. 5A and 5C) may be made of an oxide semiconductor material, but the embodiments of the present disclosure are not limited thereto. For example, the oxide semiconductor material may include, for example, ZnO, MgZnO, Zn-Sn-O (ZTO), In-Zn-O (IZO), SnO, GaO, In-Ga-O (IGO), InO, In-Sn-O (ITO), In-Ga-Zn-O (IGZO), In-Zn-Sn-O (IZTO), In-Ga-Zn-Sn-O (IGZTO), and InAlZnO (IAZO). However, the semiconductor layer of the embodiments of the present disclosure is not limited to being made of the above specific oxide semiconductor materials.

[0251] For example, the second electrode layer (see FIG. 5A) includes a plurality of data lines and sources and drains of a plurality of switching elements. For example, step S105 includes forming a second electrode film on the semiconductor layer and patterning the second electrode film using the same patterning process to form a plurality of data lines and sources and drains of a plurality of switching elements, i.e., forming a second metal layer. For example, the second electrode layer is formed of a metal material (e.g., copper, aluminum, or aluminum alloy) or other applicable material.

[0252] For example, the second insulating layer may be formed of an inorganic or organic material, such as an organic resin, silicon oxide (SiOx), silicon oxynitride (SiNxOy), or silicon nitride (SiNx).

[0253] For example, in step S107, a first via is formed in the second insulating layer at a position corresponding to the end of one of the two first source-drains away from the U-shaped electrode (the other of the two first source-drains), a second via is formed in the second insulating layer at a position corresponding to the end of one of the second source-drains away from the U-shaped electrode (the other of the two second source-drains), and a third via is formed in the second insulating layer at a position corresponding to the first protrusion of the common electrode pattern (for example, the enlarged portion 158 of the first protrusion).

[0254] For example, the third electrode layer 177 (see FIG. 6) includes a first pixel electrode, a second pixel electrode, a first connection portion, a second connection portion, and a second common electrode connection portion.

[0255] For example, step S108 includes forming a third electrode film on the base substrate in which the first via, the second via, and the third via are formed, and patterning the third electrode film using the same patterning process to form the first pixel electrode, the second pixel electrode, the first connecting portion, the second connecting portion, and the second common electrode connecting portion. For example, the third electrode layer may be formed of a transparent conductive material. For example, the transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0256] Although the present disclosure has been described in detail above through the summary description and the preferred embodiments of the present disclosure, it is obvious to those skilled in the art that various modifications and improvements can be made based on the embodiments of the present disclosure. Therefore, all such modifications and improvements made without departing from the spirit of the present disclosure belong to the protection scope of the present disclosure.

[0257] Although the exemplary embodiments of the present disclosure have been described above, they are not intended to limit the scope of protection of the present disclosure, which is defined in the appended claims. [Explanation of symbols]

[0258] 10 Display Panel 20 Display device 100 Array substrate 110 pixel unit group 121 first pixel electrode 122 First connection part 123 First switching element 131 second pixel electrode 132 Second connection part 133 Second switching element

Claims

1. an array substrate including a pixel unit group, the pixel unit group including first and second pixels arranged adjacent to each other in parallel in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode; the second pixel includes a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion; the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; an extension length of the first connection portion is not equal to an extension length of the second connection portion; the array substrate further includes data lines disposed between adjacent pixel unit groups; the first switching element and the second switching element of each pixel unit group are connected to the same data line, the data line extends in a second direction, and the first direction and the second direction intersect; the first switching element includes a first source-drain layer including two first source-drains facing each other and spaced apart from each other; the second switching element includes a second source-drain layer including two second source-drains facing each other and spaced apart from each other; the first connection portion is directly and electrically connected to the first pixel electrode, and the first connection portion is further electrically connected to one of the two first source-drains through a first via; the second connection portion is directly electrically connected to the second pixel electrode, and the second connection portion is further electrically connected to one of the two second source-drains through a second via; one of the two first source-drains covers a part of an opening region of the first via, and the remaining part of the opening region of the first via is located on a side of the one first source-drain that is closer to the first pixel electrode, or the remaining part of the opening region of the first via is located on a side of the one first source-drain that is farther from the first pixel electrode, the second pixel electrode has a recess on a side closer to a gate line that drives the second pixel; the first pixel electrode and the gate line driving the first pixel overlap each other in a second direction intersecting the first direction, and the second pixel electrode and the gate line driving the second pixel overlap each other in the second direction intersecting the first direction; An effective overlap length between the coupling structure of the first pixel electrode and the first connection part and the gate line driving the first pixel is equal to an effective overlap length between the coupling structure of the second pixel electrode and the second connection part and the gate line driving the second pixel.

1. An array substrate comprising:

2. The pixel unit group includes a first edge and a second edge facing each other in the first direction, The first switching element and the second switching element are closer to a first edge of the pixel unit group in the first direction than the second edge.

2. The array substrate according to claim 1.

3. the first pixel electrode is located between the first switching element and the second switching element in the second direction; an extending direction of the first connecting portion is the second direction, and an extending direction of the second connecting portion is the first direction; The second connection portion and the first pixel electrode at least partially overlap in the second direction.

3. The array substrate according to claim 1, wherein the first and second electrodes are electrically connected to each other.

4. The first connection portion and the first pixel electrode are integrally formed of the same material, and the second connection portion and the second pixel electrode are integrally formed of the same material.

4. The array substrate according to claim 1, wherein the first and second electrodes are electrically connected to each other.

5. one of the two first source-drains covers a part of an opening region of the first via, and the remaining part of the opening region of the first via is located on a side of the one first source-drain that is closer to the first pixel electrode; One of the two second source-drains covers a part of an opening region of the second via, and the remaining part of the opening region of the second via is located on a side of the one second source-drain that is closer to the first pixel electrode.

2. The array substrate according to claim 1.

6. The array substrate further includes a first gate line and a second gate line each extending in the first direction; the first gate line and the second gate line are located on both sides of the pixel unit group in a second direction intersecting the first direction, An orthogonal projection of the first gate line on the first source-drain layer overlaps one of the two first source-drains at at least two different positions, and an orthogonal projection of the second gate line on the second source-drain layer overlaps one of the two second source-drains at at least two different positions.

6. The array substrate according to claim 5.

7. the first gate line includes a first gate portion, a first line portion, and a first line connection portion, which are connected in sequence; the second gate line includes a second gate portion, a second line portion, and a second line connection portion, which are connected in sequence; the first gate portion is disposed as a gate of the first switching element, and the second gate portion is disposed as a gate of the second switching element; an orthogonal projection of the first gate line on the first source-drain layer at least partially overlaps one of the two first source-drains on both sides in the first direction; The orthogonal projection of the second gate line on the second source / drain layer at least partially overlaps one of the two second source / drains on both sides in the first direction.

7. The array substrate according to claim 6.

8. an orthogonal projection of a first line connection portion of the first gate line on one of the two first source-drains at least partially overlaps with one of the two first source-drains; An orthogonal projection of a second line connection portion of the second gate line on one of the two second source-drains at least partially overlaps with one of the two second source-drains.

8. The array substrate according to claim 7.

9. the first line connection portion includes a first protrusion protruding toward the first gate portion, and the second line connection portion includes a second protrusion protruding toward the second gate portion; An orthogonal projection of the first protrusion on one of the two first source-drains at least partially overlaps with one of the two first source-drains, and an orthogonal projection of the second protrusion on one of the two second source-drains at least partially overlaps with one of the two second source-drains.

9. The array substrate according to claim 7, wherein the first and second electrodes are electrically connected to each other.

10. an overlapping region between an orthogonal projection of the first protrusion on one of the two first source-drains and one of the two first source-drains is a first overlapping region, and the first overlapping region has a first overlapping edge in a second direction intersecting with the first direction; an overlapping region between an orthogonal projection of one of the two first source-drains of the first gate portion and one of the two first source-drains is a second overlapping region, and the second overlapping region has a second overlapping edge in the second direction; the first overlapping edge and the second overlapping edge have the same length, an overlapping region between an orthogonal projection of the second protrusion on one of the two second source-drains and one of the two second source-drains is a third overlapping region, and the third overlapping region has a third overlapping edge in the second direction; an overlapping region between an orthogonal projection of one of the two second source-drains of the second gate portion and one of the two second source-drains is a fourth overlapping region, and the fourth overlapping region has a fourth overlapping edge in the second direction; The third overlapping edge and the fourth overlapping edge have the same length.

10. The array substrate according to claim 9.

11. an overlapping area between an orthogonal projection of the first gate line on the first source-drain layer and one of the two first source-drains is a first value; an overlapping area between an orthogonal projection of the second gate line on the second source-drain layer and one of the two second source-drains is a second value; The first value is equal to the second value.

11. The array substrate according to claim 6, wherein the first and second electrodes are electrically connected to each other.

12. The array substrate further includes a first gate line and a second gate line, each extending in the first direction; the first gate line and the second gate line are located on both sides of the pixel unit group in a second direction intersecting the first direction, An orthogonal projection of the first gate line on the first source / drain layer overlaps one of the two first source / drains at at least two different positions, or an orthogonal projection of the second gate line on the second source / drain layer overlaps one of the two second source / drains at at least two different positions.

5. The array substrate according to claim 4.

13. the first connection portion and the second connection portion are located on both sides of the first pixel electrode in a second direction perpendicular to the first direction, the first connection portion and the second connection portion are both located between the first gate line and the second gate line in the second direction; The first gate line and the second gate line are disposed symmetrically in the second direction with respect to a center line of the pixel unit group extending in the first direction.

13. The array substrate according to claim 6, wherein the first and second electrodes are electrically connected to each other.

14. the array substrate includes a plurality of pixel unit groups arranged in an array, A first gate line for driving each of the pixel unit groups and a second gate line for driving a pixel unit group adjacent to each of the pixel unit groups in the second direction partially overlap each other in the first direction.

14. The array substrate according to claim 6, wherein the first and second electrodes are electrically connected to each other.

15. the array substrate further includes a plurality of common electrode patterns arranged in an array, the plurality of common electrode patterns and the plurality of pixel unit groups correspond one-to-one to each other; a plurality of common electrode patterns in the same row are disposed between first gate lines and second gate lines for driving pixel unit groups corresponding to the plurality of common electrode patterns in the same row; the common electrode patterns adjacent to each other in the first direction are electrically connected to each other by a first common electrode connection portion that is in the same layer as the common electrode patterns, The common electrode patterns adjacent to each other in the second direction are electrically connected to each other by second common electrode connection portions that are in the same layer as the first connection portions, and the second common electrode connection portions are electrically connected to the corresponding common electrode patterns by third vias.

15. The array substrate according to claim 14.

16. Each of the common electrode patterns includes a main body portion and a first protrusion portion extending from a first side of the main body portion, the first protrusion extends in the second direction; The common electrode patterns adjacent to each other in the second direction are electrically connected by the first protrusions of the adjacent common electrode patterns and the third vias.

16. The array substrate according to claim 15.

17. The horizontal distance between the first pixel electrode and the gate line driving the first pixel is greater than 5 microns, and the horizontal distance between the second pixel electrode and the gate line driving the second pixel is greater than 5 microns.

14. The array substrate according to claim 1, wherein the first and second electrodes are electrically connected to each other.

18. The array substrate according to any one of claims 1 to 17 is included. A display panel characterized by:

19. The display panel according to claim 18 or the array substrate according to claim 17. A display device characterized by:

20. A method for manufacturing an array substrate, comprising: forming a pixel unit group; the pixel unit group includes a first pixel and a second pixel arranged in parallel in a first direction; the first pixel includes a first pixel electrode, a first switching element, and a first connection portion extending from the first pixel electrode; the second pixel includes a second pixel electrode, a second switching element, and a second connection portion extending from the second pixel electrode; the first pixel electrode and the first switching element are electrically connected to each other via the first connection portion; the second pixel electrode and the second switching element are electrically connected to each other via the second connection portion; the length of the first connecting portion is not equal to the length of the second connecting portion; The method further includes providing a data line between adjacent pixel unit groups; forming a first switching element and a second switching element of each of the pixel unit groups connected to the same data line, and the data line extending in a second direction, the first direction and the second direction intersecting; the first switching element includes a first source-drain layer including two first source-drains facing each other and spaced apart from each other; the second switching element includes a second source-drain layer including two second source-drains facing each other and spaced apart from each other; the first connection portion is directly and electrically connected to the first pixel electrode, and the first connection portion is further electrically connected to one of the two first source-drains through a first via; the second connection portion is directly electrically connected to the second pixel electrode, and the second connection portion is further electrically connected to one of the two second source-drains through a second via; one of the two first source-drains covers a part of an opening region of the first via, and the remaining part of the opening region of the first via is located on a side of the one first source-drain that is closer to the first pixel electrode, or the remaining part of the opening region of the first via is located on a side of the one first source-drain that is farther from the first pixel electrode, the second pixel electrode has a recess on a side closer to a gate line that drives the second pixel; the first pixel electrode and the gate line driving the first pixel overlap each other in a second direction intersecting the first direction, and the second pixel electrode and the gate line driving the second pixel overlap each other in the second direction intersecting the first direction; An effective overlap length between the coupling structure of the first pixel electrode and the first connection part and the gate line driving the first pixel is equal to an effective overlap length between the coupling structure of the second pixel electrode and the second connection part and the gate line driving the second pixel.

2. A method for manufacturing an array substrate comprising:

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