Switch Circuit

Abstract

To prevent the occurrence of malfunction without increasing a circuit scale.SOLUTION: A switch circuit 1 used in a voltage detection circuit 2 includes a switch unit 3 having switches SW1 to SW4 that open and close between input nodes Nip and Nin and sampling capacitors Csp and Csn, and a control unit 4 that controls the operation of the switch unit 3 and operates at a potential different from that of the switch unit 3. The switches SW1 to SW4 include serial circuits SC1 to SC4 with a structure in which P-channel type MOS transistors 12, 13, 16, and 17 and N-channel type MOS transistors 11, 14, 15, and 18 are connected in series. Back gates of the MOS transistors 11 to 18 are connected to their sources. The control unit 4 is configured to control on / off of the switches SW1 to SW4 by driving the gates of the MOS transistors 11 to 18 through driving capacitors Cd1 to Cd8.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a switch circuit used in a voltage detection circuit configured to sample and detect the voltage of an input node. [Background technology]

[0002] Battery monitoring ICs that detect battery cell voltages often use a switch circuit called a CCSW circuit, which controls the on / off of a switch in a high-voltage system with a different potential level, such as a low-voltage system referenced to ground, from a low-voltage system control circuit. CCSW stands for Capacitively Coupled Switch. The switch in this configuration is an analog switch consisting of a single MOS transistor. Therefore, the control circuit controls the on / off of the switch by driving the gate-source voltage VGS of the MOS transistor to a high level sufficiently higher than the gate threshold voltage and a low level sufficiently lower than the gate threshold voltage.

[0003] Specifically, the above-described switch circuit is used as a switch for the high-potential input of a switched-capacitor circuit that samples the voltages of two input nodes and detects the difference between them, i.e., the voltage between the two input nodes. In such an application, if an analog switch consisting of a single MOS transistor is used as the switch, the following problem may occur. Due to the device structure, a parasitic PN junction diode exists between the body and source or between the body and drain of the MOS transistor. Therefore, if the potential difference between the two input nodes is reversed, the parasitic PN junction diode may conduct in the forward direction, making it impossible to maintain the switch in the off state.

[0004] A conventional technique for solving such problems is disclosed in Patent Document 1. Patent Document 1 discloses a configuration including a maximum selector that applies the higher of the voltages at two input nodes as the substrate potential of a P-channel MOS transistor, and a minimum selector that applies the lower of the voltages at the two input nodes as the substrate potential of an N-channel MOS transistor. According to the conventional technique described in Patent Document 1, the above problems can be prevented by using the maximum selector and minimum selector to switch between the substrate potential and the boost and drop references. Note that "boosting" here means increasing the gate potential relative to the source potential, and "dropping" means decreasing the gate potential relative to the source potential. [Prior art documents] [Non-patent literature]

[0005] [Patent Document 1] Patent No. 6673150 Summary of the Invention [Problem to be solved by the invention]

[0006] In the conventional technology, a maximum selector and a minimum selector are required separately, which raises concerns about an increase in circuit size. Furthermore, in the conventional technology, a PN junction diode is used as the selector element. Therefore, in the conventional technology, a voltage shift of approximately 0.5V to 0.8V, specifically the forward voltage VF of the diode, remains. This prevents the body potential, i.e., the substrate potential, from becoming the accurate maximum or minimum potential, which results in a corresponding decrease in the gate-source voltage VGS of the MOS transistor.

[0007] In a CCSW circuit, the drive amplitude on the high-potential side is reduced in accordance with the voltage division ratio between the drive capacitance and the parasitic capacitance associated with the gate terminal, resulting in a smaller gate drive amplitude compared to the drive amplitude on the low-potential side. For this reason, in order to ensure sufficient amplitude on the high-potential side, the CCSW circuit must be designed so that the capacitance value of the drive capacitance is sufficiently large compared to the parasitic capacitance. In conventional technology, due to the voltage shift caused by the forward voltage VF, a drive capacitance with a larger capacitance value is required to compensate for the voltage shift in order to ensure sufficient gate drive amplitude to reliably turn the switch on and off, which may result in a further increase in circuit size.

[0008] Furthermore, with conventional technology, there is also the problem of increased current consumption by the circuit due to larger charging and discharging currents for parasitic capacitance, etc. Furthermore, when high-frequency noise is superimposed on the input and the input potential fluctuates, the maximum selector and minimum selector circuits charge and discharge the parasitic PN junction diode through the diode, making it difficult to improve the tracking of the maximum potential and minimum potential.

[0009] Therefore, in the prior art, if the input fluctuation is large and the maximum selector and minimum selector cannot keep up, the switch cannot be driven on and off correctly, which may result in malfunction. Patent Document 1 also discloses a configuration in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series as a switch, but the bodies of these MOS transistors are connected to the maximum selector and minimum selector. Therefore, even with this configuration, there is still a voltage drop due to the forward voltage VF of the diode, and the above problem cannot be solved.

[0010] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switch circuit that can prevent malfunctions from occurring without increasing the circuit size. [Means for solving the problem]

[0011] The switch circuit described in claim 1 is a switch circuit used in a voltage detection circuit (2) configured to sample and detect the voltage of an input node (Nip, Nin), and includes a switch section (3) having switches (SW1 to SW4) that open and close between the input node and a sampling capacitor (Csp, Csn) provided in the voltage detection circuit, and a control section (4) that controls the operation of the switch section and operates at a potential different from that of the switch section.

[0012] The switches include series circuits (SC1 to SC4) configured by connecting P-channel MOS transistors (12, 13, 16, 17) and N-channel MOS transistors (11, 14, 15, 18) in series. The back gates of the MOS transistors are connected to their sources or drains, or to points at the same potential as the sources or drains. The control unit controls the on / off of the switches by driving the gates of the MOS transistors via drive capacitances (Cd1 to Cd8). In the series circuits (SC1, SC3) included in the switches (SW1, SW3), the N-channel MOS transistors (11, 15) and the P-channel MOS transistors (12, 16) are arranged in this order from the input node (Nip). The switches include first diodes (Dc1, Dc3) connected with the input node as the anode between the input node and intermediate nodes (N3, N5) that are interconnection nodes of the two MOS transistors that make up the series circuits.

[0013] As described above, the switch circuit described in claim 1 is based on the same CCSW circuit configuration as the prior art, and has a characteristic configuration in which the switch includes a series circuit in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series, and the back gate of the MOS transistor is connected to its source or drain, or to a location at the same potential as the source or drain.

[0014] With this configuration, even if the voltages at both ends of the switch are reversed while the switch is off, the parasitic PN junction diode of either the P-channel MOS transistor or the N-channel MOS transistor will be reversed, so the switch will remain off, and as a result, the switch can be turned on and off normally without malfunction. Furthermore, with the above configuration, since a maximum selector and a minimum selector as in the prior art are not required, the circuit scale can be reduced compared to the prior art, and the following effects can also be obtained.

[0015] That is, with the above configuration, there is no voltage loss due to the forward voltage VF of the diode, and therefore gate potential tracking is improved. Therefore, with the above configuration, even if a capacitor with a relatively small capacitance value is used as the drive capacitance, a gate-source voltage amplitude sufficient for driving the gate of the MOS transistor is ensured, and the switch can be stably controlled to turn on and off even when, for example, high-frequency noise is superimposed and the switch potential fluctuates. Therefore, with the above configuration, it is possible to obtain the excellent effect of preventing malfunctions without increasing the circuit size. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing a configuration of a switch circuit according to a first embodiment; [Figure 2] FIG. 10 is a diagram showing the configuration of a ΔΣ modulator, which is a specific application example of a switch circuit according to a second embodiment; [Figure 3] FIG. 10 is a diagram illustrating an example of a non-overlapping two-phase+delayed clock according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, several embodiments will be described with reference to the drawings. Note that substantially the same components in the respective embodiments will be denoted by the same reference numerals, and the description thereof will be omitted. (First embodiment) The first embodiment will be described below with reference to FIG.

[0018] 1, a switch circuit 1 of this embodiment is used in a voltage detection circuit 2 configured to sample and detect a voltage Vinp at an input node Nip and a voltage Vin at an input node Ninn. Specifically, the voltage detection circuit 2 has a differential configuration in which it samples the voltages Vinp and Vinn at two input nodes Nip and Nin and detects the difference voltage between them. The voltage detection circuit 2 includes the switch circuit 1, two sampling capacitors Csp and Csn that form a pair in the differential configuration, and various circuits (not shown) connected downstream of the sampling capacitors Csp and Csn.

[0019] In this case, the input node Nip, which is the higher potential of the two input nodes Nip and Nin, corresponds to the first input node, and the input node Nin, which is the lower potential of the two input nodes Nip and Nin, corresponds to the second input node. Also, in this case, the sampling capacitor Csp, which is one of the two sampling capacitors Csp and Csn, corresponds to the first sampling capacitor, and the other sampling capacitor Csn, which is the other of the two sampling capacitors Csp and Csn, corresponds to the second sampling capacitor.

[0020] The voltage detection circuit 2 is used in a battery monitoring IC mounted on a vehicle such as an automobile. IC stands for Integrated Circuit. Although not shown, the battery monitoring IC is an integrated circuit that integrates circuits that perform various operations to monitor various conditions, such as the voltage of a battery pack in which multiple battery cells are connected in series in multiple stages. In this case, the voltage detection circuit 2 detects the voltage of the battery cells, and therefore, the battery cell voltages are applied to the input nodes Nip and Nin. As described above, because the battery cells are connected in series in multiple stages with other battery cells, a common-mode voltage is superimposed on the battery cells. This common-mode voltage increases toward the upper stage of the battery pack, i.e., the higher the battery cell is connected to the higher potential side, and its maximum value is relatively high, for example, on the order of several hundred volts.

[0021] The switch circuit 1 includes a switch unit 3, a control unit 4, resistors Rp1 and Rp2, and diodes Dp1 and Dp2. The switch unit 3 includes switches SW1, SW2, SW3, and SW4 that connect and disconnect input nodes Nip and Nin and sampling capacitors Csp and Csn. The switch SW1 is provided to connect and disconnect input node Nip and sampling capacitor Csp, and functions as a first switch. Specifically, one terminal of the switch SW1 is connected to the input node Nip via resistor Rp1, and the other terminal is connected to one terminal of the sampling capacitor Csp. The resistor Rp1 is a protective resistor that protects the circuit connected downstream of the input node Nip.

[0022] The switch SW2 is provided to be able to open and close the connection between the input node Nin and the sampling capacitor Csn, and functions as a second switch. Specifically, one terminal of the switch SW2 is connected to the input node Nin via a resistor Rp2, and the other terminal is connected to one terminal of the sampling capacitor Csn. The resistor Rp2 is a protective resistor for protecting the circuit connected downstream of the input node Nin.

[0023] The switch SW3 is provided to be able to open and close the connection between the input node Nip and the sampling capacitor Csn, and functions as a third switch. Specifically, one terminal of the switch SW3 is connected to the input node Nip via a resistor Rp1, and the other terminal is connected to one terminal of the sampling capacitor Csn. The switch SW4 is provided to be able to open and close the connection between the input node Nin and the sampling capacitor Csp, and functions as a fourth switch. Specifically, one terminal of the switch SW4 is connected to the input node Nin via a resistor Rp2, and the other terminal is connected to one terminal of the sampling capacitor Csp.

[0024] Between a node N1 to which the terminal of the resistor Rp1 on the switch SW1 and SW3 side is connected and a node N2 to which the terminal of the resistor Rp2 on the switch SW2 and SW4 side is connected, two diodes Dp1 and Dp2 are connected in opposite directions for inter-terminal protection. Specifically, the anodes of the diodes Dp1 and Dp2 are connected to the nodes N1 and N2, respectively, and the cathodes of the diodes Dp1 and Dp2 are connected to each other.

[0025] The switch SW1 includes a series circuit SC1 configured by connecting an N-channel MOS transistor 11 and a P-channel MOS transistor 12 in series. In this specification, an N-channel MOS transistor may be abbreviated as NMOS, and a P-channel MOS transistor may be abbreviated as PMOS. In the series circuit SC1 included in the switch SW1, the NMOS 11 and PMOS 12 are arranged in this order from the input node Nip side.

[0026] That is, the source of NMOS 11 is connected to node N1, and its drain is connected to node N3. The source of PMOS 12 is connected to node N3, and its drain is connected to one terminal of sampling capacitor Csp. Node N3 is an example of an intermediate node, which is an interconnection node between two MOS transistors 11 and 12 that make up series circuit SC1. The back gate of NMOS 11 is connected to its source. The back gate of PMOS 12 is connected to its source.

[0027] In a MOS transistor, the back gate and the body are synonymous, so in this specification, the back gate of each MOS transistor, including NMOS11 and PMOS12, is sometimes referred to as the body. A parasitic diode D11, which is a parasitic PN junction diode, exists between the body and drain of NMOS11. A parasitic diode D12, which is a parasitic PN junction diode, exists between the body and drain of PMOS12.

[0028] The gates of NMOS11 and PMOS12 are connected to the control unit 4, and their on / off states are controlled by the control unit 4. The switch SW1 includes a diode Dc1. The anode of the diode Dc1 is connected to the node N1, and the cathode is connected to the node N3. Thus, the diode Dc1 is connected between the input node Nip and the node N3, with the input node Nip side as the anode, and functions as a first diode for accelerating charging the body parasitic capacitance of the MOS transistors that make up the series circuit SC1.

[0029] The switch SW2 includes a series circuit SC2 in which a PMOS 13 and an NMOS 14 are connected in series. In the series circuit SC2 included in the switch SW2, the PMOS 13 and the NMOS 14 are arranged in this order from the input node Nin. That is, the source of the PMOS 13 is connected to the node N2, and its drain is connected to the node N4. The source of the NMOS 14 is connected to the node N4, and its drain is connected to one terminal of the sampling capacitor Csn. The node N4 is an example of an intermediate node, which is an interconnection node between the two MOS transistors 13 and 14 that make up the series circuit SC2.

[0030] The back gate of PMOS 13 is connected to its source. The back gate of NMOS 14 is connected to its source. A parasitic diode D13, which is a parasitic PN junction diode, exists between the body and drain of PMOS 13. A parasitic diode D14, which is a parasitic PN junction diode, exists between the body and drain of NMOS 14. The gates of PMOS 13 and NMOS 14 are connected to the control unit 4, and their on / off states are controlled by the control unit 4.

[0031] The switch SW2 includes a diode Dc2. The anode of the diode Dc2 is connected to the node N4, and the cathode of the diode Dc2 is connected to the node N2. Thus, the diode Dc2 is connected between the input node Nin and the node N4, with the node N4 side serving as the anode, and functions as a second diode for accelerating the charging of the body parasitic capacitance of the MOS transistors that make up the series circuit SC2.

[0032] The switch SW3 includes a series circuit SC3 in which an NMOS 15 and a PMOS 16 are connected in series. In the series circuit SC3 included in the switch SW3, the NMOS 15 and the PMOS 16 are arranged in this order from the input node Nip side. That is, the source of the NMOS 15 is connected to the node N1, and its drain is connected to the node N5. The source of the PMOS 16 is connected to the node N5, and its drain is connected to one terminal of the sampling capacitor Csn. The node N5 is an example of an intermediate node, which is an interconnection node between the two MOS transistors 15 and 16 that make up the series circuit SC3.

[0033] The back gate of NMOS 15 is connected to its source. The back gate of PMOS 16 is connected to its source. A parasitic diode D15, which is a parasitic PN junction diode, exists between the body and drain of NMOS 15. A parasitic diode D16, which is a parasitic PN junction diode, exists between the body and drain of PMOS 16. The gates of NMOS 15 and PMOS 16 are connected to the control unit 4, and their on / off states are controlled by the control unit 4.

[0034] The switch SW3 includes a diode Dc3. The anode of the diode Dc3 is connected to the node N1, and the cathode of the diode Dc3 is connected to the node N5. Thus, the diode Dc3 is connected between the input node Nip and the node N5, with the input node Nip side serving as the anode, and functions as a first diode for accelerating charging the body parasitic capacitance of the MOS transistors that make up the series circuit SC3.

[0035] The switch SW4 includes a series circuit SC4 in which a PMOS 17 and an NMOS 18 are connected in series. In the series circuit SC4 included in the switch SW4, the PMOS 17 and the NMOS 18 are arranged in this order from the input node Nin. That is, the source of the PMOS 17 is connected to the node N2, and its drain is connected to the node N6. The source of the NMOS 18 is connected to the node N6, and its drain is connected to one terminal of the sampling capacitor Csp. The node N6 is an example of an intermediate node, which is an interconnection node between the two MOS transistors 17 and 18 that make up the series circuit SC4.

[0036] The back gate of PMOS 17 is connected to its source. The back gate of NMOS 18 is connected to its source. A parasitic diode D17, which is a parasitic PN junction diode, exists between the body and drain of PMOS 17. A parasitic diode D18, which is a parasitic PN junction diode, exists between the body and drain of NMOS 18. The gates of PMOS 17 and NMOS 18 are connected to the control unit 4, and their on / off states are controlled by the control unit 4.

[0037] The switch SW4 includes a diode Dc4. The anode of the diode Dc4 is connected to the node N6, and the cathode of the diode Dc4 is connected to the node N2. Thus, the diode Dc4 is connected between the input node Nin and the node N6 with the node N6 side as its anode, and functions as a second diode for accelerating charging the body parasitic capacitance of the MOS transistors that make up the series circuit SC4.

[0038] In the voltage detection circuit 2, the circuits located on the battery pack side across the sampling capacitors Csp and Csn are equipped with high-voltage elements that can withstand the high common-mode voltage superimposed on the battery cells, while the other circuits use low-voltage elements. Therefore, in the switch circuit 1, the switch unit 3 is configured on the high-voltage side, operating at a relatively high potential, and the control unit 4 is configured on the low-voltage side, operating at a relatively low potential.

[0039] The control unit 4 controls the operation of the switch unit 3 based on binary control signals q1d, q2d, q1db, and q2db output from a control circuit (not shown), and as described above, operates at a different potential from that of the switch unit 3. The control circuit operates by receiving a power supply voltage of, for example, +5V. Therefore, the high level of the control signals q1d to q2db is +5V, and the low level thereof is 0V.

[0040] The MOS transistors 11-18 that constitute the switches SW1-SW4 of the high-voltage side switch section 3 cannot be directly driven by the control signals q1d-q2db output from the low-voltage side control circuit. Therefore, the control section 4 is configured to control the on / off of the switches SW1-SW4 by driving the gates of the MOS transistors 11-18 via drive capacitors. The specific configuration of the control section 4 is as follows. That is, the control section 4 includes a plurality of drive capacitors Cd1, Cd2, Cd3, Cd4, Cd5, Cd6, Cd7, and Cd8 that are provided corresponding to the plurality of MOS transistors 11-18 that constitute the switches SW1-SW4, respectively, and a drive circuit 20. The control section 4 is configured to independently drive the gates of the plurality of MOS transistors 11-18 via the plurality of drive capacitors Cd1-Cd8.

[0041] The driving capacitor Cd1 is connected between a node N7 to which a control signal q1db is applied and a node N8. The node N8 is connected to the gate of a PMOS transistor 12 of the switch SW1. The driving capacitor Cd2 is connected between the node N7 and a node N9. The node N9 is connected to the gate of a PMOS transistor 13 of the switch SW2. The driving capacitor Cd3 is connected between a node N10 to which a control signal q2db is applied and a node N11. The node N11 is connected to the gate of a PMOS transistor 16 of the switch SW3. The driving capacitor Cd4 is connected between the node N10 and a node N12. The node N12 is connected to the gate of a PMOS transistor 17 of the switch SW4.

[0042] The driving capacitor Cd5 is connected between a node N13 to which a control signal q1d is applied and a node N14. The node N14 is connected to the gate of the NMOS11 of the switch SW1. The driving capacitor Cd6 is connected between the node N13 and a node N15. The node N15 is connected to the gate of the NMOS14 of the switch SW2. The driving capacitor Cd7 is connected between a node N16 to which a control signal q2d is applied and a node N17. The node N17 is connected to the gate of the NMOS15 of the switch SW3. The driving capacitor Cd8 is connected between the node N16 and a node N18. The node N18 is connected to the gate of the NMOS18 of the switch SW4.

[0043] The drive circuit 20 supplies drive signals Sd1, Sd2, Sd3, Sd4, Sd5, Sd6, Sd7, and Sd8 to the gates of the MOS transistors 11 to 18 that make up the switches SW1 to SW4, respectively. The drive signals Sd1 to Sd8 are binary signals that take on either an off level that turns off the MOS transistors 11 to 18, or an on level that turns on the MOS transistors 11 to 18. Specifically, the on level and off level are as follows:

[0044] That is, when the driving target is an NMOS, the on level is a level that satisfies the following formula (1), when the driving target is a PMOS, the on level is a level that satisfies the following formula (2), and the off level is a level that satisfies the following formula (3), where VGS is the gate-source voltage of the MOS transistor, and Vt is the threshold voltage of the MOS transistor. VGS>Vt …(1) VGS<-Vt …(2) VGS ≒ 0 … (3)

[0045] The drive circuit 20 includes P-channel MOS transistors 21, 22, 25, and 26, N-channel MOS transistors 23, 24, 27, and 28, and diodes D21, D22, D23, D24, D25, D26, D27, and D28. The drain of the PMOS 21 is connected to a node N8, and its source is connected to a signal line 29. The signal line 29 is connected to an input node Nip via a resistor Rp1. The back gate of the PMOS 21 is connected to its source.

[0046] The drain of PMOS22 is connected to node N11, and its source is connected to signal line 29. The back gate of PMOS22 is connected to its source. The gate of PMOS21 is connected to signal line 29 via diode D21 in the forward direction and is also connected to node N11. The gate of PMOS22 is connected to signal line 29 via diode D22 in the forward direction and is also connected to node N8.

[0047] The PMOSs 21 and 22 and diodes D21 and D22 connected as described above constitute a cross PMOS circuit 31. The cross PMOS circuit 31 generates drive signals Sd1 and Sd3 based on the potential of the input node Nip corresponding to the switches SW1 and SW3. The drive signal Sd1 is a signal obtained by level-shifting the control signal q1db to a higher potential, and is supplied from node N8 to the gate of PMOS 12 of switch SW1. The drive signal Sd3 is a signal obtained by level-shifting the control signal q2db to a higher potential, and is supplied from node N11 to the gate of PMOS 16 of switch SW3.

[0048] The drain of NMOS23 is connected to node N14, and its source is connected to signal line 29. The back gate of NMOS23 is connected to its source. The drain of NMOS24 is connected to node N17, and its source is connected to signal line 29. The back gate of NMOS24 is connected to its source. The gate of NMOS23 is connected to signal line 29 via diode D23 in the reverse direction, and is also connected to node N17. The gate of NMOS24 is connected to signal line 29 via diode D24 in the reverse direction, and is also connected to node N14.

[0049] The NMOSs 23 and 24 and diodes D23 and D24 connected as described above constitute a cross NMOS circuit 32. The cross NMOS circuit 32 generates drive signals Sd5 and Sd7 based on the potential of the input node Nip corresponding to the switches SW1 and SW3. The drive signal Sd5 is a signal obtained by level-shifting the control signal q1d to the high potential side, and is supplied from node N14 to the gate of the NMOS 11 of the switch S1. The drive signal Sd7 is a signal obtained by level-shifting the control signal q2d to the high potential side, and is supplied from node N17 to the gate of the NMOS 15 of the switch SW3.

[0050] The drain of PMOS25 is connected to node N9, and its source is connected to signal line 30. Signal line 30 is connected to input node Nin via resistor Rp2. The back gate of PMOS25 is connected to its source. The drain of PMOS26 is connected to node N12, and its source is connected to signal line 30. The back gate of PMOS26 is connected to its source. The gate of PMOS25 is connected to signal line 30 via diode D25 in the forward direction, and is also connected to node N12. The gate of PMOS26 is connected to signal line 30 via diode D26 in the forward direction, and is also connected to node N9.

[0051] The PMOSs 25 and 26 and diodes D25 and D26 connected as described above constitute a cross PMOS circuit 33. The cross PMOS circuit 33 generates drive signals Sd2 and Sd4 based on the potential of the input node Nin corresponding to the switches SW2 and SW4. The drive signal Sd2 is a signal obtained by level-shifting the control signal q1db to a higher potential, and is supplied from node N9 to the gate of PMOS 13 of switch SW2. The drive signal Sd4 is a signal obtained by level-shifting the control signal q2db to a higher potential, and is supplied from node N12 to the gate of PMOS 17 of switch SW4.

[0052] The drain of NMOS27 is connected to node N15, and its source is connected to signal line 30. The back gate of NMOS27 is connected to its source. The drain of NMOS28 is connected to node N18, and its source is connected to signal line 30. The back gate of NMOS28 is connected to its source. The gate of NMOS27 is connected to signal line 30 via diode D27 in the reverse direction, and is also connected to node N18. The gate of NMOS28 is connected to signal line 30 via diode D28 in the reverse direction, and is also connected to node N15.

[0053] The NMOSs 27 and 28 and diodes D27 and D28 connected as described above constitute a cross NMOS circuit 34. The cross NMOS circuit 34 generates drive signals Sd6 and Sd8 based on the potential of the input node Nin corresponding to the switches SW2 and SW4. The drive signal Sd6 is a signal obtained by level-shifting the control signal q1d to the high potential side, and is supplied from node N15 to the gate of the NMOS 14 of the switch SW2. The drive signal Sd8 is a signal obtained by level-shifting the control signal q2d to the high potential side, and is supplied from node N18 to the gate of the NMOS 18 of the switch SW4.

[0054] Next, the operation of the switch circuit 1 having the above configuration will be described. The control unit 4 controls the switches SW1 and SW2 and the switches SW3 and SW4 to turn on and off complementarily. Note that in this specification, "turning on and off complementarily" does not exclude the case where a period during which both switches are off, a so-called dead time, is provided. Hereinafter, the period during which the switches SW1 and SW2 are on and the switches SW3 and SW4 are off will be referred to as a sample period, and the period during which the switches SW1 and SW2 are off and the switches SW3 and SW4 are on will be referred to as a hold period.

[0055] In the switch circuit 1 having the above configuration, during the sample period, the sampling capacitors Csp and Csn are charged by the voltages Vinp and Vinn of the input nodes Nip and Nin, respectively, i.e., the voltages Vinp and Vinn of the input nodes Nip and Nin are sampled by the sampling capacitors Csp and Csn. Also, in the switch circuit 1 having the above configuration, during the hold period, the charges accumulated in the sampling capacitors Csp and Csn are transferred to the subsequent circuit.

[0056] During the sample period and the hold period, the drive circuit 20 operates as follows. That is, during the sample period, the drive circuit 20 applies an on-level drive signal to the gates of NMOS 11, 14 and PMOS 12, 13, i.e., drives the gates of NMOS 11, 14 positively and drives the gates of PMOS 12, 13 negatively. As a result, the drive circuit 20 turns on both of the two MOS transistors 11, 12 that make up the series circuit SC1 and turns on both of the two MOS transistors 13, 14 that make up the series circuit SC2, turning on the switches SW1 and SW2.

[0057] At this time, the corresponding MOS transistors in the cross PMOS circuits 31 and 33 and the cross NMOS circuits 32 and 34 are turned on. Therefore, during the sample period, the drive circuit 20 applies an off-level drive signal to the gates of the NMOSs 15 and 18 and the PMOSs 16 and 17, that is, sets the gate-source voltages VGS of the NMOSs 15 and 18 and the PMOSs 16 and 17 to approximately 0 V, and turns off the switches SW3 and SW4. On the other hand, during the hold period, the control signals q1db, q2db, q1d, and q2d are inverted relative to the sample period, so the drive circuit 20 operates in the opposite manner to the sample period, turning off the switches SW1 and SW2 and turning on the switches SW3 and SW4.

[0058] According to the present embodiment described above, the following effects can be obtained. The switch circuit 1 of this embodiment is premised on the configuration of a CCSW circuit similar to that of the prior art, and has a characteristic configuration in which the switches SW1 to SW4 include series circuits SC1 to SC4 in which a PMOS and an NMOS are connected in series, and the back gates of the MOS transistors are connected to their sources.

[0059] With this configuration, even if the voltages at both ends of the switches SW1 to SW4 are reversed while the switches SW1 to SW4 are turned off, the parasitic PN junction diode of either the PMOS or NMOS will be reversed, so the switches SW1 to SW4 will be maintained in the off state, and as a result, the on / off of the switches SW1 to SW4 can be controlled normally without malfunction. Furthermore, with the above configuration, since a maximum selector and a minimum selector as in the conventional technology are not required, the circuit scale can be kept smaller than in the conventional technology, and the following effects can also be obtained.

[0060] That is, with the above configuration, there is no voltage loss due to the forward voltage VF of the diode, and therefore gate potential tracking is improved. Therefore, with the above configuration, even if drive capacitances Cd1 to Cd8 have relatively small capacitance values, the amplitude of the gate-source voltage VGS is ensured to be sufficient to drive the gates of the MOS transistors, and the switches SW1 to SW4 can be stably controlled to turn on and off even when, for example, high-frequency noise is superimposed and the potential of the switches fluctuates. Therefore, this embodiment provides the excellent effect of preventing malfunctions without increasing the circuit size.

[0061] The effects obtained by this embodiment will be described in more detail below, along with a comparison with the prior art. Note that, hereinafter, of the two MOS transistors constituting the switches SW1 to SW4, the MOS transistors 11, 13, 15, and 17 arranged on the input node Nip and Nin side may be referred to as first MOS transistors, and the MOS transistors 12, 14, 16, and 18 arranged on the sampling capacitor Csp and Csn side may be referred to as second MOS transistors.

[0062] Normally, to suppress the body bias effect of a MOS transistor, it is desirable to make the body potential the same as the source potential. However, if the switches SW1 to SW4 are composed of only a single MOS transistor, simply shorting the body and source of each MOS transistor will cause the parasitic PN junction diode between the body and drain to conduct forward if the potential difference between the input nodes Nip and Nin reverses, making it impossible to maintain the off state of the switches SW1 to SW4.

[0063] For example, if switches SW1 and SW3 are configured with a single PMOS and switches SW2 and SW4 are configured with a single NMOS, when the relationship of the potential difference between input nodes Nip and Nin is "voltage Vinp>voltage Vinn", that is, in the case of a positive input, switches SW1 to SW4 can be turned on and off normally, but when "voltage Vinp<voltage Vinn", that is, in the case of a negative input, switches SW1 to SW4 cannot be maintained in the off state.

[0064] On the other hand, in the conventional technology described in Patent Document 1, a maximum selector circuit and a minimum selector circuit are used to fix the body potential of the PMOS to a maximum potential and the body potential of the NMOS to a minimum potential, thereby preventing the parasitic PN junction diode from being erroneously turned on. In contrast, in the switch circuit 1 of this embodiment, even if the polarity of the potential difference between the input nodes Nip and Nin is reversed, the PN junction between the body and drain of one of the two types of MOS transistors, NMOS and PMOS, that make up the switches SW1 to SW4 becomes reversed, thereby maintaining the off state of the switches SW1 to SW4. Therefore, according to this embodiment, the maximum selector and minimum selector used in the conventional technology are not required.

[0065] In the conventional technology, the potentials selected by the maximum selector and minimum selector are shifted by the diode forward voltage VF relative to the actual maximum and minimum potentials. In contrast, in the switch circuit 1 of this embodiment, the bodies of the first MOS transistors are connected to their respective source terminals. In this case, the common sources of the cross NMOS circuit 32 and the cross PMOS circuit 33, which serve as the boost and drop references for the gates of the first MOS transistors, are also connected to the respective source terminals.

[0066] Specifically, the sources of NMOSs 23 and 24 of the cross NMOS circuit 32 are connected to a signal line 29 and, therefore, to the source terminals of the MOS transistors 11 and 15. The sources of PMOSs 25 and 26 of the cross PMOS circuit 33 are connected to a signal line 30 and, therefore, to the source terminals of the MOS transistors 13 and 17. In this configuration, the drive circuit 20 of the control unit 4 boosts the gate potential of each MOS transistor from the low potential side, i.e., drives it to turn on, and drops it to turn it off, via the independent drive capacitances Cd1 to Cd8 provided corresponding to each MOS transistor, using the above-mentioned source potential as a reference. This eliminates a voltage drop equivalent to the forward voltage VF of the diode as in the prior art.

[0067] Therefore, according to this embodiment, even if capacitances with relatively small capacitance values ​​are used as the drive capacitances Cd1 to Cd8, it is possible to ensure an amplitude of the voltage VGS sufficient for efficient gate driving. Furthermore, according to this embodiment, even if there is a potential difference between the input nodes Nip and Nin, the gates of the MOS transistors 11 to 18 that constitute the switches SW1 to SW4 are driven via independent drive capacitances Cd1 to Cd8, so it is possible to ensure an amplitude of the voltage VGS sufficient for turning on and off the MOS transistors 11 to 18.

[0068] Furthermore, according to this embodiment, the following effect can be obtained. That is, in the maximum selector and minimum selector of the conventional technology, the parasitic capacitance of the body of the MOS transistor is charged and discharged via a diode in the forward direction. In contrast, in this embodiment, the parasitic capacitance of the body is charged and discharged by the MOS transistor, and charging and discharging is not via a diode, so potential tracking ability is significantly improved compared to the conventional technology.

[0069] In this embodiment, the source of the first MOS transistor is connected to a common source of each MOS transistor in the cross PMOS circuits 31, 33 and the cross NMOS circuits 32, 34. Therefore, in this embodiment, when the switches SW1 to SW4 are off, the corresponding MOS transistors in the cross PMOS circuits 31, 33 and the cross NMOS circuits 32, 34 are on, and the gate potentials of both the PMOS and NMOS transistors constituting the switches SW1 to SW4 follow the source potential of the first MOS transistor with good precision and responsiveness.

[0070] Therefore, according to this embodiment, even if there is a sudden fluctuation in the input potential due to high-frequency noise being superimposed on the input, one of the PMOS and NMOS constituting the switches SW1 to SW4 can be maintained in the off state, preventing erroneous turn-on. Furthermore, according to the switch circuit 1 of this embodiment, it is possible to prevent the occurrence of malfunction even in a noisy environment such as an in-vehicle environment, and it is possible to obtain the excellent effect of improving noise immunity performance.

[0071] In this embodiment, in the series circuits SC1 and SC3 included in the switches SW1 and SW3, the arrangement is in the order of "NMOS 11, 15 → PMOS 12, 16" from the input node Nip side. Also, in this embodiment, in the series circuits SC2 and SC4 included in the switches SW2 and SW4, the arrangement is in the order of "PMOS 13, 17 → NMOS 14, 18" from the input node Nin side. A configuration employing such an arrangement can achieve the following effects.

[0072] That is, with the above configuration, fluctuations in the body potential and source potential of the second MOS transistors connected to the intermediate nodes N3 to N6 are kept relatively small, so that the amount of charge and discharge of the parasitic capacitance from the input nodes Nip and Nin when the switches SW1 to SW4 turn from off to on is small. The average of this charge and discharge amount becomes the input leakage current. Furthermore, with the above configuration, there is an advantage in that a sufficient gate drive amplitude can be easily obtained even when the capacitance values ​​of the drive capacitances Cd1 to Cd8 are relatively small.

[0073] In a comparative example in which the arrangement of the two MOS transistors in the series circuits SC1 to SC4 included in the switches SW1 to SW4 is reversed from that of the present embodiment, the body parasitic capacitance is discharged through the body-drain PN junction of the second MOS transistor every time the switches SW1 to SW4 are turned off, resulting in large fluctuations in the body potential. As a result, the configuration of the comparative example has drawbacks such as large charge / discharge currents, i.e., large input leakage currents, and small gate amplitudes when the switches SW1 to SW4 switch from off to on. In contrast, the configuration of the present embodiment can eliminate all of these drawbacks.

[0074] Furthermore, according to the configuration of this embodiment, when the switches SW1 to SW4 are turned on from off, the transient voltage VGS fluctuation of the second MOS transistor is suppressed, that is, the peak value of the voltage VGS fluctuation is kept small. Therefore, according to the switch circuit 1 of this embodiment, the gate oxide film stress of the MOS transistors constituting the switches SW1 to SW4 is alleviated, and a CCSW circuit with high long-term reliability can be realized.

[0075] For example, consider a case where the voltages Vinp and Vinn have the relationship expressed by the following equation (4), the switch drive amplitude is 5V / 0V, and the switches SW1 and SW2 are turned from off to on, and the switches SW3 and SW4 are turned from on to off. Vinp=Vinn+5V …(4)

[0076] At this time, if the parasitic capacitance is small enough to be negligible, the gate potential of NMOS12 changes from "Vinp" to "Vinp+5V", and the gate potential of PMOS11 changes from "Vinp" to "Vinp-5V", turning on switch SW1 and causing the potential on its left side to rise from "Vinn" to "Vinp".

[0077] Here, if the two MOS transistors constituting the switch SW1 were arranged in the reverse order to that of this embodiment, that is, in the order of "PMOS → NMOS" from the input node Nip side, the following problem could occur: In other words, with such an inverted arrangement, when the switch SW1 is in the off state and the entire NMOS, which is the second transistor, drops to the Vinn potential, and then the switch SW1 turns from off to on and the gate potential of the NMOS suddenly rises from "Vinp" to "Vinp+5V," there is a concern that the voltage VGS will become a voltage as shown in the following equation (5) at the beginning of this transient state. VGS≒(Vinp+5V)-Vinn=(Vinp-Vinn)+5V>5V …(5)

[0078] In contrast, with the arrangement of this embodiment, even when the switch SW1 is in the off state, the source of the first transistor NMOS11 is at the potential of Vinp, and its drain also remains at a potential close to Vinp, so that the second transistor PMOS12 maintains its off state. Therefore, with the arrangement of this embodiment, even in the transient state in which the switch SW1 transitions from off to on, neither the voltage VGS of NMOS11 nor PMOS12 exceeds ±5V.

[0079] According to the arrangement of this embodiment, similarly to switch SW1, switches SW2 to SW4 can transition from off to on in a transient state without the voltage VGS of either of the two MOS transistors exceeding ±5 V. As described above, according to this embodiment, a voltage exceeding the gate breakdown voltage, for example ±5 V, is not applied to the voltage VGS of the MOS transistors constituting switches SW1 to SW4, and therefore each MOS transistor constituting switches SW1 to SW4 can be driven without impairing long-term reliability.

[0080] Furthermore, in the prior art, a MOS transistor connected to one input node and a MOS transistor connected to the other input node are driven using a single shared drive capacitor, i.e., a drive capacitor is shared between two input nodes. Therefore, in the prior art, when the potential difference between the two input nodes becomes large, the voltage VGS for one MOS transistor cannot be sufficiently ensured, and the MOS transistor may not be able to be turned on. In contrast, in this embodiment, the gates of the multiple MOS transistors M11 to M18 are independently driven via multiple drive capacitors Cd1 to Cd8, so that the voltage VGS for the MOS transistors M11 to M18 can be sufficiently ensured and the MOS transistors M11 to M18 can be reliably turned on even when the potential difference between the input nodes Nip and Nin becomes large.

[0081] In this embodiment, the switches SW1 to SW4 include diodes Dc1 to Dc4 for accelerating charging the body parasitic capacitances of the MOS transistors that make up the series circuits SC1 to SC4. This configuration further improves the responsiveness of the voltage VGS of the MOS transistors, i.e., the responsiveness of the MOS transistors when driven.

[0082] (Second embodiment) The second embodiment will be described below with reference to FIGS. 2, the ΔΣ modulator 41 of this embodiment has a configuration that uses the switch circuit 1 and sampling capacitors Csp and Csn described in the first embodiment. In addition to the above configuration, the ΔΣ modulator 41 has a well-known configuration that includes multi-bit D / A converters 42 and 43, a passive integrator 44, an offset cancellation circuit 45, a preamplifier 46, a quantizer 47, a digital integrator 48, and a digital multi-bit quantizer 49, and a description of each of these components will be omitted.

[0083] The ΔΣ modulator 41 functions as a ΔΣ A / D converter that converts differential voltages Vinp and Vinn, which are analog signals input via input nodes Nip and Nin, into an output signal DOUT, which is a digital value. Each circuit in the above configuration operates using non-overlapping clocks of phases φ1D and φ2D. Specifically, a "non-overlapping two-phase + delayed clock" can be used as such a non-overlapping clock, as shown in Figure 3.

[0084] 3, in phase φ1A, the switches for connecting the other terminals of the sampling capacitors Csp and Csn to the common mode Vicm are turned on, and the switches for connecting the other terminals of the sampling capacitors Csp and Csn to the passive integrator 44 are turned off. In phase φ2A, the switches for connecting the other terminals of the sampling capacitors Csp and Csn to the common mode Vicm are turned off, and the switches for connecting the other terminals of the sampling capacitors Csp and Csn to the passive integrator 44 are turned on.

[0085] In phase φ1D, switches SW1 and SW2 of switch circuit 1 are turned on, and switches SW3 and SW4 of switch circuit 1 are turned off. In phase φ2D, switches SW1 and SW2 of switch circuit 1 are turned off, and switches SW3 and SW4 of switch circuit 1 are turned on. According to the above configuration, the switch on the common mode Vicm side is turned off first, and then, with a slight delay, the switch on the analog input side is turned off. As described above, switch circuit 1 can be applied to various uses, but is suitably applied to the ΔΣ modulator 41 described in this embodiment.

[0086] (Other embodiments) The present invention is not limited to the embodiments described above and illustrated in the drawings, but can be modified, combined, or expanded as desired without departing from the spirit of the invention. The numerical values ​​and the like shown in the above embodiments are examples and are not limited to these.

[0087] In the above embodiments, the back gates of the MOS transistors 11 to 18 constituting the switches SW1 to SW4 are connected to their sources, but they may be connected to their drains instead. The back gates of the MOS transistors 11 to 18 may be connected to their sources or drains via resistors or other elements, for example. That is, the back gates of the MOS transistors 11 to 18 may be connected to a location at the same potential as their sources or drains. Furthermore, current-limiting resistors or other protective elements may be added to one or both sides of the MOS transistors 11 to 18.

[0088] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0089] In addition to the inventions set forth in the claims, the present disclosure includes the following inventions. [1] A switch circuit used in a voltage detection circuit (2) configured to sample and detect the voltage of input nodes (Nip, Nin), a switch section (3) including switches (SW1 to SW4) that open and close the connection between the input node and sampling capacitors (Csp, Csn) provided in the voltage detection circuit; a control unit (4) that controls the operation of the switch unit and operates at a different potential from that of the switch unit; Equipped with the switches include series circuits (SC1 to SC4) each configured by connecting P-channel MOS transistors (12, 13, 16, 17) and N-channel MOS transistors (11, 14, 15, 18) in series; the back gate of the MOS transistor is connected to the source or drain thereof, or to a location at the same potential as the source or drain thereof; The control unit is a switch circuit configured to control the on / off of the switch by driving the gate of the MOS transistor via drive capacitances (Cd1 to Cd8). [2] The control unit a plurality of the driving capacitors provided corresponding to the plurality of MOS transistors constituting the switch, The switch circuit according to [1], wherein the gates of the plurality of MOS transistors are independently driven via the plurality of drive capacitors. [3] the control unit includes a drive circuit (20) that supplies a drive signal to a gate of the MOS transistor that constitutes the switch, the drive signal being at either an off level that turns off the MOS transistor or an on level that turns on the MOS transistor; The switch circuit according to [1] or [2], wherein the drive circuit generates the drive signal based on the potential of the input node corresponding to the switch. [4] In the series circuits (SC1, SC3) included in the switches (SW1, SW3), the N-channel MOS transistors (11, 15) and the P-channel MOS transistors (12, 16) are arranged in this order from the input node (Nip), The switch circuit according to any one of [1] to [3], further comprising a first diode (Dc1, Dc3) connected with the input node as its anode between the input node and an intermediate node (N3, N5) that is an interconnection node of the two MOS transistors that make up the series circuit. [5] In the series circuits (SC2, SC4) included in the switches (SW2, SW4), the P-channel MOS transistors (13, 17) and the N-channel MOS transistors (14, 18) are arranged in this order from the input node (Nin), The switch circuit according to any one of [1] to [4], further comprising a second diode (Dc2, Dc4) connected between the input node and an intermediate node (N4, N6) that is an interconnection node of the two MOS transistors that make up the series circuit, with the intermediate node side being the anode. [6] the voltage detection circuit has a differential configuration that samples the voltages of the two input nodes and detects the difference voltage between them; The switch unit The two input nodes are connected to and disconnected from the two sampling capacitors that are paired in a differential configuration; The switch may be: a first switch (SW1) that opens and closes between a first input node (Nip) that is the high potential side of the two input nodes and a first sampling capacitor (Csp) that is one of the two sampling capacitors; a second switch (SW2) that opens and closes between a second input node (Nin) that is the lower potential side of the two input nodes and a second sampling capacitor (Csn) that is the other of the two sampling capacitors; a third switch (SW3) that opens and closes between the first input node and the second sampling capacitor; a fourth switch (SW4) that opens and closes between the second input node and the first sampling capacitor; The switch circuit according to any one of [1] to [3], comprising: [7] In the series circuits (SC1, SC3) included in the first switch and the third switch, the N-channel MOS transistors (11, 15) and the P-channel MOS transistors (12, 16) are arranged in this order from the first input node side, The switch circuit according to [6], wherein the series circuits (SC2, SC4) included in the second switch and the fourth switch are arranged in the order of the P-channel MOS transistors (13, 17) and the N-channel MOS transistors (14, 18) from the second input node side. [Explanation of symbols]

[0090] 1...switch circuit, 2...voltage detection circuit, 3...switch section, 4...control section, 5...control section, 12, 13, 16, 17...P-channel MOS transistors, 11, 14, 15, 18...N-channel MOS transistors, 20...drive circuit, Cd1 to Cd8...drive capacitances, Csp, Csn...sampling capacitances, Dc1, Dc3...diodes, Dc2, Dc4...diodes, N3, N5...nodes, N4, N6...nodes, Nip, Nin...input nodes, SC1 to SC4...series circuits, SW1 to SW4...switches.

Claims

1. A switch circuit used in a voltage detection circuit (2) configured to sample and detect the voltage of an input node (Nip, Nin), a switch section (3) including switches (SW1 to SW4) that open and close between the input node and sampling capacitors (Csp, Csn) provided in the voltage detection circuit; a control unit (4) that controls the operation of the switch unit and operates at a different potential from that of the switch unit; Equipped with The switch includes a series circuit (SC1 to SC4) configured by connecting P-channel MOS transistors (12, 13, 16, 17) and N-channel MOS transistors (11, 14, 15, 18) in series, the back gate of the MOS transistor is connected to the source or drain thereof, or to a location at the same potential as the source or drain thereof; the control unit controls the on / off of the switch by driving the gate of the MOS transistor via drive capacitances (Cd1 to Cd8); In the series circuits (SC1, SC3) included in the switches (SW1, SW3), the N-channel MOS transistors (11, 15) and the P-channel MOS transistors (12, 16) are arranged in this order from the input node (Nip), The switch is a switch circuit having a first diode (Dc1, Dc3) connected with the input node side as the anode between the input node and an intermediate node (N3, N5) which is the interconnection node of the two MOS transistors that make up the series circuit.

2. A switch circuit used in a voltage detection circuit (2) configured to sample and detect the voltage of an input node (Nip, Nin), a switch section (3) including switches (SW1 to SW4) that open and close between the input node and sampling capacitors (Csp, Csn) provided in the voltage detection circuit; a control unit (4) that controls the operation of the switch unit and operates at a different potential from that of the switch unit; Equipped with The switch includes a series circuit (SC1 to SC4) configured by connecting P-channel MOS transistors (12, 13, 16, 17) and N-channel MOS transistors (11, 14, 15, 18) in series, the back gate of the MOS transistor is connected to the source or drain thereof, or to a location at the same potential as the source or drain thereof; the control unit controls the on / off of the switch by driving the gate of the MOS transistor via drive capacitances (Cd1 to Cd8); In the series circuits (SC2, SC4) included in the switches (SW2, SW4), the P-channel MOS transistors (13, 17) and the N-channel MOS transistors (14, 18) are arranged in this order from the input node (Nin), The switch is a switch circuit having a second diode (Dc2, Dc4) connected between the input node and an intermediate node (N4, N6) which is an interconnection node of the two MOS transistors that make up the series circuit, with the intermediate node side as the anode.

3. The control unit a plurality of the driving capacitors provided corresponding to the plurality of MOS transistors constituting the switch, 3. The switch circuit according to claim 1, wherein the gates of the plurality of MOS transistors are independently driven via the plurality of drive capacitors.

4. the control unit includes a drive circuit (20) that supplies a drive signal to a gate of the MOS transistor that constitutes the switch, the drive signal being at either an off level that turns off the MOS transistor or an on level that turns on the MOS transistor; 3. The switch circuit according to claim 1, wherein the drive circuit generates the drive signal based on the potential of the input node corresponding to the switch.

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