Non-volatile Integrated Circuit

Abstract

In view of the problems inherent in intermittent computing, an object of the present invention is to provide a non-volatile integrated circuit that can significantly reduce energy overhead. [Solution] The above problem has been solved by a non-volatile integrated circuit that saves and holds each bit of information stored and held by a plurality of flip-flops when power is supplied to a non-volatile memory area when power is cut off, and is characterized in that it comprises a plurality of non-volatile memory elements whose states are written and read individually corresponding to the plurality of flip-flops, and a reference element that does not individually correspond to the plurality of flip-flops, wherein the non-volatile memory elements are connected to only one of the complementary outputs of the corresponding flip-flops, and the state of the reference element is read out in common to a number of flip-flops that is a natural fraction of the number of the plurality of flip-flops.

Description

[Technical Field]

[0001] The present invention relates to a nonvolatile integrated circuit in which a nonvolatile memory element is incorporated inside a chip. [Background technology]

[0002] The power consumption of semiconductor integrated circuits consists of dynamic power consumption and static power consumption. Dynamic power consumption is the power consumed when the circuit is operating, i.e., when transistor circuits are switching, while static power consumption is the power consumed constantly due to transistor leakage current, regardless of whether the circuit is operating or not. As circuits become more highly integrated, the proportion of static power consumption in the power consumption of semiconductor integrated circuits has been increasing in recent years, making it an issue to find ways to reduce static power consumption. In particular, in IoT technology, edge devices such as mobile terminals and in-vehicle products remain in standby mode for a while after executing processing, making reducing static power consumption an urgent issue.

[0003] A common technique used is to cut off the power supply when no computation is being performed and to save information stored in volatile memory to external non-volatile memory, thereby preventing static power consumption. This technique is called power gating technology. Figure 1 is a graph illustrating the concept of power consumption reduction in power gating technology, with the horizontal axis representing time and the vertical axis representing power consumption. Of the two graphs shown in Figure 1, the left graph shows the trend in power consumption of a conventional semiconductor circuit, and the right graph shows the trend in power consumption of a semiconductor integrated circuit using power gating technology.

[0004] The graph on the left shows that the computation execution period, i.e., the period in which dynamic power consumption occurs, is discrete, while the period in which static power consumption occurs due to transistor leakage current is continuous. On the other hand, the graph on the right shows that power gating technology eliminates static power consumption during the power-off period. However, even when transitioning from the computation execution period to the power-off period, i.e., the power gating period, power consumption still occurs due to the backup process that saves information stored in volatile memory to external nonvolatile memory. Similarly, when transitioning from the power gating period to the computation execution period, power consumption still occurs due to the restore process that restores information saved in external nonvolatile memory to volatile memory. The energy loss and processing time associated with these power consumptions, combined with the loss of circuit utilization opportunities, are called overhead. Overhead reduces the power consumption reduction effect of power gating technology and reduces the period during which computations can be performed. According to previous research, the energy consumed when exchanging data with memory such as DRAM is said to be 10,000 times that consumed in calculations, which causes an increase in overhead. If the overhead can be reduced, the power reduction effect of power gating technology can be increased, and the period during which calculations can be executed can be extended.

[0005] To reduce overhead, instead of backing up data stored in volatile memory to external nonvolatile memory, nonvolatile LSIs incorporating nonvolatile memory elements within the chip have been proposed. Nonvolatile LSIs combine logic-in-memory integrated circuit technology and nonvolatile device technology. Logic-in-memory integrated circuit technology distributes memory functions within the arithmetic circuit, significantly reducing global wiring, thereby preventing transfer delays and reducing dynamic power consumption. Nonvolatile device technology eliminates the need for data transfer to external memory and enables rapid power cutoff, thereby reducing power consumption. Nonvolatile device technology also significantly reduces circuit size by directly stacking memory devices on CMOS. Nonvolatile logic circuit technology utilizing magnetic tunnel junction (MTJ) elements, a type of spintronics element, is known as a nonvolatile device. For example, Non-Patent Document 1 describes a nonvolatile flip-flop using MTJ elements as nonvolatile memory. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] K. Usami, D. Yokoyama, A. Kamei and H. Amano, “Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations,” 2022 IEEE Nordic Circuits and Systems Conference (NorCAS), Oslo, Norway, pp.1-7, 2022. Summary of the Invention [Problem to be solved by the invention]

[0007] Nonvolatile power gating using nonvolatile logic circuits makes it possible to make all modules of an integrated circuit nonvolatile and perform fine-grained power gating. Therefore, it is expected to significantly reduce wasted power consumption compared to conventional power gating, which combines volatile logic circuits and external storage circuits. Figure 2 is a graph illustrating the difference in power consumption reduction between conventional power gating and nonvolatile power gating, with the horizontal axis representing time and the vertical axis representing stored energy. Of the two graphs shown in Figure 2, the top graph shows conventional power gating, which combines volatile logic circuits and external storage circuits, and the bottom graph shows nonvolatile power gating.

[0008] In the upper graph, the difference in stored energy is small during restore processing, and the overhead is not that great, but the difference in stored energy is large during backup processing, resulting in a large overhead.On the other hand, in the lower graph, the difference in stored energy is small during backup processing as well, and the overhead is small.Comparing the upper and lower graphs, it can be seen that the slope of the energy change during the dynamic power consumption period, i.e., the calculation execution period, is the same, and as can be seen, the dynamic power consumption period, i.e., the energy that can be consumed to execute calculations and the period during which calculations can be executed, is significantly larger.

[0009] In recent years, energy harvesting, which harvests and utilizes energy from surrounding sources such as light and vibrations, has been attracting attention in IoT technology. Energy harvesting has the potential to supply infinite energy, enabling battery-less edge devices. However, the energy supplied by energy harvesting is weak and unstable. Therefore, for edge devices to process information stably, they must accumulate energy and, once a certain amount of energy has accumulated, repeatedly perform tasks that consume energy. This type of step-by-step task execution using power management is called intermittent computing, and the development of this technology will be crucial for using energy harvesting as an energy supply source.

[0010] Intermittent computing theoretically uses the same mechanism as the power gating technology described above, which does not rely on energy harvesting. However, while power gating technology that does not rely on energy harvesting saves data just before entering standby mode after a series of processes have been executed, intermittent computing, which executes tasks in stages, often needs to cut off the power supply in the middle of processing to save data. For this reason, overhead needs to be kept as small as possible.

[0011] In view of the problems inherent in such intermittent computing, an object of the present invention is to provide a non-volatile integrated circuit that can significantly reduce energy overhead. [Means for solving the problem]

[0012] In order to solve such problems, the present invention provides a nonvolatile integrated circuit that saves and holds each bit information stored in a plurality of flip-flops when power is supplied to a nonvolatile memory area when power is cut off, the nonvolatile integrated circuit comprising: a plurality of nonvolatile memory elements whose states are written and read in correspondence with the plurality of flip-flops; and a reference element that does not correspond to the plurality of flip-flops individually; , reading information from the nonvolatile memory element Configuring the Sense Amplifier In cross-coupled inverters The reference element is connected to the source of only one of the two NMOS transistors, and the state of the reference element is read out in common to a number of flip-flops that is a natural number equal to one of the plurality of flip-flops, thereby reducing energy overhead.

[0013] In addition, the present invention is characterized in that the nonvolatile memory element is a magnetic tunnel junction element.

[0014] The present invention is also characterized in that the reference element is a reference resistor whose resistance value does not change.

[0015] Furthermore, the present invention is characterized in that the reference element is the same element as the nonvolatile memory element connected to the flip-flop, but is configured so that the resistance does not change.

[0016] The present invention is also characterized by having a selection circuit for selecting the magnetic tunnel junction element to be written or read.

[0017] The present invention is also characterized in that reading from the nonvolatile memory element is performed by amplifying the voltage difference based on the difference between the resistance value of each nonvolatile memory element corresponding to each flip-flop and the resistance value of a reference element using a sense amplifier.

[0018] Furthermore, the present invention is characterized in that a sense amplifier is provided for each flip-flop.

[0019] Furthermore, the present invention is characterized in that the sense amplifier is provided in common to a number of flip-flops that is a natural number divided by the number of flip-flops.

[0020] The present invention also provides a non-volatile integrated circuit that backs up and holds each bit of information stored in a plurality of flip-flops when power is supplied to a non-volatile memory area when power is cut off, and is characterized in that it comprises a plurality of non-volatile memory elements whose states are written and read individually corresponding to the plurality of flip-flops, a reference element that does not individually correspond to the plurality of flip-flops, and a control unit, and the control unit writes and reads the states depending on the magnitude of the resistance value of the non-volatile memory element and the resistance value of the reference element. [Effects of the Invention]

[0021] According to the present invention, it is possible to provide a non-volatile integrated circuit that can significantly reduce energy overhead, which is useful not only for intermittent computing using energy harvesting, but also for general power gating techniques that do not rely on energy harvesting. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a graph for explaining the concept of power consumption reduction in power gating technology. [Figure 2] 10 is a graph for explaining the difference in power consumption reduction between conventional power gating and non-volatile power gating. [Figure 3] 1 is a diagram illustrating the characteristics of a magnetic tunnel junction element (MTJ element). [Figure 4] FIG. 1 is a circuit diagram of a nonvolatile flip-flop constituting a conventional nonvolatile integrated circuit. [Figure 5] FIG. 1 is an explanatory diagram showing a mechanism by which a conventional nonvolatile integrated circuit holds bit information. [Figure 6] FIG. 1 is an explanatory diagram showing a mechanism by which a shared reference type nonvolatile integrated circuit holds bit information. [Figure 7] 1 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention; [Figure 8] 10A and 10B are diagrams illustrating a restore process of a nonvolatile integrated circuit according to an embodiment of the present invention. [Figure 9] FIG. 10 is a diagram illustrating a backup process of the nonvolatile integrated circuit according to the embodiment of the present invention. [Figure 10] FIG. 2 is a diagram for explaining the internal structure of a backup circuit. [Figure 11] FIG. 2 is an explanatory diagram showing a sub-register block structure of a non-volatile integrated circuit (non-volatile register). [Figure 12] 10 is a graph showing verification results for a sub-register block structure. [Figure 13] FIG. 10 is a circuit diagram of a non-volatile integrated circuit according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention is based on logic-in-memory integrated circuit technology and nonvolatile device technology, and enables high density and reduced overhead. To understand the technical concept of the present invention, it is necessary to first understand the characteristics of nonvolatile memory elements and the mechanisms by which nonvolatile registers and nonvolatile flip-flops retain bit information. This will be explained first. The following explanation will be made using drawings. However, the drawings are created for explanatory purposes, and for clarity, elements unnecessary for the explanation may be intentionally omitted. Furthermore, for the purpose of explanation, elements may be intentionally enlarged or reduced in size, and are not drawn to scale.

[0024] <Prerequisite technical elements> (Characteristics of magnetic tunnel junction devices) To realize a nonvolatile LSI, a nonvolatile memory element embedded inside the chip is essential. A nonvolatile memory element may be an element whose resistance value changes under certain conditions, such as a tunneling magnetoresistance effect or a field-induced giant resistance change, but whose resistance value is stable in a static state. Examples of such elements include MTJ elements (magnetic tunnel junction elements), ReRAM (resistive random access memory), and PCM (phase change memory). In an embodiment of the present invention, an MTJ element is used. MTJ elements have advantageous characteristics over other nonvolatile memory elements in terms of write time, write endurance, and compatibility with CMOS.

[0025] Figure 3 is a diagram explaining the characteristics of a magnetic tunnel junction element (MTJ element). An MTJ element, which is a type of spintronics element, has a three-layer structure with an insulating layer disposed between two magnetic layers. In the figure, the upper magnetic layer is a free layer in which the sign of the spin current changes depending on the sign of a current of a certain magnitude, and the lower magnetic layer is a fixed layer in which the sign of the spin current does not change regardless of the sign of the current. By applying a rewrite current equal to or greater than the reversal threshold, the MTJ element can take two states: a parallel state in which the spin currents in the two magnetic layers are in the same direction, and an antiparallel state in which the spin currents in the two magnetic layers are in opposite directions. When in the parallel state, the MTJ element has low resistance (R P ) and when in the anti-parallel state, it becomes high resistance (R AP ) as shown in the resistance-current characteristics of Figure 3. AP ) when I AP-P When a current of more than this flows, a low resistance (R P ) the resistance value changes, but even if the applied current is removed in this state, the resistance value does not change. However, I P-AP If the current flows in the reverse direction, a high resistance (R AP ) The resistance value changes. These two resistance values ​​are used as bit information. In this way, the MTJ element can be said to have the dual properties of a variable resistor and a non-volatile memory.

[0026] (Regarding bit information retention in non-volatile flip-flops) Figure 4 is a circuit diagram of a nonvolatile flip-flop that constitutes a conventional nonvolatile register. If nonvolatile flip-flops are arranged in an array equal to the number of bits required, they will function as a nonvolatile register. A nonvolatile flip-flop is a flip-flop equipped with a nonvolatile power gating function. In the example shown here, a master-slave D flip-flop is given the functions of saving data to an MTJ element and restoring data from the MTJ element.

[0027] While power is supplied, data is held by two latches, just as in a normal flip-flop. Meanwhile, just before power is cut off, a backup process is performed by the backup circuit applying a rewrite current to the MTJ element. When power is subsequently restored, the slave latch acts as a sense amplifier to read the resistance difference, and a restore process is performed to restore the bit information held by the MTJ element to the D flip-flop.

[0028] In this way, the nonvolatile flip-flop that constitutes the conventional nonvolatile register has two MTJ elements corresponding to the complementary outputs of the flip-flop, and stores bit information by the difference in their resistance states. P ,R AP or R AP ,R P However, writing to an MTJ element requires a relatively large current, which results in a situation where the backup process accounts for a large portion of the energy consumption overhead, as shown in the upper graph of Figure 2.

[0029] In addition to the energy consumption overhead issue, nonvolatile flip-flops require large-sized transistors capable of applying sufficient current to the MTJ element. The inversion threshold current of an MTJ element is approximately 100 μA at room temperature, which is too large for a normal-sized transistor to pass. Therefore, data writing is only possible by using multiple dedicated backup control transistors with gate widths four to twelve times larger than the normal transistor. Since the write transistors occupy a large portion of the nonvolatile flip-flop, this results in significant area overhead. Therefore, the inventors propose a new nonvolatile register, which can be called a shared reference system, instead of the conventional nonvolatile register. Below, we explain the advantages of the shared reference system over the conventional system by examining the difference in the mechanism for retaining bit information.

[0030] (Comparison of old and new bit information retention in non-volatile integrated circuits) FIG. 5 is an explanatory diagram showing the mechanism by which a conventional non-volatile integrated circuit holds bit information, and FIG. 6 is an explanatory diagram showing the mechanism by which a shared reference non-volatile integrated circuit according to the present invention holds bit information.

[0031] When a conventional nonvolatile integrated circuit, or more precisely, a conventional nonvolatile flip-flop, stores bit information, two MTJ elements are used per bit, as shown in Figure 5, to generate and compare the difference in resistance required for the restore process from the MTJ elements. P ,R AP or R AP ,R P The two MTJ elements are written to have either of the complementary resistance states.

[0032] In contrast, the newly proposed shared reference method, as shown in Figure 6, prepares a reference MTJ element with a resistance value intermediate between high and low resistance, and reads bit information by comparing the resistance of the reference MTJ element with the resistance of the data retention MTJ element. In the shared reference method, the number of MTJ elements that are written per bit is reduced from two to one compared to the conventional method. This makes it possible to significantly reduce the write energy to the MTJ element that rewrites the value.

[0033] As shown in Figure 6, the reference MTJ element, whose resistance value is intermediate between high and low resistances, is constructed by combining four MTJ elements with the same resistance as the data-retention MTJ element. If a resistor with an intermediate resistance between the two MTJ element resistances can be prepared, it is not necessary to use an MTJ element to form a constant resistor. However, when actually designing a circuit, fabricating a fixed resistor using a semiconductor process creates area overhead and resistance variation due to manufacturing variations becomes an issue. In this regard, MTJ elements are implemented three-dimensionally in the wiring layer above the semiconductor, which is expected to reduce area overhead. However, implementing MTJ elements with different resistance values ​​on a single chip is technically difficult. For these reasons, a constant resistor is formed by combining four MTJ elements. However, if the above-mentioned problems can be overcome, it is of course possible to use another constant resistance element as the reference element. Having explained the premise of the present invention, we will now explain embodiments of the present invention.

[0034] <Embodiments of the present invention> (Non-volatile register configuration) 7 is a circuit diagram of a non-volatile integrated circuit according to an embodiment of the present invention. Here, an example of a non-volatile register is shown. The non-volatile register 100 according to an embodiment of the present invention is an N-bit register, and includes N bit information storage units 1, a shared read circuit 2, a controller circuit 3, and a backup circuit 4, as shown in FIG.

[0035] The bit information storage unit 1 has the functions of both volatile and nonvolatile memory by incorporating a data retention MTJ element 12 as a nonvolatile memory element inside the chip, and is realized by directly stacking the MTJ element, which is a storage device, on CMOS. The bit information storage unit 1 has a flip-flop 11 as volatile memory and a sense amplifier 13 for reading bit information. The flip-flop 11 is a D flip-flop.

[0036] The shared read circuit 2 is composed of a reference MTJ element 21 as a reference element and an MTJ selector circuit 22. The MTJ selector circuit 22 is disposed between the sense amplifier 13 and the reference MTJ element 21, and plays a role of selecting and connecting each of the bit information storage units 1. The fact that the reference MTJ element 21 is shared with each of the bit information storage units 1 is the greatest feature of the present invention, and is the reason for the name "shared reference system." Furthermore, in the nonvolatile register 100 according to the embodiment of the present invention, in addition to sharing the reference MTJ element 21 as a reference element, sharing of circuit functions is also achieved.

[0037] Conventional nonvolatile registers can be constructed by simply arranging their elemental nonvolatile flip-flops. However, in order to share the reference MTJ element and circuit functions, it is necessary to redesign the circuit structure of the entire register. Furthermore, because the reference MTJ element 21 is shared by each individual bit information storage unit 1, the operation that was performed all at once in the conventional method must now be performed one bit at a time in sequence, and a circuit to control this operation must be incorporated. The circuits for this purpose are the controller circuit 3, the shared read circuit 2, and the backup circuit 4.

[0038] The controller circuit 3 outputs a signal for selecting a bit for backup processing or restore processing. Specifically, the controller circuit 3 receives a signal WB or a signal LB from outside the nonvolatile register 100 and outputs bit selection signals S1 to SN. Specifically, in the backup processing, when the pulse signal WB is input N times, the values ​​of the bit selection signals S1 to SN are switched in sequence accordingly, and a write current flows to the data retention MTJ element 12 that retains the data of the selected bit. In the restore processing, when the pulse signal LB is input N times, the values ​​of the bit selection signals S1 to SN are switched in sequence accordingly, and the selected sense amplifier 13 and the reference MTJ element 21 are electrically connected, and the value stored in the data retention MTJ element 12 is read out to the flip-flop 11.

[0039] The MTJ selector circuit 22 in the shared read circuit 2 receives a bit selection signal Sn output from the controller circuit 3 and connects the corresponding n-th sense amplifier 13 to the reference MTJ element 21 by turning on an internal NMOS transistor. The sense amplifier 13 amplifies the voltage difference based on the resistance value of the data retention MTJ element 12 and the resistance value of the reference MTJ element 21. The result is read into the flip-flop 11 as a volatile memory, and a restore process is performed.

[0040] The backup circuit 4 is integrated and incorporated into the entire nonvolatile register 100. Details of the backup circuit 4 will be described after the explanation of the restore process and backup process.

[0041] (Data restoration process) The data restore process will now be described. Fig. 8 is a diagram illustrating the restore process of the nonvolatile integrated circuit (nonvolatile register) according to an embodiment of the present invention, and is a partial circuit diagram of the rectangular area A indicated by the dashed line in the circuit diagram of Fig. 7.

[0042] In the restore process, first, the controller circuit 3 outputs bit selection signals S1 to SN, and one of the bit selection signals S1 to SN is input to the MTJ selector circuit 22. Next, the MTJ selector circuit 22 connects the selected one sense amplifier 13 to the reference MTJ element 21. At this time, the controller circuit 3 supplies a read signal LB to the sense amplifier 13. In response to this, the sense amplifier 13 supplies a read current I to the data retention MTJ element 12 and the reference MTJ element 21. READ The information is read by applying a voltage difference between the two MTJ elements, which is generated by the difference in the amount of current due to the difference in resistance between the two MTJ elements, and amplifying the voltage difference.

[0043] In this way, the bit information stored in the data retention MTJ element 12 is restored to the flip-flop 11. A series of restore processes is executed for each bit within one clock cycle. For example, if the register bit length is 32 bits, 32 clocks are required for restore.

[0044] (Data backup processing) The data backup process will now be described. Fig. 9 is a diagram illustrating the backup process of a nonvolatile integrated circuit (nonvolatile register) according to an embodiment of the present invention, and is a partial circuit diagram of the rectangular area B indicated by the dashed line in the circuit diagram of Fig. 7. Fig. 10 is a diagram illustrating the internal structure of a backup circuit, with the left side showing the internal structure of the backup circuit in a conventional nonvolatile register and the right side showing the internal structure of the backup circuit in a shared reference nonvolatile register.

[0045] In the backup process, the controller circuit 3 inputs the bit selection signals S1 to SN and the write signal WB to the backup circuit 4. The backup circuit 4 applies a write current only to the data retention MTJ element 12 selected in response to the bit selection signals S1 to SN. At this time, the backup circuit 4 determines the direction of the current to be passed according to the bit information of the selected flip-flop 11.

[0046] As shown on the left side of Figure 10, the backup circuit in a conventional non-volatile register uses eight write transistors per bit to pass write current to the MTJ element. In contrast, as shown on the right side of Figure 10, the backup circuit in a non-volatile register with a shared reference uses two write transistors per bit, and the two write transistors are shared. As indicated by the arrow on the right side of Figure 10, one of the write transistors and the shared write transistor form a current path, allowing the write current to pass only to a specific MTJ element. As a result, the shared reference method uses only one-fourth the number of write transistors compared to the conventional method, significantly reducing the area overhead.

[0047] Regarding energy overhead, although the write operation that was performed once in conventional nonvolatile registers must be performed N times depending on the number of bits, the number of MTJ elements targeted by each write operation is reduced to 1 / N, so the impact of this on overhead is small. Rather, the effect of reducing the number of transistors contributes greatly to reducing not only the area but also the energy overhead.

[0048] On the other hand, the time required for read and write processing is N times, which is longer than that of conventional methods. However, while the typical interval between intermittent operations in intermittent computing is several ms, the time required for register backup and restore processing is at most several μs, and the former time is significantly longer than the latter time, so the increase in the time required for read and write processing is not a major problem.

[0049] (Performance evaluation) In the above embodiments, the number of integrated flip-flops has been described as N for an N-bit register. However, the number of integrated flip-flops can be freely selected for a shared reference non-volatile register. For example, even if the total bit length is 32 bits, there are several options, such as 32 integrated flip-flops, eight sub-register blocks integrated in 4-bit increments, or four sub-register blocks integrated in 8-bit increments. Increasing the integration density of the non-volatile register allows for a more compact circuit configuration, but the backup and restore control becomes more complex.

[0050] To find the optimal integration granularity, we integrated a 32-bit nonvolatile register at multiple granularities and performed verification. Figure 11 shows the sub-register block structure of a nonvolatile register. (1) shows a conventional nonvolatile register consisting of 32 nonvolatile flip-flops with two MTJ elements per bit. (2) shows a 32-bit nonvolatile register designed to write data to only one MTJ element by replacing one MTJ element with a reference resistor. (3) shows a schematic diagram of the sub-register block structure integrated into 2-, 4-, 8-, 16-, and 32-bit units for a 32-bit nonvolatile register (4- and 8-bit units are shown as representatives in the figure). These nonvolatile registers were designed using 55-nm CMOS / MTJ hybrid process technology and evaluated using the circuit simulator "HSPICE."

[0051] Figure 12 is a graph showing the verification results for the sub-register block structure. The graph on the left shows the circuit area converted into the number of transistors, specifically the area calculated by converting the sum of the product of the gate width W, gate length L, and parallel number M of the transistors that make up the non-volatile register into the minimum number of transistors. The graph on the top right shows the energy consumption during backup processing, and the graph on the bottom right shows the energy consumption during restore processing.

[0052] When a 32-bit non-volatile register was integrated with an 8-bit granularity, the circuit area was reduced by 39% and the power consumption was reduced by 49% compared to conventional non-volatile registers. However, when the integration level was increased to 16 bits or 32 bits, the control circuit became more complex, which resulted in an increase in the circuit area and a slight increase in the energy consumption during restore.

[0053] <Another embodiment of the present invention> FIG. 13 is a circuit diagram of a nonvolatile integrated circuit according to another embodiment of the present invention. A nonvolatile register 100A according to another embodiment of the present invention, taking an 8-bit register as an example, includes eight flip-flops 11A, eight data-holding MTJ elements 12A, one reference MTJ element 21A, a shared read circuit 2A, one shared sense amplifier 13A, an MTJ selector circuit 22A, a controller circuit 3A, a backup circuit 4A, and a demultiplexer 5A, as shown in FIG. 13. The shared read circuit 2A includes the reference MTJ element 21A, as in the previously described embodiment. However, the shared read circuit 2A includes only one shared sense amplifier 13A, which differs from the previously described embodiment. That is, while the previously described embodiment includes sense amplifiers in the same number as the number of bits, this embodiment includes only one sense amplifier.

[0054] Regarding the operation process, the operation of the flip-flop during the dynamic power consumption period and the backup process are the same as in the previously described embodiment. Only the specifications for the restore process are different. Specifically, the bit selection signal switched by the input of the pulse signal LB turns on the NMOS transistor inside the MTJ selector circuit 22A, connecting the data retention MTJ element 12A to the shared read circuit 2A. The bit selection signal also simultaneously controls the demultiplexer 5A located between the shared read circuit 2A and the flip-flop 11A, restoring data to the specified flip-flop 11A. Although the area reduction achieved by sharing the sense amplifier may not be significant, it is shown here because it allows for alternative circuit designs.

[0055] Although the nonvolatile integrated circuits according to the embodiments and other embodiments of the present invention have been described in detail above, the specific configurations are not limited to these embodiments, and the present invention also includes design changes within the scope of the present invention. For example, a static random access memory (SRAM) may be used instead of a register, an NMOS transistor switch may be configured as a CMOS, and a flip-flop described as a D flip-flop may be configured as an RS flip-flop or a JK flip-flop. The nonvolatile memory elements are also not limited to MTJ elements, and other nonvolatile memory elements such as a ReRAM (resistive random access memory) or a PCM (phase change memory) may be used.

[0056] However, the technical advantage of sharing the reference MTJ element reduces the energy consumption when writing to the MTJ element and significantly reduces energy overhead, which leads to an increase in the available calculation time to the point where the length of time required for backup processing can be ignored, and its advantages should be properly understood. [Explanation of symbols]

[0057] 1-bit information storage unit 11. Flip-Flop 12 Data retention MTJ element 13 Sense Amplifier 2 Shared readout circuit 21 Reference MTJ element 22 MTJ selector circuit 3 Controller circuit 4 Backup circuit 100 Non-volatile Registers 11A Flip-Flop 12A data retention MTJ element 13A Sense Amplifier 2A shared readout circuit 21A Reference MTJ element 22A MTJ selector circuit 3A controller circuit 4A backup circuit 5A Demultiplexer 100A non-volatile register

Claims

1. A nonvolatile integrated circuit that saves and holds each bit information stored in a plurality of flip-flops when power is supplied to a nonvolatile storage area when power is cut off, a plurality of nonvolatile memory elements whose states are written and read in correspondence with the plurality of flip-flops; a reference element that does not individually correspond to the plurality of flip-flops; the nonvolatile memory element is provided in a corresponding flip-flop, and is connected to only one source of two NMOS transistors in a cross-coupled inverter that constitutes a sense amplifier that reads information from the nonvolatile memory element; the reference element has a state read out in common to a number of flip-flops that is a natural fraction of the number of flip-flops; This reduces the energy overhead. A non-volatile integrated circuit comprising:

2. The nonvolatile memory element is a magnetic tunnel junction element.

2. The nonvolatile integrated circuit according to claim 1.

3. The reference element is a reference resistor whose resistance value does not change.

3. The nonvolatile integrated circuit according to claim 2.

4. The reference element is the same element as the nonvolatile memory element connected to the flip-flop, but is configured so that the resistance does not change.

3. The nonvolatile integrated circuit according to claim 2.

5. A selection circuit is provided to select the magnetic tunnel junction element to be written or read.

5. The nonvolatile integrated circuit according to claim 4.

6. Reading from the nonvolatile memory element is performed by amplifying a voltage difference based on the difference between the resistance value of each nonvolatile memory element corresponding to each flip-flop and the resistance value of the reference element using a sense amplifier.

6. The nonvolatile integrated circuit according to claim 5.

7. The sense amplifier is provided for each flip-flop.

7. The nonvolatile integrated circuit according to claim 6.

8. a control unit; The control unit executes writing and reading of the state depending on the magnitude of the resistance value of the nonvolatile memory element and the resistance value of the reference element.

2. The nonvolatile integrated circuit according to claim 1.

Images