Semiconductor-superconductor hybrid devices with electrode arrays

Abstract

The semiconductor-superconductor hybrid device (100) comprises a semiconductor member (110) having a channel in the form of a nanowire in use, a superconducting member (120) capable of inducing superconductivity in the semiconductor member by proximity effect, and an array of finger gates (140). The finger gates are individually actuatable to apply respective electrostatic fields to respective segments of the channel. The array of finger gates allows localized control over the electrical potential within corresponding segments of the nanowire. Methods of fabricating and operating the semiconductor-superconductor hybrid device are also provided.

Description

[Technical Field]

[0001] This application relates to a semiconductor-superconductor hybrid device having an electrode array. [Background technology]

[0002] Semiconductor nanowires in close proximity to superconductors are expected to host topological phases of matter under appropriate conditions. This makes them promising candidates as building blocks for fault-tolerant quantum computers. A practical realization is provided by semiconductor nanowires based on two-dimensional electron gases ("2DEG") in close proximity to conventional superconductors, which are typically grown as part of epitaxial 2D wafer stacks but can also be deposited after material growth during fabrication. This material platform possesses reasonable spin-orbit coupling and a large electron g-factor, which are key elements for the formation of topological states. The 2D platform enables complex device geometries via top-down lithographic patterning, including etching and deposition.

[0003] The topological phase manifests itself in the form of a pair of Majorana zero modes (MZMs) at the ends of the nanowire. Along the bulk of the wire, there exists a gap in the single-electron spectrum, moving away from the ends. Experiments typically use tunneling spectroscopy at the ends of the nanowire, detecting a zero-bias peak (ZBP) in the tunneling conductance.

[0004] By forming a network of such nanowires and inducing topological regions in parts of the network, it is possible to form quantum bits (qubits), which can be manipulated for quantum computing. A quantum bit, also called a qubit, is an element that can perform a measurement that has two possible outcomes, but at any given time (when not measured), can actually be a quantum superposition of two states corresponding to different outcomes.

[0005] To induce a topological phase, the device is cooled to a temperature where the superconductor (e.g., aluminum) exhibits superconducting behavior. The superconductor induces a proximity effect in the adjacent semiconductor, causing the region of the semiconductor near its interface to exhibit superconducting properties, i.e., inducing a superconducting pair gap in the adjacent semiconductor. In this region of the semiconductor, a magnetized zone metal (MZM) forms when a magnetic field is applied to the device. Summary of the Invention [Problem to be solved by the invention]

[0006] The role of a magnetic field is to lift the spin degeneracy of a semiconductor. Degeneracy in a quantum system refers to the case where different quantum states have the same energy levels. Lifting degeneracy means forcing such states to adopt different energy levels. Spin degeneracy refers to the case where different spin states have the same energy levels. Spin degeneracy can be lifted by a magnetic field, resulting in a splitting of energy levels between differently spin-polarized electrons. This is known as the Zeeman effect. The Zeeman energy, i.e., the magnitude of the energy level splitting, needs to be at least as large as the superconducting gap to close the tiny superconducting gap and reopen the topological gap in the system.

[0007] Furthermore, inducing MZMs typically requires tuning the electrostatic potential of charge carriers within the nanowire by gating the nanowire with an electrostatic potential. The electrostatic potential is applied using a gate electrode. The application of an electrostatic potential manipulates the number of charge carriers in the conduction band or valence band of the semiconductor material.

[0008] There is a need to characterize the electronic properties of semiconductor-superconductor hybrid systems. [Means for solving the problem]

[0009] In one aspect, the present invention provides a semiconductor-superconductor hybrid device comprising, in use, a semiconductor member having a channel in the form of a nanowire, a superconductor member capable of inducing superconductivity in the semiconductor member by proximity effect, and an array of finger gates, the finger gates being individually actuatable to apply respective electrostatic fields to respective segments of the channel.

[0010] In another aspect, the present invention provides a method of operating a semiconductor-superconductor hybrid device, the method comprising the steps of cooling the semiconductor-superconductor hybrid device to a temperature at which the superconductor member exhibits superconductivity, applying a magnetic field to the channel of the semiconductor-superconductor hybrid device, and applying a voltage to the finger gate.

[0011] In yet another aspect, the present invention provides a method for fabricating a semiconductor-superconductor hybrid device, the method comprising the steps of fabricating the semiconductor member, fabricating the superconductor member, and fabricating the array of finger gates.

[0012] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Nor is the claimed subject matter limited to embodiments that solve any or all of the problems described herein.

[0013] To facilitate an understanding of embodiments of the present disclosure, and to show how such embodiments may be put into practice, reference is made to the accompanying drawings, which are for illustrative purposes only. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a plan view of a semiconductor-superconductor hybrid device. [Figure 2] FIG. 2 is a schematic cross-sectional view of a portion of the device of FIG. 1. [Figure 3a] 2 is an optical microscope photograph of a chip having a device of the type shown in FIG. 1, the device being positioned at position A. [Figure 3b] 3a is a scanning electron microscope (SEM) image of position A in FIG. 3a. [Figure 4] 1 is a schematic cross-sectional view illustrating an array of finger gates disposed on a semiconductor heterostructure. [Figure 5] 1 is a flow chart outlining a method for operating a semiconductor-superconductor hybrid device. [Figure 6] 1 is a plot showing an example of irregular potential along the length of a channel compared to an ideal case. [Figure 7] 1 is a flowchart illustrating a method for fabricating a semiconductor-superconductor hybrid device. DETAILED DESCRIPTION OF THE INVENTION

[0015] As used herein, the verb "have" is used as a shorthand for "comprise or consist of." In other words, the verb "have" is intended to be an open term. However, replacing this term with the closed term "consisting of" is expressly contemplated, particularly when used in reference to chemical compositions.

[0016] Directional terms such as "top," "bottom," "left," "right," "upper," "lower," "horizontal," and "vertical" are used herein for convenience of description and refer to the directions shown in the associated drawings. For the avoidance of doubt, this terminology is not intended to limit the orientation of the device in an external frame of reference.

[0017] As used herein, the term "channel" refers to a region of a semiconductor through which electrical current can flow, rather than a physical trench in the material. The channel may, in particular, be in the form of a nanowire.

[0018] As used herein, the term "superconductor" refers to a material with a critical temperature T c "Superconductivity" refers to a material that becomes superconducting when cooled to a temperature below 1000 K. The use of this term is not intended to limit the temperature of the device.

[0019] A "nanowire" is an elongated member having a nanoscale width, with a length-to-width ratio of at least 100, at least 500, or at least 1000. Typical examples of nanowires have widths of 10 to 500 nm, optionally 50 to 100 nm, or 75 to 125 nm. The length is usually on the order of micrometers, e.g., at least 1 pm, or at least 10 pm. Nanowires can be considered to be quasi-one-dimensional.

[0020] The ends of the nanowires may be defined by a material boundary (e.g., in the case of selective area grown nanowires in semiconductors), or electrostatically (e.g., by applying an electrostatic field to deplete charge carriers from the semiconductor and define the ends), or by a combination of the two (e.g., one end may be a material boundary and the other end may be defined electrostatically).

[0021] The term "bonding" in the context of this disclosure refers to the hybridization of energy levels.

[0022] The term "magnetic field" encompasses "real" and "effective" magnetic fields unless the context clearly indicates otherwise. "Real" magnetic fields are referred to as "classical" magnetic fields and are the types of fields produced by electromagnets or permanent magnets. "Effective" magnetic fields result from the spin-dependent scattering of electrons from the boundary between a conducting or superconducting component and a ferromagnetic insulating component.

[0023] A "semiconductor-superconductor hybrid structure" has semiconductor and superconductor members that can be coupled together under certain operating conditions. In particular, the term refers to a structure that can exhibit topological behavior, such as Majorana zero modes, or other excitations useful for quantum computing applications. Generally, the operating conditions are determined by the T c cooling the structure to a temperature below 1000 K, applying a magnetic field to the structure, and electrostatically gating the structure. Generally, at least a portion of the semiconductor member is in intimate contact with the superconductor member; for example, the superconductor member may be epitaxially grown on the semiconductor member. However, certain device structures have been proposed that have one or more additional members between the semiconductor member and the superconductor member.

[0024] One technique used to measure the potential is scanning tunneling microscopy (STM). STM involves scanning a sample with a sharp metal tip, obtaining information about the density of states from electrons tunneling between the tip and the sample. Applying STM to semiconductor-superconductor hybrid devices is extremely challenging. STM measurements are difficult to perform under the conditions required to induce topological phases (low temperatures, high magnetic fields, etc.). Furthermore, most measurements end up measuring the density of states of the parent superconductor.

[0025] For semiconductor-superconductor hybrid nanowires, tunneling conductance measurements can be performed. In tunneling conductance measurements, the end of the nanowire, which is not coated with superconductor material, can be operated like the tip of a scanning tunneling microscope. Electrons can tunnel from the end of the semiconductor nanowire into the proximity system, revealing information about the density of states at the end of the nanowire. However, this type of measurement is only applicable to the end of the device, which is not coated with superconductor material. It would be beneficial to be able to perform measurements directly on the portion of the device that is coated with superconductor material.

[0026] Furthermore, disorder in a nanowire (i.e., random variations in potential) can create undesirable topological boundaries along the length of the nanowire, which are detrimental to the topological phase and reduce its value in topological quantum computation. Furthermore, non-uniformity in potential along the nanowire can also result in zero-bias peaks due to non-topological Andreev bound states (ABS), especially near the ends of the nanowire. The devices provided herein may be operable to compensate for the disorder.

[0027] Disclosed herein are device architectures that allow in-situ fine tuning of the potential along a nanowire. For example, the devices allow tuning of the potential, eliminating unwanted variations due to irregularities, or allowing the investigation of potentials with different shapes. The device architectures described herein may provide a means to form one or more tunnel contacts on the sides of the wire in any arrangement. Tuning and measurement over length scales on the order of 100 nm may be achieved.

[0028] An example of a semiconductor-superconductor hybrid device 100 will now be described with reference to Figures 1 to 3. Figure 1 is a schematic plan view of the device. Figure 2 is a schematic cross-sectional view of a portion of the device. Figure 3a is an optical microscope photograph of an example tip incorporating the device, and Figure 3b is a scanning electron microscope image of an example device.

[0029] The device 100 includes a semiconductor member 110 and a superconductor member 120 disposed on the semiconductor member 110. As shown in FIG.

[0030] The substrate 105 provides a base on which the semiconductor material 110 is grown. The substrate 105 typically comprises a wafer, i.e., a piece of single crystal material. One example wafer material is indium phosphide. Other examples of wafer materials include gallium arsenide, indium antimony, indium arsenide, and silicon.

[0031] The substrate may further include additional structures disposed on or above the wafer. The substrate may include two or more layers of material. In particular, the substrate may include a buffer layer. It is desirable to obtain a good lattice match between immediately adjacent layers of material. In other words, it is preferable that adjacent layers have lattice constants that are as similar as possible. To this end, the buffer layer may include a material selected to have a lattice constant between that of the crystalline substrate 105 and the subsequent layer, which in this example is the lower barrier 112 of the semiconductor member 110.

[0032] The semiconductor component 110 in this example is a semiconductor heterostructure having a lower barrier 112 epitaxially disposed on the substrate 105, a quantum well 114 epitaxially disposed on the lower barrier 112, and an upper barrier 116 epitaxially disposed on the quantum well 114. The lower barrier 112, the quantum well 114, and the upper barrier 116 are each in the form of a layer.

[0033] This structure is called a heterostructure because the quantum well has a material that is different from the material of the lower and upper barrier layers, each of which may be selected independently.

[0034] The configuration of the lower barrier 112 and the upper barrier 116 is not particularly limited, so long as these layers trap electrons in the quantum well 114. The lower barrier 112 may include one or more layers of one or more different materials. The upper barrier 116 may include one or more layers of one or more different materials. Constructing the barriers from multiple layers may provide defect filtering, i.e., reduce the effects of dislocations in the crystal structure of the materials used.

[0035] The quantum well layer 114 comprises a layer of semiconductor material that may have a relatively small bandgap compared to the materials of the lower barrier 122 and the upper barrier 126. Examples of materials useful for forming quantum wells are described, for example, in Odoh and Njapba, “A Review of Semiconductor Quantum Well Devices,” Advances in Physics Theories and Applications, vol. 46, 2015, pp. 26-32; and S. Kasap, P. Capper (Eds.), “Springer Handbook of Electronic and Photonic Materials,” DOI 10.1007 / 978-3-319-48933-9_40.

[0036] In operation, charge is localized in the quantum well 114. In particular, the quantum well may host a two-dimensional electron gas. The two-dimensional electron gas may be further confined to region 114a through the use of a gate electrode, as described in more detail below. In particular, region 114a may be in the form of a nanowire. Beneficial excitations, such as Majorana zero modes, may be generated in such nanowires. Region 114a is also referred to as a channel.

[0037] The device further includes a superconductor member 120. In this example, the superconductor member includes an elongated strip of superconductor material with contact pads at each end. FIG. 3a shows an example of contact pads 335. Each of the contact pads may be connected to an electrical ground. The elongated strip is disposed across the channel of the semiconductor member 110. Upon actuation, energy level hybridization may occur between the superconducting material of the elongated strip and the semiconductor material of the channel 114a.

[0038] The nature of the superconductor is not particularly limited and may be selected as appropriate. The superconductor is typically an s-wave superconductor. Any of a variety of conventionally known s-wave superconductors may be used. Examples include aluminum, indium, tin, and lead. In some embodiments where aluminum is used, the superconductor member may have a thickness in the range of 3 to 20 nm.

[0039] 2, instead of being disposed directly on the channel 114a, the superconductor member is disposed on an upper barrier layer 116 of the semiconductor member 110. The upper barrier layer 116 may serve to adjust the strength of the interaction between the superconductor member 120 and the channel. The concept of using a barrier layer to adjust the strength of the interaction between a superconductor and a semiconductor is described in detail in U.S. Patent Application Publication No. 2021 / 0126181 A1.

[0040] Device 100 further includes a boundary depletion gate 130. In operation, boundary depletion gate 130 is used to apply an electrostatic field that defines one end of channel 114a by depleting charge carriers from quantum well 114 in the region below boundary depletion gate 130. The electrostatic field applied using boundary depletion gate 130 may also provide coarse adjustment of the potential in channel 114a.

[0041] The boundary depletion gate has edges that, in a plane, are parallel to the edges of the elongated strip portion of superconductor member 120. As shown in Figure 2, boundary depletion gate 130 may overlap superconductor member 120 and may be separated from superconductor member 120 by dielectric material 160. In such an embodiment, the superconductor member at least partially shields channel 114a from the electrostatic field applied by the boundary depletion gate.

[0042] Device 100 further includes an array of finger gates 140a, 140b...140n. The array of gate electrodes 140 is disposed along an opposite side of superconductor member 120 from boundary depletion gate 130. Each finger gate in the array has an end, in a plane, adjacent channel 114a.

[0043] Finger gates are narrow gate electrodes. Typically, finger gates have widths of 150 nm or less, and sometimes less than 50 nm or even 25 nm. It is desirable to make each finger gate as narrow as possible. The minimum width is limited only by the resolution of the method chosen to fabricate the finger gates.

[0044] The spacing between laterally adjacent finger gates is preferably small, for example, may be less than 10 nm. As shown with reference to Figure 4, laterally adjacent finger gates do not necessarily have to be in the same plane. The finger gates are separated from each other by a dielectric material to prevent current flow between them.

[0045] The number of finger gates may be selected as needed, depending, for example, on the channel length of the device. Typically, a device will have at least 10 finger gates. There is no particular upper limit to the number of finger gates in the array.

[0046] The device may be configured so that an individually selected voltage can be applied to each finger gate of the array 140. For example, each finger gate may be connected to a respective contact pad. Figure 3a shows a number of contact pads 345 for the array of finger gates.

[0047] During operation, a voltage is applied to the finger gates of the array 140. The finger gates operate to define the ends of the channel 114a. Each finger gate of the array applies an electrostatic field to a corresponding segment of the channel 114a. By applying individually selected voltages to individual ones of the finger gates 140, it is possible to control the potential of individual segments of the channel. Fine control over the potential within the channel is useful for a variety of different purposes, which will be described in more detail below with reference to methods of operating the device.

[0048] Figure 3b is a scanning electron microscope (SEM) image of a portion of region A of the tip shown in Figure 3a. As can be seen, the device has an array of closely spaced finger gates. The image is annotated to show the location of the superconductor member 320. The channel of this device is below the superconductor member.

[0049] The device 100 further includes leads 150a and 150b. The leads 150a and 150b are electrodes disposed under each group of finger gates 140. A group of finger gates that is a subset of the array 140 may also be referred to as a subarray. The leads 150a and 150b are separated from the finger gates by a dielectric 160. Each of the leads 150a and 150b may be operably coupled to a respective amplifier circuit. The amplifier circuit may be disposed on the same substrate as the device. Alternatively, each of the leads may be connected to a respective contact pad (e.g., contact pads 355a and 355b in FIG. 3a), which may then be connected to the amplifier circuit. An example of a suitable commercially available amplifier is the SP938c current-to-voltage converter available from Basel Precision Instruments.

[0050] The ends of the leads 150a, 150b are adjacent to the channel 114a in a plan view. The distance between the ends of the leads 150a, 150b and the channel is selected to allow electrons to tunnel between the leads and the channel 114a when an appropriate electrostatic field is applied to one of the finger gates of the subarray. By passing a tunneling current between the channel and one or both of the leads, various measurements can be made on the channel. Exemplary measurement methods are discussed below.

[0051] The leads may be fabricated from the same material as the superconductor member 120. By applying a magnetic field in a direction parallel to the elongated strip portion of the superconductor member, the leads act as normal conductors while the elongated strip of the superconductor member becomes superconducting.

[0052] Various modifications may be made to the example device.

[0053] The inclusion of a boundary depletion gate is optional. Alternatively, the channel end may be provided by a material boundary. The material boundary may be formed by etching a semiconductor heterostructure to form a semiconductor member in the form of a mesa disposed on a substrate. Alternatively, the semiconductor member may be in the form of a selectively-area-grown nanowire.

[0054] Although the illustrated example includes a single boundary depletion gate, two or more boundary depletion gates may be used. In such an embodiment, each boundary depletion gate may be located on an opposite side of a subarray of the array of gate electrodes. According to a further possibility, the boundary depletion gate may be replaced by a second array of finger gates of the type described with reference to the array of finger gates 140. The second array of finger gates may be associated with one or more leads of the type described with reference to leads 150a, 150b.

[0055] An example device has two leads. There may be any number of leads. The device may include a single lead, or three or more leads.

[0056] In embodiments where the ability to perform tunneling measurements is not necessary, the inclusion of leads is optional. In such embodiments, an array of electrodes may be used to define the channel length and / or compensate for channel irregularities. Suitable gate voltages can be determined by trial and refinement, for example, by incrementally adjusting individual gate voltages. The incremental adjustments may be controlled by a classical computer implementing a suitable optimization process.

[0057] An exemplary configuration of an array of finger gates will now be described with reference to Figure 4, which shows a schematic cross section perpendicular to the array of finger gates in a device of the type shown in Figure 1.

[0058] The structure 400 shown is disposed on a semiconductor member 410 on top of a substrate 405. The semiconductor member 410 is as described with reference to Figures 1 and 2 and includes a quantum well 414 disposed between a lower barrier 412 and an upper barrier 416.

[0059] Disposed over the semiconductor member 410 is a dielectric 460. Examples of materials useful as the dielectric include silicon oxide (SiO x ), silicon nitride (SiN x ), aluminum oxide (AlO x ), and hafnium oxide (HfO x) are included. More than one dielectric layer may be present. Dielectric 460 is beneficial in preventing short circuits that would otherwise occur between the finger gate or superconductor member and the semiconductor member. Dielectric 460 may be beneficial in protecting the semiconductor member during fabrication of the finger gate, particularly in embodiments where the step of fabricating the finger gate includes an etching operation. Dielectric 460 may be omitted in embodiments where a Schottky barrier is present between the semiconductor member and the superconductor member / finger gate.

[0060] A first layer of finger gates 442a, 442b, 442c, 442d is disposed on the dielectric 460. The finger gates of the first layer 442 are laterally spaced apart from one another.

[0061] The second dielectric 462 covers the first layer of the finger gates 442. In this embodiment, the second dielectric 460 also extends beyond the spaces between the finger gates of the first layer 442. The material used to form the second dielectric 462 is not particularly limited, and may be, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), and hafnium oxide (HfO x ) may be included.

[0062] The first layer of the finger gate may be fabricated from a metal having an insulating native oxide. Examples of such metals include aluminum, niobium, or tantalum, with aluminum being particularly preferred. This allows the second dielectric 462 to be more suitably formed by oxidation of the metal. For example, the finger gate may be patterned and then exposed to oxygen to form the second dielectric 462. Alternatively, the finger gate may be patterned simultaneously with the fabrication of the second dielectric by using selective anodization to pattern the finger gate 442. In particular, the finger gate may include aluminum, and the second dielectric may include aluminum oxide.

[0063] The second layer of finger gates 444a, 444b, 444c are disposed on the second dielectric 462 in the spaces between the finger gates of the first layer 442. Forming the finger gates in two stages allows for smaller lateral spacing between adjacent finger gates than would otherwise be possible. The second dielectric allows for a planned overlap of the first and second layers of finger gates without creating shorts between the finger gates.

[0064] In the example shown, the second dielectric 362 extends into the spaces between the first set of finger gates, but in other embodiments, the second dielectric 362 need not be a single layer and may just cover the finger gates 442 themselves. In particular, in embodiments in which the finger gates include aluminum, the dielectric may be a native oxide that forms on aluminum when exposed to oxygen. The form of the dielectric 362 is not particularly limited, so long as adjacent finger gates are electrically insulated from each other.

[0065] A method for operating a semiconductor-superconductor hybrid device will now be described with reference to Figure 5. Figure 5 is a flow chart outlining the method.

[0066] In block 501, a semiconductor-superconductor hybrid device is cooled to a temperature at which the superconductor members become superconducting. In other words, the device is cooled to a temperature below the critical temperature of the superconductor members. In one example, a typical operating temperature for a device of the type provided herein may be 50 mK or less. The device is maintained below the critical temperature during its operation.

[0067] Various cryogenic systems suitable for cooling superconductor devices to operating temperatures are well known, one illustrative example being a dilution refrigerator.

[0068] In block 502, a magnetic field is applied to at least the channel of the device.

[0069] The magnetic field may be a "real" magnetic field, in other words a classical magnetic field, applied externally, such as by means of an electromagnet.

[0070] The magnetic field may be an "effective" magnetic field. The device may have a ferromagnetic insulator member, which may provide spin-dependent scattering of electrons from the interface between the superconductor and the ferromagnetic insulator. The spin-dependent scattering of electrons acts as an effective magnetic field. Examples of ferromagnetic insulators include EuS and EuO.

[0071] The effective magnetic field provided by the ferromagnetic insulator may be used in combination with the actual magnetic field provided by the electromagnet, and in such an embodiment, the strength of the effective magnetic field can be controlled by averaging it with the actual applied magnetic field.

[0072] Applying a real or effective magnetic field to the device (via spin-dependent scattering) allows different spin states within the device to adopt different energy levels. This effect is called "lifting spin degeneracy." Lifting the spin degeneracy may close a small superconducting gap within the device and reopen a topological gap.

[0073] The magnetic field may include a component perpendicular to the spin-orbit field direction, e.g., a component parallel to the length of the elongated portion of the superconductor member disposed above the channel 114a. The critical magnetic field of a member fabricated from a superconductor material may be anisotropic, i.e., may vary depending on the direction of the magnetic field. In embodiments where the device includes leads, when a magnetic field is applied in a direction parallel to the length of the elongated portion of the superconductor member, the superconductor member may maintain superconductivity while the leads function as normal conductors. This allows for normal-insulator-super (NIS) tunneling conductance between the channel and the leads, rather than super-insulator-super (SIS) tunneling conductance. For example, the critical magnetic field of the leads in a direction parallel to the channel may be on the order of approximately 200 mT.

[0074] The magnetic field is applied throughout the operation of the device. For example, the magnetic field strength may be 1 T or greater.

[0075] In embodiments where a boundary depletion gate is used to define the end of the channel, a gate voltage is applied to the boundary depletion gate, which electrostatically defines the end of the channel by depleting charge carriers from the region of the semiconductor material below the boundary depletion gate, and may provide coarse electrostatic adjustment of the potential in the channel.

[0076] In block 503, voltages are applied to the finger gates, which then apply respective electrostatic fields to respective segments of the channel. The voltages applied to each finger gate may be individually selected, allowing control over the electrostatic potential in the channel. Various effects may be achieved by selecting the gate voltages.

[0077] The electrostatic potential within a nanowire varies randomly along its length. This is called spatial disorder, or simply disorder. Various sources of disorder are postulated. Without wishing to be bound by theory, it is believed that charges trapped at the interface between the material and impurities within the material may contribute to the disorder. Disorder makes it difficult to induce extended topological phases in hybrid structures.

[0078] One use of an array of finger gates is to compensate for irregularities. By individually selecting a gate voltage for each finger gate, local variations in electrostatic potential at the corresponding segment of the nanowire can be counterbalanced. Each portion of the nanowire experiences a different electrostatic field, and these different fields may act to smooth out the irregularities.

[0079] In particular, an array of finger gates may be used to control the potential at different sections along the nanowire. For example, it may be desirable to investigate the effect of different potentials on the behavior of the device. For example, it may be desirable to investigate the effect of potential dips, potential bumps, or periodic (spatial oscillations at various wavelengths) variations in potential, or, for example, U-shaped variations in potential. Finger gates may be used to compensate for irregularities while providing a desired tailored potential profile.

[0080] Another use of the finger gates in the array allows for control of the length of the channel. When a suitable voltage is applied to a finger gate, that finger gate may deplete a corresponding segment of the nanowire. In other words, the corresponding segment of the nanowire is finely tuned. The depleted segment effectively becomes the end of the channel. Thus, the length of the channel can be selected by actuating selected ones of the finger gates to define the location of the end of the channel.

[0081] Any combination of these three modes of operation, i.e., compensating for irregularities, adjusting potential, and controlling effective length, is possible. For example, outer finger gates may be selected to define the length of the channel, and finger gates between the selected outer finger gates may be actuated to control the electrostatic potential within the channel, compensate for irregularities, and / or provide a tailored potential profile. The selected outer finger gates may be single finger gates or groups of finger gates.

[0082] These two use cases are illustrated in Figure 6, which is a simulated plot showing the electrostatic potential along the length of a nanowire.

[0083] The solid trace in Figure 6 shows the idealized case where a constant electrostatic potential is induced in the nanowire across the channel of total length x.

[0084] The dashed trace in Figure 6 shows a diagram of the chaotic variation of the electrostatic potential along the length of the nanowire compared to the idealized case.

[0085] The array of finger gates is operable to control the channel length x by selecting a finger gate or group of finger gates at either end of the nanowire and depleting a corresponding region of the nanowire with the selected finger gate. The finger gates positioned along the channel length x are operable to compensate for irregularities in the electrostatic potential, causing the actual potential to approach the ideal case.

[0086] In this example, a single channel is defined on the nanowire. It is also envisioned that an array of finger gates can be actuated to define two or more channels along a single nanowire. In other words, the finger gates are actuable to define junctions between multiple channels arranged in series. This can be useful in building qubit devices with multiple operably linked channels.

[0087] In embodiments where the semiconductor-superconductor hybrid device has at least one lead, the finger gate is operable to allow various measurements of the electronic properties of the channel.

[0088] These measurements rely on electron tunneling between the channel and the leads. The array of finger gates allows control over where tunneling occurs, allowing characterization of electronic properties at different points along the nanowire. This offers a replacement for scanning tunneling microscopy, which is difficult to apply in practice to semiconductor-superconductor hybrid devices due to the conditions under which they are operated and the challenges posed by the presence of a superconductor layer above the channel.

[0089] A finger gate located above the lead is selected to allow electron tunneling between the channel and the lead. A voltage is applied to the selected finger gate that does not completely deplete the semiconductor material between the channel and the lead. This voltage is typically zero or a positive voltage compared to the potential of the channel. This allows tunneling conductance between the channel and the lead at the location of the selected finger gate, with the semiconductor acting as a tunable tunnel barrier. Finger gates operated in this manner are referred to herein as "spectroscopic mode."

[0090] At the same time, other finger gates in the array may be actuated to define the ends of the channel, compensate for irregularities, and / or adjust the potential within the channel, as described above. In particular, other finger gates may be actuated to counteract or correct any changes in the electrostatic potential within the channel caused by actuating the selected finger gate in the spectroscopic mode.

[0091] A tunneling current through the leads is measured, which may include using an amplifier circuit connected to the leads to amplify the tunneling current. Based on the measured tunneling current, information about the electronic properties of the channel at the location of the selected finger gate may be determined. For example, a zero-bias peak may be observed if a Majorana zero mode exists at the location of the selected finger gate, or in other words, if the selected finger gate corresponds to the edge of a topological region. Conversely, if a finger gate in a spectroscopic mode is placed at the center of the topological region, a gap in the tunneling conductance near zero bias may be observed.

[0092] If desired, a voltage bias may be applied to the leads and the tunneling current may be measured as a function of the voltage bias.

[0093] The channel characteristics may be scanned by repeatedly selecting one or more different finger gates of the array to operate in spectroscopic mode and measuring the tunneling current of the selected finger gates. One finger gate, or any combination of finger gates, may be operated in spectroscopic mode at a time, depending on the measurement being performed.

[0094] When a new gate is selected and operated in spectroscopic mode, the voltages applied to the other gates of the array may be modified to counteract or modify any changes in the electrostatic potential in the channel caused by the selected gate operating in spectroscopic mode. In other words, each iteration may include modifying the voltages applied to one or more additional finger gates in addition to modifying the voltages applied to the selected finger gate.

[0095] The measured tunneling current may be a local tunneling current. To measure the local tunneling current, one finger gate of the array is operated in a spectroscopic mode. The method may include determining a local conductance based on the local tunneling current.

[0096] The measured tunneling current may be a nonlocal tunneling current. The nonlocal tunneling current may be measured when the device includes two leads and at least one finger gate associated with each lead is operated in a spectroscopic mode. The tunneling current may provide a measure of the current through the channel, since current may flow through the channel from one lead to the other. Based on the nonlocal tunneling current, the nonlocal conductance may be determined. The size of the topological gap of the channel may be determined based on the nonlocal conductance.

[0097] More generally, any number of finger gates located on any number of leads may be operated in spectroscopic mode, allowing measurements via any number of terminals.

[0098] A voltage bias may be applied to the leads during the measurement, and it may be desirable to measure the tunneling conductance as a function of the voltage bias on the leads.

[0099] The spatial resolution of the measurement depends on the spacing of the finger gates. A spatial resolution of about 100 nm is achievable.

[0100] A method for fabricating a semiconductor-superconductor hybrid device of the type described herein will now be described with reference to Figure 7, which is a flow diagram outlining the method.

[0101] In block 701, a semiconductor component is fabricated. Fabricating a semiconductor component typically involves growing one or more layers of one or more semiconductor materials on a substrate. Examples of useful techniques for growing semiconductor components include molecular beam epitaxy (MBE), metalorganic vapor phase epitaxy (MOVPE), etc.

[0102] If desired, fabricating the semiconductor component may further include selectively etching the layer of semiconductor material to form the semiconductor component having a desired shape. For example, the layer may be etched to form a mesa. Etching may be performed before or after fabricating the superconductor component. An exemplary etchant composition useful for etching III-V semiconductor materials includes an aqueous solution of citric acid, phosphoric acid, and hydrogen peroxide.

[0103] In block 702, a superconductor member is fabricated.

[0104] Fabricating a superconductor member may include globally depositing a layer of superconductor material on a semiconductor member and then patterning the layer of superconductor material to form the superconductor member. As used herein, the term "global deposition" means covering the entire surface of the deposited material. The patterning process may include a lift-off process or selective etching controlled by a mask. Suitable etchants for superconductor materials are commercially available. One example of an etchant suitable for etching aluminum is Transene D, which is an aqueous solution of phosphoric acid, sodium n-nitrobenzene sulfonic acid, and acetic acid.

[0105] Alternatively, the superconductor member may be fabricated by selective deposition of the superconductor material. For example, the superconductor member may be fabricated by directional deposition controlled by a shadow wall. A shadow wall is a material disposed on a substrate that blocks a beam of material, thereby defining a shadow region where no material is deposited. One example of a method utilizing a shadow wall is described in U.S. Patent Application Publication No. 2020 / 0243742 A1.

[0106] In embodiments in which the device has one or more leads, the one or more leads may be fabricated from the superconductor material at the same time that the superconductor member is fabricated. Alternatively, the one or more leads may be fabricated in a separate step. If the one or more leads are fabricated separately from the superconductor member, the one or more leads may comprise a different material than the superconductor member.

[0107] An array of finger gates is fabricated in block 703. Optional boundary depletion gates or additional gate electrodes may be fabricated simultaneously with the array of finger gates.

[0108] In embodiments where the semiconductor-superconductor hybrid device has one or more leads, fabricating the array of finger gates may include depositing a layer of dielectric material on top of the one or more leads and the superconductor member, and then forming the array of finger gates on the layer of dielectric material. The layer of dielectric material may be grown by atomic layer deposition.

[0109] The step of forming the array of finger gates includes globally depositing an electrode material, and then patterning the electrode material to form the array of finger gates.

[0110] The array of finger gates may be fabricated in stages. A first set of spaced apart finger gates may be fabricated on a layer of dielectric material. A dielectric may then be formed on the first set of finger gates. Forming the dielectric may include depositing a layer of dielectric by, for example, atomic layer deposition. Alternatively, in embodiments in which the finger gates are formed from a metal having an insulating native oxide, such as aluminum, forming the dielectric may include oxidizing the surfaces of the first set of finger gates. After forming the dielectric, a second set of finger gates may be formed in the gaps between the first set of finger gates, allowing for closer packing of the finger gates.

[0111] It will be understood that the above-described embodiments are presented by way of example only.

[0112] More generally, in one aspect disclosed herein, there is provided a semiconductor-superconductor hybrid device which, in use, comprises a semiconductor member having a channel in the form of a nanowire, a superconductor member capable of inducing superconductivity in the semiconductor member by proximity effect, and an array of finger gates individually actuatable to apply respective electrostatic fields to respective segments of the channel, the array of finger gates enabling localized control over the electrical potential at corresponding segments of the nanowire.

[0113] The channel may have, for example, a width in the range of 10 to 125 nm and a length of at least 1 pm. The superconductor member may include an elongated strip disposed above the channel.

[0114] The semiconductor element may be a heterostructure with a quantum well disposed between an upper barrier and a lower barrier. The use of an array of finger gates has been investigated, particularly for quantum well-based devices. Alternatively, other semiconductor elements may be used, such as selective-area grown elements.

[0115] The device may further include a boundary depletion gate operable to electrostatically define a first end of the channel, and the array of finger gates may be operable to electrostatically define a second end of the channel opposite the first end.

[0116] The semiconductor-superconductor hybrid device may further include a first lead disposed under a first subarray of the array of finger gates, and a dielectric disposed between the lead and the array of finger gates. The first lead has an end that may be spaced from the channel by a distance selected to allow electron tunneling between the channel and the lead. For example, the distance may be in the range of 20 to 200 nm. In such an embodiment, when the finger gates are adjusted to a suitable regime, it is possible to measure the tunneling current between the lead and the channel, thereby enabling investigation of the electronic properties of the channel.

[0117] The leads may be operably coupled to an amplifier circuit, which may be a current-to-voltage amplifier, which is beneficial because it amplifies the tunneling current and facilitates detection of the tunneling current.

[0118] The semiconductor-superconductor hybrid device may further include a second lead. The second lead may be disposed below a second subarray of the array of finger gates, separate from the first subarray. A dielectric may be disposed between the second lead and the array of finger gates. The second lead may have an end, and the end may be spaced from the channel by a distance selected to allow electron tunneling between the channel and the second lead.

[0119] Like the first lead, the second lead may be operably coupled to an amplifier circuit, which may be a current-to-voltage amplifier.

[0120] The inclusion of at least two leads allows for the measurement of a wider range of electronic properties of the channel, for example, it may enable non-local conductance measurements.

[0121] The devices provided herein may have any number of leads.

[0122] The array of finger gates may include a lower layer of finger gates and an upper layer of finger gates. The device may further include a dielectric covering the lower layer of finger gates. The upper layer of finger gates may be disposed on top of the dielectric and may be laterally offset from the lower layer of finger gates. The dielectric may define recesses corresponding to spaces between the finger gates of the lower layer. The finger gates of the upper layer may be at least partially disposed in the recesses. A higher density of finger gates may be achieved by fabricating the array of finger gates in two stages. For example, a first set of finger gates may provide a template to aid in the fabrication of a second set of finger gates.

[0123] The underlying finger gates may comprise a metal with an insulating native oxide. The dielectric layer may include the native oxide of the metal, which may make it easier to form the dielectric between the finger gates. For example, the metal may be aluminum, which may form a native oxide simply upon exposure to oxygen.

[0124] Each finger gate may have a width of 150 nm or less, and if necessary, a width of 25 nm or less. The spacing between adjacent finger gates may be 25 nm or less. Providing narrow, closely spaced finger gates may allow for higher resolution control and / or measurement of the electronic properties of the channel.

[0125] The number of finger gates may be suitably selected depending on the length of the channel. The array of finger gates may have at least 10 finger gates, and if necessary, at least 40 gate electrodes. Providing a large number of finger gates allows for greater control over the electronic properties of the nanowire.

[0126] The superconductor member may include an elongated strip of superconductor. The elongated strip may be disposed above the channel. The elongated strip may have a width of 125 nm or less. The superconductor member may have two ends. Each of the ends may be electrically grounded.

[0127] In another aspect, a method of operating a semiconductor-superconductor hybrid device is provided, the method comprising the steps of cooling the semiconductor-superconductor hybrid device to a temperature at which the superconductor member exhibits superconductivity, applying a magnetic field to at least a channel of the semiconductor-superconductor hybrid device, and applying a voltage to a finger gate.

[0128] Applying a voltage to the finger gates may include applying an individually selected voltage to each of the finger gates. For example, applying a voltage to the finger gates may include actuating at least one finger gate to compensate for local irregularities in each segment of the channel. "Local irregularities" refer to random deviations of the electrostatic potential of the nanowire from a target electrostatic potential. Local irregularities can arise, for example, from trapped charges, impurities in the material, and other sources. Compensating for irregularities in the channel can induce extended topological phases in the device.

[0129] Alternatively or additionally, applying an individually selected voltage to each of the finger gates may include inducing a predetermined potential profile in the channel.

[0130] The method may further include selecting a finger gate to act as a first end finger gate, wherein applying a voltage includes actuating the first end finger gate to deplete charge carriers from a respective segment of the channel, thereby defining a first end of an active portion of the channel.

[0131] The method may further include selecting finger gates to act as second end finger gates, and applying a voltage may include actuating the second finger gates to deplete charge carriers from respective segments of the channel, thereby defining a second end of the active portion of the channel. The array of finger gates may be actuated to control the length of the active portion of the channel by selectively depleting charge carriers from the end of the channel. The method may further include changing the length of the active portion of the channel, for example, by selecting a new combination of finger gates to act as first and second end finger gates.

[0132] In addition to controlling the length of the channel, the method may include compensating for irregularities in the channel and / or adjusting the potential. For example, the first end finger gate and the second end finger gate may further have a finger gate therebetween, and applying a voltage may include actuating another finger gate to compensate for local irregularities in each segment of the channel.

[0133] Finger gates not aligned with the active portion of the channel, i.e., beyond the first end finger gate and the second end finger gate, may be actuated to deplete charge carriers from respective segments of the channel. Adjacent groups of finger gates may be actuated to define a first end of the channel. Adjacent groups of finger gates may be actuated to define a second end of the channel.

[0134] The device may further include a first lead disposed under a subarray of the array of finger gates and a dielectric disposed between the lead and the array of finger gates. The first lead may have an end separated from the channel by a distance selected to allow electron tunneling between the channel and the lead. In such an embodiment, the method may further include selecting a finger gate of the first subarray and measuring a tunneling current by applying a voltage to the selected finger gate, the selected finger gate being selected to cause electron tunneling between the segment of the channel corresponding to the selected finger gate and the first lead, and measuring the current through the first lead. Measuring the tunneling current may enable determination of electronic properties of the channel. For example, detection of a zero-bias peak may indicate the presence of a Majorana zero mode in the segment of the channel corresponding to the selected finger gate.

[0135] The method may further include applying a bias voltage to the first lead.

[0136] The method may include measuring a tunneling current using a selected finger gate and simultaneously actuating at least one other finger gate to compensate for local irregularities in the channel. The method may further include simultaneously controlling a length of the channel using at least one other finger gate.

[0137] The method may further include selecting different finger gates of the first subarray and measuring the tunneling current. Electronic properties along the length of the channel may be characterized by measuring the tunneling current at different segments of the nanowire. Measuring the tunneling current provides a measure of the electrical potential within the channel, which may itself be useful for characterizing the properties of the channel.

[0138] The device may further include a second lead, the second lead being disposed beneath a second subarray of the array of finger gates, separate from the first subarray, and a dielectric may be disposed between the second lead and the array of finger gates. The second lead may have an end, the end being spaced from the channel by a distance selected to allow electron tunneling between the channel and the second lead. The method may further include selecting a finger gate of the second subarray, measuring a tunneling current by applying a voltage to the selected finger gate, the voltage being selected to cause electron tunneling between the segment of the channel corresponding to the selected finger gate and the first lead, and measuring the current through the second lead. By simultaneously measuring the tunneling current through two or more leads, it is possible to determine the nonlocal conductance through the channel based on the tunneling current. The method may further include applying bias voltages, e.g., source and drain biases, to the first and second leads.

[0139] The method may further comprise selecting different combinations of finger gates and measuring the tunneling current. By repeating the finger gate combinations, electronic properties through different portions of the channel may be measured.

[0140] The method may further comprise determining a non-local conductance through the channel based on the measured current.

[0141] It will be understood that the devices used to practice the method aspects may have any of the features described with reference to the device aspects.

[0142] In yet another aspect, there is provided a method of fabricating a semiconductor-superconductor hybrid device of the type described above, the method comprising the steps of fabricating a semiconductor member, fabricating a superconductor member, and fabricating an array of finger gates.

[0143] The step of fabricating the semiconductor component may comprise forming a semiconductor heterostructure in the form of a stack on a substrate, and then selectively removing the semiconductor heterostructure by etching to form the semiconductor component in the form of a mesa.

[0144] Next, additional metal features, such as bond pads and transmission lines, may be fabricated. The array of finger gates may then be fabricated. Fabricating the additional metal features separately from the gates in the active portion of the device is advantageous because the additional metal may be thicker than the gates, allowing a lower resolution fabrication process to be used.

[0145] The step of forming the array of finger gates may include the steps of: forming a lower layer of finger gates, the lower layer of finger gates having a plurality of finger gates with spaces between them; forming a dielectric on the lower layer of finger gates; and forming an upper layer of finger gates on the dielectric, the upper layer of finger gates being disposed above the spaces between the lower layer of finger gates. In this way, by fabricating the array of finger gates in two steps, a higher density of finger gates can be achieved. Constraints otherwise imposed by limited-resolution techniques, such as electron beam lithography, may be eliminated.

[0146] The lower layer of the finger gate may be formed from a metal having an insulating native oxide, the dielectric comprising a native oxide of the metal, which allows for a simple formation of the dielectric and avoids the step of depositing a layer of dielectric on top of the lower layer of the finger gate.

[0147] Other modifications or applications of the disclosed technology will become apparent to those skilled in the art once disclosed herein, and the scope of the disclosure is limited only by the appended claims, rather than by the described embodiments.

Claims

1. A semiconductor-superconductor hybrid device comprising: In use, a semiconductor member having channels in the form of nanowires; a superconductor member capable of inducing superconductivity in the semiconductor member by a proximity effect; an array of finger gates, the finger gates being individually actuatable to apply respective electrostatic fields to respective segments of the channel; and the array of finger gates comprises a lower layer of finger gates and an upper layer of finger gates; The device further comprises a dielectric layer covering an underlying layer of the finger gate; The semiconductor-superconductor hybrid device, wherein the upper layer of the finger gate is disposed on top of the dielectric layer and is laterally offset from the lower layer of the finger gate.

2. moreover, a first lead disposed below a first subarray of the array of finger gates; a dielectric disposed between the first lead and the array of finger gates, the first lead having an end spaced from the channel by a distance selected to allow electron tunneling between the channel and the first lead; and The semiconductor-superconductor hybrid device of claim 1 , wherein the first lead is operably coupled to an amplifier circuit.

3. Further, it has a second lead, the second lead is disposed below a second subarray of the array of finger gates, separate from the first subarray; the dielectric is further disposed between the second lead and the array of finger gates; the second lead has an end, the end being spaced from the channel by a distance selected to allow electron tunneling between the channel and the second lead; The semiconductor-superconductor hybrid device of claim 2 , wherein the second lead is operably coupled to an amplifier circuit.

4. the semiconductor member is a heterostructure having a quantum well disposed between an upper barrier and a lower barrier; i) the semiconductor-superconductor hybrid device further comprises a boundary depletion gate operable to electrostatically define a first end of the channel, and the array of finger gates operable to electrostatically define a second end of the channel opposite the first end; or ii) The semiconductor-superconductor hybrid device of any one of claims 1 to 3, further comprising another array of finger gates disposed on an opposite side to the array of finger gates, the array of finger gates operable to define electrostatically opposed ends of the channel.

5. A semiconductor-superconductor hybrid device as described in any one of claims 1 to 4, wherein the underlying finger gate comprises a metal having an insulating native oxide, and the dielectric layer has the native oxide of the metal.

6. the dielectric layer defines recesses corresponding to spaces between the finger gates of the underlying layer; The semiconductor-superconductor hybrid device of claim 5 , wherein the finger gate of the upper layer is at least partially disposed in the recess.

7. i) each of said finger gates has a width of 150 nm or less; and / or ii) The semiconductor-superconductor hybrid device according to any one of claims 1 to 6, wherein the array of finger gates comprises at least 10 finger gates.

8. the superconductor member comprises an elongated strip of superconductor; the elongated strip is disposed above the channel, the elongated strip having a width of 125 nm or less; 8. The semiconductor-superconductor hybrid device according to claim 1, wherein the superconductor member has two ends, each of which is electrically grounded.

9. A method of operating the semiconductor-superconductor hybrid device of any one of claims 1 to 8, comprising the steps of: The method comprises: cooling the semiconductor-superconductor hybrid device to a temperature at which the superconductor member exhibits superconductivity; applying a magnetic field to at least the channel of the semiconductor-superconductor hybrid device; applying a voltage to the finger gate; A method comprising:

10. applying a voltage to the finger gates includes applying an individually selected voltage to each of the finger gates; 10. The method of claim 9, wherein applying a voltage to the finger gates comprises actuating at least one finger gate to compensate for local irregularities in each segment of the channel.

11. moreover, selecting a finger gate to function as a first end finger gate; applying the voltage includes actuating the first end finger gate to deplete charge carriers from a respective segment of the channel, thereby defining a first end of an active region of the channel; The method further includes selecting a finger gate to function as a second end finger gate; 11. The method of claim 9 or 10, wherein applying the voltage comprises actuating the second end finger gate to deplete charge carriers from a respective segment of the channel, thereby defining a second end of the active region of the channel.

12. and / or further comprising varying the length of the active region of the channel; 12. The method of claim 11 , wherein the first end finger gate and the second end finger gate have another finger gate therebetween, and wherein applying a voltage comprises actuating the another finger gate to compensate for local irregularities in each segment of the active region of the channel.

13. The device further comprises: a first lead disposed below a first subarray of the array of finger gates; a dielectric disposed between the leads and the array of finger gates; and the first lead has an end, the end being spaced from the channel by a distance selected to allow electron tunneling between the channel and the first lead; The method further comprises: selecting one finger gate of the first subarray; applying a voltage to the selected finger gate, the selected finger gate being selected to cause electron tunneling between the segment of the channel corresponding to the selected finger gate and the first lead; and measuring the current through the first lead; measuring the tunneling current by and 13. The method of claim 9, further comprising the steps of selecting different finger gates of the first sub-array and measuring the tunneling current.

14. The device further comprises a second lead; the second lead is disposed below a second subarray of the array of finger gates, separate from the first subarray; the dielectric is further disposed between the second lead and the array of finger gates; the second lead has an end spaced from the channel by a distance selected to allow electron tunneling between the channel and the second lead; The method further comprises: selecting one finger gate of the second subarray; applying a voltage to the selected finger gate, the selected finger gate being selected to cause electron tunneling between the segment of the channel corresponding to the selected finger gate and the first lead; applying respective voltage biases to the first lead and the second lead; and measuring the current through the second lead; measuring the tunneling current by and 14. The method of claim 13, further comprising selecting a different finger gate of the second sub-array and measuring the tunneling current.

15. 10. A method for fabricating the semiconductor-superconductor hybrid device of claim 1, comprising: The method comprises: A step of manufacturing the semiconductor member; fabricating the superconductor member; fabricating an array of said finger gates; and The step of fabricating the array of finger gates comprises: forming a lower layer of the finger gates, the lower layer of the finger gates having a plurality of finger gates with spaces therebetween; forming a dielectric on top of the lower layer of the finger gate; forming an upper layer of finger gates on the dielectric, the upper layer finger gates being disposed across spaces between the lower layer finger gates; and The method of claim 1, wherein an underlayer of the finger gate is formed of a metal having an insulating native oxide, and the dielectric comprises the native oxide of the metal.

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