Amplifier circuit, power amplifier circuit, and bias generation circuit

Abstract

To provide an amplification circuit capable of applying a gate bias not exceeding the withstand voltage of a transistor even when a power-supply voltage varies.SOLUTION: An amplification circuit includes: an input terminal to which an amplification target signal is inputted; a first FET having a gate to which the signal inputted to the input terminal is applied; a second FET and a third FET connected between a power supply and a reference potential together with the first FET; an output terminal for outputting an amplified signal, and provided between the third FET arranged at a nearest side to the power supply and a load; a voltage-dividing resistor circuit for generating a bias to be applied to the gates of the second FET and the third FET; and a clamp circuit for clamping a bias applied to the gate of the third FET when the bias applied to the gate of the second FET from the voltage-dividing resistor circuit exceeds a predetermined reference voltage. The first FET to the third FET are vertically stacked and connected.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit, a power amplifier circuit, and a bias generation circuit. [Background technology]

[0002] An amplifier circuit in which transistors, which are amplifying elements, are connected in a vertical stack is known (for example, Patent Document 1). In the amplifier circuit of Patent Document 1, multiple stages of transistors are provided between a power supply and a reference potential. Furthermore, a signal to be amplified is input to the base of the transistor of the multiple stages that is closest to the ground potential. Furthermore, a load is connected between the power supply and the transistor of the multiple stages that is closest to the power supply. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-097643 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in communication devices, the power supply voltage may not be constant but may fluctuate. For example, the power supply voltage may fluctuate depending on the output power, i.e., the power mode, of the mobile communication device. In such cases, if the amplifier circuit of Patent Document 1 described above is used, the following problems may occur. Specifically, if the gate bias of the transistor is set to match a high power supply voltage, when the power supply voltage drops, the gate voltage may be too high and exceed the transistor's withstand voltage. On the other hand, if the gate bias of the transistor is set to match a low power supply voltage, when the power supply voltage increases, the gate voltage may be too low and exceed the transistor's withstand voltage.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide an amplifier circuit, a power amplifier circuit, and a bias generation circuit that can apply a gate bias that does not exceed the withstand voltage of a transistor even when the power supply voltage fluctuates. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, an amplifier circuit according to an embodiment of the present disclosure includes an input terminal to which a signal to be amplified is input, a first FET having a gate to which the signal input to the input terminal is applied, second and third FETs connected together with the first FET between a power supply and a reference potential, an output terminal provided between a load and the third FET, which of the second and third FETs is located closer to the power supply, and which outputs an amplified signal, a voltage dividing resistor circuit for generating a bias to be applied to each gate of the second FET and the third FET, and a clamp circuit for clamping the bias to be applied to the gate of the third FET when the bias applied from the voltage dividing resistor circuit to the gate of the second FET exceeds a predetermined reference voltage, and the first FET, the second FET, and the third FET are connected in tandem. The voltage dividing resistor circuit includes a first resistor, a second resistor connected in series to the first resistor, and a third resistor connected in series to the second resistor, a reference potential is connected to the first resistor side, and the power supply is connected to the third resistor side, and a voltage generated by the first resistor is used as a bias to be applied to the gate of the second FET, and a voltage generated by the second resistor is used as a bias to be applied to the gate of the third FET. do.

[0007] Furthermore, an amplifier circuit according to another aspect of the present disclosure includes a plurality of FETs each having a drain and a source connected to each other, and uses voltages generated by voltage division of a plurality of resistors connected in series as bias voltages, the plurality of series-connected resistors are connected between a power supply and a reference potential; The biases are applied to the gates of the plurality of FETs, and when one of the biases exceeds a predetermined reference voltage, the other biases are clamped. The other bias is generated at a position closer to the power supply than the first bias. It is an amplifier circuit.

[0008] Moreover, the power amplifier circuit of the present disclosure uses any one of the amplifier circuits described above as a driver stage amplifier circuit, and further includes a power stage amplifier circuit that receives an output of the driver stage amplifier circuit as an input.

[0009] The bias generation circuit of the present disclosure includes a voltage dividing resistor circuit, which is composed of at least three stages of resistors connected in series and generates a bias from each stage by resistive voltage division, and a clamping circuit, which clamps the bias of another stage closer to a power supply than the stage when the bias generated in the stage exceeds a predetermined reference voltage; the voltage dividing resistor circuit is connected between the power supply and a reference potential; The bias is applied to each gate of a plurality of FETs whose adjacent drains and sources are connected to each other. [Effects of the Invention]

[0010] According to the present disclosure, even when the power supply voltage fluctuates, it is possible to apply a gate bias that does not exceed the breakdown voltage of the transistor. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram for explaining the case where a power amplifier is created using bipolar transistors. [Figure 2] FIG. 2 is a diagram illustrating the case where a power amplifier is created using a field effect transistor. [Figure 3] FIG. 3 is a diagram showing an example of a vertically stacked connection of a plurality of FETs. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of an amplifier when the power supply voltage is constant. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of an amplifier when the power supply voltage fluctuates. [Figure 6] FIG. 6 is a diagram showing the state of the drain-source voltage Vds of each stage in cascaded FETs when the power supply voltage is relatively high. [Figure 7] FIG. 7 is a diagram showing the state of the drain-source voltage of each stage in cascaded FETs when the power supply voltage is relatively low. [Figure 8] FIG. 8 is a circuit diagram showing an amplifier circuit according to a first comparative example. [Figure 9] FIG. 9 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 10]FIG. 10 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 11] FIG. 11 is a circuit diagram showing an amplifier circuit according to a second comparative example. [Figure 12] FIG. 12 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 13] FIG. 13 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 14] FIG. 14 is a circuit diagram showing an amplifier circuit according to the first embodiment. [Figure 15] FIG. 15 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 16] FIG. 16 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 17] FIG. 17 is a diagram illustrating an example of the operation of the amplifier circuit illustrated in FIG. [Figure 18] FIG. 18 is a circuit diagram showing an amplifier circuit according to the second embodiment. [Figure 19] FIG. 19 is a circuit diagram showing an amplifier circuit according to the third embodiment. [Figure 20] FIG. 20 is a circuit diagram showing an amplifier circuit according to the fourth embodiment. [Figure 21] FIG. 21 is a circuit diagram showing an example of a hybrid amplifier circuit in which the driver stage is made of Si and the power stage is made of GaAs. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment, components that are the same as or equivalent to those in other embodiments will be given the same reference numerals, and their description will be simplified or omitted. The present invention is not limited to each embodiment. Furthermore, the components of each embodiment include those that are easily replaceable by those skilled in the art, or those that are substantially the same. Note that the configurations described below can be combined as appropriate. Furthermore, the configurations can be omitted, replaced, or modified within the scope of the gist of the invention.

[0013] In order to facilitate understanding of the embodiment, a comparative example will be described first.

[0014] (Comparative Example) Fig. 1 is a diagram illustrating a case where a power amplifier is created using bipolar transistors, and Fig. 2 is a diagram illustrating a case where a power amplifier is created using field effect transistors.

[0015] Figure 1 shows the creation of a power amplifier (hereinafter referred to as PA) using a GaAs bipolar transistor Tr. The bipolar transistor Tr is a current-controlled element that is controlled by the current supplied to its base.

[0016] Figure 2 shows a field effect transistor, or FET (hereafter referred to as FET). FETs are voltage-controlled elements that are controlled by a voltage applied to the gate. FETs used in SOI (Silicon on Insulator) CMOS (Complementary Metal-Oxide-Semiconductor) PAs use a miniaturization process to improve FET performance (cutoff frequency ft, transconductance gm, etc.). For this reason, FETs used in SOI CMOS PAs have a lower breakdown voltage than GaAs bipolar transistors Tr.

[0017] Here, a configuration in which multiple FETs are connected in a vertical stack between a power supply Vdd and a reference potential (hereinafter referred to as a vertical stack connection) is considered. FIG. 3 is a diagram showing an example of a vertical stack connection using multiple FETs. FIG. 3 shows an example of a five-stage vertical stack connection using five FETs. In FIG. 3, FETs 11, 12, 13, 14, and 15 are vertically connected between a reference potential and the power supply Vdd. The reference potential is, for example, ground potential. In the vertical stack connection shown in FIG. 3, adjacent drains and sources of consecutively connected FETs are connected. However, in this specification, FETs that are not consecutively connected between the reference potential and the power supply Vdd may also be referred to as a vertical stack connection. For example, when FETs 12 and 14 are connected in a vertical stack, FETs 12 and 14 are not connected because FET 13 is present between them. This non-direct connection is also included in the vertical stack connection. The same applies to the following explanation.

[0018] Resistors 31, 32, 33, 34, and 35 are connected to the gates of FETs 11, 12, 13, 14, and 15, respectively. Capacitors 41, 42, 43, 44, and 45 are provided between the gates of FETs 11, 12, 13, 14, and 15 and the reference potential. The gate of FET 11 is connected to the input terminal RFin via the capacitor 41. A choke coil L is connected between FET 15 and a power supply Vdd. An output terminal RFout is connected between FET 15 and the choke coil L via a matching circuit MN. A load RL is connected to the output terminal RFout. When viewed from the drain of FET 15, the portion of the load RL including the choke coil L and the matching circuit MN appears as a load impedance.

[0019] Here, the source-drain voltage of FET 11 is voltage Vds1, the source-drain voltage of FET 12 is voltage Vds2, the source-drain voltage of FET 13 is voltage Vds3, the source-drain voltage of FET 14 is voltage Vds4, and the source-drain voltage of FET 15 is voltage Vds5. To prevent breakdown of each of FETs 11, 12, 13, 14, and 15, the voltages Vds1, Vds2, Vds3, Vds4, and Vds5 must be below the breakdown voltage at the maximum value of the power supply Vdd. Therefore, the voltage values ​​of the biases vg1, vg2, vg3, vg4, and vg5 applied to each gate must be controlled so that the source-drain voltage does not exceed the breakdown voltage.

[0020] The voltage value of the power supply Vdd may be fixed or may fluctuate. Figure 4 shows an example of the amplifier configuration when the power supply voltage is constant. As shown in Figure 4, the power supply voltage Vcc generated by an LDO (Low Dropout) regulator is input to the PA. The PA amplifies the input signal S1 and outputs it as an output signal S2. The power supply voltage V10 of the PA is constant regardless of the output power V11.

[0021] On the other hand, for example, in the case of the power supply of an amplifier used in a communication device for a cellular telephone network, the power supply voltage fluctuates depending on the power mode in order to reduce power consumption. FIG. 5 is a diagram showing an example of the configuration of an amplifier when the power supply voltage fluctuates. When the power mode changes, the fluctuated power supply voltage Vcc is input to the PA. It is necessary to fluctuate the power supply voltage V20 according to the output power V21. For example, the power supply voltage Vcc, whose voltage value has been changed by a DC-DC converter, is input to the PA.

[0022] When the power supply voltage is varied according to the power mode, it is necessary to control it so that it does not exceed the withstand voltage of the FET. As shown in Figure 3, by connecting FETs in a vertical stack, the voltage applied to each stage can be kept below the withstand voltage. If the transistor gate bias is set to match a high power supply voltage, the gate voltage may be too high when the power supply voltage drops, exceeding the transistor's withstand voltage. On the other hand, if the transistor gate bias is set to match a low power supply voltage, the gate voltage may be too low when the power supply voltage rises, exceeding the transistor's withstand voltage. To prevent the transistor's withstand voltage from being exceeded, the gate bias must be controlled to track the power supply Vdd voltage.

[0023] FIG. 6 shows the state of the drain-source voltage Vds at each stage of vertically connected FETs when the power supply Vdd voltage is relatively high. In the case of FIG. 6, for example, the power supply voltage value is at its maximum value. In the case of FIG. 6, the voltage Vds is evenly distributed to each stage of the FET. In other words, "Vds large" indicates that the voltage Vds is large at each stage of the FET.

[0024] Figure 7 shows the drain-source voltage Vds of each FET in a stacked configuration when the power supply Vdd voltage is relatively low. In Figure 7, for example, the power supply voltage is lower than the maximum value. In Figure 7, the voltage Vds1 of FET 11, which is closest to the reference potential, is labeled "Vds large," indicating a high voltage Vds. The voltage Vds2 of FET 12, which is second closest to the reference potential, is labeled "Vds medium," indicating a medium voltage Vds. The voltages Vds3, Vds4, and Vds5 of the other FETs 13, 14, and 15 are labeled "Vds small," indicating a low voltage Vds. To control the gate bias in accordance with the power supply Vdd voltage, the gate bias must be controlled as shown in Figures 6 and 7.

[0025] (First Comparative Example) 8 is a circuit diagram showing an amplifier circuit 100 according to a first comparative example. In FIG. 8, amplifier circuit 100 of this example includes FETs 11, 12, 13, 14, and 15, resistors 21, 22, 23, 24, and 25, resistors 31, 32, 33, 34, and 35, capacitors 41, 42, 43, 44, and 45, and an FET 16.

[0026] FETs 11, 12, 13, 14, and 15 are connected between a reference potential and a power supply Vdd. FETs 11, 12, 13, 14, and 15 are connected in a stacked configuration. That is, the drain of FET 11 is connected to the reference potential, and the source of FET 11 is connected to the drain of FET 12. The source of FET 12 is connected to the drain of FET 13. The source of FET 13 is connected to the drain of FET 14. The source of FET 14 is connected to the drain of FET 15. The source of FET 15 is connected to the power supply Vdd via a choke coil L. An output terminal RFout is connected between the source of FET 15 and the choke coil L via a matching circuit MN. In this document, FET 11 may be referred to as the first FET, FET 12 as the second FET, FET 13 as the third FET, FET 14 as the fourth FET, and FET 15 as the fifth FET.

[0027] The power supply Vdd is a variable power supply, and its voltage value is not fixed but fluctuates. Of the FETs 11 to 15 connected in series, FET 15, which is closest to the power supply Vdd, has a choke coil L connected between it and the power supply Vdd. An output terminal RFout is connected between the choke coil L and FET 15 via a matching circuit MN. A load RL is connected to the output terminal RFout.

[0028] The resistor 31 and the capacitor 41 are provided corresponding to the FET 11. One end of the resistor 31 and one end of the capacitor 41 are connected to the gate of the FET 11. The other end of the capacitor 41 is connected to an input terminal RFin. A signal to be amplified is input to the input terminal RFin.

[0029] The resistor 32 and the capacitor 42 are provided corresponding to the FET 12. One end of the resistor 32 and one end of the capacitor 42 are connected to the gate of the FET 12. The other end of the capacitor 42 is connected to the reference potential.

[0030] The resistor 33 and the capacitor 43 are provided corresponding to the FET 13. One end of the resistor 33 and one end of the capacitor 43 are connected to the gate of the FET 13. The other end of the capacitor 43 is connected to the reference potential.

[0031] The resistor 34 and the capacitor 44 are provided corresponding to the FET 14. One end of the resistor 34 and one end of the capacitor 44 are connected to the gate of the FET 14. The other end of the capacitor 44 is connected to the reference potential.

[0032] The resistor 35 and the capacitor 45 are provided corresponding to the FET 15. One end of the resistor 35 and one end of the capacitor 45 are connected to the gate of the FET 15. The other end of the capacitor 45 is connected to the reference potential.

[0033] The drain and gate of the FET 16 are connected together to form a so-called diode connection, and the FET 16 is provided between the resistor 21 and the reference potential.

[0034] Resistors 21, 22, 23, 24, and 25 are ladder resistors connected in series between the power supply Vdd and the reference potential. The resistors 21, 22, 23, 24, and 25 form a voltage-dividing resistor circuit 20. By realizing each of the resistors 21, 22, 23, 24, and 25 as the same ladder resistor, it is possible to prevent the reversal of the gate bias of each stage due to mismatches between resistor pairs. Here, "the same ladder resistor" refers to ladder resistors manufactured using the same process and materials.

[0035] One end of the resistor 21 is connected to the drain and gate of the FET 16. One end of the resistor 21 is connected to a reference potential via a diode formed by the FET 16. The FET 16 is connected to the reference potential side of the voltage-dividing resistor circuit 20. Therefore, the FET 16 is provided between the voltage-dividing resistor circuit 20 and the reference potential.

[0036] In the voltage-dividing resistor circuit 20, resistors 21 and 22 are connected in series. The junction between resistors 21 and 22 is connected to the other end of resistor 32. The voltage at the junction between resistors 21 and 22 is applied to the gate of FET 12 as bias vg2. Resistors 22 and 23 are connected in series. The junction between resistors 22 and 23 is connected to the other end of resistor 33. The voltage at the junction between resistors 22 and 23 is applied to the gate of FET 13 as bias vg3. Resistors 23 and 24 are connected in series. The junction between resistors 23 and 24 is connected to the other end of resistor 34. The voltage at the junction between resistors 23 and 24 is applied to the gate of FET 14 as bias vg4. Resistors 24 and 25 are connected in series. The junction between resistors 24 and 25 is connected to the other end of resistor 35. The voltage at the connection point between the resistors 24 and 25 is applied to the gate of the FET 15 as a bias vg5.

[0037] 8, the amplifier circuit 100 of this example includes an FET 17 and a constant current source 60. The constant current source 60 outputs a constant current. The FET 17 is connected to the output side of the constant current source 60. The drain and gate of the FET 17 are connected, forming a so-called diode connection. The other end of the resistor 31 is connected to the FET 17. The FET 17 is a replica transistor that forms a current mirror circuit together with the first FET 11. The current mirror circuit formed by the FET 1 and the FET 17 causes a current proportional to the constant current output from the constant current source 60 to flow between the drain and source of the FET 1.

[0038] (Operation of the first comparative example) 8, a bias generated by resistive voltage division in a voltage-dividing resistor circuit 20 is applied to the gates of FETs 12 to 15. The amplifier circuit 100 amplifies a radio frequency signal input to an input terminal RFin. The amplifier circuit 100 outputs the amplified signal from an output terminal RFout.

[0039] 9 and 10 are diagrams showing an example of the operation of the amplifier circuit 100 shown in FIG. 8. FIG. 9 is a diagram showing the results of a simulation of the bias applied to the gate of each FET in the amplifier circuit 100. In FIG. 9, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the voltage value [V] of the bias voltage vg applied to the gate of the FET (i.e., the gate bias). FIG. 9 shows the change in the voltage value of each bias with respect to the change in the voltage value of the power supply Vdd. Hereinafter, the gate bias may be abbreviated as "bias."

[0040] 9, when the voltage value of the power supply Vdd fluctuates, the voltage values ​​of the biases vg2 to vg5 fluctuate. The voltage value of the bias vg1 remains constant. As shown by the arrow YJ in FIG. 9, when the voltage value of the power supply Vdd drops, the voltage values ​​of the low potential side (the side closer to the reference potential), especially the biases vg2 and vg3, drop too much.

[0041] FIG. 10 shows the simulation results of the drain-gate potential difference. In FIG. 10, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the drain-gate voltage value Vdg [V]. The reciprocating arrows in FIG. 10 indicate the unbroken region A1 of each FET. The unbroken region is a region in which the FET will not be destroyed if it operates within that region. As shown in FIG. 10, the biases vg1 to vg5 all have voltage values ​​within the unbroken region A1.

[0042] (Second Comparative Example) FIG. 11 is a circuit diagram showing an amplifier circuit 101 according to a second comparative example. In FIG. 11, amplifier circuit 101 of this example differs from amplifier circuit 100 described with reference to FIG. 8 in that it generates a bias using a fixed power supply in addition to power supply Vdd, which is a variable power supply. For example, it uses power supply Vbat, which is the output of the battery of a mobile communication device. Power supply Vdd supplied to cascaded FETs 11, 12, 13, 14, and 15 is a variable power supply, as in the case of FIG. 8. Other configurations of amplifier circuit 101 in FIG. 11 are the same as those of amplifier circuit 100 described with reference to FIG. 8.

[0043] In the amplifier circuit 101 according to the second comparative example, if the gate bias is set according to a high voltage value of the power supply Vdd, the gate potential may be too high and exceed the non-destructive region when the voltage of the power supply Vdd drops. Also, if the gate bias is set according to a low voltage value of the power supply Vdd, the gate potential may be too low and exceed the non-destructive region when the voltage of the power supply Vdd rises.

[0044] (Operation of the second comparative example) 12 and 13 are diagrams showing an example of the operation of the amplifier circuit 101 shown in FIG. 11. FIG. 12 is a diagram showing the results of a simulation of the bias applied to the gate of each FET in the amplifier circuit 101. In FIG. 12, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the voltage value [V] of the bias voltage vg applied to the gate of the FET (i.e., the gate bias). FIG. 12 shows the change in the voltage value of each bias with respect to the change in the voltage value of the power supply Vdd. As shown in FIG. 12, even if the voltage value of the power supply Vdd changes, the biases vg1 to vg5 each have a constant voltage value.

[0045] FIG. 13 shows the results of a simulation of the drain-gate potential difference. In FIG. 13, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the drain-gate voltage value Vdg [V]. As shown in FIG. 13, if the gate bias is set to a high voltage value of the power supply Vdd, when the voltage of the power supply Vdd drops, the gate potential may become too high and exceed the non-destructive region A1. In this example, the voltage values ​​Vdg1 and Vdg2 corresponding to the biases vg1 and vg2 are within the non-destructive region A1. In contrast, the voltage values ​​Vdg3, Vdg4, and Vdg5 corresponding to the biases vg3, vg4, and vg5 drop beyond the range of the non-destructive region A1. In this case, the difference between the voltage values ​​Vdg3, Vdg4, and Vdg5 and the voltage value Vdg5 becomes large, exceeding the breakdown voltage, which may lead to the destruction of FETs 13, 14, and 15.

[0046] (Key points of the amplifier circuit according to the present disclosure) One way to solve the above problem is to control the gate bias in accordance with fluctuations in the power supply Vdd. That is, when the power supply Vdd voltage is high, the bias is set so that the drain-source voltage Vds of the FETs is evenly distributed. On the other hand, when the power supply Vdd voltage is low, the bias is set so that the voltages Vdg1 and Vdg2 corresponding to the lower FETs 1 and 2 in the vertical stack are kept large, while the voltages Vds3, Vdg4, and Vdg5 corresponding to the upper FETs 3, 4, and 5 in the vertical stack are relatively small.

[0047] In the amplifier circuit disclosed herein, the variable power supply Vdd is divided by a voltage-dividing resistor circuit 20 using ladder resistors. In the voltage-dividing resistor circuit 20, the voltage division ratio is also reduced for the low-potential side, such as biases vg2 and vg3. For example, if the bias vg2 is divided by (1 / 5) × Vdd, when the power supply Vdd is 5 V, the bias vg2 becomes 1 V. If the voltage division ratio is reduced to (1 / 2) Vdd, when the power supply Vdd is 5 V, the bias vg2 becomes 2.5 V. By reducing the voltage division ratio in this way, even when the power supply Vdd fluctuates and the voltage value drops, the voltages of the biases vg2 and vg3 do not drop too much. However, simply reducing the voltage division ratio would result in the bias becoming too high when the power supply Vdd voltage value is high. Therefore, a clamp circuit is provided to clamp the bias vg3 voltage at a desired potential when the power supply Vdd voltage value is high. For biases vg4 and vg5, which require higher voltages, an even higher voltage is used.

[0048] The amplifier circuit of the present disclosure provides the following effects. (1) The optimum bias can be achieved over a wide voltage range of the power supply Vdd, preventing FET breakdown and maintaining its characteristics. In addition, the power supply Vdd voltage can be controlled with a high degree of freedom, making it easy to obtain the effects of varying the power supply Vdd voltage. (2) The configuration of the amplifier circuit is simplified, minimizing the increase in mounting area. (3) By creating biases vg2 to vg5 using the same ladder resistors, it is possible to prevent the gate bias of each stage from being reversed due to mismatching of the pairings. (4) The drain-source voltage Vds of the lower FET in the vertical stack connection, which is important for high-frequency characteristics, can be determined with high precision.

[0049] Incidentally, to ensure PA performance, it is preferable to maintain the drain-source voltages Vds1 and Vds2 as high as possible even when the power supply Vdd voltage is low. Therefore, when the power supply Vdd voltage is low, the bias inevitably decreases on the upper side of the cascaded PA. When cascaded PAs are operated at low voltage, the drain-source voltage Vds on the upper side decreases, causing the PA to operate in the linear region. This has the disadvantage of making the effects of on-resistance visible and making it difficult to obtain output.

[0050] Therefore, in this disclosure, the voltage division ratios of each stage of the voltage-dividing resistor circuit are set to different values ​​rather than being equal. Specifically, the resistor voltage division ratios of the biases vg2 and vg3 in the lower stages of the vertical stack connection are increased to prevent potential drops even when the power supply Vdd voltage is low and to prevent excessive increases when the power supply Vdd voltage is high. For biases requiring high potentials, such as biases vg4 and vg5, the biases are configured to increase in accordance with the power supply Vdd. That is, the voltage of bias vg2 is monitored by a clamp circuit 50, and bias vg3 is clamped. This allows a single clamp circuit 50 to precisely control the drain-source voltage Vds1 of the bottom-most FET 11 and the drain-source voltage Vds2 of the FET 12 in the stage immediately above it, which are important for performance. Furthermore, the biases vg4 and vg5 continue to increase in accordance with the power supply Vdd even after the clamp circuit 50 operates, allowing the bias voltage values ​​to be controlled so as to satisfy the withstand voltage conditions even when the power supply Vdd reaches its maximum voltage value.

[0051] (First embodiment) Next, an embodiment will be described.

[0052] (composition) Fig. 14 is a circuit diagram showing an amplifier circuit 100a according to the first embodiment. In Fig. 14, the amplifier circuit 100a has a configuration in which a clamp circuit 50 is added to the amplifier circuit 100 described with reference to Fig. 8. The clamp circuit 50 and the voltage-dividing resistor circuit 20 are included in a bias generation circuit 250a, which will be described later.

[0053] (clamp circuit) As shown in FIG. 14, the clamp circuit 50 of this embodiment includes a comparison circuit 51, a transistor 52, and a reference voltage Vref. The comparison circuit 51 can be realized by, for example, an operational amplifier. The comparison circuit 51 has a positive input terminal (+) and a negative input terminal (-). A predetermined reference voltage Vref is input to the negative input terminal of the comparison circuit 51. The voltage value of a node N1 is input to the positive input terminal of the comparison circuit 51. In this example, the node N1 is at the same potential as the connection point N21 between the resistors 21 and 22. The potential of the node N1 is a bias vg2.

[0054] In this example, the transistor 52 is an N-type MOS transistor. The output terminal of the comparison circuit 51 is connected to the gate of the transistor 52. The source of the transistor 52 is connected to a reference potential. The drain of the transistor 52 is connected to a node N2. In this example, the node N2 is at the same potential as the connection point N22 between the resistors 22 and 23. The potential of the node N2 is a bias vg3.

[0055] The transistor 52 is a switching element that is turned on based on the output of the comparison circuit 51. The comparison circuit 51 compares the voltage value of the bias vg2 applied to the gate of the FET 12 from the voltage-dividing resistor circuit 20 with a reference voltage Vref. When the voltage value of the bias vg2 exceeds the reference voltage Vref, the comparison circuit 51 applies a voltage to the gate of the transistor 52 to turn the transistor 52 on.

[0056] In the clamp circuit 50, when the potential of the node N1, i.e., the voltage value of the bias vg2 input to the positive input terminal of the comparator circuit 51, does not exceed the reference voltage Vref, the output of the comparator circuit 51 is at a low level. At this time, the transistor 52 is in an off state.

[0057] On the other hand, when the potential of node N1, i.e., the voltage value of bias vg2, exceeds the reference voltage Vref, the output of comparator circuit 51 goes high. This turns on transistor 52. When transistor 52 turns on, current flows through transistor 52, lowering the potential of node N2. In other words, current is drawn from node N2 on the path from voltage-dividing resistor circuit 20 to the gate of FET 13, lowering the potential of node N2. When the potential of node N2 drops, the potential of node N1 also drops, reducing the current of transistor 52 and providing feedback so that the potential of node N1 becomes equal to reference voltage Vref. Therefore, the voltage value of bias vg3 is clamped so that bias vg2 does not exceed reference voltage Vref.

[0058] As described above, clamp circuit 50 receives as input the voltage of node N1, which has the same potential as node N21 between resistors 21 and 22. Clamp circuit 50 then clamps the voltage of node N2, which has the same potential as node N22 between resistors 22 and 23.

[0059] That is, amplifier circuit 100a includes input terminal RFin to which a signal to be amplified is input, first FET 11 having a gate to which the signal input to input terminal RFin is applied, second FET 12 and third FET 13 connected in a cascade configuration together with first FET 11 between power supply Vdd and a reference potential, output terminal RFout provided between power supply Vdd and third FET 13, which is located closer to power supply Vdd among second FET 12 and third FET 13, and for outputting an amplified signal, and voltage-dividing resistor circuit 20 for generating biases vg2 and vg3 to be applied to the gates of second FET 12 and third FET 13. Amplifier circuit 100a further includes clamp circuit 50 for clamping bias vg3 to be applied to the gate of third FET 13 when bias vg2 applied from voltage-dividing resistor circuit 20 to the gate of second FET 12 exceeds a predetermined reference voltage. In the amplifier circuit 100a, the first FET 11, the second FET 12, the third FET 13, the fourth FET 14, and the fifth FET 15 are connected in series between the power supply Vdd and the reference potential.

[0060] By providing the clamp circuit 50, the resistive voltage division ratio of the biases vg2 and vg3 is increased (the voltage division ratio is increased), making it difficult for the potential to drop even when the voltage value of the fluctuating power supply Vdd is low, and clamping it so that it does not rise too much when the voltage value of the fluctuating power supply Vdd is high. In other words, the clamp circuit 50 controls the potentials of the biases vg2 and vg3, which are made difficult to drop when the voltage value of the power supply Vdd is low by increasing the resistive voltage division ratio, so that they do not rise too much when the voltage value of the power supply Vdd is high.

[0061] (Bias voltage value for each stage) For biases requiring a high potential such as biases vg4 and vg5, the clamp circuit 50 is not provided, so that the voltage value increases further following the power supply Vdd.

[0062] Here, the value of the reference voltage Vref is Vclamp, the voltage value of the power supply Vdd is vdd, and the voltage corresponding to the diode-connected FET 16 is Vt. The voltage values ​​of the biases vg2, vg3, vg4, and vg5 can be expressed by the following equations (1) to (8).

[0063] That is, when vg2≦Vclamp, vg2=Vt+(Vdd-Vt) / (R5+R4+R3+R2+R1)×R1…(1) vg3=Vt+(Vdd-Vt) / (R5+R4+R3+R2+R1)×(R1+R2)…(2) vg4=Vt+(Vdd-Vt) / (R5+R4+R3+R2+R1)×(R1+R2+R3)…(3) vg5=Vt+(Vdd-Vt) / (R5+R4+R3+R2+R1)×(R1+R2+R3+R4)…(4) is.

[0064] Also, when vg2>Vclamp, vg2=Vclamp…(5) vg3=Vclamp+(Vclamp-Vt) / R1×R2…(6) vg4=vg3+(Vdd-vg3) / (R5+R4+R3)×R3…(7) vg5=vg3+(Vdd-vg3) / (R5+R4+R3)×(R3+R4)…(8) is.

[0065] Here, the voltage-dividing resistor circuit 20 includes a first resistor 21, a second resistor 22, and a third resistor 23. Resistor 21 is located closest to the reference potential. Resistor 22 is located closer to the power supply Vdd than resistor 21. Resistor 23 is located closer to the power supply Vdd than resistor 22. The resistance values ​​of resistors 21 and 22 are preferably greater than that of resistor 23. Furthermore, the resistance value of resistor 21 is preferably greater than that of resistor 22. By setting the resistance values ​​of each resistor in this manner, a bias that does not exceed the withstand voltage of the FET can be more reliably applied to the gate of the FET, even when the voltage value of the power supply Vdd fluctuates. In addition, in the case of a five-stage vertical connection, the resistance value of resistor 22 is preferably greater than that of resistors 23, 24, and 25, and the resistance value of resistor 21 is preferably greater than that of resistor 22. In the case of a four-stage vertical connection, it is preferable that the resistance value of resistor 22 is greater than the resistance values ​​of resistors 23 and 24 , and that the resistance value of resistor 21 is greater than the resistance value of resistor 22 .

[0066] (operation) 15, 16, and 17 are diagrams showing an example of the operation of the amplifier circuit 100a shown in FIG. 14. FIG. 15 is a diagram showing the results of a simulation of the bias applied to the gate of each FET in the amplifier circuit 100. In FIG. 15, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the value [V] of the bias voltage vg applied to the gate of the FET (i.e., the gate bias). FIG. 15 shows the change in the voltage value of each bias with respect to the change in the voltage value of the power supply Vdd.

[0067] As shown in FIG. 15, when the voltage value of the power supply Vdd rises from 1 [V], the biases vg1 to vg5 also change accordingly. However, the biases vg2 and vg3 are clamped when the voltage value of the power supply Vdd is 3 [V] and remain constant when the voltage value of the power supply Vdd is 3 [V] or higher. In other words, in addition to bias vg3, bias vg2 is also clamped. The principle is as follows: The potential of bias vg3 is divided by resistor 22, resistor 21, and FET 16, and the voltage extracted at the junction of resistors 21 and 22 becomes bias vg2. Therefore, if bias vg3 is clamped, bias vg2 is also clamped. As shown in FIG. 15, in this example, bias vg2 does not exceed approximately 1.7 [V]. Furthermore, bias vg3 does not exceed approximately 2.6 [V].

[0068] The FET 41 has the greatest influence on the characteristics of the amplifier. The drain voltage of this FET 41 is determined by the bias vg2 of the adjacent FET 42. Therefore, if the bias input to the clamp circuit 50, i.e., the bias monitored by the clamp circuit 50, is set to the bias vg2 of the FET 42, the amplifier circuit 100a can be driven with higher precision.

[0069] FIG. 16 shows the results of a simulation of the drain-gate potential difference. In FIG. 16, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the value [V] of the drain-gate voltage Vdg. As shown in FIG. 16, when the voltage value of the power supply Vdd rises from 1 [V], the values ​​of the voltages Vdg corresponding to the biases vg1 to vg5 also change accordingly. The voltages Vdg corresponding to the biases vg2 and vg3 are clamped when the voltage value of the power supply Vdd is 3 [V], and remain constant in the range where the voltage value of the power supply Vdd is 3 [V] or higher. None of the voltages Vdg corresponding to the biases vg1 to vg5 exceed the non-destructive region A1.

[0070] FIG. 17 is a diagram showing the simulation results of the drain-source potential difference. In FIG. 17, the horizontal axis represents the voltage value [V] of the power supply Vdd, and the vertical axis represents the value [V] of the drain-source voltage Vds. As shown in FIG. 17, when the voltage value of the power supply Vdd rises from 1 [V], the values ​​of the voltages Vds corresponding to the biases vg1 to vg5 also change accordingly. The voltages Vds corresponding to the biases vg2 and vg3 are clamped when the voltage value of the power supply Vdd is 3 [V], and remain constant in the range where the voltage value of the power supply Vdd is 3 [V] or higher. None of the voltages Vds corresponding to the biases vg1 to vg5 exceed the non-destructive region A1.

[0071] Unlike the second embodiment described later, this embodiment includes an FET 16. The inclusion of the FET 16 provides the following effect. That is, if the threshold values ​​of FETs 42 to 45 fluctuate due to variations in the manufacturing process or temperature changes, the inclusion of the FET 16 causes the biases (vg2, vg3, vg4, and vg5) to fluctuate by the same amount as the threshold fluctuation. This offsets the threshold fluctuation, thereby suppressing the effects of fluctuations in the drain voltage of each FET.

[0072] (effect) As described above, the amplifier circuit 100a according to this embodiment can apply a bias that is close to optimal to the gate when the voltage value of the power supply Vdd is low, and can apply a bias that satisfies the withstand voltage condition to the gate when the voltage value of the power supply Vdd is high. That is, as described with reference to FIGS. 16 and 17, the drain-gate voltage Vdg and the drain-source voltage Vds can be adjusted to within the undestructed region A1.

[0073] (Second embodiment) Next, a second embodiment will be described.

[0074] (composition) Fig. 18 is a circuit diagram showing an amplifier circuit 100b according to the second embodiment. The amplifier circuit 100b shown in Fig. 18 differs from the amplifier circuit 100a shown in Fig. 14 in that the FET 16 (see Fig. 14) between the voltage-dividing resistor circuit 20 and the reference potential is omitted. Therefore, one end of the resistor 21 of the voltage-dividing resistor circuit 20 is directly connected to the reference potential. The voltage values ​​of the biases vg2, vg3, vg4, and vg5 generated by the voltage-dividing resistor circuit 20 can be expressed by the following equations (9) to (16).

[0075] That is, when vg2≦Vclamp, vg2=Vdd / (R5+R4+R3+R2+R1)×R1…(9) vg3=Vdd / (R5+R4+R3+R2+R1)×(R1+R2)…(10) vg4=Vdd / (R5+R4+R3+R2+R1)×(R1+R2+R3)…(11) vg5=Vdd / (R5+R4+R3+R2+R1)×(R1+R2+R3+R4)…(12) is.

[0076] Also, when vg2>Vclamp, vg2=Vclamp…(13) vg3=Vclamp+Vclamp / R1×R2…(14) vg4=vg3+(Vdd-vg3) / (R5+R4+R3)×R3…(15) vg5=vg3+(Vdd-vg3) / (R5+R4+R3)×(R3+R4)…(16) is.

[0077] (operation) 18 also includes a clamp circuit 50. Therefore, the operation of the amplifier circuit 100b is similar to that described with reference to FIGS.

[0078] (effect) According to the amplifier circuit 100b of the second embodiment, when the voltage value of the power supply Vdd is low, a bias that is close to optimal can be applied to the gate, and when the voltage value of the power supply Vdd is high, a bias that satisfies the withstand voltage condition can be applied to the gate. Furthermore, the amplifier circuit 100b does not have an FET 16 (see FIG. 14) between the voltage-dividing resistor circuit 20 and the reference potential. This allows for a reduction in the area required for implementing the amplifier circuit 100b.

[0079] (Third embodiment) Next, a third embodiment will be described.

[0080] (composition) 19 is a circuit diagram showing an amplifier circuit 100c according to the third embodiment. As shown in FIG. 19, the amplifier circuit 100c according to the third embodiment includes a clamp circuit 50a. That is, the amplifier circuit 100c uses the clamp circuit 50a instead of the clamp circuit 50 used in the amplifier circuits 100a and 100b.

[0081] In the clamp circuit 50a, the transistor 52a provided on the output side of the comparison circuit 51 is a P-type MOS transistor. That is, the clamp circuit 50a uses the transistor 52a, which is a P-type MOS transistor, instead of an N-type MOS transistor. Because a PMOS transistor is used, a reference voltage Vref is input to the positive input terminal of the comparison circuit 51.

[0082] (operation) When the voltage value of the node N1, that is, the voltage value of the bias vg2 input to the negative input terminal of the comparator circuit 51, does not exceed the reference voltage Vref, the output of the comparator circuit 51 is at a high level. At this time, the transistor 52a is in an off state.

[0083] When the voltage value of node N1, i.e., the voltage value of bias vg2, exceeds the reference voltage Vref, the output of the comparator circuit 51 goes low. This turns on transistor 52a. When transistor 52a turns on, current flows through transistor 52a, and the potential of node N2 drops. In other words, by drawing current from node N2, the potential of node N2 drops. When the potential of node N2 drops, the potential of node N1 also drops, reducing the current through transistor 52a, and feedback is applied so that the potential of node N1 and the potential of reference voltage Vref become equal. In other words, the voltage value of bias vg3 is clamped so that bias vg2 does not exceed the reference voltage Vref.

[0084] (effect) According to the amplifier circuit 100c of the third embodiment, when the voltage value of the power supply Vdd is low, a bias that is close to optimal can be applied to the gate, and when the voltage value of the power supply Vdd is high, a bias that satisfies the withstand voltage condition can be applied to the gate. Furthermore, even if a P-type MOS transistor is used in the clamp circuit 50a, the same effect as when an N-type MOS transistor is used can be obtained.

[0085] (Fourth embodiment) Next, a fourth embodiment will be described.

[0086] (composition) Fig. 20 is a circuit diagram showing an amplifier circuit 100d according to the fourth embodiment. In Fig. 20, the amplifier circuit 100d includes a clamp voltage generation circuit 70 that generates a reference voltage used in the clamp circuit 50b, that is, a clamp voltage.

[0087] The clamp voltage generation circuit 70 includes a bandgap reference circuit (BGR) 71, a non-inverting amplifier circuit including an operational amplifier 72 and resistors 73 and 74, and a voltage-dividing resistor circuit including resistors 75 and 76 and an FET 77. The bandgap reference circuit 71 generates a reference voltage (i.e., a bandgap reference voltage) that is independent of the power supply voltage, temperature, and the like. The drain and gate of the FET 77 are connected together, forming a so-called diode connection. A desired reference voltage can be generated by adjusting the ratio of the resistance values ​​of the resistors 73 and 74 and the resistors 75 and 76. The generated reference voltage is input to the negative input terminal of the comparator circuit 51 in the clamp circuit 50b.

[0088] The clamp voltage generation circuit 70 generates a constant voltage value based on the bandgap reference voltage generated by the reference voltage generation circuit, and uses this constant voltage value as the reference voltage for the comparison circuit 51.

[0089] (operation) In the amplifier circuit 100d shown in Fig. 20, similarly to the amplifier circuit 100a, the biases vg2 and vg3 are clamped when the power supply Vdd is at a predetermined voltage value and remain constant in a range above the predetermined voltage value, as shown in Fig. 15. Furthermore, as shown in Fig. 16 and Fig. 17, the voltages Vdg and Vds corresponding to the biases vg2 and vg3 do not exceed the non-destructive range A1. (effect) 20, when the voltage value of the power supply Vdd is low, a bias that is close to the optimum can be applied to the gate, and when the voltage value of the power supply Vdd is high, a bias that satisfies the withstand voltage condition can be applied to the gate. That is, as described with reference to FIGS. 16 and 17, the drain-gate voltage Vdg and the drain-source voltage Vds can be adjusted to within the undestructed region A1.

[0090] As described above, the amplifier circuits of the first to fourth embodiments are all amplifier circuits that divide voltage using multiple resistors connected in series, use the voltages generated by each resistor as biases vg2 and vg3, and apply each bias vg2 and vg3 to the gates of multiple FETs connected in tandem, so that when one bias vg2 exceeds a predetermined reference voltage, the other bias vg3 is clamped.

[0091] (Variation) In the first to fourth embodiments, the number of vertically connected FETs is five, but the number of vertically connected FETs is not limited to this and may be three or more. That is, it is sufficient that the FETs are vertically connected in at least three stages. A greater number of vertically connected stages may also be used.

[0092] In the first to fourth embodiments, the voltage of the bias vg2 is monitored and the bias vg3 is clamped by the clamp circuit 50. However, the present invention is not limited to this, and other biases may be monitored and other biases may be clamped.

[0093] Although the above description has been given of a case where the voltage value of the power supply Vdd fluctuates, the amplifier circuit according to the present disclosure can also be used when the voltage value of the power supply Vdd does not fluctuate and is a fixed value. However, the amplifier circuit according to the present disclosure can be used more effectively when used when the voltage value of the power supply Vdd fluctuates.

[0094] (Bias generation circuit) In the first to fourth embodiments, a bias generation circuit is used. Returning to Fig. 14, the amplifier circuit 100a includes a bias generation circuit 250a.

[0095] The bias generation circuit 250a includes a voltage-dividing resistor circuit 20, which is composed of at least three stages of resistors 21, 22, 23, etc. connected in series and generates biases vg2, vg3, etc. from each stage by resistive voltage division, and a clamp circuit 50, which clamps the bias vg3 of a stage closer to the power supply Vdd than the stage where the bias vg2 generated in that stage exceeds a predetermined reference voltage. The bias generation circuit 250a applies biases vg2, vg3, etc. to the gates of the cascade-connected FETs 12, 13, etc. The bias generation circuit 250a can apply biases that do not exceed the withstand voltage of the FETs even when the power supply voltage fluctuates.

[0096] 18, the amplifier circuit 100b of the second embodiment includes a bias generating circuit 250b. The bias generating circuit 250b has a voltage dividing resistor circuit 20 and a clamp circuit 50.

[0097] 19, an amplifier circuit 100c according to the third embodiment includes a bias generating circuit 250c. The bias generating circuit 250c includes a voltage dividing resistor circuit 20 and a clamp circuit 50a.

[0098] 20, an amplifier circuit 100d according to the fourth embodiment includes a bias generating circuit 250d. The bias generating circuit 250d includes a voltage dividing resistor circuit 20 and a clamp circuit 50b.

[0099] (power amplifier circuit) Incidentally, by using the above-described amplifier circuit as a driver stage amplifier circuit and adding a power stage amplifier circuit that receives the output of the driver stage amplifier circuit as its input, it is possible to realize a power amplifier circuit that can be used in a communication device.

[0100] (composition) Fig. 21 is a diagram showing an example configuration of a power amplifier circuit 1000. In Fig. 21, the power amplifier circuit 1000 includes an input terminal Pin, an input matching network (MN) 300, a driver stage amplifier circuit 100a, an inter-stage matching network (MN) 400, a power stage amplifier circuit 200, an output matching network (MN) 500, and an output terminal Pout. The power amplifier circuit 1000 of this example is realized by two substrates 800 and 900.

[0101] In this example, the input matching circuit 300 and the amplifier circuit 100a are formed on the same substrate 800. The substrate 800 is, for example, a Si substrate. As described above, the driver stage amplifier circuit 100a is preferably formed by vertically connected FETs.

[0102] In this example, the inter-stage matching circuit 400, the power stage amplifier circuit 200, and the output matching circuit 500 are formed on the same substrate 900. The substrate 900 is, for example, a GaAs substrate. The power stage amplifier circuit 200 is preferably formed using a bipolar transistor. The power stage amplifier circuit 200 can be formed using an HBT (Heterojunction Bipolar Transistor). The inter-stage matching circuit 400 and the output matching circuit 500 may be formed or mounted on the substrate 800 or a module substrate on which the substrate 900 is mounted.

[0103] As described above, the power amplifier circuit 1000 uses the amplifier circuit 100a as a driver stage amplifier circuit and further includes a power stage amplifier circuit 200 that receives the output of the driver stage amplifier circuit 100a as its input. The power amplifier circuit 1000 shown in Fig. 21 uses the amplifier circuit 100a according to the first embodiment. Note that in Fig. 21, any one of the amplifier circuits 100b, 100c, and 100d may be used instead of the driver stage amplifier circuit 100a.

[0104] (operation) In the power amplifier circuit 1000, a signal input to an input terminal Pin is amplified in a driver stage amplifier circuit 100a, and further amplified in a power stage amplifier circuit 200. The signal amplified by the amplifier circuit 200 is output from an output terminal Pout.

[0105] (effect) As described above, by forming the first-stage amplifier circuit 100a, which requires a relatively low output power, using FETs, the manufacturing cost of the amplifier circuit can be reduced compared to when it is formed using bipolar transistors. Also, by forming the second-stage amplifier circuit 200, which requires a relatively high output power, using HBTs, it is possible to achieve both a compact circuit and good gain characteristics.

[0106] With respect to the claims, the present disclosure may take the following forms. <1> an input terminal to which a signal to be amplified is input; a first FET having a gate to which a signal input to the input terminal is applied; a second FET and a third FET connected together with the first FET between a power supply and a reference potential; an output terminal that is provided between a load and the third FET, the third FET being located closer to the power supply, and that outputs an amplified signal; a voltage dividing resistor circuit for generating a bias to be applied to each gate of the second FET and the third FET; a clamp circuit that clamps the bias applied to the gate of the third FET when the bias applied from the voltage dividing resistor circuit to the gate of the second FET exceeds a predetermined reference voltage; and an amplifier circuit in which the first FET, the second FET, and the third FET are connected in series; <2> the voltage dividing resistor circuit includes a first resistor, a second resistor, and a third resistor; the first resistor is provided at a position closest to a reference potential, the second resistor is provided closer to the power supply than the first resistor, the third resistor is provided closer to the power supply than the second resistor, The resistance value of the first resistor and the resistance value of the second resistor are greater than the resistance value of the third resistor. <1> The amplifier circuit according to claim 1. <3> The resistance value of the first resistor is greater than the resistance value of the second resistor. <2> The amplifier circuit according to claim 1. <4> The clamp circuit a comparison circuit that compares a bias voltage value applied to the gate of the second FET from the voltage dividing resistor circuit with the reference voltage; a switching element that is turned on based on the output of the comparison circuit; Including, When the switching element is in an on state, the bias applied to the gate of the third FET is reduced. <1> from <3> 10. An amplifier circuit according to claim 9, wherein: <5> The comparison circuit when a bias voltage value applied from the voltage dividing resistor circuit to the gate of the second FET exceeds the reference voltage, a voltage for turning on the switching element is applied to the switching element; When the switching element is in an on state, a current is drawn from a node on a path from the voltage dividing resistor circuit to the gate of the third FET, thereby reducing the bias applied to the gate of the third FET. <4> The amplifier circuit according to claim 1. <6> The switching element is an N-channel or P-channel MOSFET. <4> or <5> The amplifier circuit according to claim 1. <7> a reference voltage generating circuit that generates a bandgap reference voltage; and a constant voltage generating circuit that generates a constant voltage value based on the bandgap reference voltage generated by the reference voltage generating circuit, The constant voltage value generated by the constant voltage generating circuit is set as the reference voltage. <4> or <5> The amplifier circuit according to claim 1. <8> The voltage dividing resistor circuit further includes a diode-connected FET provided between the voltage dividing resistor circuit and a reference potential. <1> from <5> 10. An amplifier circuit according to claim 9, wherein: <9> a constant current source that outputs a constant current; and a replica FET that forms a current mirror circuit together with the first FET, The current mirror circuit generates a bias corresponding to the constant current output by the constant current source and provides it to the first FET. <1> from <6> 10. An amplifier circuit according to claim 9, wherein: <10> The voltage dividing resistor circuit includes: a first resistor, a second resistor connected in series with the first resistor, and a third resistor connected in series with the second resistor; a reference potential is connected to the first resistor side, and the power supply is connected to the third resistor side; the voltage generated by the first resistor is used as a bias for the gate of the second FET; The voltage generated by the second resistor is used as a bias to be applied to the gate of the third FET. <1> from <9> 10. An amplifier circuit according to claim 9, wherein: <11> a fourth FET provided between the third FET and a load; a fourth resistor provided between the third resistor and the power supply; a voltage generated by the third resistor is used as a bias to be applied to the gate of the fourth FET. <10> The amplifier circuit according to claim 1. <12> The voltage value of the power supply varies. <1> from <11> 10. An amplifier circuit according to claim 9, wherein: <13> An amplifier circuit including a plurality of FETs in which adjacent drains and sources are connected, each voltage generated by voltage division of a plurality of resistors connected in series is used as a bias, each bias is applied to each gate of the plurality of FETs, and when one of the biases exceeds a predetermined reference voltage, the other biases are clamped. <14> <1> from <13> 10. A power amplifier circuit comprising: a driver stage amplifier circuit comprising the amplifier circuit according to any one of claims 1 to 9; and a power stage amplifier circuit having an output from the driver stage amplifier circuit as an input. <15> The power stage amplifier circuit is composed of bipolar transistors. <14> The power amplifier circuit according to claim 1. <16> a voltage-dividing resistor circuit consisting of at least three stages of resistors connected in series, which generates a bias from each stage by resistor voltage division; a clamp circuit that clamps the bias of another stage closer to a power supply than a stage when the bias generated in the stage exceeds a predetermined reference voltage; and applying the bias to each gate of a plurality of FETs whose adjacent drains and sources are connected to each other; Bias generation circuit. [Explanation of symbols]

[0107] 11~17 FET 20 Voltage divider resistor circuit 21~25, 31~35 Resistance 41~45 Capacitor 50, 50a, 50b Clamp circuit 51 Comparison circuit 52, 52a Transistor 60 constant current source 70 Clamp voltage generation circuit 100, 100a-100d, 101, 200 Amplification circuit 250a~250d Bias generation circuit 300 Input matching circuit 400 Interstage matching circuit 500 output matching circuit 800, 900 board 1000 Power Amplifier Circuit L choke coil MN matching circuit Vdd power supply

Claims

1. an input terminal to which a signal to be amplified is input; a first FET having a gate to which a signal input to the input terminal is applied; a second FET and a third FET connected together with the first FET between a power supply and a reference potential; an output terminal provided between a load and the third FET, the third FET being located closer to the power supply, and configured to output an amplified signal; a voltage dividing resistor circuit for generating a bias to be applied to each gate of the second FET and the third FET; a clamp circuit that clamps the bias applied to the gate of the third FET when the bias applied to the gate of the second FET from the voltage dividing resistor circuit exceeds a predetermined reference voltage; and the first FET, the second FET, and the third FET are connected in series, The voltage dividing resistor circuit includes: a first resistor, a second resistor connected in series with the first resistor, and a third resistor connected in series with the second resistor; a reference potential is connected to the first resistor side, and the power supply is connected to the third resistor side; the voltage generated by the first resistor is used as a bias for the gate of the second FET; The voltage generated by the second resistor is used as a bias to be applied to the gate of the third FET. Amplification circuit.

2. In the voltage dividing resistor circuit, the first resistor is provided at a position closest to the reference potential, the second resistor is provided closer to the power supply than the first resistor, the third resistor is provided closer to the power supply than the second resistor, The amplifier circuit according to claim 1 , wherein the resistance value of the first resistor and the resistance value of the second resistor are greater than the resistance value of the third resistor.

3. The amplifier circuit according to claim 2 , wherein the resistance value of the first resistor is greater than the resistance value of the second resistor.

4. The clamp circuit a comparison circuit that compares a bias voltage value applied to the gate of the second FET from the voltage dividing resistor circuit with the reference voltage; a switching element that is turned on based on the output of the comparison circuit; Including, When the switching element is in an on state, the bias applied to the gate of the third FET is reduced.

4. The amplifier circuit according to claim 1.

5. The comparison circuit when a bias voltage value applied from the voltage dividing resistor circuit to the gate of the second FET exceeds the reference voltage, a voltage for turning on the switching element is applied to the switching element; When the switching element is in an on state, a current is drawn from a node on a path from the voltage dividing resistor circuit to the gate of the third FET, thereby reducing the bias applied to the gate of the third FET.

5. The amplifier circuit according to claim 4.

6. 5. The amplifier circuit according to claim 4, wherein the switching element is an N-channel or P-channel MOSFET.

7. a reference voltage generating circuit that generates a bandgap reference voltage; and a constant voltage generating circuit that generates a constant voltage value based on the bandgap reference voltage generated by the reference voltage generating circuit, 5. The amplifier circuit according to claim 4, wherein the constant voltage value generated by the constant voltage generating circuit is used as the reference voltage.

8. 4. The amplifier circuit according to claim 1, further comprising a diode-connected FET provided between the voltage-dividing resistor circuit and a reference potential.

9. a constant current source that outputs a constant current; and a replica FET that forms a current mirror circuit together with the first FET, The current mirror circuit generates a bias corresponding to the constant current output by the constant current source and applies it to the first FET.

4. The amplifier circuit according to claim 1.

10. a fourth FET provided between the third FET and a load; a fourth resistor provided between the third resistor and the power supply; a voltage generated by the third resistor is used as a bias to be applied to the gate of the fourth FET.

2. The amplifier circuit according to claim 1.

11. 4. The amplifier circuit according to claim 1, wherein the voltage value of the power supply varies.

12. The transistor includes a plurality of FETs each having adjacent drains and sources connected to each other, and uses voltages generated by voltage division of a plurality of resistors connected in series as bias voltages; the plurality of series-connected resistors are connected between a power supply and a reference potential; applying each of the biases to the gates of the plurality of FETs, and clamping the other of the biases when one of the biases exceeds a predetermined reference voltage; An amplifier circuit in which the other bias is generated at a position closer to the power supply than one of the biases.

13. 4. A power amplifier circuit, comprising: an amplifier circuit according to claim 1 as a driver stage amplifier circuit; and a power stage amplifier circuit having an output from the driver stage amplifier circuit as an input.

14. 14. The power amplifier circuit according to claim 13, wherein the power stage amplifier circuit is configured by bipolar transistors.

15. a voltage-dividing resistor circuit consisting of at least three stages of resistors connected in series, which generates a bias from each stage by resistor voltage division; a clamp circuit that clamps the bias of another stage closer to a power supply than the stage in question when the bias generated in the stage exceeds a predetermined reference voltage; and the voltage dividing resistor circuit is connected between the power supply and a reference potential; applying the bias to each gate of a plurality of FETs whose adjacent drains and sources are connected to each other; Bias generation circuit.

Images