Pillar Select Transistors for 3D Cross-Point Memory

Abstract

To provide a pillar select transistor which increases the memory density while minimizing the decoder transistor footprint in a cross point memory array.SOLUTION: A memory device structure 100 includes a vertical pillar select transistor 102 having a channel layer 104 between a source structure 106 and a drain structure 108, and a gate electrode 110 adjacent to the channel. A gate dielectric layer 111 is between the gate electrode and the channel layer. A first terminal 112 of a first interconnect 112 is coupled with the source structure or the drain structure. The memory device structure further includes a pair of memory cells 118, 120 (136, 138). Each memory cell includes a selector and a memory element. First terminals of the individual memory cells are coupled to respective second and third terminals of the first interconnect. Second terminals of the individual memory cells are coupled to individual ones in a pair of second interconnects.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] A three-dimensional (3D) cross-point memory array may have tiers or decks of memory cells. However, increasing the total number of memory cells in this manner may proportionally increase the number of decoder transistors required, thereby increasing the overall decoder transistor footprint. Therefore, a solution is needed to increase memory density while minimizing the decoder transistor footprint. [Brief explanation of the drawings]

[0002] The materials described herein are illustrated for purposes of illustration and not limitation in the accompanying figures. For simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" shapes and arrangements for clarity of discussion, although it will be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and orthogonal intersections may be depicted while ignoring the finite roughness, chamfers, and imperfect angle intersections characteristic of structures formed by nanofabrication techniques. Furthermore, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or similar elements. [Figure 1A] 1 is a cross-sectional view of a memory device structure including vertical transistors coupled to a tiered memory array. [Figure 1B] 1B is a plan view of a line segment passing through the midplane of the transistor in FIG. 1A. [Figure 1C] 1 is a cross-sectional view of a memory cell according to an embodiment of the present disclosure. [Figure 1D] 1 is a cross-sectional view of a memory cell according to an embodiment of the present disclosure. [Figure 2A] 1 is a cross-sectional view of a memory element according to an embodiment of the present disclosure. [Figure 2B] 1 is a cross-sectional view of a memory element according to an embodiment of the present disclosure. [Figure 2C] 1 is a cross-sectional view of a selector element according to an embodiment of the present disclosure. [Figure 2D] 1 is a cross-sectional view of an embedded memory selector cell, where the insulating layer exhibits properties of the memory element and the selector element. [Figure 2E] FIG. 10 is a cross-sectional view of a switching layer adjacent to an insulator layer according to an embodiment of the present disclosure. [Figure 3A] 1 is an isometric view of a memory device structure including a vertical transistor array coupled to a tiered memory array according to an embodiment of the present disclosure. [Figure 3B] FIG. 3B is a plan view of a portion of a tier of the memory device structure of FIG. 3A. [Figure 3C] FIG. 3B is a plan view of a portion of a tier of the memory device structure in FIG. 3A. [Figure 4A] 1 shows a material layer stack formed over a substrate. [Figure 4B] 4B is a cross-sectional view of the structure in FIG. 4A after a masking and etching process to form a staircase structure. [Figure 4C] 4C is a cross-sectional view of a portion of the material layer stack in FIG. 4B after an etching process to form a plurality of openings. [Figure 4D] The structure of FIG. 4C is shown after a process in which portions of the dielectric are selectively laterally recessed to form a plurality of recesses. [Figure 4E] 4D after the formation of electrode material in the multiple lateral recesses. [Figure 4F] The structure of FIG. 4E is shown after a process in which some of the electrode material is etched away from the plurality of openings and some of the lateral recesses. [Figure 4G] 4F after deposition of selector material in recesses adjacent to the electrode material. [Figure 4H] The structure of Figure 4G is shown after a process in which a portion of the selector material is etched away from a portion of the lateral recess adjacent to the electrode material. [Figure 4I] The structure of Figure 4H is shown after formation of electrode material adjacent to the selector material. [Figure 4J] 4I shows the structure of FIG. 4I after deposition of one or more layers of memory material in the recesses adjacent to the electrode material. [Figure 4K] The structure of FIG. 4J is shown after a process in which a portion of the memory material is etched away from a portion of the lateral recess adjacent to the electrode material. [Figure 4L] The structure of Figure 4K is shown after formation of electrode material adjacent to the memory material. [Figure 5A] 4L shows the structure of FIG. 4L after formation of a dielectric in the multiple openings. [Figure 5B] 5B is an isometric view of the structure in FIG. 5A taken through line A-A'. [Figure 6A] 1 is a cross-sectional view of a cut mask implementation to form individual memory cells. [Figure 6B] FIG. 5B is a plan view of a portion of a mask over the structure of FIG. 5A. [Figure 7] FIG. 5B is an isometric view of the structure of FIG. 5A after a cut-etch process. [Figure 8A] 8 is a cross-sectional view of the structure in FIG. 7 through line A-A' after the process of forming electrodes. [Figure 8B] 8B shows the structure of FIG. 8A after formation of a first set of conductors and a second set of conductors in a three-level memory array. [Figure 9] 1A-1B are methods of fabricating the transistor described in connection with FIGS. 1A-1B, according to embodiments of the present disclosure. [Figure 10A] 1 is a cross-sectional view of an electrode formed on a substrate. [Figure 10B] The structure of FIG. 10C is shown after the process of forming a material layer stack on the first dielectric over the electrode. [Figure 10C] 10C after the formation of an opening in the material layer stack. [Figure 10D] The structure of FIG. 10C is shown after formation of a gate dielectric layer in the opening. [Figure 10E]The structure of Figure 10D is shown after a process in which a portion of the gate dielectric layer is etched away from above the electrode. [Figure 10F] The structure of FIG. 10E is shown after formation of channel layer material in the openings over the electrodes and over the gate dielectric layer. [Figure 10G] The structure of FIG. 10F is shown after formation of a second dielectric in the opening. [Figure 10H] The structure of Figure 10G is shown after a process that selectively recesses the second dielectric relative to the gate dielectric layer and the channel layer. [Figure 10I] After forming the top electrode, the structure is shown in FIG. 10H. [Figure 11] 1 is a cross-sectional view of a transistor structure in which the source and drain structures each have the same lateral thickness. [Figure 12A] 1 is a cross-sectional view of an array of transistors. [Figure 12B] 1 is a cross-sectional view of a tiered memory array over a logic transistor array according to an embodiment of the present disclosure. [Figure 13] FIG. 1 is a block diagram of an example computing system including a pillar select transistor array coupled to a memory device array to enable decoder transistor footprint scaling. [Figure 14] FIG. 1 is a block diagram of an example system in which a memory includes a pillar select transistor array coupled to a memory device array to enable decoder transistor footprint scaling. DETAILED DESCRIPTION OF THE INVENTION

[0003] Pillar select transistors for 3D cross points and fabrication methods are described below. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other cases, known features, such as field-effect transistors (FETs) and operations associated with memory or selector elements, are not described in detail in order to avoid obscuring the embodiments of the present disclosure. Furthermore, the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0004] In some instances, in the following description, well-known methods and devices are shown in block diagram form rather than in detail to avoid obscuring the present disclosure. Throughout this specification, a reference to an "embodiment" or "one embodiment" or "some embodiments" means that a specific feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in an embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, and specific features, structures, functions, or characteristics associated with the two embodiments are not necessarily mutually exclusive.

[0005] As used in this description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that as used herein, the term "and / or" refers to and includes any and all possible combinations of one or more of the associated listed items.

[0006] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between two or more components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect physical, electrical, or magnetic contact with each other (with other intervening elements therebetween) and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0007] As used herein, the terms "over," "under," "between," and "on" refer to the relative location of one component or material to another component or material, where such physical relationship is noteworthy. For example, in the context of materials, a material disposed above or below another may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material / ingredient. In the context of component assemblies, a similar distinction is made. As used throughout this description and claims, a list of items combined by the terms "at least one of" or "one or more of" may mean any combination of the listed terms.

[0008] As used herein, the term "adjacent" generally refers to a position that is laterally next to another (e.g., immediately adjacent, with one or more things in between) or that joins (e.g., abuts) one another.

[0009] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references.

[0010] The term "device" may generally refer to an apparatus depending on the context of use of the term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and / or passive components, etc. Generally, a device is a three-dimensional structure having a plane along the x-y direction of an x-y-z Cartesian coordinate system and a height along the z direction. The plane of a device may also be the plane of an apparatus that contains the device.

[0011] As used throughout this description and claims, series of items joined with the terms "at least one of" or "one or more of" may mean any combination of the listed terms.

[0012] Unless otherwise specified in the explicit context of use, the terms "substantially equal," "approximately equal," and "nearly equal" mean that the difference between the two items so described is no more than random variation. In the art, such variation is typically no more than ±10% of a predetermined target value.

[0013] Terms such as "left," "right," "front," "back," "top," "bottom," "over," and "under" in this description and claims, if any, are used for descriptive purposes and do not necessarily describe permanent positional relationships. For example, as used herein, terms such as "over," "under," "front side," "back side," "top," "bottom," "over," "under," and "on" refer to the relative location of one component, structure, or material within a device relative to another referenced component, structure, or material. Here, such physical relationships are noteworthy. These terms are used herein for descriptive purposes only, primarily within the context of the device's z-axis, and thus may be relative to the device's orientation. Thus, in the context of the figures provided herein, a first material "above" a second material may also be "below" the second material if the device is in an upside-down orientation relative to the context of the figures provided. In the context of materials, a material disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with that second material. In the context of component assembly, a similar distinction is made.

[0014] The term "between" may be used in the context of the z-axis, x-axis, or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or may be separated from both of the other two materials by one or more intervening materials. Thus, a material that is "between" two other materials may be in contact with either of the other two materials, or may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or may be separated from both of the other two devices by one or more intervening devices.

[0015] Memory cells are used in conjunction with large arrays of decoder transistors for various 3D cross-point memory applications. 3D cross-point memory arrays often include a series of word lines on a first plane and a series of bit lines on a second plane above the first plane, with the word lines orthogonal above the bit lines (or vice versa). A memory cell is located at each point of crossover between the word lines and bit lines (cross-point), and the memory cell couples the word line with the corresponding bit line to form a single memory array deck, or decks as we call them.

[0016] In embodiments, the effective cell size of a cross-point memory cell is equal to the square of the cell pitch divided by the number of decks. In some embodiments, the number of memory decks is approximately six or less. When the upper limit of the number of memory decks is reached, memory scaling may be limited by the specific memory pitch (lateral spacing between memory cells). Memory density can be increased in conventional 3D cross-point memory by pitch scaling and stacking layers (increasing the number of decks). However, production costs can increase significantly as the number of decks increases, depending on the number of process steps required to manufacture each deck.

[0017] However, the present inventors have devised an apparatus that allows for an increase in the number of stacks in a memory device structure without a concomitant increase in memory device production costs. According to an embodiment of the present disclosure, a memory device structure includes memory cells, with the memory elements laterally coupled to a selector element in each memory cell. In a further embodiment, the memory device structure may include a plurality of memory cells in an array that extends in two orthogonal directions in a plane to form tiers or decks. The memory device structure may include a plurality of decks that are stacked. In operation, the memory device structure: To access a pair of memory cells, Wordline, bitline, and tier / deck addresses Unique Set Selection Choice of It can be made possible.

[0018] The memory device structures described herein may advantageously reduce the number of decoder or programming transistors, providing a reduction in chip area. To address a specific memory cell in a tier, a decoder transistor may be individually coupled to each word line and bit line. As the number of memory cells increases, the number of bit lines and word lines increases proportionally, and the number of decoder transistors required to address each memory cell (bit cell) also increases. To accommodate a large number of decoder transistors near the cross-point array, such as below the cross-point memory array, the relative lengths of the word lines and bit lines may be increased. Alternatively, the decoder transistors may occupy an area laterally adjacent to the memory array. In either example, a larger chip area may be utilized.

[0019] Increasing the number of memory cell layers (tiers) to form a three-dimensional array can increase memory density per unit area. However, increasing the number of memory cells also increases the number of decoder transistors required proportionally. In some examples, a single tier may contain 4,000 bit lines and 4,000 word lines. Thus, a single 4,000 x 4,000 tier may require 8,000 decoder transistors. Because the number of decoder transistors increases proportionally with the number of tiers, it can be very difficult to enable a high-density memory array for a given die size.

[0020] According to some embodiments, to reduce the number of decoder transistors, multiple (e.g., two) memory cells in a tier are coupled through a common electrode. The common electrode may further be coupled to the source or drain of the decoder transistor immediately below. In addition to coupling multiple memory cells by a common electrode to reduce the total number of decoder transistors, confining the decoder transistors within the footprint of a memory cell is also advantageous in reducing the device footprint.

[0021] Another advantage of memory device structures according to embodiments is that memory cells in various tiers can be manufactured in parallel, which can significantly reduce manufacturing costs per memory cell.

[0022] 1A is a cross-sectional view of a memory device structure 100 including a vertical pillar select transistor 102 coupled to a tier memory structure 103. As shown, the pillar select transistor 102 includes a channel layer 104 between a source structure 106 and a drain structure 108. As shown, the channel layer 104 is Vertical The pillar select transistor 102 is oriented along a direction axis (along the y-axis in the figure). The pillar select transistor 102 also includes a gate electrode 110 adjacent to the channel layer 104. The gate electrode 110 VerticalThe gate electrode 110 has a length in a direction perpendicular to the direction axis (along the x-axis). The gate dielectric layer 111 is between the gate electrode 110 and the channel layer 104. The memory device structure 100 further includes an interconnect 112, which is connected to the pillar select transistor 102. Vertical directional axis. In the exemplary embodiment, terminal 112A of interconnect 112 is coupled to drain structure 108. In the exemplary embodiment, interconnect 112 is coupled to interconnect 113 through pillar select transistor 102. Interconnect 113 represents a bit line in memory device structure 100. In the exemplary embodiment, interconnect 113 underlies and is coupled to source structure 106.

[0023] As shown, the pillar select transistor 102 is a thin film transistor. In the exemplary embodiment, the channel layer 104 includes a horizontal channel portion 104A and a vertical channel portion 104B. The horizontal portion 104A is adjacent to the source structure 106, and the vertical portion 104B is adjacent to the gate dielectric layer 111. The channel layer 104 may laterally overlap the drain structure 108. In the exemplary embodiment, the vertical channel portion 104B laterally confines the drain structure 108. In other embodiments, the vertical channel portion 104B is below the drain structure 108. The channel layer 104 is also adjacent to a dielectric 124. The dielectric 124 defines a gate length L of the pillar select transistor 102. G Adjust Vertical The pillar select transistor 102 has a vertical thickness along the direction axis. The electrical gate length of the pillar select transistor 102 is Vertical It is determined by the thickness of the gate electrode 110 along the direction axis. G is between 50 nm and 500 nm. G V ≡ ...

[0024] In the cross-sectional view, the gate electrode 110 extends from the source structure 106 VerticalHowever, the gate electrodes 110 are spaced apart along a direction axis (e.g., the y-axis). Vertical The gate electrode 110 may overlap the drain structure 108 along a directional axis. In some embodiments, the gate electrode 110 may laterally overlap the drain structure 108 with an intervening dielectric 124 between the channel layer 104 and the gate electrode 110.

[0025] 1B is a plan view through line A-A' of FIG. 1A. As shown, the various layers in the pillar select transistor 102 are substantially conformal overlays around the dielectric 124. As shown, the channel layer 104 overlays the dielectric 124, the gate dielectric layer 111 overlays the channel layer 104, and the gate electrode 110 overlays the gate dielectric layer 111. The dielectric 124 is formed to a lateral thickness W of the channel layer 104. C and the lateral thickness W of the gate dielectric layer 111 GDL Substantially greater lateral thickness W DE In an embodiment, the channel layer 104 has a lateral thickness W that is between 5 nm and 20 nm. C In some embodiments, the gate dielectric layer 111 has a lateral thickness W that is between 1 nm and 3 nm. G It has.

[0026] The gate electrode 110 is formed on the channel layer 104. Vertical Length L in the direction perpendicular to the direction axis GE L GE is the L shown in Figure 1A G , or transistor gate length. The gate electrode 110 has a width W GE W GE is measured along the z-axis in a direction along interconnect 114 or 116 (not shown). In an exemplary embodiment, W GE is less than 150 nm.

[0027] Referring again to FIG. 1A, along the x-axis, the drain structure 108 has a lateral thickness W D and the source structure 106 has a lateral thickness W SIn an exemplary embodiment, W D is W S In an exemplary embodiment, the source structure 106 has a lateral thickness equal to the combined sum of the lateral thickness of the drain structure 108, twice the lateral thickness of the gate dielectric layer 111, and twice the lateral thickness of the channel layer 104. The transistor 102 is coupled to the tier memory structure 103 through an interconnect 112.

[0028] Tiered memory structure 103 includes multiple tiers. In the exemplary embodiment, two tiers are shown, e.g., tier 132 and tier 134 directly above tier 132. As shown, tier 132 includes a pair of memory cells 118 and 120 and a pair of interconnects (such as interconnects 114 and 116 that extend orthogonally (e.g., in the z-axis) to interconnect 112). Interconnects 116 and 114 are examples of word lines of memory device structure 100. As shown, each memory cell 118 and 120 is symmetrically coupled to a portion of interconnect 112 laterally between interconnects 114 and 116, respectively.

[0029] In the exemplary embodiment, memory cells 118 and 120 each include terminal 121 and terminal 122 opposite terminal 121. One of terminal 121 or 122 of each memory cell is coupled to transistor 102 (through interconnect 112), and the other of terminal 121 or 122 is coupled to either interconnect 114 or 116. As shown, terminal 121 of each memory cell is coupled to interconnect 112, and terminal 122 of each memory cell is coupled to either interconnect 114 or interconnect 116. In the exemplary embodiment, terminal 121 of each of memory cells 118 and 120 is coupled to terminals 112B and 112C, respectively, of interconnect 112 in tier 132. Also as shown, terminal 122 of memory cell 118 is coupled to interconnect 114, and terminal 122 of memory cell 120 is coupled to interconnect 116.

[0030] In the exemplary embodiment, tiered memory structure 103 further includes an additional pair of memory cells 136 and 138 symmetrically coupled to a portion of interconnect 112 within tier 134. In the exemplary embodiment, memory cells 136 and 138 are directly above memory cells 118 and 120, respectively. Tier 134 also includes a pair of interconnects, such as interconnect 140 and interconnect 142, that are above and parallel to interconnects 114 and 116, respectively. Interconnects 140 and 142 are examples of word lines of memory device structure 100. In the exemplary embodiment, terminal 121 of each memory cell 136 and 138 is coupled to terminals 112D and 112E of interconnect 112, respectively. As shown, terminal 122 of memory cell 136 is coupled to interconnect 140, and terminal 122 of memory cell 138 is coupled to interconnect 142.

[0031] It should be understood that the interconnects 114 , 116 , 140 and 142 may be independently voltage biased to program any of the four memory cells 118 , 120 , 136 or 138 in the memory device structure 100 .

[0032] The tier 134 is a Vertical A distance S from the tier 132 along a direction axis (e.g., the y-axis) TT In an embodiment, the distances are S TT The thickness of the tier 132 and the tier 134 is between 5 nm and 30 nm. Vertical The vertical thickness T measured along the direction axis T Embodiment T T is between 5nm and 20nm.

[0033] As shown, the interconnect structure 112 has a lateral thickness W I W Iis measured along the x-direction. As shown, each memory cell 118 and 120 has a lateral thickness W that is between 100 nm and 120 nm. MC In an exemplary embodiment, interconnects 140 and 142 have a lateral thickness W of memory cells 118 and 120 and a lateral thickness W of interconnect structure 112, as shown in equation [1]. I The lateral thickness W along the x-axis is equal to the combined EE You can leave a gap of just that.

[0034] W EE =W I +2*W MC [1] where W MC is the lateral thickness of each of the memory cells 118, 120, 136 and 138. In an exemplary embodiment, W MC is the same or substantially the same for each memory cell 118, 120, 136 and 138. I is W EE To keep W fixed, MC may be increased or decreased proportionally.

[0035] The lateral thickness of the pillar select transistor 102 feature is related to the dimensions of the memory cells 118 and 120 and the interconnect 112 in the tier 132. EE is W S However, for functionality, W S Advantageously, W is equal to another lateral dimension of the memory array. To prevent the gate dielectric layers of adjacent transistors (in the array) from connecting, the source contact is located at the lateral thickness W of the memory unit, which is described by equations [2] and [3] below: MU Transverse thickness W related to S It has. W S <W MU [2]

[0036] W MU =WI +2*(W MC +1 / 2W E ) [3] W E is equal to the lateral thickness of the interconnects 140 and 142. In an embodiment, W E is between 35nm and 50nm.

[0037] The lateral thickness of the tier memory structure 103 features may also be related to the lateral thickness of the pillar select transistor 102 features. I is W S In an embodiment, W I is between 50nm and 70nm, and W S is at least 200 nm but less than 300 nm. In an embodiment, the source structure 106 has a lateral thickness that is less than twice the lateral thickness of the memory cell. S is 2*W MC is less than.

[0038] In embodiments, the transistor channel layer 104 comprises a polycrystalline or amorphous material suitable for a thin film transistor channel. In some embodiments, the channel layer 104 comprises an n-type semiconductor material. Examples of n-type semiconductor materials include two or more of In, Ga, Zn, Mg, Al, Sn, Hf, O, W, such as In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, InWO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, or InMgZnO.

[0039] The n-type transistor channel layer 104 can be doped with, for example, Ti, W, Cu, Mn, Mg, Fe, Hf, Al, Ni, CO, or Ru. 16 ~10 20 atoms / cm 3In another embodiment, the channel layer 104 comprises a p-type material. An example of a p-type semiconductor material is CuO. x (x is 1 or 2), NbO, NiO, CoO, SnO, CuO, AgAlO, CuAlO, AlScOC, SrBPO, LaSiOSe, LaCuSe, RbSnO, LaOS, KSnO, NaFeOSe, or ZnRhO. The thickness of the channel layer 104 may depend on the material and may be between 1 nm and 80 nm.

[0040] In an embodiment, the gate dielectric layer 111 comprises a material having a high dielectric constant or high-K material. Examples of gate dielectric layers 111 include oxygen and one or more of elements such as hafnium, silicon, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, or zinc. Examples of high-K materials that may be used for the gate dielectric layer 111 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0041] In an embodiment, the gate electrode 110 comprises at least one P-type or N-type work function metal, depending on whether the transistor is to be a P-FET or N-FET transistor. Examples of N-type materials include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide. Examples of P-type materials include ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides, such as ruthenium oxide.

[0042] In embodiments, the interconnects 112 include copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, ruthenium, molybdenum, cobalt, alloys thereof, or compounds including nitrogen and one or more of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, titanium, tin, or lead. In some embodiments, the interconnects 112 include a metal carbide, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide.

[0043] In embodiments, interconnects 114 and 116 each comprise copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, ruthenium, molybdenum, cobalt, and alloys thereof, or alloys comprising nitrogen and one or more of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, titanium, tin, or lead. In some embodiments, interconnect 112 comprises a metal carbide, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide.

[0044] In embodiments, interconnects 140 and 142 each comprise copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, ruthenium, molybdenum, cobalt, and alloys thereof, or alloys comprising nitrogen and one or more of copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, titanium, tin, or lead. In some embodiments, interconnect 112 comprises a metal carbide, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, or aluminum carbide.

[0045] In an embodiment, memory cell portions 118A, 120A, 136A, and 138A each include a selector element coupled in series with a non-volatile memory element.

[0046] FIG. 1C is a cross-sectional view of a memory cell, such as memory cell 118. In an exemplary embodiment, memory cell 118 includes a memory element 126 and a selector element 128 coupled through terminal 130. In an embodiment, either all memory elements 126 or all selector elements 128 of memory cells 118, 120, 136, or 138 are simultaneously coupled to interconnect 112 (dashed box) through terminal 121. For example, as shown, memory element 126 is adjacent to terminal 121 and selector element 128 is adjacent to terminal 122. In another embodiment, memory element 126 is adjacent to terminal 122 and selector element 128 is adjacent to terminal 122 (configuration not shown). Referring again to FIG. 1A, for operational advantages, a combination of voltage biases on gate electrode 110 and source structure 106 in pillar select transistor 102, relative to interconnect 112, can activate each pair of memory cells in tiers 132 and 134. Symmetrically positioned selectors or memory elements within each memory cell 118, 120, 136, or 138 relative to interconnect 112 may enable uniform programming operations, such as set or reset, in, for example, a filamentary resistance random access memory device. However, although terminals 121 of all memory cells 118, 120, 136, and 138 are supplied with electricity by transistor 102, a single memory cell may be selected for programming by applying a bias voltage to any one of interconnects 114, 116, 140, and 142.

[0047] 1D , memory element 126 is directly adjacent to selector element 128. In some such embodiments, for example, there are no electrodes between one or more switching layers in memory element 126 and one or more insulator layers in selector element 128. Descriptions of the switching and insulator layers of memory element 126 and selector element 128, respectively, are provided herein.

[0048] 2A is a cross-sectional view of a memory element. In some embodiments, all memory cells in a given tier 132 or 134 have the same configuration. The memory elements may include phase change memory (PCM), resistive random access memory (R-RAM), ovonic threshold switch (OTS) memory, or conductive bridge RAM (CBRAM).

[0049] In one embodiment, memory element 126 is a resistive random access memory (RRAM®) device. In the embodiment shown, memory element 126 includes an electrode 202, a switching layer 204 adjacent to electrode 202, an oxygen exchange layer 206 adjacent to switching layer 204, and an electrode 208 adjacent to oxygen exchange layer 206. Switching layer 204 and oxygen exchange layer 206 may collectively be referred to as storage layer 207. In embodiments in which electrode 202 comprises the material of terminal 121, switching layer 204 may be directly adjacent to terminal 121. In some such embodiments, electrode 208, when present, may be directly adjacent to a selector element, such as selector element 128 shown in FIG. 1C .

[0050] Referring again to FIG. 2A , in an embodiment, electrode 202 comprises an amorphous layer. In an embodiment, electrode 202 is a topographically smooth electrode. In an embodiment, electrode 202 comprises a material such as W, Ta, Mo, Ru, Co, TaN, or TiN. In an embodiment, electrode 202 has a lateral thickness between 1 nm and 10 nm. In an embodiment, electrode 208 comprises a material such as W, Ta, Mo, Ru, Co, TaN, or TiN. In an embodiment, electrode 208 has a lateral thickness between 1 nm and 10 nm. In an embodiment, electrode 202 and electrode 208 comprise the same material to facilitate symmetric RRAM switching characteristics.

[0051] The switching layer 204 may be, for example, a metal oxide containing atoms of oxygen and one or more metals such as, but not limited to, Hf, Zr, Ti, Ta, or W. In the case of titanium or hafnium, or tantalum, which has an oxidation state of +4, the switching layer 204 has the chemical composition MO X where O is oxygen and X is 2 or substantially close to 2. For tantalum, which has an oxidation state of +5, the switching layer 204 has the chemical composition MO X where O is oxygen and X is 5 or substantially close to 5. In an embodiment, the switching layer 204 has a thickness between 1 nm and 5 nm.

[0052] The oxygen exchange layer 206 acts as a source of oxygen vacancies or 2‐ In an embodiment, the oxygen exchange layer 206 is composed of a metal such as, but not limited to, hafnium, tantalum, or titanium. In an embodiment, the oxygen exchange layer 206 has a thickness between 5 nm and 20 nm. In an embodiment, the thickness of the oxygen exchange layer 206 is at least twice the thickness of the switching layer 204. In another embodiment, the thickness of the oxygen exchange layer 206 is at least twice the thickness of the switching layer 204. The combined lateral thickness of the storage layer 207 can be between 3 nm and 15 nm. In an embodiment, the memory element 126 has a lateral thickness W that is between 15 nm and 35 nm. M In an embodiment, the memory element 126 has a vertical thickness T V In embodiments in which electrode 202 comprises a material (not shown) that is the same as the material of terminal 121, the memory element does not include a separate electrode 202. In some such embodiments in which memory element 126 is directly adjacent to the insulator (not shown) of selector element 128, element 126 has a lateral thickness W that is between 7 nm and 15 nm. M It has.

[0053] In other embodiments, nonvolatile memory element 126 includes only electrodes 202 and 208 and an insulator 209 therebetween, as shown in FIG. 2B . In some such embodiments, insulator layer 209 exhibits charge carrier tunneling behavior. In some such embodiments, insulator layer 209 includes oxygen and a metal, such as, but not limited to, aluminum, hafnium, tantalum, and titanium. In further embodiments, insulator layer 209 is also doped with atoms of one or more metals, such as, but not limited to, copper, silver, or gold. In some such embodiments, insulator layer 209 is doped with atoms of one or more metals, such as copper, silver, or gold, to a concentration of between 2% and 10% (atoms). In embodiments, insulator layer 209 has a thickness of between 2 nm and 5 nm.

[0054] In another embodiment, the insulator layer 209 comprises a threshold switch material, e.g., a phase change material. In some examples, the insulator layer 209 may comprise a phase change material that exhibits at least two different electrical states characterized by two different resistances, such as a conductive state and a resistive state. In some examples, the phase change material exhibits at least two different material states, such as amorphous and crystalline, corresponding to two different resistance states. In embodiments, the phase change material in the entirely crystalline phase is It is conductive, When the phase change material is in an amorphous state teeth However, by adjusting the relative extent of the crystalline and amorphous phases in a given volume of the phase change material, the resistance of the phase change material can be adjusted. In embodiments, the resistive state of the phase change material may be set by heating and cooling the phase change material in a specific manner, for example, by applying a voltage bias between electrodes 202 and 208 to induce Joule heating.

[0055] In an embodiment, the phase change material includes Ge and Te. In an embodiment, the phase change material further includes Sb. In an embodiment, the phase change material includes a ternary alloy of Ge, Te, and Sb, such as Ge2Sb2Te5. In an embodiment, the phase change material includes a binary, ternary, or quaternary alloy including at least one element from the Group V periodic table, such as Te, Se, or S. In an embodiment, the phase change material includes a binary, ternary, or quaternary alloy having at least one of Te, Se, or S, the alloy further including an element from the Group V periodic table, such as Sb. In an embodiment, the phase change material includes a dopant, such as silver, indium, gallium, nitrogen, silicon, or germanium. In an embodiment, the dopant concentration is between 5% and 20% of the total composition of the phase change material. In an embodiment, the insulator layer 209 has a thickness (e.g., measured along the x-axis) of between 2 nm and 15 nm.

[0056] FIG. 2C is a cross-sectional view of a structure of a selector element 128 according to an embodiment of the present disclosure. As shown, the selector device includes a metal-insulator-metal (MIM) stack. The MIM stack of selector element 128 includes a selector electrode 210 and an insulator layer 211 between selector electrode 210 and selector electrode 212. In an embodiment, insulator layer 211 includes an ovonic threshold switching material. In an embodiment, the insulator includes an alloy of Ge, As, and Se, such as GeAsSe, GeSe, or AsSe. In some embodiments, the alloy of Ge, As, and Se may include a dopant, such as, for example, As-doped GeSe, Ge-doped AsSe, or In-, Te-, or Sb-doped GeAsSe. In an embodiment, insulator layer 211 has a thickness that depends on the material. In an exemplary embodiment, the thickness is between 5 nm and 30 nm. Electrodes 210 and 212 may comprise a material that is the same or substantially the same as the material of electrodes 202 and 208 .

[0057] In another embodiment, insulator layer 211 comprises a material capable of undergoing a reversible insulator-to-metal transition. In an embodiment, the transition is triggered by a thermal process. In another embodiment, the transition is triggered by an electrical process. The insulator-to-metal transition is characterized by a high-resistivity insulator state and a low-resistivity metallic state. In some such embodiments, the insulator layer transition involves the development of filamentary conduction, in which filaments may extend through the insulator and couple to selector electrodes 210 and 212. The extent of such filaments may be adjusted during the transition between the insulator state and the metallic state depending on the voltage applied to selector electrodes 210 and 212. In some such embodiments, insulator layer 211 comprises oxygen and atoms of one or more metals, such as, but not limited to, niobium, vanadium, and tantalum. In some specific examples, insulator layer 211 comprises vanadium(IV) oxide VO, vanadium(V) oxide VO, or niobium(V) oxide NbO. In one particular example, insulator layer 211 includes niobium (V) oxide NbO and may exhibit filamentary conduction. When insulator layer 211 includes a material that exhibits filamentary conduction, filaments may appear in insulator layer 211. In an embodiment, insulator layer 211 is amorphous. In an embodiment, insulator layer 211, which may undergo an insulator-metal transition, has a thickness between 5 nm and 30 nm.

[0058] In some embodiments where an insulator-metal transition occurs, the insulator layer 211 further comprises a dopant, such as silver, copper, or gold. In embodiments, the dopant concentration is between 0.1 and 10% of the total composition of the insulator layer 211. A dopant concentration between 0.1 and 10% can facilitate filament conduction. Reducing the thickness of the insulator layer 211 can reduce the amount of voltage across the selector electrodes 210 and 212 required for filament conduction to develop, but can lead to unstable filament collapse and degradation. In embodiments, the selector electrode 210 comprises a conductive material such as TiN and TaN, or a metal such as Ta, W, or Pt. In embodiments, the selector electrode 210 has a thickness between 2 nm and 10 nm. In embodiments, the selector electrode 212 comprises a conductive material such as TiN and TaN, or a metal such as Ta, W, or Pt. In embodiments, the selector electrode 212 has a lateral thickness between 2 nm and 25 nm. In an embodiment, the selector element 128 has a vertical thickness T between 5 nm and 35 nm. V It has.

[0059] Figure 2D shows end Children 121 and 122 and , end Between child 121 and 122 Includes selector and memory cell characteristics Insulator layer 214 and1 is a cross-sectional view of a memory cell 118 including a memory cell 118 having a memory cell 118A and a memory cell 118B. In some such embodiments, insulator layer 214 includes an ovonic threshold-switching material, such as layer 211, which can function as a built-in selector memory. In embodiments, insulator layer 214 can exhibit selector or memory behavior that depends on the polarity and magnitude of a voltage pulse applied between terminals 121 and 122. In one embodiment, the insulator exhibits RRAM-like behavior, in which an applied voltage induces a resistance change in insulator layer 214. Application of an electrical pulse drives dopants in insulator layer 214 toward terminals 121 or 122, changing the electrochemical potential of insulator layer 214. The change in electrochemical potential can be manifested as a resistance change. In other embodiments, application of a one-time voltage pulse (OTP) causes electrical breakdown and allows conduction through insulator layer 214. This is selector-like behavior.

[0060] In some such embodiments, the insulator layer 209 or the storage layer 207 of the memory element is directly adjacent to the insulator layer 211 of the selector element, as shown in FIG. 2E. In some such embodiments, there is no electrode between the insulator layer 209 or the storage layer 207 and the insulator layer 211. In some such embodiments, each of the terminals 121 and 122 can also function as an electrode for the memory cell 118.

[0061] 3A is an isometric view of the structure of a multi-tier memory array 300. In an exemplary embodiment, the multi-tier memory array 300 includes an array of transistors 302 (herein referred to as transistor array 302) along the x-axis. In the exemplary embodiment, the transistor array 302 includes pillar select transistors 102, 304A, 304B, and 304C. As shown, each pillar select transistor 102, 304A, 304B, and 304C is coupled to an interconnect, such as interconnect 112. As shown, transistor 304A is coupled to interconnect 306A, transistor 304B is coupled to interconnect 306B, and transistor 304C is coupled to interconnect 306C. In an exemplary embodiment, transistors 304A, 304B, and 304C are substantially identical to pillar select transistor 102, and gate electrode 110 is shared between each pillar select transistor 102, 304A, 304B, and 304C. In embodiments in which gate electrode 110 includes a work function metal and a fill metal, the work function metal overlies gate dielectric layer 111.

[0062] In the exemplary embodiment, interconnect 306A is connected to transistor 304A. Vertical The interconnect 306B is collinear with the direction axis (e.g., the y-axis) of the transistor 304B. Vertical The interconnect 306C is collinear with the direction axis of the transistor 304A. Vertical The interconnects 306A, 306B, and 306C include a material that is the same or substantially the same as the material of the interconnect 112.

[0063] Tier 132 also includes: VerticalEach memory cell includes a single memory cell between an interconnect extending in the vertical direction and an electrode extending along the horizontal direction. For example, memory cell 308 is coupled between interconnect 116 and interconnect 306A, and memory cell 310 is coupled between interconnect 306A and electrode 312. Memory cells 308 and 310 include one or more features of memory cells 118 or 120. Interconnect 116 is shared between memory cells 308 and 120.

[0064] Multi-tier memory array 300 further includes multiple transistor arrays parallel to transistor array 302. In an exemplary embodiment, there are eight transistor arrays parallel to transistor array 302. In other embodiments, the number of transistor arrays is greater than eight. Each array includes one or more features of transistor array 302. In an exemplary embodiment, transistor array 314 is adjacent to, but isolated from, array 302. Each gate electrode, such as electrodes 110, 316, 318, 320, 322, 324, 326, and 328 in different transistor arrays, can each be electrically coupled to a respective routing conductor (not shown).

[0065] As shown, two or more interconnects on a single tier are coupled to one of two lateral extensions, such as lateral extension 330. In the exemplary embodiment, interconnects 116 and 331 are coupled to the same lateral extension 330. As shown, interconnect 332 on tier 333 is coupled to the other of the two lateral extensions, which is in front of multi-tier memory array 300 but is not shown for clarity. Lateral extension 330 comprises the same material as interconnect 116.

[0066] 3B is a plan view of a portion of transistor arrays 302 and 314 through the midplane (along line A-A') of tier 132 in FIG. 3A. As shown, gate electrode 316 (in a dashed box) of transistor array 314 extends laterally below interconnect 334, interconnect 116, and interconnect 336. Also shown is gate electrode 110 (in a dashed box) of transistor array 302 extending laterally below interconnect 112, interconnect 116, and interconnect 306. For clarity, only two transistor arrays 302 and 314 are shown in the figure.

[0067] The gate electrodes 110 and 316 are spaced apart along the z-axis by a distance D TT In an embodiment, D TT is between 40 nm and 70 nm. In an exemplary embodiment, the spacing D TT is W GE The lateral distance L between memory cells 118 and 338 (e.g., along the z-axis) is less than MC is the maximum width W of the gate electrodes 110 and 306 GE In an embodiment, D TT The minimum cell area is L MC and W EE (the lateral spacing between interconnects 112 and 306).

[0068] The gate electrode 110 extends and electrically couples to each pillar select transistor 102, 304A, etc., while the source structure of each transistor is spaced apart by a spacing S TR In an embodiment, the lateral distances are S TR is between 50nm and 70nm.

[0069] In the exemplary embodiment, interconnect 116 extends along the z-axis, orthogonal to the lateral placement of memory cells 118, 120, etc., and orthogonal to interconnects 112, 306, 334, and 336. Lateral extension 330 connects with a single interconnect 116 in the plan view embodiment. Lateral extension 330 may connect with multiple interconnects, for example, interconnects parallel to interconnect 116 (in the X-Z plane), to enable selective addressing of multiple memory cells on tier 132.

[0070] 3C is a plan view of a portion of transistor arrays 302 and 314 through the midplane (along line A-A') of tier 132 in FIG. 3A. In an exemplary embodiment, interconnect 113 is coupled to source structure 106 of transistor 102 and to source structure 340 of transistor 344. Transistor 344 is a transistor in transistor array 314. Interconnect structure 340 advantageously allows source structures from multiple transistors from different transistor arrays (e.g., 302 and 314) to be activated simultaneously. For clarity, only two transistor arrays 302 and 314 are shown in the figure.

[0071] Additionally, as shown, interconnect 344 is coupled to source structure 346 of transistor 304A and to source structure 348 of transistor 350. Transistor 350 is a transistor in transistor array 314. Interconnect structure 344 advantageously allows source structures from multiple transistors from different transistor arrays (such as 302 and 314) to be activated simultaneously. Interconnects 113 and 344 may be operated independently.

[0072] 4A-8B show various cross-sectional and isometric views associated with operations for fabricating a memory cell such as memory cell 118 or 120. FIG.

[0073] FIG. 4A shows a material layer stack 400 formed on a dielectric 402. In an exemplary embodiment, forming the material layer stack 400 includes forming a plurality of bilayers 404, each bilayer 404 including a dielectric layer 406 and a dielectric layer 408 on the dielectric layer 406. In an embodiment, the dielectric layer 406 is blanket deposited by a PECVD or chemical vapor deposition (CVD) process. In an embodiment, the dielectric layer 406 includes silicon and at least one of nitrogen or carbon (e.g., silicon nitride or silicon carbide). The dielectric layer 406, in the lowest bilayer, acts as an etch stop during the formation of the pillar via. The deposition process continues with the deposition of a dielectric layer 408 on the dielectric layer 406. In an embodiment, the dielectric layer 408 includes silicon and oxygen. In another embodiment, the dielectric layer 408 includes silicon, oxygen, and at least one of nitrogen or carbon. The material of dielectric layer 406 is different from the material of dielectric layer 408, where either dielectric layer 406 or dielectric layer 408 can be selectively removed or etched relative to the other. Dielectric layer 408 can be blanket deposited by a PECVD or chemical vapor deposition (CVD) process to a thickness between 20 nm and 40 nm. The thickness of dielectric layer 408 determines the maximum thickness of the memory cells that can be formed. The deposition process continues to form a plurality of bilayers 404.

[0074] In an embodiment, the dielectric 402 comprises silicon and one or more of oxygen, nitrogen, or carbon, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, or silicon carbide.

[0075] 4B is a cross-sectional view of the structure in FIG. 4A after a masking and etching process to form a staircase structure. In an embodiment, a plasma etching process is utilized to mask and etch the dielectric layers 406 and 408 in two individual layers. In an embodiment, the staircase structure represents the plurality of laterally extending portions described herein. In an embodiment, the lowest level of the dielectric 408 represents the lateral extension portion 330 (before the conductive formation of the lateral extension portion 330) described in connection with FIG. 3A.

[0076] 4C is a cross-sectional view of material layer stack portion 410 of structure FIG. 4B after a process of etching and forming a plurality of openings 412 and 413. In an embodiment, a plasma etching process is utilized to etch the plurality of bilayers 404. In an embodiment, openings 412 and 413 have a sidewall profile that is substantially vertical with respect to the top surface of dielectric 402.

[0077] Figure 4D shows multiple Recess A portion of the dielectric 406 is laterally removed selectively to the dielectrics 408 and 402 to form 409. Recess Machining 4C after the process of Recess can be formed by an atomic layer etching process, a plasma etching process, a wet chemical process, or a combination thereof.

[0078] In an embodiment, the lateral direction in the dielectric 406 in the material layer stack portions 410A, 410B, and 410C Recess have substantially similar widths. Recess is a width W selected to accommodate the formation of memory cells such as memory cell 118. MAdditionally, in cross section, dielectric 406 has three portions 406A, 406B, and 406C in each of two layers 404. For example, portion 406A is in material layer stack portion 410A, portion 406B is in material layer stack portion 410B, and portion 406B is in material layer stack portion 410C. In an embodiment, material layer stack portions 410A and 410C have widths selected to accommodate the formation of one memory cell, and material layer stack portion 410B has a width selected to accommodate the formation of two memory cells adjacent to dielectric 406.

[0079] Dielectric 406 is a material that, in downstream operation, replaces the conductor material of a tier, such as conductor 124 or 126. Dielectric 406 has a vertical thickness that represents the thickness of a tier, such as tier 132 or 134.

[0080] FIG. 4E illustrates a plurality of lateral electrodes adjacent to the dielectric 406. Recess 4D after the formation of electrode material 414 in openings 412 and 413. In an embodiment, electrode material 414 is also deposited on dielectric 402. In an embodiment, the electrode material comprises a material that is the same or substantially the same as the material of interconnect 114 or 116.

[0081] FIG. 4F shows the lateral view from openings 412 and 413 and adjacent dielectric 406. Recess 4E shows the structure of FIG. 4E after a process that etches and removes a portion of the electrode material 414 from a portion of 409. A portion of the electrode material 414 remains adjacent to the dielectric 406 between the two alternating dielectric layers 408. In an embodiment, the electrode material 414 is removed by atomic layer etching, a plasma etching process, a wet etching process, or a combination thereof. In an exemplary embodiment, the electrode material 414 is also removed from the surface of the dielectric 402.

[0082] FIG. 4G shows openings 412 and 413 and a plurality of adjacent electrode material 414. Recess4F shows the structure of FIG. 4F after deposition of selector material 416 in 409. Selector material 416 is also deposited adjacent to dielectric 408. One or more layers of selector material 416 may be deposited by an atomic layer deposition process. In an embodiment, selector material 416 is also deposited on dielectric 402.

[0083] FIG. 4H shows the lateral direction of the electrode material 414 Recess 4G shows the structure of FIG. 4G after a process of etching and removing a portion of the selector material 416 from a portion of 409. A portion of the selector material 416 remains adjacent to the electrode material 414 between the two alternating dielectric layers 408. In an embodiment, the selector material 416 is removed by atomic layer etching, a plasma etching process, a wet etching process, or a combination thereof. In an exemplary embodiment, a portion of the selector material 416 is also removed from the surface of the dielectric 402.

[0084] 4I shows the structure of FIG. 4H after the formation of electrode material 418 adjacent to selector material 416. In an embodiment, the process for forming electrode material 418 is the same or substantially the same as the process for forming electrode material 414. Electrode material 418 is deposited in openings 412 and 413 and in a plurality of openings adjacent to selector material 416 by an atomic layer deposition process. Recess A portion of the electrode material 418 may be deposited on the dielectric 402 and on the sidewalls of the dielectric 408, as well as on the plurality of Recess It can be etched and removed from the portion 409.

[0085] FIG. 4J shows openings 412 and 413 and a plurality of adjacent electrode material 418. Recess 4I after deposition of one or more layers of memory material 420 in 409. Memory material 420 is also deposited on dielectric 402 adjacent to selector material 416. In an embodiment, one or more layers of memory material 420 are deposited by an atomic layer deposition process, forming a plurality of Recess Fill 409.

[0086] FIG. 4K shows the lateral direction of the electrode material 418 adjacent to the electrode material 418. Recess 4J shows the structure of FIG. 4J after a process of etching and removing a portion of memory material 420 from portions of 409 and from between two alternating dielectric layers 408. In an embodiment, the portion of memory material 420 is removed by atomic layer etching, a plasma etching process, a wet etching process, or a combination thereof. In an exemplary embodiment, memory material is also removed from the surface of dielectric 402.

[0087] FIG. 4L shows the structure of FIG. 4K after forming electrode material 422 adjacent to memory material 420 between any two alternating dielectric layers 408.

[0088] In embodiments, the process for depositing and removing the portions of the electrode material 422 is the same or substantially the same as the process utilized to deposit and remove the portions of the electrode material 414. In embodiments, the electrode material 422 is deposited between two alternating dielectric layers 408 and adjacent to the memory material 420 in a plurality of layers. Recess A portion of the electrode material 422 is deposited on the dielectric 402 and on the plurality of Recess Portions such as 409 are etched and removed as described above.

[0089] 5A shows the structure of FIG. 4L after the formation of dielectric 500 in openings 412 and 413. In an embodiment, dielectric 500 is deposited in openings 412 and 413 on dielectric 402, adjacent to dielectric 408, electrode material 422. Dielectric 500 may include silicon and one or more of oxygen, nitrogen, or carbon. However, dielectric 500 includes a material that can be selectively etched relative to dielectrics 402, 406, and 408 in subsequent downstream operations.

[0090] 5B is an isometric view of the structure in FIG. 5A through line A-A'. As shown, dielectric 500 is laterally surrounded by electrode material 422. In an exemplary embodiment, electrode material 422 is laterally surrounded by memory material 420, which is laterally surrounded by electrode material 418, which is laterally surrounded by selector material 416, which is laterally surrounded by electrode material 414. In an exemplary embodiment, the formation of two ring structures may allow for the formation of four memory cells.

[0091] 6A is a cross-sectional view of a cut mask implementation for forming individual memory cells. In an exemplary embodiment, a mask 600 is formed over the structure of FIG. 5A. Mask 600 has features such as multiple openings 602, 604. In the exemplary embodiment, openings 602 and 604 are used to remove end caps, and multiple openings 606 are used to form memory cells.

[0092] 6B is a plan view of a portion of a mask over the structure of FIG. 5A. In an exemplary embodiment, openings 602 and 604 are utilized to form isolated memory cells. Electrode material 422, memory material 420, electrode material 418, selector material, and electrode material 414 are outlined via dashed lines to indicate the areas removed by portions of mask 600.

[0093] 7 is an isometric view of the structure in FIG. 5A after a cut-etch process. In an exemplary embodiment, the cut-etch process etches dielectrics 408 and 406, dielectric 500, electrode material 422, memory material 420, electrode material 418, and a portion of selector material 416. In an exemplary embodiment, the etching process forms cell blocks 700A and 700B. A single tier is shown in isometric view.

[0094] The etching also forms a plurality of discrete dielectric blocks, such as dielectric blocks 500A and 500B. The etching process also forms memory cells 700, 702, 704, and 706. The memory cells in the exemplary embodiment are rectangular prism-shaped. As shown, the memory cells have sidewall surfaces that are substantially vertical. In other embodiments, the sidewalls may be tapered. In some embodiments, the cut-etch process forms sidewalls of memory cells 700, 702, 704, and 706 that are substantially coplanar with the sidewalls of dielectric portions 500A and 500B. In other embodiments, the sidewalls of memory cells 700, 702, 704, and 706 are not coplanar with the sidewalls of dielectric portions 500A and 500B.

[0095] As shown, dielectric blocks 500A and 500B are formed between memory cells 700 and 702, and between 704 and 706, respectively. Also as shown, the etching process forms terminals 121, 122, 130, selector element 128, and memory element 126 in each memory cell. In an exemplary embodiment, there are 16 memory cells in each cell block. The desired number of memory cells can be selected by design of mask 600 (not shown).

[0096] It should be understood that after the cut-etch process, the dielectric 406 is separated into two portions: dielectric portion 406A and dielectric portion 406B.

[0097] In other embodiments, the processes described above can be modified to change the composition of memory cells such as memory cell 700.

[0098] 8A is a cross-sectional view of the structure in FIG. 7 through line A-A' after the process of forming electrodes 802 and 804. In the exemplary embodiment, three layers or tiers of vertically arranged memory cells are shown. In other embodiments, the number of tiers can be up to eight.

[0099] In an embodiment, dielectric blocks 500A and 500B are removed. In an embodiment, plasma etching, wet etching, or a combination thereof may be utilized to remove dielectric blocks 500A and 500B and reform openings 412 and 413. In an embodiment, electrode material is deposited on dielectric 402 adjacent terminal 122 of each memory cell and in openings 412 and 413. The electrode material may be polished after deposition to form multi-tier memory array 800.

[0100] 8B shows the structure of FIG. 8A after the formation of conductors 800A, 800B, and 800C, and conductors 804A, 804B, and 804C in three levels of a memory array. In an embodiment, dielectric 406A is removed from the structure of FIG. 8A. In an embodiment, a wet chemical process is utilized to remove dielectric 408 and dielectric 406A adjacent to terminal 122 to form openings between alternating layers of dielectric 408. An electrode material is then deposited, filling the openings formed by the removal of dielectric 406A.

[0101] In an embodiment, dielectric 406B is removed from the structure of FIG. 8A. In an embodiment, a wet chemical process is utilized to remove dielectric 408 and dielectric 406B adjacent to terminal 122 to form openings between alternating layers of dielectric 408. An electrode material is then deposited, filling the openings formed by the removal of dielectric 406B. Dielectric 406B may be removed in parallel with dielectric 406A.

[0102] In embodiments, dielectric portions 406A and 406B may be removed simultaneously and the same electrode material may be utilized to form conductors 800A, 800B, 800C and conductors 804A, 804B, 804C.

[0103] 9 illustrates a method 900 for fabricating the transistor described in connection with FIG. 1A according to an embodiment of the present disclosure. Method 900 begins with operation 910, which includes forming a first electrode structure on a substrate. Method 900 continues with operation 920, which includes forming a material layer stack including a gate electrode material on a first dielectric above the first electrode, and then depositing a second dielectric on the gate electrode material. Method 900 continues with operation 930, which includes forming an opening in the material layer stack to expose the first electrode. Method 900 continues with operation 940, which includes forming a gate dielectric layer in the opening. Method 900 continues with operation 950, which includes forming a channel layer in the opening above the gate dielectric layer. Method 900 continues with operation 960, which includes forming a second dielectric in the opening, the dielectric partially filling the opening. Method 900 concludes with operation 970, which includes forming a second electrode in the opening.

[0104] 10A is a cross-sectional view of an electrode 1000 formed on a substrate 1001. In an embodiment, the electrode material is blanket deposited and patterned on the substrate. A lithography mask may be formed on the electrode material. In an embodiment, a plasma etching process is utilized to etch the electrode material to form the electrode 1000.

[0105] The fabrication process continues with the blanket deposition of dielectric 1002 on electrode 1000. In an embodiment, a chemical mechanical polishing (CMP) process is utilized to planarize dielectric 1002. Dielectric 1002 is then deposited at or above the level of top surface 1000A of electrode 1000, as shown. Recess In an embodiment, a finite thickness of dielectric 1002 above electrode 1000 prevents the gate electrode from shorting to electrode 1000. In an embodiment, substrate 1001 includes materials such as single crystal silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as substrate formations of other semiconductor materials, such as III-V materials. In an exemplary embodiment, substrate 1001 includes silicon and at least one of oxygen, nitrogen, or carbon.

[0106] 10B shows the structure of FIG. 10C after a process of forming a material layer stack 1004 on the dielectric 1002. In an embodiment, the process involves blanket depositing a gate electrode material 1006 on the dielectric 1002. The blanket deposition process may utilize PECVD (plasma-enhanced chemical vapor deposition), physical vapor deposition (PVD), or chemical vapor deposition (CVD) techniques. In an embodiment, the gate electrode material 1006 comprises a material that is the same or substantially the same as the material of the gate electrode 110 described above. In an embodiment, the gate electrode material has a thickness T , which determines the maximum gate length of the pillar transistor that will be formed. G In the embodiment, the film is deposited to a thickness T G is between 30 nm and 200 nm.

[0107] The deposition process continues with the formation of a dielectric 1008 over the gate electrode material 1006. In an embodiment, the dielectric 1008 comprises a material that is the same or substantially the same as the material of the dielectric 1002.

[0108] 10C shows the structure of FIG. 10C after the formation of opening 1009 in material layer stack 1004. In an embodiment, a mask 1011 is formed on dielectric 1008. In an embodiment, mask 1011 comprises a photoresist material. In an embodiment, a plasma etching process is utilized to pattern material layer stack 1004 to form opening 1009. In an embodiment, the plasma etching process forms the opening in dielectric 1008. In an exemplary embodiment, a second etching process using an etchant selective to dielectric 1008 is utilized to continue etching gate electrode material 1006 to form opening 1009. The etching process forms sidewalls 1006A in gate electrode material 1006 that are substantially coplanar with sidewalls 1008A formed in dielectric 1008. The etching process continues until a portion of dielectric 1002 is etched to expose underlying electrode 1000. In some embodiments, a thickness T of dielectric 1002 above electrode 1000 is etched. DEis between 1 nm and 3 nm and is determined during the formation of the material layer stack 1004.

[0109] In an embodiment, the opening 1009 has a lateral thickness W along the length of the gate electrode material 1006. O In an embodiment, once the transistor is formed, W O is determined by the memory cell size being manufactured. O may also be determined by the lateral thickness of the electrode 1000, the minimum thickness of the gate dielectric layer, and the channel layer to be formed.

[0110] 10D shows the structure of FIG. 10C after formation of a gate dielectric layer 1012 in the opening 1009. In an embodiment, the gate dielectric layer 1012 is deposited by an atomic layer deposition process. The ALD process can form a substantially conformal layer of the gate dielectric layer 1012 on the sidewalls 1006A and 1008A. In an exemplary embodiment, the gate dielectric layer 1012 can also be deposited on the electrode 1000 and on the top surface 1008B of the dielectric 1008.

[0111] Figure 10E shows the structure of Figure 10F after a process that etches and removes a portion of the gate dielectric layer 1012 from over the electrode 1000. In an embodiment, a plasma etching process that is anisotropic is utilized to etch and remove the gate dielectric layer 1012 from the electrode surface 1000A and from over the dielectric surface 1008A, but not from the sidewalls 1006A and 1008A.

[0112] 10F shows the structure of FIG. 10E after forming a channel layer 1014 in opening 1009 over electrode 1000 adjacent to gate dielectric layer 1012 on dielectric 1008. In embodiments, a PVD, PECVD, CVD, or ALD process may be utilized to deposit the channel layer. In embodiments, channel layer 1014 is deposited to a thickness of between 5 nm and 20 nm.

[0113] 10G shows the structure of FIG. 10F after formation of dielectric 1016 in opening 1009. In an embodiment, dielectric 1016 comprises a different material than dielectric 1008. In an embodiment, dielectric 1008 comprises one or more of silicon, nitrogen, and oxygen or carbon, and dielectric 1016 comprises silicon and oxygen. In an embodiment, dielectric 1016 is deposited in substantially the same manner as the deposition process utilized to form dielectric 1008. In an embodiment, dielectric 1016 is deposited in opening 1009 on an upper portion of gate dielectric layer 1012 and adjacent to channel layer 1014.

[0114] After the deposition process, the dielectric 1016 is planarized. In an embodiment, the planarization process includes a CMP process.

[0115] FIG. 10H shows the selective deposition of dielectric 1016 relative to dielectric 1008, gate dielectric layer 1012, and channel layer 1014. Recess Machining 10G after the process. In the exemplary embodiment, the dielectric 1016 is Further down By wet etching process Recess In an embodiment, the dielectric 1016 is formed to the level of the top surface 1006B of the gate electrode material 1006. Recess It can be done.

[0116] In an embodiment, both the channel layer 1014 and the gate dielectric layer 1012 are As indicated by dashed line 1017 , top surface 1008B twist under However, Top surface 1006B twist Up to the upper level Recessed In an embodiment, the channel layer 1014 and the gate dielectric layer 1012 are below the top surface 1008B. On the other hand, to the level of the top surface 1016A of the dielectric 1016 Recess (indicated by dashed line 1017) Here, top surface 1016A is above surface 1006B.

[0117] FIG. 10I shows the structure of FIG. 10H after the formation of electrode 1018. In an embodiment, the electrode material is blanket deposited in opening 1009. In an embodiment, the electrode material is blanket deposited using a PVD, CVD, PECVD, or ALD process. In an exemplary embodiment, the electrode material is deposited on the top portion of gate dielectric layer 1012 and on dielectric surface 1008B, adjacent to channel layer 1014, and on dielectric 1016. After deposition, the electrode material may be planarized by a CMP process to form drain structure 1018 and complete the formation of pillar select transistor 1020 as shown.

[0118] In embodiments, the drain structure 1018 is adjacent to the channel layer 1014 and the gate dielectric layer 1012, as shown in Figure 11. In some such embodiments, the drain structure 1018 is approximately the same as the lateral thickness W of the source structure 1000. S a lateral thickness W that is the same as or substantially the same as D It has.

[0119] Although the manufacturing process described in connection with Figures 10A-10I shows how to form a single transistor, an array of transistors can be formed by forming multiple openings, such as opening 1009, in material layer stack 1004 as shown in Figure 10C.

[0120] FIG. 12A is a cross-sectional view of a transistor array 1019 including transistors 1020A and 1020B. Transistors 1020A and 1020B have one or more features of the pillar select transistors 1020 shown in FIG. 10I. In an exemplary embodiment, gate electrode material 1006 is shared between pillar select transistors 1020A and 1020B, a feature of the fabrication process described above. In an embodiment, edge portions of the gate electrode material are etched to form a shared gate electrode 1022 such as that shown. The lateral spacing between the respective electrodes 1000 of each pillar select transistor 1020A and 1020B may depend on the cell spacing, the lateral thickness of each memory cell, and the thickness of the gate electrode in the plane of the figure (e.g., along the z-axis).

[0121] 12B is a cross-sectional view of a multi-tier memory array, such as multi-tier memory array 800, formed over a transistor array 1019 including a pair of transistors 1020A and 1020B according to an embodiment of the present disclosure to form a memory device structure 1200. Memory device structure 1200 may be formed by a combination of the process steps described in connection with FIGS. 4A-8B and 10A-10I. One or more routing structures may be formed adjacent gate electrode 1022 and electrode 1000 to facilitate operation of transistors 1020A and 1020B.

[0122] 13 is a block diagram of an example computing system including a pillar select transistor array coupled to a memory device array to enable decoder transistor footprint scaling. System 1300 represents a computing device according to any example herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device.

[0123] The system 1300 includes a memory array in the memory 1330, which may be a memory array according to the example memory device structure 300 of FIG. 3A. In one example, the pillar select transistors 1390 represent pillar select transistors according to any of the examples provided herein. The pillar select transistors enable the memory 1330 to provide selection of target cells within the memory array. The use of the described pillar select transistors enables selection with less energy usage compared to conventional decoder transistors.

[0124] System 1300 includes a processor 1310. In an embodiment, processor 1310 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or combination, and provide instruction processing or execution for system 1300. Processor 1310 controls the overall operation of system 1300 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0125] In one example, system 1300 includes an interface 1312 coupled to processor 1310 and may represent a high-speed or high-throughput interface for system components requiring a high-bandwidth connection, such as memory subsystem 1320 or graphics interface component 1340. Interface 1312 represents an interface circuit. In an embodiment, interface 1312 may be a standalone component or may be integrated into the processor die. Interface 1312 may be integrated into the processor die as a circuit or may be integrated into a chip as a component. If present, graphics interface 1340 interfaces to a graphics component for providing a visual display to a user of system 1300. Graphics interface 1340 may be a standalone component or may be integrated on the processor die or on a system-on-chip. In one example, graphics interface 1340 can drive a high-definition (HD) display that provides output to a user. In one example, the display may include a touchscreen display. In one example, graphics interface 1340 generates a display based on data stored in memory 1330, or based on operations performed by processor 1310, or both.

[0126] The memory subsystem 1320 represents the main memory of the system 1300 and provides storage for code executed by the processor 1310 or data values ​​used in executing routines. The memory subsystem 1320 can include one or more memory devices 1330, such as one or more of various random access memories (RAMs), such as read-only memory (ROM), flash memory, DRAM, or other memory devices, or a combination of such devices. In some embodiments, the memory subsystem 1320 includes persistent memory (PMem), which can provide higher RAM capacity than traditional DRAM. The 3D crosspoint is an example of persistent memory. The 3D crosspoint is a byte-addressable, write-in-place 3D crosspoint nonvolatile memory device. The PMem can operate in persistent mode, i.e., it can utilize a nonvolatile memory (NVM) device integrated into the selector in a tier architecture to store data without applying power to the memory subsystem 1320 for nonvolatile data storage. The NVM device is memory whose state is deterministic even when power to the device is interrupted.NVM devices may also include single or multi-level phase change memory (PCM) or phase change memory with switches (PCMS), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glasses), resistive memory including metal oxide-based, oxygen vacancy-based, and conductive bridge random access memory (CBRAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM®), magnetoresistive random access memory (MRAM) incorporating memristor technology, spin-transfer torque (STT) MRAM, spintronic magnetic junction memory-based devices, magnetic tunneling junction (MTJ)-based devices, DW (domain wall) and SOT (spin orbit transfer)-based devices, thyristor-based memory devices, or combinations of any of the above or other memories, or other byte-addressable write-in-place NVM devices (also referred to as persistent memory). In other embodiments, memory subsystem 1320 includes a solid-state drive (SSD) containing 3D cross-point memory present in a NAND package for high-speed storage, or a dual in-line memory module (DIMM) in circuitry containing one or more 3D cross-point memory devices.

[0127] Memory 1330 stores and hosts operating system (OS) 1332, providing a software platform for the execution of instructions in system 1300. Furthermore, applications 1334 can execute on the software platform of OS 1332 from memory 1330. Applications 1334 represent programs. Such programs have their own operating logic for performing one or more functions. Processes 1336 represent agents or routines that provide auxiliary functionality to OS 1332 or one or more applications 1334, or a combination. OS 1332, applications 1334, and processes 1336 provide software logic for providing functionality to system 1300. In one example, memory subsystem 1320 includes memory controller 1322, which generates and issues commands to memory 1330. It will be understood that memory controller 1322 can be a physical part of processor 1310 or a physical part of interface 1312. For example, memory controller 1322 may be an integrated memory controller that is integrated on a circuit with processor 1310, for example, on a processor die or system-on-chip.

[0128] Although not specifically shown, it is understood that system 1300 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or the like. A bus or other signal line can communicatively or electrically couple components together, or both communicatively and electrically couple components. A bus can include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuit, or a combination. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other bus, or a combination.

[0129] In one example, system 1300 includes interface 1314, which may be coupled to interface 1312. Interface 1314 may be a lower speed interface than interface 1312. In one example, interface 1314 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface components, peripheral components, or both, couple to interface 1314. Network interface 1350 provides system 1300 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 1350 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a USB (Universal Serial Bus) or other wired or wireless standards-based interface or a proprietary interface. Network interface 1350 may exchange data with remote devices, including transmitting data stored in memory or receiving data stored in memory.

[0130] In one example, system 1300 includes one or more input / output (I / O) interfaces 1360. I / O interface 1360 may include one or more interface components through which a user interacts with system 1300 (e.g., audio, alphanumeric, haptic / touch, or other interface modalities). Peripheral interface 1370 may include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that depend on and connect to system 1300. A dependent connection is one in which system 1300 provides a software or hardware platform, or both, on which operations execute and with which a user interacts.

[0131] In one example, system 1300 includes a storage subsystem 1380 that stores data in a nonvolatile manner. In one example, in a system implementation, at least some components of storage 1380 may overlap with components of memory subsystem 1320. Storage subsystem 1380 includes storage device 1384, which may be or include any conventional medium for storing large amounts of data in a nonvolatile manner, such as one or more magnetic, solid-state, including 3D cross-point memory, or optical-based disks, or a combination. Storage 1384 holds code or instructions and data 1386 in a persistent state (i.e., values ​​are retained even when power to system 1300 is interrupted). Memory 1330 is typically the execution or operating memory that provides instructions to processor 1310, although storage 1384 may collectively be considered "memory." While storage 1384 is nonvolatile, memory 1330 may include volatile memory (i.e., the value or state of the data is indeterminate when power to system 1300 is interrupted). In one example, storage subsystem 1380 includes a controller 1382 that interfaces with storage 1384. In one example, controller 1382 can be a physical part of interface 1314 or processor 1310, or can include circuitry or logic in both processor 1310 and interface 1314.

[0132] The power source 1302 provides power to the components of the system 1300. More specifically, the power source 1302 typically interfaces with one or more power supplies 1304 in the system 1300 to provide power to the components of the system 1300. In one example, the power supply 1304 includes an AC-DC (alternating current-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar-powered) power source 1302. In one example, the power source 1302 includes a DC power source, such as an external AC-DC converter. In one example, the power source 1302 or the power supply 1304 includes wireless charging hardware that charges via proximity to a charging magnetic field. In one example, the power source 1302 can include an internal battery or fuel cell power source.

[0133] 14 is a block diagram of an example system 1400 including a pillar select transistor array coupled to a memory device array to enable decoder transistor footprint scaling. System 1400 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wearable computing device, or other mobile device, or an embedded computing device.

[0134] The system 1400 includes a memory array in the memory 1462, which may be a memory array according to the example memory device structure 300 of FIG. 3A. In one example, the pillar select transistors 1490 represent pillar select transistors according to any of the examples provided herein. The pillar select transistors enable the memory 1462 to provide selection of target cells within the memory array. The use of the described pillar select transistors enables selection with less energy usage compared to conventional decoder transistors.

[0135] System 1400 includes a processor 1410, which performs the primary processing operations of system 1400. Processor 1410 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations performed by processor 1410 include the execution of an operating platform or operating system on which applications and device functions are executed. The processing operations may include operations related to I / O (input / output) with a human user or other device, operations related to power management, operations related to connecting system 1400 to another device, or a combination thereof. The processing operations may also include operations related to audio I / O, display I / O, or other interface methods, or a combination thereof. Processor 1410 may execute data stored in memory. Processor 1410 may write or edit data stored in memory.

[0136] In one example, system 1400 includes one or more sensors 1412. Sensors 1412 represent embedded sensors or interfaces, external sensors, or a combination. Sensors 1412 enable system 1400 to monitor or detect one or more conditions of the environment or device in which system 1400 is implemented. Sensors 1412 may include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors or combinations. Sensors 1412 may also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems that detect or recognize user characteristics. Sensors 1412 should be understood broadly and are not limited to the many different types of sensors that may be implemented with system 1400. In one example, the one or more sensors 1412 couple to the processor 1410 via front-end circuitry integrated into the processor 1410. In one example, the one or more sensors 1412 couple to the processor 1410 via another component of the system 1400.

[0137] In one example, system 1400 includes an audio subsystem 1420 that represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality can include a speaker or headphone output and a microphone input. Devices for such functionality can be integrated into or connected to system 1400. In one example, a user interacts with system 1400 by providing audio commands that are received or processed by processor 1410.

[0138] Display subsystem 1430 represents hardware (e.g., display devices) and software components (e.g., drivers) that provide visual displays for presentation to a user. In one example, the display includes a tactile component or touchscreen element through which a user interacts with the computing device. Display subsystem 1430 includes display interface 1432, which includes the specific screen or hardware device used to provide the display to a user. In one example, display interface 1432 includes logic (e.g., a graphics processor) separate from processor 1410 that performs at least some processing related to the display. In one example, display subsystem 1430 includes a touchscreen device that provides both output and input to a user. In one example, display subsystem 1430 includes a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to a user. In one example, the display subsystem includes or drives a touchscreen display. In one example, display subsystem 1430 generates display information based on data stored in memory, based on operations performed by processor 1410, or both.

[0139] I / O controller 1440 represents hardware devices and software components involved in interaction with a user. I / O controller 1440 can operate to manage hardware that is part of audio subsystem 1420 or display subsystem 1430, or both. Additionally, I / O controller 1440 represents connection points for additional devices that connect to system 1400 through which a user may interact with the system. For example, devices that can be attached to system 1400 can include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with particular applications, such as a card reader or other device.

[0140] As described above, I / O controller 1440 can interact with audio subsystem 1420, display subsystem 1430, or both. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of system 1400. Furthermore, audio output can be provided instead of or in addition to display output. In another example, if the display subsystem includes a touchscreen, the display device can also function as an input device and be managed at least in part by I / O controller 1440. Additionally, additional buttons or switches can be present on system 1400 to provide I / O functions managed by I / O controller 1440.

[0141] In one example, I / O controller 1440 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that may be included in system 1400 or sensors 1412. The inputs may be part of direct user interaction, as well as provide environmental input to the system to affect system operation (such as filtering for noise, adjusting a display for brightness detection, applying a camera flash, or other features).

[0142] In one example, system 1400 includes power management 1450, which manages battery power usage and features related to battery charging and power-saving operation. Power management 1450 manages power from a power source 1452, which provides power to components of system 1400. In one example, power source 1452 includes an AC-DC (alternating current-to-direct current) adapter for plugging into a wall outlet. Such AC power can be renewable energy (e.g., solar power, motion-based power). In one example, power source 1452 includes only DC power, which can be provided by a DC power source such as an external AC-DC converter. In one example, power source 1452 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, power source 1452 can include an internal battery or a fuel cell power source.

[0143] The memory subsystem 1460 includes a memory device 1462 for storing information in the system 1400. The memory subsystem 1460 may include non-volatile (state remains unchanged when power is removed from the memory device) or volatile (state is indeterminate when power is removed from the memory device) memory devices, or a combination thereof. The memory 1460 may store application data, user data, music, photos, documents, or other data and system data (whether long-term or temporary) related to the execution of applications and functions of the system 1400. In one example, the memory subsystem 1460 includes a memory controller 1464 (which may also be considered part of the control of the system 1400 and potentially part of the processor 1410). The memory controller 1464 includes a scheduler that generates and issues commands to control access to the memory device 1462.

[0144] Connections 1470 include hardware devices (e.g., wireless or wired connectors and communications hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to allow system 1400 to communicate with external devices. External devices can be other computing devices, separate devices such as wireless access points or base stations, and peripherals such as headsets, printers, or other devices. In one example, system 1400 exchanges data with external devices for storage in memory or display on a display device. The exchanged data can include data to be stored in memory or data already stored in memory, for reading, writing, or editing data.

[0145] Connection 1470 can include multiple different types of connections. For generalization, system 1400 is depicted with cellular connection 1472 and wireless connection 1474. Cellular connection 1472 generally refers to a cellular network connection provided by a wireless carrier, such as provided via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, LTE (Long Term Evolution, or referred to as "4G"), or other cellular service standards. Wireless connection 1474 refers to a non-cellular wireless connection and may include a personal area network (such as Bluetooth), a local area network (such as WiFi), or a wide area network (such as WiMax), or other wireless communications, or a combination. Wireless communications refers to transferring data through the use of modulated electromagnetic radiation over a non-solid medium. Wired communications occur over a solid communications medium.

[0146] Peripheral connections 1480 include hardware interfaces and connectors as well as software components (e.g., drivers, protocol stacks) that make the peripheral connections. It is understood that system 1400 can be a peripheral device to (1482 “to”) other computing devices, as well as have peripheral devices connected to it (1484 “from”). System 1400 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading, uploading, modifying, synchronizing) content on system 1400. Additionally, the docking connector may enable system 1400 to connect to certain peripherals that, for example, allow system 1400 to control the output of content to audiovisual or other systems.

[0147] In addition to proprietary docking connectors or other proprietary connection hardware, system 1400 can make peripheral connections 1480 via common or standards-based connectors. Common types include Universal Serial Bus (USB) connectors (which can include any of several different hardware interfaces), DisplayPorts, including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), or other types.

[0148] In a first example, a memory device structure includes vertical pillar select transistors coupled to pairs of memory cells through vertical interconnect structures. The transistors include a channel between a source and a drain, the channel being a Vertical The transistor further includes a gate electrode adjacent to the channel, the gate electrode comprising: Vertical The gate electrode and the channel are coupled to a first terminal of the first interconnect, the first terminal of the first interconnect being coupled to the source or the drain, and the first interconnect being coupled to a first terminal of the first interconnect. Vertical The second pair of interconnects are aligned in the first direction and Vertical The memory device structure further includes a pair of memory cells, each of which includes a selector and a memory element, a first terminal of each of the memory cells coupled to a second and third terminal of the first interconnect, and a second terminal of each of the memory cells coupled to a respective one of the pair of second interconnects.

[0149] In a second example, for any of the first examples, further including a second pair of memory cells above the first pair, each of the second pair of memory cells including a selector and a memory element, a first terminal of each of the second pair of memory cells coupled to each of the fourth and fifth terminals of the first interconnect, and a second terminal of each of the second pair of memory cells coupled to each of the pair of third interconnects, the pair of third interconnects being parallel to and above the pair of second interconnects.

[0150] In a third example, for any of the first to second examples, the memory element is coupled to the first terminal and the selector element is coupled to the second terminal.

[0151] In a fourth example, for any of the first to third examples, the memory element is coupled to the second terminal and the selector element is coupled to the third terminal.

[0152] In a fifth example, for any of the first through fourth examples, the transistor channel comprises polycrystalline or amorphous material.

[0153] In a sixth example, for any of the first through fifth examples, the polycrystalline or amorphous material is selected from the group consisting of In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, ZnRh2O4, and CuO x and X is 1 or 2.

[0154] In a seventh example, for any of the first to sixth examples, the channel surrounds the core including the dielectric material in the first and second directions, the gate dielectric layer surrounds the channel layer in the first and second directions, and the gate electrode surrounds the gate dielectric layer in the first and second directions.

[0155] In an eighth example, for any of the first to seventh examples, the drain structure is above the source structure, and the gate electrode is substantially equidistant between the bottom surface of the drain structure and the top surface of the source electrode.

[0156] In a ninth example, for any of the first to eighth examples, the gate electrode is at least 1 nm above the top surface of the source electrode.

[0157] In a tenth example, for any of the first to eighth examples, the transistor is an array of transistors along the first direction, and each gate electrode of the transistors in the array of transistors is electrically coupled in parallel.

[0158] In an eleventh example, for any of the first to tenth examples, each of the memory cells has a first lateral thickness along the first direction, the first lateral thickness being between 100 nm and 120 nm.

[0159] In a twelfth example, for any of the first to eleventh examples, the source or drain has a second lateral thickness along the first direction, the second lateral thickness being less than twice the first lateral thickness.

[0160] In a thirteenth example, for any of the first to twelfth examples, the first interconnect has a second lateral thickness along the first direction, the second lateral thickness being between 50 nm and 70 nm, and each of the pair of second interconnects has a third lateral thickness, the third lateral thickness being between 35 nm and 50 nm.

[0161] In a fourteenth example, a method for fabricating a vertical transistor includes forming a first electrode structure on a substrate. The method further includes forming a material layer stack on the first electrode material layer, where forming the material layer stack includes depositing a gate electrode material on a first dielectric over the first electrode and depositing a second dielectric over the gate electrode material. The method further includes forming an opening in the material layer stack to expose the first electrode and forming a gate dielectric layer in the opening adjacent to the gate electrode material. The method further includes forming a channel layer in the opening on the gate dielectric layer and forming a second dielectric in the opening, where the dielectric partially fills the opening and forms a second electrode in the opening.

[0162] In a fifteenth example, for any of the fourteenth to fourteenth examples, the step of forming the first electrode includes the steps of patterning a first electrode material on a substrate, forming a dielectric material on the first electrode, and planarizing the dielectric material.

[0163] In a sixteenth example, for any of the fourteenth to fifteenth examples, forming the opening includes etching the second dielectric and etching the gate electrode material to form the opening.

[0164] In a seventeenth example, for any of the fourteenth to sixteenth examples, forming the gate dielectric layer includes depositing a gate dielectric layer material in the opening and on the first electrode, and etching the gate dielectric layer in contact with the first electrode to expose the first electrode.

[0165] In an eighteenth example, for any of the fourteenth to seventeenth examples, forming the second dielectric includes blanket depositing the second dielectric to fill the opening, and depositing the second dielectric to the level of the top surface of the gate electrode material. Recess Machining and

[0166] In a nineteenth example, a system includes a power supply and a memory device structure. The memory device structure includes vertical pillar select transistors coupled to pairs of memory cells through vertical interconnect structures. The transistors include channels between a source and a drain, the channels being connected to the transistors. Vertical The transistor further includes a gate electrode adjacent to the channel, the gate electrode comprising: Vertical The gate electrode and the channel are coupled to a first terminal of the first interconnect, the first terminal of the first interconnect being coupled to the source or the drain, and the first interconnect being coupled to a first terminal of the first interconnect. Vertical The second pair of interconnects are aligned in the first direction and Vertical The memory device structure further includes a pair of memory cells, each of which includes a selector and a memory element, a first terminal of each of the memory cells coupled to a second and third terminal of the first interconnect, and a second terminal of each of the memory cells coupled to a respective one of the pair of second interconnects.

[0167] In a twentieth example, for any of the nineteenth examples, the system further includes a battery and an antenna coupled to the memory device structure. [Other possible items] (Item 1) 1. A memory device structure comprising: A transistor, A channel between the source and drain of the transistor Vertical a channel along a direction axis; the above Vertical a gate electrode along a first direction perpendicular to the direction axis; a gate dielectric layer between the gate electrode and the channel; a transistor including a first interconnect coupled to the source or the drain, the first interconnect being collinear with the channel; the above Vertical a pair of second interconnects along a second direction orthogonal to both the direction axis and the first direction; a pair of memory cells, each of which includes a selector element and a memory element, the first terminals of the respective pairs of memory cells being coupled to the first interconnect, and the second terminals of the respective pairs of memory cells being coupled to the respective pairs of second interconnects; A memory device structure comprising: (Item 2) the pair of memory cells is a first pair of memory cells in a first tier; the memory device structure further includes a second pair of memory cells above the first pair of memory cells in a second tier; each of the second pair of memory cells includes a selector and a memory element; the respective first terminals of the second pair of memory cells are coupled to a portion of the first interconnect in the second tier; the respective second terminals of the second pair of memory cells are coupled to respective ones of a pair of third interconnects, the pair of third interconnects being parallel to and above the pair of second interconnects; Item 1. The memory device structure of item 1. (Item 3) the memory elements and the selector elements in the first pair of memory cells and the second pair of memory cells are connected in series; 3. The memory device structure of claim 2, wherein either the individual memory elements or the selector elements of the first pair of memory cells and the second pair of memory cells are each coupled to the first interconnect. (Item 4) Item 10. The memory device structure of item 1, wherein the channel comprises polycrystalline or amorphous material. (Item 5) The polycrystalline or amorphous material may be In2O3, Ga2O3, ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu2O, AgAlO, CuAlO3, AlScOC, Sr3BPO3, La2SiO4Se, LaCuSe, Rb2Sn2O3, La2O2S2, K2Sn2O3, Na2FeOSe2, ZnRh2O4 or CuO x Item 5. The memory device structure of item 4, comprising: (Item 6) Item 10. The memory device structure of item 1, wherein the channel surrounds a core comprising a dielectric material, the gate dielectric layer surrounds the channel, and the gate electrode surrounds the gate dielectric layer. (Item 7) 7. The memory device structure of claim 6, wherein the drain is above the source and the core, the drain is between a portion of the channel adjacent to the gate dielectric layer, and the source is adjacent to the gate dielectric layer and a portion of the channel that extends along the first direction. (Item 8) Item 8. The memory device structure of item 7, wherein the drain and the core each have substantially the same lateral thickness along the first direction. (Item 9) 7. The memory device structure of claim 6, wherein the drain is above the source, the core is directly between the source and the drain, and the source and the drain each have substantially the same lateral thickness along the first direction. (Item 10) 2. The memory device structure of claim 1, wherein the transistors are an array of transistors along the first direction, and the gate electrodes of the individual transistors in the array of transistors are electrically coupled in parallel. (Item 11) 3. The memory device structure of claim 2, wherein the source or the drain has a first lateral thickness along the first direction, and each of the memory cells in the first pair of memory cells and the second pair of memory cells has a second lateral thickness along the first direction, and the first lateral thickness is less than twice the second lateral thickness. (Item 12) 2. The memory device structure of claim 1, wherein the first interconnect has a first lateral thickness along the first direction, the first lateral thickness being between 50 nm and 70 nm, and each of the pair of second interconnects has a second lateral thickness, the second lateral thickness being between 35 nm and 50 nm. (Item 13) 3. The memory device structure of claim 2, wherein the first interconnect has a first lateral thickness along the first direction, and each of the memory cells in the first pair of memory cells and the second pair of memory cells has a second lateral thickness along the first direction, and the first lateral thickness is less than the second lateral thickness. (Item 14) 1. A method of fabricating a vertical transistor, comprising: forming a first electrode structure on a substrate; forming a material layer stack on the first electrode structure, the forming of the structure including depositing a gate electrode material on a first dielectric over the first electrode and depositing a second dielectric over the gate electrode material; forming an opening in the material layer stack to expose the first electrode; forming a gate dielectric layer in the opening adjacent the gate electrode material; forming a channel layer in the opening adjacent to the gate dielectric layer; forming a second dielectric in the opening adjacent the channel layer, the dielectric partially filling the opening; forming a second electrode in the opening; A method for providing (Item 15) Item 15. The method of item 14, wherein forming the first electrode comprises patterning a first electrode material on a substrate, forming a dielectric material on the first electrode, and planarizing the dielectric material to hide the first electrode. (Item 16) Item 15. The method of item 14, wherein forming the opening comprises etching the second dielectric and etching the gate electrode material to form an opening. (Item 17) The step of forming the gate dielectric layer comprises: depositing a gate dielectric layer material in the opening and over the first electrode; etching the gate dielectric layer in contact with the first electrode to expose the first electrode; Item 15. The method according to item 14, comprising: (Item 18) The forming of the second dielectric includes blanket depositing the second dielectric to fill the opening and to a level that is substantially flush with the top surface of the gate electrode material. Recess Machining Item 15. The method according to item 14, comprising the step of: (Item 19) 1. A system comprising: a battery for powering the system; 1. A memory device structure comprising: A transistor, A channel between the source and drain of the transistor Vertical a channel along a direction axis; the above Vertical a gate electrode along a first direction perpendicular to the direction axis; a gate dielectric layer between the gate electrode and the channel; a transistor including a first interconnect coupled to the source or the drain, the first interconnect being collinear with the channel; the above Vertical a pair of second interconnects along a second direction orthogonal to both the direction axis and the first direction; a pair of memory cells, each of which includes a selector element and a memory element, the first terminals of the respective pairs of memory cells being coupled to the first interconnect, and the second terminals of the respective pairs of memory cells being coupled to the respective pairs of second interconnects; a memory device structure including: A system comprising: (Item 20) 20. The system of claim 19, further comprising a memory controller coupled to the memory device structure.

Claims

1. 1. A memory device structure comprising: A transistor, a channel along a vertical axis of the transistor between a source and a drain, the channel including vertical portions on opposing sidewalls of one of the source or the drain and a horizontal portion on the other of the source or the drain; a gate electrode along a first direction perpendicular to the vertical axis; a gate dielectric layer between the gate electrode and the channel; a transistor including: a first interconnect coupled to the one of the source or the drain, the first interconnect being collinear with the channel; a pair of second interconnects along a second direction orthogonal to both the vertical axis and the first direction; a pair of memory cells, each of the pair of memory cells including a selector element and a memory element, a first terminal of the each of the pair of memory cells coupled to the first interconnect, and a second terminal of the each of the pair of memory cells coupled to a second interconnect of the pair of second interconnects; A memory device structure comprising:

2. The memory device structure of claim 1, further comprising a pair of dielectric layers in contact with the first interconnect, wherein a first dielectric layer of the pair of dielectric layers is below the second interconnect and the memory cell, and a second dielectric layer of the pair of dielectric layers is above the second interconnect and the memory cell.

3. the pair of memory cells is a first pair of memory cells in a first tier; the memory device structure further includes a second pair of memory cells in a second tier above the first pair of memory cells; each memory cell of the second pair of memory cells includes a selector element and a memory element; a first terminal of the individual memory cell of the second pair of memory cells is coupled to a portion of the first interconnect in the second tier; a second terminal of each memory cell of the second pair of memory cells is coupled to a respective third interconnect of a pair of third interconnects, the pair of third interconnects being parallel to and above the pair of second interconnects; The memory device structure of claim 1 .

4. the memory elements and the selector elements in the first pair of memory cells and the second pair of memory cells are connected in series; 4. The memory device structure of claim 3, wherein either the memory element or the selector element of the individual memory cell of the first pair of memory cells and the individual memory cell of the second pair of memory cells are respectively coupled to the first interconnect.

5. The memory device structure of claim 1 , wherein the channel comprises a polycrystalline or amorphous material.

6. The polycrystalline or amorphous material may be In ２ O ３ , Ga ２ O ３ , ZnO, InGaZnO, InZnO, InGaO, GaZnO, InAlO, InSnO, InMgO, GaZnMgO, GaZnSnO, GaAlZnO, GaAlSnO, HfZnO, HfInZnO, HfAlGaZnO, InMgZnO, NbO, NiO, CoO, SnO, Cu ２ O, AgAlO, CuAlO ３ , AlScOC, Sr ３ BPO ３ , La ２ SiO ４ Se, LaCuSe, Rb ２ Sn ２ O ３ , La ２ O ２ S ２ , K. ２ Sn ２ O ３ , Na ２ FeOSe ２ , ZnRh ２ O ４ or CuO ｘ 6. The memory device structure of claim 5, comprising:

7. 7. The memory device structure of claim 1, wherein the channel surrounds a core comprising a dielectric material, the gate dielectric layer surrounds the channel, and the gate electrode surrounds the gate dielectric layer.

8. 8. The memory device structure of claim 7, wherein the drain overlies the source and the core, the drain between a portion of the channel adjacent to the gate dielectric layer, and the source adjacent to the gate dielectric layer and a portion of the channel extending along the first direction.

9. The memory device structure of claim 8 , wherein the drain and the core each have substantially the same lateral thickness along the first direction.

10. 10. The memory device structure of claim 7, wherein the drain is above the source, the core is directly between the source and the drain, and the source and the drain each have substantially the same lateral thickness along the first direction.

11. 11. The memory device structure of claim 3, wherein the source or the drain has a first lateral thickness along the first direction, and the individual memory cells in the first pair of memory cells and the second pair of memory cells each have a second lateral thickness along the first direction, and the first lateral thickness is less than twice the second lateral thickness.

12. 11. The memory device structure of claim 3, wherein the first interconnect has a first lateral thickness along the first direction, and the individual memory cells in the first pair of memory cells and the second pair of memory cells each have a second lateral thickness along the first direction, the first lateral thickness being less than the second lateral thickness.

13. 13. The memory device structure of claim 1, wherein the transistors are in an array of transistors along the first direction, and the gate electrodes of individual transistors in the array of transistors are electrically coupled in parallel.

14. 13. The memory device structure of claim 1, wherein the first interconnect has a first lateral thickness along the first direction, the first lateral thickness being between 50 nm and 70 nm, and each second interconnect of the pair of second interconnects has a second lateral thickness, the second lateral thickness being between 35 nm and 50 nm.

15. 1. A method of fabricating a vertical transistor, comprising: forming a first electrode on a substrate; forming a material layer stack over the first electrode, wherein forming the material layer stack includes depositing a gate electrode material on a first dielectric above the first electrode and depositing a second dielectric on the gate electrode material; forming an opening in the material layer stack to expose the first electrode; forming a gate dielectric layer in the opening adjacent to the gate electrode material; forming a channel layer in the opening, the channel layer including a horizontal portion adjacent the gate dielectric layer and overlying the first electrode; forming a third dielectric in the opening adjacent to the channel layer, the third dielectric partially filling the opening; forming the second electrode in the opening such that the channel layer further includes vertical portions located on opposing sidewalls of the second electrode; A method for providing the above.

16. 16. The method of claim 15, wherein forming the first electrode comprises patterning a first electrode material on the substrate, forming a dielectric material over the first electrode, and planarizing the dielectric material to hide the first electrode.

17. 17. The method of claim 15 or 16, wherein forming the opening comprises etching the second dielectric and etching the gate electrode material to form an opening.

18. The step of forming the gate dielectric layer comprises: depositing a gate dielectric layer material in the opening and over the first electrode; etching the gate dielectric layer in contact with the first electrode to expose the first electrode; 18. The method of any one of claims 15 to 17, comprising:

19. 19. The method of any one of claims 15 to 18, wherein forming the third dielectric comprises blanket depositing the third dielectric to fill the opening and recessing the third dielectric to a level that is substantially coplanar with an upper surface of the gate electrode material.

20. 1. A system comprising: A battery, a memory device structure, the memory device structure comprising: A transistor, a channel along a vertical axis of the transistor between a source and a drain, the channel including a vertical portion and a horizontal portion, one of the source or the drain being between the vertical portions and the other of the source or the drain being on the horizontal portion; a gate electrode along a first direction perpendicular to the vertical axis; a gate dielectric layer between the gate electrode and the channel; a transistor including: a first interconnect coupled to the one of the source or the drain, the first interconnect being collinear with the channel; a pair of second interconnects along a second direction orthogonal to both the vertical axis and the first direction; a pair of memory cells, each of the pair of memory cells including a selector element and a memory element, a first terminal of the each of the pair of memory cells coupled to the first interconnect, and a second terminal of the each of the pair of memory cells coupled to a second interconnect of the pair of second interconnects; Including, the system.

21. 21. The system of claim 20, further comprising a memory controller coupled to the memory device structure.

22. A transistor comprising: a channel along the vertical axis of the transistor between the source and drain; a gate electrode along a first direction perpendicular to the vertical axis; a transistor including a gate dielectric layer between the gate electrode and the channel; a first interconnect coupled to the source or the drain, the first interconnect being collinear with the channel; a pair of second interconnects along a second direction orthogonal to both the vertical axis and the first direction; a pair of memory cells, each memory cell of the pair of memory cells including a selector element and a memory element, a first terminal of the each memory cell of the pair of memory cells coupled to the first interconnect, and a second terminal of the each memory cell of the pair of memory cells coupled to a respective second interconnect of the pair of second interconnects; a pair of dielectric layers in contact with the first interconnect, a first dielectric layer of the pair of dielectric layers below the second interconnect and the memory cell, and a second dielectric layer of the pair of dielectric layers above the second interconnect and the memory cell; An apparatus comprising:

23. The pair of memory cells is a first pair of memory cells in a first tier, and the device further comprises: a second pair of memory cells in a second tier above the first pair of memory cells; the second dielectric layer of the pair of dielectric layers is between the first pair of memory cells and the second pair of memory cells, a third dielectric layer is over the second pair of memory cells, each memory cell of the second pair of memory cells includes a selector element and a memory element, and a first terminal of each memory cell of the second pair of memory cells is coupled to a portion of the first interconnect in the second tier; 23. The device of claim 22, wherein second terminals of the individual memory cells of the second pair of memory cells are coupled to individual third interconnects of a pair of third interconnects, the pair of third interconnects being parallel to and above the pair of second interconnects.

24. The memory elements and the selector elements in the first pair of memory cells and the second pair of memory cells are connected in series; 24. The apparatus of claim 23, wherein either the memory element or the selector element of the individual memory cell of the first pair of memory cells and the individual memory cell of the second pair of memory cells are respectively coupled to the first interconnect.

25. The device described in claim 24, wherein each of the memory cells includes an electrode between the corresponding memory element and the selector element, the electrode coupling the corresponding memory element and the selector element.

26. The device described in claim 25, wherein the channel includes a first portion and a second portion, the first portion contacting opposing sidewalls of one of the source or the drain, and the second portion contacting the other of the source or the drain.

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