Thick gate oxide device selection for nanosheet devices

Abstract

The apparatus includes a substrate, a thin-gate oxide nanosheet device disposed on the substrate and having a first plurality of nanosheet layers, each of the first plurality of nanosheet layers having a first thickness located at a center of the nanosheet, and a thick-gate oxide nanosheet device disposed on the substrate and having a second plurality of nanosheet layers, each of the second plurality of nanosheet layers having a second thickness, the first thickness being less than the second thickness.

Description

[Technical Field]

[0001] The present invention relates generally to the field of nanosheets, and more particularly to the simultaneous formation of thick-gate and thin-gate oxide nanosheet devices on the same substrate. [Background technology]

[0002] Gate-all-around devices such as nanosheet field-effect transistors (FETs) are becoming an increasingly important technology, and research and development is focused on forming standalone gate-all-around nanosheet devices. Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0004] The apparatus includes a substrate, a thin-gate oxide nanosheet device disposed on the substrate and having a first plurality of nanosheet layers, each of the first plurality of nanosheet layers having a first thickness located at a center of the nanosheet, and a thick-gate oxide nanosheet device disposed on the substrate and having a second plurality of nanosheet layers, each of the second plurality of nanosheet layers having a second thickness, the first thickness being less than the second thickness.

[0005] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0006] [Figure 1A] FIG. 1 is a diagram of a thin-gate oxide nanosheet device according to an embodiment of the present invention. [Figure 1B]FIG. 1 is a diagram of a thick-gate oxide device formed on the same substrate as a thin-gate oxide nanosheet device, according to an embodiment of the present invention. [Figure 2A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 2B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 2C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 3A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 3B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 3C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 4A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 4B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 4C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 5A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 5B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 5C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 6A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 6B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 6C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 7A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 7B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 7C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 8A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 8B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 8C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 9A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 9B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 9C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 10A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 10B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 10C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 11A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 11B]1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 11C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 12A] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 12B] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. [Figure 12C] 1A-1C are different cross-sectional views of devices on the same substrate during different stages of fabrication according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following description of the accompanying drawings is provided to aid in a comprehensive understanding of exemplary embodiments of the invention as defined by the claims and their equivalents. The following description includes numerous specific details to aid in understanding, but these should be considered merely as examples. Therefore, those skilled in the art will understand that various changes and modifications to the embodiments described herein can be made without departing from the scope of the present invention. In addition, descriptions of well-known functions and configurations may be omitted for clarity and conciseness.

[0008] The terms and words used in the following description and claims are not limited to their bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present invention. Therefore, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only, and not for limiting the present invention, as defined by the appended claims and their equivalents.

[0009] The singular forms "a," "an," and "the" are understood to include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "one component surface" includes a reference to one or more of such surfaces unless the context clearly dictates otherwise.

[0010] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present embodiments.

[0011] References in the specification to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but all embodiments may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is said to be within the knowledge of one of ordinary skill in the art or to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0012] For purposes of the remainder of this specification, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, will refer to the disclosed structures and methods as oriented in the depicted figures. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0013] In order to avoid obscuring the description of the embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for representational and illustrative purposes, and in some instances may not be described in detail. In other instances, some processing steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on the unique features or elements of various embodiments of the present invention.

[0014] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternate embodiments may be devised without departing from the scope of the present invention. It should be noted that various connections and positional relationships (e.g., above, below, adjacent to, etc.) are described between elements in the following description and in the drawings. These connections and / or positional relationships may be direct or indirect unless expressly stated otherwise, and the present invention is not intended to be limited in this respect. Thus, joining entities can be referred to as either a direct or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, reference in this description to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B," so long as the relevant properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0015] The following definitions and abbreviations should be used for interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover non-exclusive inclusions. For example, a composition, mixture, process, method, article, or device comprising a list of elements need not be limited to only those elements, but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or device.

[0016] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "a plurality" may be understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connection" may include both an indirect and a direct connection.

[0017] As used herein, the term "about" modifying the amount of a raw material, component, or reactant of the present invention used refers to variations in numerical quantities that may occur through typical measuring and liquid handling procedures used, for example, to make concentrates or solutions. Furthermore, variations may arise from inadvertent errors in measuring procedures, manufacturing differences, sources, or purity of raw materials utilized to make compositions or carry out methods, etc. The terms "about" or "substantially" are intended to include the degree of error associated with measuring a particular quantity based on equipment available at the time of filing the application. For example, about can include a range of ±8%, or 5%, or 2% of a given value. In another embodiment, the term "about" means within 5% of the reported numerical value. In another embodiment, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0018] Various processes, falling into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography, are used to form microchips that are packaged into integrated circuits (ICs). Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from a wafer. Examples include etching processes (either wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, typically by diffusion and / or ion implantation. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate electrical components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be altered with the application of a voltage.

[0019] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The present invention is directed to the simultaneous formation of a thin-gate oxide nanosheet device and a thick-gate oxide device on the same substrate. The thin-gate oxide nanosheet device is formed by thinning specific layers of nanosheets during fabrication. Furthermore, the thickness of the thick-gate oxide device is maintained during the thinning process (e.g., the nanosheet layer thickness does not change).

[0020] 1A illustrates a thin-gate oxide nanosheet device 100 according to an embodiment of the present invention. FIG. 1B illustrates a thick-gate oxide device 102 formed on the same substrate as the thin-gate oxide nanosheet device 100 according to an embodiment of the present invention. Figures with "A" in the figure number illustrate a cross-section of the thin-gate oxide nanosheet device 100. Figures with "B" or "C" in the figure number illustrate a cross-section of the thick-gate oxide device 102.

[0021] 2A, 2B, and 2C each illustrate different cross sections of a device on the same substrate during various stages of fabrication, according to an embodiment of the present invention. Multiple layers are formed on the substrate 105 to create the nanosheet stack. The substrate 105 may be, for example, a silicon wafer, a sapphire wafer, a metallic layer, a dielectric layer, an insulator layer, or any type of layer suitable for forming the thin-gate oxide nanosheet device 100 and the thick-gate oxide device 102. Both devices are formed on the same substrate 105. FIG. 2A represents cross section A as identified in FIG. 1A, FIG. 2B represents cross section B as identified in FIG. 1B, and FIG. 2C represents cross section C as identified in FIG. 1B. While the nanosheet stack is composed of multiple alternating layers, the number of alternating layers described herein is for illustrative purposes only. The nanosheet stack may have more or fewer alternating layers than those shown. First layers 110A, 110B, and 110C are formed on substrate 105. First layers 110A, 110B, and 110C are sacrificial layers that may be, for example, SiGe 30 and have a thickness in the range of approximately 3 to 8 nm. Second layers 112A, 112B, and 112C are formed on first layers 110A, 110B, and 110C. Second layers 112A, 112B, and 112C may be, for example, epitaxially grown layers of Si or another suitable material and have a thickness in the range of approximately 10 to 15 nm. Third layers 114A, 114B, and 114C are formed on second layers 112A, 112B, and 112C. Third layers 114A, 114B, and 114C are sacrificial layers that may be, for example, SiGe 30 and have a thickness in the range of approximately 3 to 8 nm. Fourth layers 116A, 116B, 116C may be formed on the third layers 114A, 114B, 114C. The fourth layers 116A, 116B, 116C may be, for example, epitaxially grown layers of Si or another suitable material and have a thickness in the range of approximately 10 to 15 nm. Fifth layers 118A, 118B, 118C may be formed on the fourth layers 116A, 116B, 116C. The fifth layers 118A, 118B, 118C may be, for example, sacrificial layers of SiGe30 and have a thickness in the range of approximately 3 to 8 nm.Sixth layers 120A, 120B, and 120C are formed on fifth layers 118A, 118B, and 118C. Sixth layers 120A, 120B, and 120C may be, for example, epitaxially grown layers of Si or another suitable material and have a thickness in the range of approximately 10 to 15 nm. Seventh layers 122A, 122B, and 122C are formed on sixth layers 120A, 120B, and 120C. Seventh layers 122A, 122B, and 122C are sacrificial layers that may be, for example, SiGe30 and have a thickness in the range of approximately 3 to 8 nm.

[0022] 3A, 3B, and 3C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention.

[0023] The layers of FIGS. 3A and 3B are not processed at this stage. The layer of FIG. 3C is etched to form at least one fin. FIG. 3C illustrates the formation of two fins for illustrative purposes only. A single fin or multiple fins may be formed based on the design for the final product. During the device fin etch, the substrate 105 is etched to form trenches in the substrate 105. The trenches are filled with trench filler 124C. The trench filler 124C may be composed of a shallow trench isolation material. The trench filler 124C fills the formed trench in the substrate 105 and extends to the bottom of the first layer 110C. The trench filler 124C may be formed by depositing a thin SiN layer, followed by a SiO2 bulk fill, followed by CMP and recessing.

[0024] 4A, 4B, and 4C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention.

[0025] FIG. 4A illustrates the initial formation of the thin-gate oxide nanosheet device 100. A dummy gate 126A is formed on the seventh layer 122A. A hard mask 128A is formed on the dummy gate 126A, and the device is etched to form at least one pillar. While FIG. 4A illustrates the formation of three pillars, fewer or more pillars may be formed for the thin-gate oxide nanosheet device 100. Spacers 130A are formed on the sides of the dummy gate 126A and the hard mask 128A, and the spacers 130A are formed on the seventh layer 122A. The spacers 130A may be selected from the group consisting of SiBCN, SiOCN, SiN, or similar materials. FIG. 4B illustrates the formation of a portion of the thick-gate oxide device 102. A dummy gate 126B is formed on the seventh layer 122B, and a hard mask 128B is formed on the dummy gate 126B. The layer is etched to form pillars of a desired width, as illustrated by FIG. 4B. Spacers 130B are formed on the sides of the dummy gate 126B and the sides of the hard mask 128B. The spacers 130B are formed on the seventh layer 122B. The spacers 130B may be selected from the group consisting of SiBCN, SiOCN, SiN, or similar materials. FIG. 4C illustrates fins surrounded by dummy gates 126C. The dummy gates 126C are formed on the trench filler 124C, on the seventh layer 122C, and along the sidewalls of each of the fins to surround each of the fins, as illustrated by FIG. 4C. A hard mask 128C is formed on the dummy gates 126C. The dummy gates 126A, 126B, 126C may consist of a thin SiO liner followed by a bulk material such as amorphous Si. As illustrated by Figure 4A, the thin-gate oxide nanosheet device 100 is a short-channel device with a short gate length. As illustrated by Figures 4B and 4C, the thick-gate oxide device 102 is a long-channel device with a long gate length.

[0026] 5A, 5B, and 5C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. The first layer 110A, the third layer 114A, the fifth layer 118A, and the seventh layer 122A are etched / recessed to form an open cavity. The open cavity is filled with second spacers 134A (inner spacers), followed by an isotropic etch-back of the spacer liners, resulting in second spacers 134A on the sides of the first layer 110A, the third layer 114A, the fifth layer 118A, and the seventh layer 122A. An epilayer 132A is formed between each pillar, as illustrated by FIG. 5A. The epilayer 132 may be, for example, epitaxially grown heavily doped Si or SiGe. As illustrated by FIG. 5B, epi layer 132B is formed over exposed substrate 105 and over exposed sidewalls of second layer 112B, fourth layer 116B, and sixth layer 120B.

[0027] 6A, 6B, and 6C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. As illustrated by FIG. 6A, a dielectric layer 136A is formed on epi layer 132A. Portions of hard mask 128A and spacers 130A are planarized to expose dummy gate 126A. As illustrated by FIG. 6B, a dielectric layer 136B is formed on epi layer 132B. The top surface is planarized to remove hard mask 128B and expose dummy gate 126B. As illustrated by FIG. 6C, the top surface is planarized to remove hard mask 128C and expose dummy gate 126C.

[0028] 7A, 7B, and 7C each illustrate different cross sections of a device on the same substrate during a fabrication stage in accordance with an embodiment of the present invention, illustrating the removal of dummy gates 126A, 126B, and 126C, as well as first layers 110A, 110B, and 110C, third layers 114A, 114B, and 114C, fifth layers 118A, 118B, and 118C, and seventh layers 122A, 122B, and 122C.

[0029] Figures 8A, 8B, and 8C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. Figures 8A, 8B, and 8C illustrate a patterning process in which a lithography mask is used to expose the thin-gate oxide nanosheet device 100 for a Si thinning process. Figure 8C illustrates an OPL 138C formed on the exposed surfaces of the substrate 105 and trench filler 124C. The OPL 138C surrounds each of the second layer 112C, fourth layer 116C, and sixth layer 120C. Figure 8B illustrates that the OPL 138B is formed in the gap resulting from the removal of the first layer 110B, third layer 114B, fifth layer 118B, and seventh layer 122B. The OPL 138B is formed on the spacer 130B and dielectric layer 136B. The OPLs 138B and 138C protect the second layers 112B, 112C, the fourth layers 116B, 116C, and the sixth layers 120B, 120C from being damaged / thinned during thinning of the second layer 112A, the fourth layer 116A, and the sixth layer 120A. FIG. 8A illustrates the results of isotropic etching / thinning of the second layer 112A, the fourth layer 116A, and the sixth layer 120A. Trimming the layers reduces the thickness of the second layer 112A, the fourth layer 116A, and the sixth layer 120A near the center of each layer. The second spacer 134A causes the edges of the second layer 112A, the fourth layer 116A, and the sixth layer 120A to trim at a slower rate than the center of the layers. The trimming exposes portions of the top and bottom surfaces of the second spacer 134A. The central portions of the second layer 112A, fourth layer 116A, and sixth layer 120A have a thickness of d1. Thus, the trimming process causes the second layer 112A, fourth layer 116A, and sixth layer 120A to have thicknesses that vary across the horizontal axis of the layers. The second layer 112A, fourth layer 116A, and sixth layer 120A have thicker portions toward the ends of the horizontal axis of the layers and thinner portions toward the center. Trimming the layers increases the spacing (d2) between the central portions of the second layer 112A, fourth layer 116A, and sixth layer 120A. The thickness d1 is less than the distance d2.The second layers 112B, 112C, the fourth layers 116B, 116C, and the sixth layers 120B, 120C have a thickness d3. The second layers 112B, 112C, the fourth layers 116B, 116C, and the sixth layers 120B, 120C have a constant thickness d3 throughout the horizontal portions of the layers. Thickness d3 is greater than thickness d1.

[0030] 9A, 9B, and 9C respectively illustrate different cross sections of a device on the same substrate during stages of fabrication in accordance with an embodiment of the present invention, illustrating the removal of OPLs 138B, 138C from the surface of the device.

[0031] 10A, 10B, and 10C each illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. FIG. 10C illustrates an oxide layer 140C formed on the substrate 105 and on the trench filler 124C. The oxide layer 140C surrounds the second layer 112C, the fourth layer 116C, and the sixth layer 120C. The oxide layer 140C pinches off (i.e., fills) the spaces between the substrate 105, the second layer 112C, the fourth layer 116C, and the sixth layer 120C. FIG. 10B illustrates the oxide layer 140B filling the spaces between the substrate 105, the second layer 112B, the fourth layer 116B, and the sixth layer 120B. Furthermore, oxide layer 140B is formed on the exposed surfaces of dielectric layer 136B, spacer 130B, second spacer 134B, and sixth layer 120B. Figure 10A illustrates oxide layer 140A formed on the exposed surfaces of substrate 105, second layer 112B, fourth layer 116B, sixth layer 120B, and second spacer 134A. Oxide layer 140A does not fill / truncate the spaces between substrate 105, second layer 112A, fourth layer 116A, and sixth layer 120A. An oxide layer 140A is formed on the exposed surface of the second spacer 134A such that a portion of the oxide layer 140A is sandwiched between the second spacer 134A and another surface of the substrate 105, the second layer 112A, the fourth layer 116A, or the sixth layer 120A. The oxide layer 140A is formed on the dielectric layer 136A, the spacer 130A, the exposed surface of the second spacer 134A, and the sixth layer 120A.

[0032] 11A, 11B, and 11C illustrate different cross sections of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. FIGS. 11A, 11B, and 11C show a patterning process in which the thin-film gate oxide nanosheet device 100 region is re-exposed by utilizing an isotropic oxide etch-back process. As illustrated by FIG. 11C, an OPL layer 142C is formed on the exposed surface of oxide layer 140C. As illustrated by FIG. 11B, an OPL layer 142B is formed on the upper surface of oxide layer 140B over dielectric layer 136B, spacer 130B, and sixth layer 120B. OPL layers 142C and 142B prevent oxide layers 140C and 140B from being removed during the etching of oxide layer 140A. The oxide layer 140A is removed by the etching process, while the second spacer 134A protects a portion of the oxide layer 140A sandwiched between the second spacer 134A and the layer above or below the second spacer 134A. As illustrated by FIG. 11A , most of the oxide layer 140A is removed, but a portion of the oxide layer 140A remains. As illustrated by the dashed circle 150A, the remaining oxide layer 140A is located between the second spacer 134A and the layer above or below the second spacer 134A. The dashed circle 150A highlights the remaining oxide layer 140A located between the second spacer 134A and the sixth layer 120A.

[0033] FIGS. 12A, 12B, and 12C each illustrate a different cross-section of a device on the same substrate during different stages of fabrication, according to an embodiment of the present invention. FIG. 12C illustrates that OPL layer 142C has been removed and replaced with high-K metal gate 144C. High-K metal gate 144C is formed on oxide layer 140C. As illustrated by FIG. 12B, OPL layer 142B has been removed and replaced with high-K metal gate 144B. High-K metal gate 144B is planarized to expose dielectric layer 136B, the top surface of spacer 130B, and the top surface of a portion of oxide layer 140B. FIG. 12A illustrates high-K metal gate 144A formed within the space within each of the pillars. High-K metal gate 144A fills the space between substrate 105, second layer 112A, fourth layer 116A, and sixth layer 120A. A high-K metal gate 144A fills the space above the sixth layer 120A between the spacers 130A.

[0034] While the present invention has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the scope of the invention as defined by the appended claims and equivalents thereof.

[0035] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements to market-recognized technology of one or more embodiments, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A substrate; a thin film gate oxide nanosheet device disposed on the substrate and having a first plurality of nanosheet layers, each of the first plurality of nanosheet layers having a first thickness located at a center of each of the plurality of nanosheet layers; a thick-gate oxide nanosheet device disposed on the substrate and having a second plurality of nanosheet layers, each of the second plurality of nanosheet layers having a second thickness; and Equipped with the first thickness is less than the second thickness; the thick-gate oxide nanosheet device is comprised of a first oxide layer located between each of the second plurality of nanosheet layers and the substrate; Device.

2. The device of claim 1 , wherein a side edge of each of the first plurality of nanosheet layers has a thickness that is greater than the first thickness for each of the first plurality of nanosheet layers.

3. The device of claim 2 , further comprising a first spacer layer positioned below and / or above a side edge of each of the first plurality of nanosheet layers.

4. 4. The device of claim 3, further comprising a second oxide layer located between the first spacer layer and one of the first plurality of nanosheet layers located above and / or below the first spacer layer.

5. 5. The device of claim 4, further comprising a high-k metal gate located above and below each of the first plurality of nanosheet layers.

6. The device of claim 5 , wherein a portion of the high-k metal gate contacts the second oxide layer.

7. The device of claim 1 , wherein the first oxide layer truncates a space between each of the second plurality of nanosheet layers and the substrate.

8. 10. The device of claim 1, wherein each of the first plurality of nanosheet layers is in contact with an oxide layer, a spacer layer, and a high-k metal gate layer.

9. A semiconductor device, a substrate having a thin-gate oxide nanosheet device and a thick-gate oxide nanosheet device disposed thereon; the thin film gate oxide nanosheet device is comprised of a plurality of first nanosheet layers, each of the plurality of first nanosheet layers having a thickness that varies across a horizontal axis relative to the plurality of first nanosheet layers, and the thinnest portion of each of the plurality of first nanosheet layers is located at the center of each first nanosheet layer; the thick-film gate oxide nanosheet device is comprised of a plurality of second nanosheet layers, each of the plurality of second nanosheet layers having a constant thickness; the constant thickness of each of the plurality of second nanosheet layers is greater than the thinnest portion of each of the plurality of first nanosheet layers; a first oxide layer truncating a space between each of the plurality of second nanosheet layers, the first oxide layer truncating a space between the substrate and one of the plurality of second nanosheet layers; Semiconductor device.

10. The semiconductor device according to claim 9 , wherein the first oxide layer is located above and below the side edges of each of the plurality of first nanosheet layers.

11. The semiconductor device according to claim 9 , wherein the thickest portion of each of the plurality of first nanosheet layers is located at an end of the respective first nanosheet layer.

12. The semiconductor device according to claim 11 , further comprising a first spacer layer positioned below and above the end of each of the plurality of first nanosheet layers.

13. The semiconductor device of claim 12 , further comprising a second oxide layer located between the first spacer layer and one of the plurality of first nanosheet layers located above, below, or both the first spacer layer.

14. The semiconductor device of claim 13 , further comprising a high-k metal gate located above and below each of the plurality of first nanosheet layers.

15. forming a nanosheet stack on a substrate, the nanosheet stack being composed of a plurality of alternating layers of Si and SiGe 30 containing 30% Ge; treating a first portion of the alternating layers of Si and SiGe 30 to form a thick gate oxide nanosheet device; treating a second portion of the alternating layers of Si and SiGe 30 to form a thin gate oxide nanosheet device; Including, processing the first portion of the nanosheet stack to form the thick-gate oxide nanosheet device further comprises forming a first oxide layer that reduces a space between the plurality of Si layers, the first oxide layer reducing a space between the substrate and one of the plurality of Si layers; method.

16. 16. The method of claim 15, further comprising forming a spacer layer at an end of each layer of Si, said spacer layer being formed on a top and bottom surface of each layer of Si.

17. 17. The method of claim 16, wherein processing the second portion of the nanosheet stack to form the thin-film gate oxide nanosheet device comprises thinning each Si layer of the second portion of the nanosheet stack, wherein each thinned layer of Si has a thickness that varies across a horizontal axis, and the thinnest portion of each layer of Si is located in the center of the horizontal axis for each layer of Si.

18. 20. The method of claim 17, further comprising forming an oxide layer between each spacer layer and one of the layers of Si.

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