Doherty Amplifier

Abstract

To provide a Doherty amplifier which suppresses deterioration in characteristic.SOLUTION: A Doherty amplifier comprises: a first output electrode 20 to which a plurality of first output fingers 25 is connected; a first amplifier that amplifies at least one signal of two signals obtained by distributing an input signal, and outputs the signal to the first output electrode; a second output electrode 30 to which a plurality of second output fingers 35 is connected; a second amplifier that amplifies the other signal of the two signals and outputs the signal to the second output electrode; a bonding wire 41 that is connected between a first region 20a and a second region 30a in the second output electrode; a bonding wire 42 that is connected between a third region 20b which is closer to the second output electrode than the first region and a fourth region 30b which is closer to the first output electrode than the second region; and at least one capacitor of a capacitor C1 connected serially to the bonding wire 41 between the first region and the second region and a capacitor C2 connected in parallel to the bonding wire 42 between the third region and the fourth region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a Doherty amplifier. [Background technology]

[0002] Doherty amplifiers are known as amplifiers that amplify high-frequency signals such as microwaves. In a Doherty amplifier, a main amplifier and a peak amplifier amplify input signals in parallel, and the amplified signals are combined by a combiner. In the combiner, a quarter-wave line is provided between the main amplifier and the combining point. It is known to use an output capacitance and a bonding wire in the main amplifier instead of the quarter-wave line (for example, see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 8,228,123 Summary of the Invention [Problem to be solved by the invention]

[0004] It is conceivable to form a combiner by connecting the output electrodes of the main amplifier and the peak amplifier using bonding wires. However, if the output electrodes of the main amplifier and the peak amplifier are wide, multiple bonding wires are connected between the output electrodes. In this case, the electrical lengths between the main amplifier and the combining point via the multiple bonding wires may differ. This may deviate from the ideal combiner conditions and result in degraded characteristics.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a Doherty amplifier capable of improving characteristics. [Means for solving the problem]

[0006] One embodiment of the present disclosure includes a first amplifier including a plurality of first output fingers and a first output electrode to which the plurality of first output fingers are connected, the first amplifier amplifying one of two signals into which an input signal is divided and outputting the one signal to the first output electrode; a second amplifier including a plurality of second output fingers and a second output electrode to which the plurality of second output fingers are connected, the second amplifier being disposed in a direction intersecting with an extension direction of the plurality of first output fingers and an extension direction of the plurality of second output fingers with respect to the first amplifier, the second amplifier amplifying the other of the two signals and outputting the other signal to the second output electrode; a first bonding wire connected between a first region of the first output electrode and a second region of the second output electrode; a second bonding wire connected between a third region of the first output electrode that is closer to the second output electrode than the first region and a fourth region of the second output electrode that is closer to the first output electrode than the second region; and at least one of a first capacitor connected in series to the first bonding wire between the first region and the second region, and a second capacitor connected in parallel to the second bonding wire between the third region and the fourth region, wherein the first region and the third region are regions to which the plurality of first output fingers are connected, and the second region and the fourth region are regions to which the plurality of second output fingers are connected. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a Doherty amplifier capable of improving characteristics. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a Doherty amplifier according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of the Doherty amplifier according to the first embodiment. [Figure 3] FIG. 3 is a plan view of the Doherty amplifier according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of the capacitor in the first embodiment. [Figure 5] FIG. 5 is a plan view of the Doherty amplifier in the first comparative example. [Figure 6] FIG. 6 is a plan view of a Doherty amplifier in Comparative Example 2. As shown in FIG. [Figure 7] FIG. 7 is a circuit diagram of a Doherty amplifier in Comparative Example 3. As shown in FIG. [Figure 8] FIG. 8 is a plan view of a Doherty amplifier in Comparative Example 3. As shown in FIG. [Figure 9] FIG. 9 is a plan view of a Doherty amplifier according to a first modification of the first embodiment. [Figure 10] FIG. 10 is a plan view of a Doherty amplifier according to a second modification of the first embodiment. [Figure 11] FIG. 11 is a plan view of the Doherty amplifier according to the second embodiment. [Figure 12] FIG. 12 is a plan view of a Doherty amplifier according to a first modification of the second embodiment. [Figure 13] FIG. 13 is a plan view of a Doherty amplifier according to a second modification of the second embodiment. [Figure 14] FIG. 14 is a circuit diagram of a Doherty amplifier according to the third embodiment. [Figure 15] FIG. 15 is a plan view of the Doherty amplifier according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a first amplifier including a plurality of first output fingers and a first output electrode to which the plurality of first output fingers are connected, the first amplifier amplifying one of two signals into which an input signal is divided and outputting the one signal to the first output electrode; a second amplifier including a plurality of second output fingers and a second output electrode to which the plurality of second output fingers are connected, the second amplifier being arranged in a direction intersecting with the extension direction of the plurality of first output fingers and the extension direction of the plurality of second output fingers with respect to the first amplifier, the second amplifier amplifying the other of the two signals and outputting the other signal to the second output electrode; a first bonding wire connected between a first region of the first output electrode and a second region of the second output electrode; a second bonding wire connected between a third region of the first output electrode that is closer to the second output electrode than the first region and a fourth region of the second output electrode that is closer to the first output electrode than the second region, and at least one of a first capacitor connected in series to the first bonding wire between the first region and the second region and a second capacitor connected in parallel to the second bonding wire between the third region and the fourth region, wherein the first region and the third region are regions to which the plurality of first output fingers are connected, and the second region and the fourth region are regions to which the plurality of second output fingers are connected, thereby improving the characteristics of the Doherty amplifier. (2) It is preferable that the first output electrode is separated between the first region and the third region, and the second output electrode is separated between the second region and the fourth region. (3) It is preferable that the first bonding wire and the second bonding wire do not cross each other. (4) It is preferable that the first region and the second region are connected without the third region and the fourth region being interposed therebetween, and that the third region and the fourth region are connected without the first region and the second region being interposed therebetween. (5) It is preferable that the signal output by the first amplifier and the signal output by the second amplifier are combined at the second output electrode. (6) It is preferable to include a harmonic processing circuit connected to the second output electrode, which processes harmonic components of the signals amplified by the first amplifier and the second amplifier.

[0010] [Details of the embodiments of the present disclosure] Specific examples of Doherty amplifiers according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 is a block diagram of a Doherty amplifier according to a first embodiment. As shown in FIG. 1, in the Doherty amplifier, a main amplifier 10 and a peak amplifier 11 are connected in parallel between an input terminal Tin and an output terminal Tout. A high-frequency signal is input to the input terminal Tin as an input signal. A divider 16 divides the input signal into two signals. One of the divided signals is input to the main amplifier 10. The main amplifier 10 (first amplifier) ​​amplifies the input signal and outputs it to a combiner 14. The other signal divided by the divider 16 is input to a peak amplifier 11 via a quarter-wave line 15. The peak amplifier 11 (second amplifier) ​​amplifies the input signal and outputs it to the combiner 14. The combiner 14 combines the output signal of the main amplifier 10 and the output signal of the peak amplifier 11 and outputs the combined signal to the output terminal Tout.

[0012] The main amplifier 10 and the peak amplifier 11 include, for example, FETs (Field Effect Transistors) 12 and 13, respectively. In the FETs 12 and 13, the sources S are grounded, a high-frequency signal is input to the gates G, and a signal is output from the drains D. The FETs 12 and 13 are, for example, GaN FETs or LDMOS (Laterally Diffused Metal Oxide Semiconductors). The main amplifier 10 and the peak amplifier 11 may each include multiple FETs 12 and 13. The FETs 12 and 13 have drain-source capacitances Cds1 and Cds2, respectively. The drain-source capacitances Cds1 and Cds2 are internal capacitances of the FETs 12 and 13, and are depicted using dotted lines in FIG. 1. The combiner 14 includes the drain-source capacitance Cds1 of the main amplifier 10, an inductor L0, and a combining point N1. The drain-source capacitance Cds1 and inductor L0 function as an impedance inverter at the center frequency of the Doherty amplifier band and are used in place of a quarter-wave line. At a combining point N1, the signal amplified by the main amplifier 10 and the signal amplified by the peak amplifier 11 are combined.

[0013] The main amplifier 10 operates in class AB or class B, and the peak amplifier 11 operates in class C. As a result, when the input power is small, the main amplifier 10 mainly amplifies the input signal. When the input power is large, the main amplifier 10 and the peak amplifier 11 amplify the input signal. Matching circuits may be connected between the divider 16 and the main amplifier 10, between the divider 16 and the peak amplifier 11, and between the combiner 14 and the output terminal Tout. When the input power of the high-frequency signal input to the input terminal Tin is large and the peak amplifier 11 operates, the main amplifier 10 and the peak amplifier 11 are set to operate optimally at saturated power (for example, to maximize efficiency). When the input power is small and the peak amplifier 11 does not operate, the main amplifier 10 is set to operate optimally at saturated power (for example, to maximize efficiency).

[0014] Fig. 2 is a circuit diagram of the Doherty amplifier in the first embodiment. As shown in Fig. 2, FET 12 has a plurality of FETs 12a to 12d connected in parallel, and FET 13 has a plurality of FETs 13a to 13d connected in parallel. FETs 12 and 13 are multi-finger FETs, and FETs 12a to 12d and FETs 13a to 13d are schematic illustrations of multi-finger FETs. FETs 12a to 12d and FETs 13a to 13d have drain-source capacitances Cds1a to Cds1d and Cds2a to Cds2d, respectively.

[0015] An inductor L1 and a capacitor C1 (first capacitor) are connected in series between the drains of FETs 12a and 12b and the drains of FETs 13c and 13d. An inductor L2 and a capacitor C2 (second capacitor) are connected in parallel between the drains of FETs 12c and 12d and the drains of FETs 13a and 13b. The drain-source capacitances Cds1a and Cds1b of FETs 12a and 12b, the inductor L1, and the capacitor C1 form a combiner 14a. The drain-source capacitances Cds1c and Cds1d of FETs 12c and 12d, the inductor L2, and the capacitor C2 form a combiner 14b.

[0016] FIG. 3 is a plan view of the Doherty amplifier according to the first embodiment. As shown in FIG. 3, FETs 12 and 13 are provided on a semiconductor chip 40 and arranged in the Y direction. FET 12 is a multi-finger FET having multiple source fingers 23, multiple gate fingers 24, and multiple drain fingers 25. The source fingers 23, gate fingers 24, and drain fingers 25 extend in the X direction. The multiple drain fingers 25 are connected to a drain electrode 20. The multiple gate fingers 24 are connected to a gate electrode 22. The source fingers 23 are connected to the ground on the underside of the semiconductor chip 40 via via holes. FET 13 has multiple source fingers 33, multiple gate fingers 34, multiple drain fingers 35, a drain electrode 30, and a gate electrode 32. The configurations of the source fingers 33, gate fingers 34, drain fingers 35, drain electrode 30, and gate electrode 32 in FET 13 are the same as those in FET 12, and therefore will not be described here. Since the source fingers 23 and 33, the gate fingers 24 and 34, and the drain fingers 25 and 35 are arranged in the Y direction, the drain electrodes 20 and 30 and the gate electrodes 22 and 32 are wide in the Y direction.

[0017] Of the drain electrode 20 of FET 12, the region farther from the drain electrode 30 of FET 13 is the first region 20a, and the region closer to the drain electrode 30 is the third region 20b. Of the drain electrode 30 of FET 13, the region farther from the drain electrode 20 of FET 12 is the second region 30a, and the region closer to the drain electrode 20 is the fourth region 30b.

[0018] A pad 26 connected to the region 20a is provided on the +X side of the region 20a. +A pad 36 is provided on the X side and connected to region 30a. A pad 38 is provided in the +Y direction of pad 36. A capacitor C1 is connected between pads 36 and 38. Pads 26 and 38 are connected by a bonding wire 41. The regions where bonding wire 41 is bonded to pad 26 and pad 38 are regions 20c and 30c, respectively. Regions 20a and 30a are connected via pad 26, bonding wire 41, pad 38, capacitor C1, and pad 36. The distances D4 (electrical lengths) between the multiple drain fingers 25 connected to region 20a and region 20c are approximately the same. The distances D5 between the multiple drain fingers 35 connected to region 30a and region 30c are approximately the same.

[0019] Regions 20b and 30b are connected by a bonding wire 42. The regions where the bonding wire 42 is bonded to the drain electrodes 20 and 30 are regions 20d and 30d, respectively. A capacitor C2 is connected in parallel to the bonding wire 42 between regions 20d and 30d. The distances D3 between the multiple drain fingers 25 connected to region 20b and region 20d are approximately the same. The distances D3 between the multiple drain fingers 35 connected to region 30b and region 30d are approximately the same.

[0020] Capacitors C1 and C2 are MIM (Metal Insulator Metal) capacitors having an upper electrode 44, a lower electrode 46, and a dielectric film 45. The drain electrode 30 is connected to a matching circuit 18 via a bonding wire 43. The region where the bonding wire 43 is bonded to the drain electrode 30 is region 30e. The matching circuit 18 is connected to the output terminal Tout. The drain electrodes 20 and 30, gate electrodes 22 and 32, pads 26, 36, and 38, upper electrode 44, and lower electrode 46 are metal layers such as gold layers. The distributor 16 and gate electrode 22, and the quarter-wavelength line 15 and gate electrode 32 are connected by bonding wires, which are not shown in the figure.

[0021] FIG. 4 is a cross-sectional view of the capacitor in Example 1. As shown in FIG. 4, a drain electrode 20 and a pad 38 (and a drain electrode 30) are provided on a semiconductor chip 40. The drain electrode 20 is connected to an upper electrode 44, and the pad 38 (and a drain electrode 30) is connected to a lower electrode 46. In the capacitor C1 (and C2), a dielectric film 45 is provided between the upper electrode 44 and the lower electrode 46. The dielectric film 45 is an inorganic dielectric film such as a silicon nitride film or a silicon oxide film. An insulating film 45a is provided so as to cover the upper electrode 44. Both ends of a bonding wire 41 (and 42) are bonded to the region 20c (and 20d) and the region 30c (and 30d). The drain electrode 20 may be connected to the lower electrode 46, and the pad 38 (and a drain electrode 30) may be connected to the upper electrode 44.

[0022] [Comparative Example 1] FIG. 5 is a plan view of a Doherty amplifier in Comparative Example 1. As shown in FIG. 5, in Comparative Example 1, capacitors C1 and C2 are not provided. Regions 20c and 30c to which bonding wire 41 is bonded are between regions 20a and 20b, and between regions 30a and 30b, respectively. Bonding wire 42 is not provided. The other configurations are the same as those in Example 1.

[0023] In Comparative Example 1, the signal phase is almost the same at the point where the drain electrodes 20 (and 30) are connected to the drain fingers 25 (and 35). The distance D1 between the drain fingers 25 (and 35) far from the region 20c (and 30c) and the region 20c (and 30c) is longer than the distance D2 between the drain fingers 25 (and 35) close to the region 20c (and 30c) and the region 20c (and 30c). This allows the region 20c (and 30c) to The phases of the signals output from the drain fingers 25 (and 35) combined in the cascade are different, which increases loss.

[0024] Comparative Example 2 FIG. 6 is a plan view of a Doherty amplifier in Comparative Example 2. As shown in FIG. 6, bonding wires 41 and 42 are provided. Regions 20c and 30c to which bonding wire 41 is bonded are provided in regions 20a and 30b, respectively. Regions 20d and 30d to which bonding wire 42 is bonded are provided in regions 20b and 30a, respectively. The reason that bonding wire 41 connects regions 20c and 30c and bonding wire 42 connects regions 20d and 30d is to prevent the phases of the signals flowing through bonding wires 41 and 42 from shifting from each other by making the lengths of bonding wires 41 and 42 the same and making the inductances the same. The other configurations are the same as those of Comparative Example 1.

[0025] In Comparative Example 2, regions 20a and 20b (or 30a and 30b) Areas 20c and 20d are located near the center of (or 30c and 30d) are provided. Therefore, the distance D3 between the drain finger 25 (or 35) and the regions 20c and 20d (or 30c and 30d) is approximately the same. Therefore, the phases of the signals output from each drain finger 25 (or 35) combined in the regions 20c and 20d (or 30c and 30d) are approximately the same. This reduces loss. Although the example in which the regions 20a and 20b (or 30a and 30b) are provided for two drain fingers 25 (or 35) has been described, the regions 20a and 20b (or 30a and 30b) may be provided for three or more drain fingers 25 (or 35). Even in this case, the phases of the signals combined in the regions 20c and 20d (or 30c and 30d) can be aligned in Comparative Example 2 compared to Comparative Example 1. However, in Comparative Example 2, the bonding wires 41 and 42 are connected so as to cross each other in order to make the lengths of the bonding wires 41 and 42 the same. However, the resistance of the bonding wires 41 and 42 increases due to the proximity effect, and the Q value of the bonding wires 41 and 42 (that is, the inductors L1 and L2) decreases.

[0026] Comparative Example 3 FIG. 7 is a circuit diagram of a Doherty amplifier in Comparative Example 3. FIG. 8 is a plan view of the Doherty amplifier in Comparative Example 3. As shown in FIGS. 7 and 8, in Comparative Example 3, regions 20c and 30c to which bonding wire 41 is bonded are provided in regions 20a and 30a, respectively. Regions 20d and 30d to which bonding wire 42 is bonded are provided in regions 20b and 30b, respectively. Bonding wires 41 and 42 correspond to inductors L1 and L2, respectively. The other configurations are the same as those in Comparative Example 2.

[0027] The distance D3 between the drain finger 25 and the regions 20c and 20d is approximately the same. This ensures that the signal phases in the regions 20c and 20d are approximately the same. Similarly, the distance D3 between the drain finger 35 and the regions 30c and 30d is approximately the same, which ensures that the signal phases in the regions 30c and 30d are approximately the same. However, the lengths of the bonding wires 41 and 42 are different, resulting in different inductances for the inductors L1 and L2. Furthermore, the electrical length from the region 20a to the region 30e via the bonding wire 41 and region 30a is different from the electrical length from the region 20b to the region 30e via the bonding wire 42 and region 30b. This makes it difficult to set both combiners 14a and 14b to have a quarter-wavelength electrical length at the center frequency of the band. Even if the lengths of the bonding wires 41 and 42 are approximately the same, the electrical length between the region 20a and the combining point N1 and the electrical length between the region 20b and the combining point N1 are different.

[0028] According to the first embodiment, as shown in FIG. 3 , a bonding wire 41 (first bonding wire) is connected between a region 20a (first region) of the drain electrode 20 (first output electrode) and a region 30a (second region) of the drain electrode 30 (second output electrode). A bonding wire 42 (second bonding wire) is connected between a region 20b (third region) of the drain electrode 20 that is different from the region 20a, and a region 30b (fourth region) of the drain electrode 30 that is different from the region 30a. Connecting different regions 20a and 20b in the drain electrode 20 to different regions 30a and 30b in the drain electrode 30 in this manner would result in different electrical lengths between the combiners 14a and 14b, degrading the characteristics of the Doherty amplifier. Therefore, a capacitor C1 (first capacitor) is provided between the regions 20a and 30a, connected in series or in parallel to the bonding wire 41. A capacitor C2 (second capacitor) is provided between the regions 20b and 30b and is connected in series or parallel to the bonding wire 42. This allows the electrical lengths of the combiners 14a and 14b to be approximately the same, thereby suppressing deterioration of the characteristics of the Doherty amplifier.

[0029] Region 20b is closer to drain electrode 30 than region 20a, and region 30b is closer to drain electrode 20 than region 30a. In this case, the distance between region 20a and combination point N1 is longer than the distance between region 20b and combination point N1. Therefore, capacitor C1 is connected in series with bonding wire 41 between region 20a and region 30a. Capacitor C2 is connected in parallel with bonding wire 42 between region 20b and region 30b. As a result, the total electrical length between region 20a and combination point N1 via the series connection of bonding wire 41 and capacitor C1 can be substantially shorter than when capacitor C1 is not included. The total electrical length between region 20b and combination point N1 via the parallel connection of bonding wire 42 and capacitor C2 can be substantially longer than when capacitor C2 is not included. Therefore, the electrical length between the region 20a and the combining point N1 can be made substantially the same as the electrical length between the region 20b and the combining point N1.

[0030] The main amplifier 10 includes a plurality of drain fingers 25 (first output fingers), and regions 20a and 20b are regions to which the plurality of drain fingers 25 are connected. The peak amplifier 11 includes a plurality of drain fingers 35 (second output fingers), and regions 30a and 30b are regions to which the plurality of drain fingers 35 are connected. In such a multi-finger FET, the phases of the regions 20a and 20b to which the drain fingers 25 are connected are substantially the same. Therefore, if the electrical length between the region 20a and the combining point N1 differs from the electrical length between the region 20b and the combining point N1, the characteristics of the Doherty amplifier will deteriorate. Therefore, it is preferable to provide capacitors C1 and C2.

[0031] In a multi-finger FET, the widths of the drain electrodes 20 and 30 are wider in a direction intersecting the extension direction (X direction) of the drain fingers 25 and 35. Therefore, if the main amplifier 10 and the peak amplifier 11 are arranged in a direction intersecting the extension direction of the drain fingers 25 and 35, respectively, the electrical length between the region 20a and the combining point N1 and the electrical length between the region 20b and the combining point N1 tend to differ. Therefore, it is preferable to provide capacitors C1 and C2.

[0032] Regions 20d and 30d are provided within regions 20b and 30b, to which bonding wire 42 is bonded. On the other hand, pads 26 and 36 are provided to extend regions 20a and 30a in the +X direction, respectively, and bonding wire 42 is bonded to regions 20c and 30c located in the +X direction from regions 20a and 30a. 41 This prevents the bonding wires 41 and 42 from crossing each other, thereby preventing a decrease in the Q value as in Comparative Example 2. 。

[0033] Furthermore, the signal output from the main amplifier 10 and the signal output from the peak amplifier 11 are combined at the drain electrode 30. This tends to cause a difference in electrical length between the region 20a and the combining point N1 and the region 20b and the combining point N1. Therefore, it is preferable to provide capacitors C1 and C2.

[0034] When regions 20a and 30a are connected via region 20b, signals from drain fingers 25 connected to region 20a and signals from drain fingers 25 connected to region 20b are combined in region 20b. This results in signals of different phases being combined, causing loss. When regions 20a and 30a are connected via region 30b, signals of different phases are combined in region 30b, causing loss. Similarly, when regions 20b and 30b are connected via region 20a or 30a, signals of different phases are combined in region 20a or 30a, causing loss. According to Example 1, regions 20a and 30a are connected without regions 20b and 30b being connected, and regions 20b and 30b are connected without regions 20a and 30a being connected. This reduces loss.

[0035] [Modification 1 of Example 1] FIG. 9 is a plan view of a Doherty amplifier according to a first modification of the first embodiment. As shown in FIG. 9, the pad 36 is drawn out from the region 30a in the +X direction and further bent in the +Y direction. A region 30c is provided to which a bonding wire 41 is bonded to the pad 36. A capacitor C1 is not connected in series or parallel to the bonding wire 41 between the regions 20a and 30a. A capacitor C2 is connected in parallel to the bonding wire 42 between the regions 20b and 30b. The other configurations are the same as those of the first embodiment, and a description thereof will be omitted. As in the first modification of the first embodiment, only the capacitor C2 of the capacitors C1 and C2 may be provided.

[0036] [Modification 2 of Example 1] 10 is a plan view of a Doherty amplifier according to a second modification of the first embodiment. As shown in FIG. 10, a capacitor C1 is connected in series with a bonding wire 41 between regions 20a and 30a. A capacitor C2 is not connected in series or parallel with a bonding wire 42 between regions 20b and 30b. The other configurations are the same as those of the first embodiment, and a description thereof will be omitted. As in the second modification of the first embodiment, only the capacitor C1 may be provided out of the capacitors C1 and C2.

[0037] As in Example 1 and its Modifications 1 and 2, at least one of the capacitors C1 and C2 may be provided. Whether both the capacitors C1 and C2 are provided or only one of the capacitors C1 and C2 can be determined by appropriately designing the capacitors so that the electrical length between the region 20a and the combining point N1 is approximately the same as the electrical length between the region 20b and the combining point N1.

[0038] In addition, although an example has been described in which FETs 12 and 13 are provided on the same semiconductor chip 40, FETs 12 and 13 may be provided on different semiconductor chips. Although an example has been described in which main amplifier 10 and peak amplifier 11 include FETs 12 and 13, respectively, main amplifier 10 and peak amplifier 11 may include transistors other than FETs. Although MIM capacitors have been used as capacitors C1 and C2, capacitors other than MIM capacitors may also be used.

[0039] Although the example in which the drain electrode 20 has two regions 20a and 20b and the drain electrode 30 has two regions 30a and 30b has been described, the drain electrode 20 may have three or more regions and the drain electrode 30 may have three or more regions. For example, the region between the regions 20a and 20b in the drain electrode 20 and the region between the regions 30a and 30b in the drain electrode 30 may be connected by bonding wires other than the bonding wires 41 and 42.

[0040] Although the main amplifier 10 and the peak amplifier 11 have been described as examples of the first amplifier and the second amplifier, respectively, the first amplifier and the second amplifier may be the peak amplifier 11 and the main amplifier 10, respectively.

[0041] [Example 2] Fig. 11 is a plan view of a Doherty amplifier in Example 2. As shown in Fig. 11, regions 20a and 20b of drain electrode 20 are divided by dividing region 29. Regions 30a and 30b of drain electrode 30 are divided by dividing region 39. Region 30b and pad 36 are electrically connected via lower electrode 46 of capacitor C1 without via region 30a. The other configurations are the same as those in Example 1, and therefore will not be described again.

[0042] [Modification 1 of Example 2] FIG. 12 is a plan view of a Doherty amplifier in a first modification of the second embodiment. As shown in FIG. 12, a capacitor C1 is not connected in series or parallel to the bonding wire 41 between the regions 20a and 30a. Divided regions 29 and 39 of the drain electrodes 20 and 30 are provided. The regions 30a and 30b are not directly connected, but are connected via a pad 36. A capacitor C2 is connected in parallel to a bonding wire 42 between the regions 20b and 30b. The other configurations are the same as those in the second embodiment, and a description thereof will be omitted. As in the first modification of the second embodiment, only the capacitor C2 of the capacitors C1 and C2 may be provided.

[0043] [Modification 2 of Example 2] 13 is a plan view of a Doherty amplifier according to a second modification of the second embodiment. As shown in FIG. 13, a capacitor C1 is connected in series with a bonding wire 41 between regions 20a and 30a. A capacitor C2 is not connected in series or parallel with a bonding wire 42 between regions 20b and 30b. The other configurations are the same as those of the second embodiment, and a description thereof will be omitted. As in the second modification of the second embodiment, only the capacitor C1 may be provided out of the capacitors C1 and C2.

[0044] When regions 20a and 20b are connected and regions 30a and 30b are connected as in Example 1 and its modified example, the characteristics are improved but oscillation is likely to occur. Therefore, as in Example 2 and its modified example, regions 20a and 20b are separated and regions 30a and 30b are separated. This makes it possible to suppress oscillation.

[0045] [Example 3] FIG. 14 is a circuit diagram of a Doherty amplifier according to a third embodiment. As shown in FIG. 14, a harmonic processing circuit 48 is connected between a combining point N1 and ground. The harmonic processing circuit 48 includes an inductor L3 and a capacitor C3 connected in series between the combining point N1 and ground. The inductor L3 and the capacitor C3 form a series resonant circuit, which has a resonant frequency in the frequency band of harmonics of the Doherty amplifier band. The other circuit configurations are the same as those shown in FIG. 2 of the first embodiment, and therefore will not be described again.

[0046] FIG. 15 is a plan view of a Doherty amplifier according to the third embodiment. As shown in FIG. 15, a capacitor C3 includes a dielectric film 49, an upper electrode 51, and a lower electrode (not shown). A bonding wire 47 corresponds to the inductor L3 and connects the drain electrode 30 and the upper electrode 51. The lower electrode is connected to ground. The other configurations are the same as those of the first embodiment, and therefore a description thereof will be omitted.

[0047] According to the third embodiment, the harmonic processing circuit 48 is connected to the drain electrode 30 and processes the harmonic components of the signals amplified by the main amplifier 10 and the peak amplifier 11. By providing the harmonic processing circuit 48 at the drain electrode 30 corresponding to the combining point N1, it is possible to process the harmonics of both the main amplifier 10 and the peak amplifier 11 using a single harmonic processing circuit 48. This allows the Doherty amplifier to be made smaller. The harmonic processing circuit 48 may be provided in the modified example of the first embodiment, the second embodiment, and their modified examples.

[0048] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0049] 10 Main amplifier (first amplifier) 11 Peak amplifier (second amplifier) 12, 12a~12d, 13, 13a~13d FET 14, 14a, 14b combiner 15 1 / 4 wavelength line 16 Distributor 18 Matching circuit 20 Drain electrode (first output electrode) 20a area (first area) 20b area (3rd area) 20c, 20d area 30a area (second area) 30b area (4th area) 30c~30e area 22, 32 Gate electrode 23, 33 Sauce Finger 24, 34 gate fingers 25 Drain finger (first output finger) 26, 36, 38 pads 29, 39 divided area 30 Drain electrode (second output electrode) 35 Drain finger (second output finger) 40 Semiconductor Chips 41 Bonding wire (first bonding wire) 42 Bonding wire (second bonding wire) 43, 47 Bonding wire 44, 51 Upper electrode 45, 49 Dielectric film 45a Insulating film 46 Lower electrode 48 Harmonic Processing Circuit C1 Capacitor (first capacitor) C2 capacitor (second capacitor)

Claims

1. a first amplifier including a plurality of first output fingers and a first output electrode connected to the plurality of first output fingers, amplifying one of two signals obtained by dividing an input signal and outputting the amplified signal to the first output electrode; a second amplifier including a plurality of second output fingers and a second output electrode connected to the plurality of second output fingers, the second amplifier being disposed in a direction intersecting with the extension direction of the plurality of first output fingers and the extension direction of the plurality of second output fingers with respect to the first amplifier, amplifying the other of the two signals and outputting the signal to the second output electrode; a first bonding wire connected between a first region of the first output electrode and a second region of the second output electrode; a second bonding wire connected between a third region of the first output electrode that is closer to the second output electrode than the first region and a fourth region of the second output electrode that is closer to the first output electrode than the second region; at least one of a first capacitor connected in series to the first bonding wire between the first region and the second region and a second capacitor connected in parallel to the second bonding wire between the third region and the fourth region; Equipped with the first region and the third region are regions to which the plurality of first output fingers are connected, and the plurality of first output fingers extend from the first region and the third region, respectively; the second region and the fourth region are regions to which the plurality of second output fingers are connected, and the plurality of second output fingers extend from the second region and the fourth region, respectively; the first output electrode and the second output electrode are aligned in a direction intersecting an extension direction of the plurality of first output fingers and an extension direction of the plurality of second output fingers, and the first region, the third region, the second region, and the fourth region are aligned; the signal output from the first amplifier and the signal output from the second amplifier are combined at a combining point; the first region is connected to the synthesis point via the first bonding wire; the third region is connected to the joining point via the second bonding wire; the combining point is provided on the second output electrode and connected to an output terminal; the second output fingers, the second region, and the synthesis point are aligned in an extension direction of the plurality of second output fingers, A Doherty amplifier in which the signal combined at the combining point is output from the combining point to the output terminal.

2. 2. The Doherty amplifier of claim 1, wherein the first output electrode is separated between the first region and the third region, and the second output electrode is separated between the second region and the fourth region.

3. 3. The Doherty amplifier of claim 1, wherein the first bonding wire and the second bonding wire do not cross each other.

4. 4. The Doherty amplifier according to claim 1, wherein the first region and the second region are connected without the third region and the fourth region intervening therebetween, and the third region and the fourth region are connected without the first region and the second region intervening therebetween.

5. a harmonic processing circuit connected to the second output electrode, for processing harmonic components of the signal amplified by the first amplifier and the signal amplified by the second amplifier; 2. The Doherty amplifier according to claim 1, wherein one end of the harmonic processing circuit is connected to the second output electrode, and the other end of the harmonic processing circuit is grounded.

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