Processing device and processing method

Abstract

To speed up a square root operation by suppressing an increase in a circuit scale and increasing the number of bits of a partial root obtained by one repeated calculation.SOLUTION: An arithmetic processing unit acquires an approximate value (k) of the inverse of the square root of input data X, obtains a partial root (qn) as a bit to be calculated in a square root to be obtained by using a residual variable Tn for showing a residual obtained based on the approximate value (k), obtains a new residual variable Tn by subtracting a product 2*qn*Sn of the double value of an intermediate variable Sn for showing an intermediate root obtained based on the approximate value (k) and the partial root (qn) and a product k*qn2 of the approximate value (k) and the square value of the partial root (qn) from the previously obtained residual variable Tn, obtains a new intermediate variable Sn by adding the product k*qn of the approximate value (k) and the partial root (qn) and the previously obtained intermediate variable Sn, obtains a new intermediate root Qn by adding the previously obtained intermediate root Qn and the partial root (qn) obtained by a first operation part, and outputs the intermediate root Qn having a predetermined number of digits as a square root of input data X.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processing device and a processing method. [Background technology]

[0002] In processors and other arithmetic processing units, square root instructions are important instructions that are implemented almost as frequently as division instructions, and there is a demand for faster processing, just like division instructions. Known methods for calculating square roots in hardware include linear convergence methods such as the Sweeney, Robertson, and Tocher (SRT) method, which calculates the root sequentially in units of a predetermined number of bits.

[0003] For example, when using Newton's method for square root extraction, a method is known in which a table storing calculated values ​​corresponding to the division terms of a recurrence formula is used to avoid repeated division (see, for example, Patent Document 1).Also, as a method for calculating square roots, an algorithm is known in which squaring, determining whether the result is larger or smaller, and adding or subtracting each bit are repeated, and finally squaring, determining whether the result is larger or smaller, and adding or subtracting the least significant bit twice (see, for example, Patent Document 2).

[0004] In a processing device that performs square root extraction, a method is known in which a part of a circuit that finds a residual by iterative calculation is moved to a path separate from the main iterative calculation path to improve the critical path of the iterative calculation (see, for example, Patent Document 3). Also, a processing device that performs exponential or logarithmic calculations using the STL (Sequential Table Lookup) method is known (see, for example, Patent Document 4). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2010 / 058521 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-195933 [Patent Document 3] International Publication No. 2020 / 079802 [Patent Document 4] International Publication No. 2020 / 090025 Summary of the Invention [Problem to be solved by the invention]

[0006] In linear convergence methods such as the SRT method, the more bits are calculated in one iteration, the fewer iterations are required to obtain the square root, and the faster the square root calculation can be performed.However, the more bits are calculated in one iteration, the larger the circuit scale becomes.

[0007] In one aspect, the present invention aims to speed up square root calculation by increasing the number of bits of a partial root obtained in one iterative calculation while suppressing an increase in circuit size. [Means for solving the problem]

[0008] According to one aspect, the arithmetic processing device is a arithmetic processing device that iteratively calculates the square root of input data X so as to reduce a residual, which is the difference between the square value of an intermediate root obtained during the calculation and the input data, and calculates an approximate value k of the reciprocal of the square root of the input data X. By looking up the table containing the approximate value k a first calculation unit that uses a residual variable Tn indicating a residual calculated based on the approximate value k to calculate a partial root qn, which is a bit to be calculated in the square root to be calculated; and a product 2·qn·Sn of the partial root qn and the doubled value of the intermediate variable Sn indicating the intermediate root calculated based on the approximate value k, and a product k·qn of the approximate value k and the square of the partial root qn. 2 a second calculation unit that subtracts the product k·qn of the approximation value k and the partial root qn from the previously calculated residual variable Tn to calculate a new residual variable Tn; a third calculation unit that adds the product k·qn of the approximation value k and the partial root qn to the previously calculated intermediate variable Sn to calculate a new intermediate variable Sn; and a fourth calculation unit that adds the previously calculated intermediate root Qn to the partial root qn calculated by the first calculation unit to calculate a new intermediate root Qn and outputs the intermediate root Qn with a predetermined number of digits calculated as the square root of the input data X. [Effects of the Invention]

[0009] By increasing the number of bits of the partial root obtained in one iterative calculation while suppressing an increase in circuit size, the square root calculation can be sped up. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processing unit according to an embodiment. [Figure 2] 2 is a flow chart showing an example of the operation of the arithmetic processing device of FIG. 1. [Figure 3] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. [Figure 4] 4 is a flowchart showing an example of the operation of the arithmetic processing device of FIG. 3. [Figure 5] FIG. 10 is a block diagram illustrating an example of another arithmetic processing device. [Figure 6] 6 is a flowchart showing an example of the operation of the arithmetic processing device of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings.

[0012] Fig. 1 shows an example of a processing device according to an embodiment. The processing device 10 shown in Fig. 1 has a function of calculating a square root based on a square root extraction command, and is mounted on a processor such as a CPU (Central Processing Unit). Below, a method for calculating a square root using the processing device 10 will be described, followed by a description of the circuit configuration of the processing device 10.

[0013] The square root calculation method using a linear convergence method such as the SRT method, which is performed in hardware, is almost the same as square root calculation using long division. For example, let the number for which you want to find the square root be data X. Data X is scaled in advance to a range that is easy to calculate. For example, data X is based on the mantissa part of a floating-point number, and a number adjusted so that both the mantissa part and the exponent part are easy to calculate is selected. For example, X is scaled to a range such as 1≦X<4 or 0.25≦X<1.

[0014] In the square root extraction, the intermediate result of the square root at a certain point in time is defined as the intermediate root Qn, and the difference between the square of the intermediate root Qn and the data X is defined as the residual Rn. In this case, the data X is expressed by equation (1). Equation (1) is always satisfied while the square root extraction is being performed, and the calculation processing device 10 stores the intermediate root Qn and the residual Rn, which have the relationship of equation (1), as a pair. X=Qn 2 +Rn …(1)

[0015] In square root extraction, a calculation procedure is repeated to find a root with a predetermined precision (number of digits). For example, the magnification B is used to refine the weight of the least significant digit of the intermediate root Qn with each iteration. Refining the weight means shifting the position of the digit being calculated toward the less significant digit. For example, in long division calculations where the square root of decimal data X is calculated digit by digit, the weight of the intermediate root Qn is refined by 10 times, so the magnification B = 10. Hereinafter, the magnification B is also referred to as the base B.

[0016] Conventional hardware square root extraction circuits often use a radix B of either 2 or 4. In this case, one iteration of the square root extraction operation yields one or two bits. A larger radix B reduces the number of iterations and may enable faster square root extraction, but it also increases the circuit size. Furthermore, the larger the radix B, the longer the processing time required for one iteration, which may result in the failure to achieve the desired performance.

[0017] Here, in the repeated calculation of square root extraction, the unit of precision (bit position) of the number to be obtained in a certain iteration is B -m For example, if you want to find the root (partial root) in two bits for each iteration of the square root operation, and you want to find the two bits just below the decimal point in the first iteration (i.e., 0.25=4 -1 is the least significant digit), the initial value of the variable m is 1. The procedure for square root calculation is shown below.

[0018] First, let n=0 and X=Q0 2 The initial value Q0 of the intermediate root and the initial value R0 of the residual are set so as to satisfy +R0 and be easy to calculate. For example, Q0=1 and R0=X-1 are set.

[0019] Next, the intermediate root Qn, which is an intermediate result of the square root, is updated by equation (2). Q[n+1]=Qn+qn …(2)

[0020] The symbol qn in equation (2) is called a partial root. The partial root qn is a partial root to be calculated each time the square root calculation is repeated, and is expressed as (an integer within a predetermined range) × B -m In typical hardware methods such as the SRT method, integers in a given range are often (-1, 0, +1) when B=2 (calculated one bit at a time), and often integers between -2 and +2 or between -3 and +3 when B=4 (calculated two bits at a time). For example, in the case of long division using decimal numbers (B=10), integers between 0 and 9 are selected.

[0021] The partial root qn is selected so that the intermediate root Q[n+1] found in the next iteration of the square root operation is as close as possible to the true square root, SQRT(X) (SQRT stands for square root). However, since the value of SQRT(X) is the object being found and cannot be known directly, it is usually judged by the residual Rn, and the partial root qn is selected so that the absolute value of the residual R[n+1] corresponding to the intermediate root Q[n+1] is as small as possible. For example, in long division using decimal numbers, the partial root qn is selected so that the residual R[n+1] is non-negative and smallest.

[0022] When the intermediate root Q[n+1] is updated by equation (2), the residual R[n+1] is expressed by equation (3) based on equations (1) and (2). "·" in the equation indicates the multiplication sign. R[n+1]=XQ[n+1] 2 =X-(Qn+qn) 2 =X-Qn 2 -2·Qn·qn-qn 2 =Rn-2 Qn qn-qn 2 …(3)

[0023] To reduce the absolute value of the intermediate root R[n+1], the intermediate roots Rn and 2·Qn·qn+qn 2 However, since it is not realistic to select the partial root qn precisely in consideration of the calculation time and circuit scale, some approximations are made.

[0024] First, qn in equation (3) 2 As the calculation progresses and the absolute value of the partial root qn becomes smaller, the absolute value of the term becomes several orders of magnitude smaller than the residual Rn and 2·Qn·qn. 2 By ignoring, we obtain equation (4). R[n+1]=Rn-2·Qn·qn …(4)

[0025] In equation (4), it is preferable to select the partial root qn so that the difference between the residual Rn and 2·Qn·qn is small. Therefore, if the partial root qn is selected to be close to Rn / 2·Qn, the right-hand side of equation (4) can be brought closer to zero, and the residual Rn[n+1] can be made small. Equation (5) shows the case where the partial root qn of equation (4) is set to Rn / 2·Qn. R[n+1]=Rn-2·Qn·(Rn / 2·Qn) …(5)

[0026] Dividing the residual Rn by the intermediate root Qn to find the partial root qn requires a divider, so further approximation is performed. Since the intermediate root Qn is an intermediate result in the process of finding the square root, it can be expected to be somewhat close to the true square root SQRT(X). Therefore, before repeatedly calculating the square root, an approximation k of 1 / SQRT(X) with a specified accuracy is found. Multiplying the numerator and denominator of Rn / 2·Qn in equation (5) by the found approximation k gives equation (6). Then, the partial root qn closest to the value k·Rn / 2·k·Qn is selected. R[n+1]=Rn-2·Qn·(k·Rn / 2·k·Qn) …(6)

[0027] Since the approximate value k is close to 1 / SQRT(X) and the intermediate root Qn is close to SQRT(X), k·Qn in equation (6) is approximately 1. Therefore, if the approximation is within an acceptable range, k·Rn / 2·k·Qn in equation (6) can be approximated to k·Rn / 2, and equation (7) is obtained. R[n+1]=Rn-2·Qn·(k·Rn / 2) …(7)

[0028] From equations (4) and (7), k·Rn / 2=qn, so it is possible to set the partial root qn to a value close to k·Rn / 2.

[0029] In hardware, division of an arbitrary value by 2 requires only a bit position change (i.e., a one-bit right shift of the bit value), so circuit delay is negligible. Therefore, the partial root qn can be obtained by changing the bit position of the most significant digit of k·Rn in equation (7). For example, in each iteration of the square root calculation, the partial root qn can be obtained by extracting a specific most significant bit of the value of k·Rn and changing the weight to one less significant digit.

[0030] In this embodiment, some values ​​are approximated and truncated, but any deviation (error) from the true value obtained in each iteration of the square root extraction can be corrected in subsequent iterations. Therefore, even if the generation unit qnGEN (described later) finds the partial root qn using k·Rn / 2 shown in equation (7) instead of table lookup, this does not significantly affect other parts of the square root extraction procedure.

[0031] The following (Case A) to (Case D) are possible deviations (errors) in values ​​during repeated calculations of the square root extraction. The algorithm for the square root extraction performed by the calculation processing device 10 is designed so that the sum of deviations (errors) shown in (Case A) to (Case D) is acceptable. (Case A) Fluctuations in partial roots qn caused by using SQRT(X) instead of intermediate roots Qn (Case B) Possible error in the approximation k of 1 / SQRT(X) (Case C) Errors caused by discarding lower digits when finding the partial root qn from the residual variable Tn (Case D) When selecting a partial root qn, the square term of the partial root qn (qn 2 ) and the resulting fluctuation of the partial root qn Below, (Case A) and (Case B) will be considered as examples.

[0032] In case A, the intermediate root Qn is furthest from SQRT(X) at the first intermediate root Q0 (initial value) of the iterative calculation. As the iterative calculation progresses, the intermediate root Qn approaches SQRT(X), and the deviation gradually decreases. In contrast, in the method described later in FIG. 5, in which the calculation starts with the initial value Q0 of the intermediate root Qn set to 1, the deviation in the first iterative calculation increases as the value X for which the square root is to be found deviates from 1. In this case, the initial value R0 of the residual Rn may become so large that it becomes difficult to converge even in the second and subsequent iterative calculations.

[0033] In this embodiment, when starting the square root extraction, the calculation processing device 10 acquires an approximation value k of 1 / SQRT(X) and simultaneously acquires an approximation value of SQRT(X) as the initial value Q0 of the intermediate root Qn. This allows the use of an intermediate root Q0 close to SQRT(X) from the first iteration of the square root extraction, thereby reducing the fluctuation due to the factor (Case A).

[0034] (Case B) is the sum of the elements of (Case B1) and (Case B2) shown below. (Case B1) is an error that occurs due to the precision (number of bits) of the approximate value k itself output from table TBL1. (Case B2) is an error component that occurs when input data X is quantized (rounded) in advance to match the resolution of table TBL.

[0035] In both cases (Case B1) and (Case B2), if you try to reduce the error, the circuit size of the table TBL1 will increase. Also, the more precision you increase in the number of bits of the approximate value k, the more difficult it becomes to iteratively calculate the approximate value k as the partial root qn or the squared value qn of the partial root qn. 2 In the process of multiplying by the multiplier, the number of bits of the multiplier increases, and the amount of circuitry and delay increases.

[0036] On the other hand, the larger the error in the approximate value k, the more the partial root qn generated by the generation unit qnGEN deviates from the correct value. In other words, there is a trade-off determined by the design values ​​of (Case B) between the accuracy obtained in one iterative calculation of the square root extraction and the amount of circuitry and delay. For this reason, it is preferable to appropriately set the approximate value k and the accuracy obtained in each iterative calculation, taking into account the balance between the number of bits of the approximate value k, the amount of circuitry, and the amount of delay.

[0037] The repeated square root calculation by the arithmetic processing device 10 is devised to find a multi-bit partial root qn without performing a cumbersome table search, thereby increasing the precision (number of bits) of the root found in one repeated calculation.

[0038] The arithmetic processing device 10 includes a plurality of registers REG (REG1, REG2, REG3, REG4, REG5, REG6), an even numbering circuit EXEVN that makes exponents even, a table TBL1, and selectors SEL (SEL1, SEL2, SEL3, SEL4). The arithmetic processing device 10 also includes multipliers MUL (MUL1, MUL2, MUL3, MUL4), adders ADD (ADD1, ADD2, ADD3, ADD4), a generator qnGEN that generates a partial root qn, a squaring circuit SQR, and a rounding processor RND. The operation of each selector SEL is controlled by a selection controller (not shown) installed in the arithmetic processing device 10.

[0039] For example, each register REG has a storage element such as a flip-flop or a latch. Selectors SEL1, SEL2, and SEL3 select data output from table TBL1 in the initial state when the arithmetic processing unit 10 executes a square root extraction instruction, and then select data to be transferred via the feedback loop. Selector SEL4 selects data output from adder ADD1 in the initial state when the arithmetic processing unit 10 executes a square root extraction instruction, and then selects data to be transferred via the feedback loop.

[0040] In FIG. 1 and in FIGS. 3 and 5 described below, thick arrows indicate the transfer of data represented by a set of two binary digits, a sum and a carry. The sum is an example of a value represented by a binary digit that does not include a carry component during addition, and the carry is an example of a binary digit that indicates whether or not a carry component occurs during addition. Thin arrows indicate the transfer of data represented by a normal binary digit. The normal binary digit is, for example, the same as the notation of the mantissa of floating-point number data in IEEE (Institute of Electrical and Electronics Engineers) 754 (floating-point arithmetic standard).

[0041] 1 is an example, and is determined to achieve an appropriate balance between the circuit size and the data propagation delay throughout the circuit. Therefore, if the calculation time fits within a predetermined number of clock cycles (design value), data may be transferred without using the sum and carry.

[0042] Register REG1 holds data X for which the square root is to be calculated. For example, the data X is floating-point number data, although not limited thereto. The even number conversion circuit EXEVN converts the exponent part of the data X to an even number and stores the data Xeven obtained by converting the exponent part to an even number in register REG2. When the exponent part is odd, the even number conversion circuit EXEVN doubles the mantissa part of the data X to store the data Xeven in register REG2. When the exponent part is even, the even number conversion circuit EXEVN stores the data X directly as data Xeven in register REG2. In the following explanation, it is assumed that data X is the mantissa part of floating-point number data.

[0043] Table TBL1 holds an approximation k (=1 / SQRT(X)) of the reciprocal of the square root of data X corresponding to each value of a predetermined number of upper bits of data X, and an initial value Q0 which is the approximation k (=SQRT(X)) of the square root of data X. The symbol SQRT indicates a square root. The initial value Q0 is the initial value of an intermediate root Qn which is set to find the accurate square root of data X. Table TBL1 also holds the product k·Q0 of the approximation k and the initial value Q0 and the product k·Q0 of the approximation k and the square of the initial value Q0 corresponding to each value of the approximation k and each value of the initial value Q0. 2 and hold.

[0044] The arithmetic processing device 10 refers to table TBL1 to obtain the approximate value k and the initial value Q0 corresponding to the data Xeven held in register REG2. A functional unit (not shown) of the arithmetic processing device 10 that refers to table TBL1 to obtain the approximate value k and the initial value Q0 is an example of an obtaining unit.

[0045] Furthermore, the calculation processing device 10 refers to the table TBL1 to obtain the product k·Q0 and the product k·Q0 corresponding to the approximate value k and the initial value Q0. 2 The arithmetic processing device 10 stores the obtained approximate value k in the register REG3, and stores the obtained initial value Q0 in the register REG4. In addition, the arithmetic processing device 10 stores the obtained product k·Q0 in the register REG5 as the initial value of the intermediate variable Sn.

[0046] The multiplier MUL1 calculates the product k·Q0 of the approximate value k obtained by the calculation processing unit 10 by referring to the table TBL1 and the initial value Q0, and outputs the product to the adder ADD1. The adder ADD1 functions as a subtractor SUB. The adder ADD1 calculates the product k·Q0 from the product k·X. 2 The initial value T0 of the residual variable Tn is calculated by subtracting the sum of the multiplier MUL1 and the adder ADD1 from the residual variable Tn, and the calculated initial value T0 is stored in the register REG6 via the selector SEL4. The multiplier MUL1 and the adder ADD1 are an example of a fifth arithmetic unit.

[0047] The generation unit qnGEN divides the residual variable Tn held in the register REG6 by 2 to obtain the partial root qn. The generation unit qnGEN is an example of a first calculation unit. Here, the residual variable Tn represents k·Rn shown in equation (7). The generation unit qnGEN may, for example, extract the significant most significant digits of the residual variable Tn held in the register REG6 up to a certain number of bits from the most significant bit, and divide the extracted most significant bits by 2 to obtain the partial root qn. In this case, the generation unit qnGEN may refer to the values ​​of digits lower than the least significant bit of the multiple bits to be extracted, and correct the partial root qn to reduce the extraction error.

[0048] For example, the generation unit qnGEN may add 2 to the found partial root qn when the sum and carry of the least significant digits are both 1. The generation unit qnGEN may add 1 to the found partial root qn when either the sum or carry of the least significant digits is 1. The generation unit qnGEN may output the found partial root qn without correction when the sum and carry of the least significant digits are both zero.

[0049] The squaring circuit SQR squares the partial root qn obtained by the generation unit qnGEN to obtain the squared value qn 2 to the multiplier MUL4. Since square numbers have specific properties, the squaring circuit SQR, which is specialized for squaring calculations, can be realized with a simpler circuit than a multiplier. Note that the arithmetic processing device 10 may use a multiplier or a circuit that outputs a squared value qn corresponding to each value of the partial root qn instead of the squaring circuit SQR. 2 The multiplier MUL4 may have a table for storing the approximation value k and the square value qn 2 Product of k·qn 2 and outputs the result to the adder ADD4. The squaring circuit SQR and the multiplier MUL4 are an example of a sixth calculation unit.

[0050] The multiplier MUL3 calculates the product 2·qn·Sn of the partial root qn and the double value of the intermediate variable Sn, and outputs the product to the adder ADD4. The adder ADD4 functions as a subtractor SUB. The adder ADD4 calculates the product 2·qn·Sn and the product k·qn from the residual variable Tn calculated last time. 2 The squaring circuit SQR, the multipliers MUL3, MUL3, and the adder ADD4 are an example of a second calculation unit.

[0051] The approximate value k, intermediate root Qn, and intermediate variable Sn are always positive values ​​during the calculation, while the residual variable Tn can be either positive or negative during the calculation. Furthermore, with each iteration of the loop, a predetermined number of bits from the most significant digit of the residual variable Tn become zero. This is due to the nature of the linear convergence method, in which the values ​​that the absolute value of the residual can take are reduced at a constant rate with each iteration of the loop. Bits that are determined to be zero due to this nature do not need to be stored.

[0052] Therefore, in the linear convergence method and the like, when storing the residual in a storage element such as a register, a method is often used in which the most significant digits that are confirmed to be zero are closed each time, and the storage position of the bit value is sequentially shifted to the most significant side. This allows the storage position of the bit value to always be the same. In this embodiment, too, by sequentially shifting the storage position of the bit value to the most significant side, the capacity of the storage element that holds the residual variable Tn can be reduced. Furthermore, since the same location can be referenced regardless of the number of times the loop processing is performed, it is possible to easily extract the most significant digits of the residual variable Tn when generating the partial root qn.

[0053] The multiplier MUL2 calculates the product k·qn of the approximate value k and the partial root qn and outputs the product to the adder ADD3. The adder ADD3 adds the product k·qn of the approximate value k and the partial root qn to the intermediate variable Sn to calculate a new intermediate variable S[n+1], and stores the calculated intermediate variable S[n+1] in the register REG5. The multiplier MUL2 and the adder ADD3 are an example of a third calculation unit.

[0054] The adder ADD2 adds the intermediate root Qn and the partial root qn to obtain a new intermediate root Qn[n+1], stores the obtained intermediate root Qn[n+1] in the register REG4, and outputs it to the rounding processor RND via the register REG7. The adder ADD2 is an example of a fourth calculation unit. The adder ADD2 calculates the intermediate root Qn without using the approximation value k.

[0055] The calculation of the intermediate root Qn by the adder ADD2 is performed in parallel with the calculation of the intermediate variable Sn during the iterative calculation. Therefore, the adder ADD2 can output the intermediate root Qn obtained by the predetermined number of iterative calculations as the calculation result (square root) to the rounding processor RND. In contrast, if the intermediate root Qn is not calculated in parallel with the intermediate variable Sn, a complex calculation is required after the iterative calculations are completed: to accurately divide the intermediate variable Sn by the approximate value k to find the square root. In this case, the circuit size increases and the calculation time for finding the square root increases.

[0056] When the intermediate root Qn has been obtained to a predetermined number of digits, the rounding processor RND converts the intermediate root Qn, which is input using the sum and carry, into a normal binary number.The rounding processor RND then rounds the intermediate root Qn, expressed in normal binary number, in a proper direction by referring to the sign of the residual variable Tn, and outputs the square root of the input data X (the operation result).When the input data X is floating-point number data, the rounding processor RND outputs the operation result as a mantissa in accordance with the output format of the floating-point number data.Note that when the intermediate root Qn has been obtained to a predetermined number of digits, the adder ADD2 may output the intermediate root Qn to the rounding processor RND.

[0057] Because the residual variable Tn is obtained by multiplying the residual Rn by a positive approximation value k, the positive / negative / zero state of the residual variable Tn is the same as the positive / negative / zero state of the residual Rn. Therefore, the rounding unit RND can perform rounding using the residual variable Tn instead of the residual Rn, thereby omitting the calculation of the residual Rn. In other words, the arithmetic processing device 10 does not need to have a circuit for calculating the residual Rn, thereby suppressing an increase in the circuit size.

[0058] The rounding processor RND has a function of converting a value expressed by a sum and a carry into a normal binary number and a function of rounding the normal binary number. Note that the rounding processor RND may receive an intermediate root Qn expressed into a normal binary number, in which case it does not have the function of converting into a normal binary number but only has the function of rounding.

[0059] By using carry save adders (CSA) that use a sum and carry for the adders ADD1-ADD4, the propagation delay time of the carry can be reduced. This makes it possible to keep the operation time almost constant regardless of the number of digits of the data to be operated on, and reduces the operation time compared to adders that perform operations using normal binary numbers.

[0060] The multipliers MUL1, MUL2, MUL3, and MUL4 output the operation result as a sum and a carry. For example, a typical multiplier often has a front-stage section called a multiplication array or multiplication tree that outputs the operation result as a sum and a carry, and a back-stage section that converts the operation result expressed as a sum and a carry into a normal binary number. The multipliers MUL1, MUL2, MUL3, and MUL4 of this embodiment can be implemented using only the front-stage section, excluding the back-stage section, allowing for a reduced circuit scale compared to typical multipliers.

[0061] Furthermore, one input of multipliers MUL2 and MUL4 and two inputs of multiplier MUL3 receive a sum and a carry. In this case, multipliers MUL2, MUL3, and MUL4 may first convert the received sum and carry into normal binary numbers before performing multiplication, or may convert them into predetermined integers every two or three digits using Booth encoding. Alternatively, multipliers MUL2, MUL3, and MUL4 may perform multiplication by using the distributive law, such as "(s+c)·a=s·a+c·a," where "s" is the sum and "c" is the carry. However, the multiplication method when receiving a sum and a carry is not limited to the above.

[0062] Incidentally, square root or division circuits using the SRT method and other techniques sometimes use a technique called "on-the-fly conversion." "On-the-fly conversion" takes advantage of the fact that in a circuit that holds intermediate calculation results for a root or quotient (for example, intermediate root Qn), the final result can only take on two closely spaced values ​​in its normal binary representation from the most significant digit to the final calculation digit. Instead of using a sum and carry, the intermediate calculation results are stored in two normal binary representations, and are converted to normal binary while adding the partial root qn.

[0063] With "on-the-fly conversion," rounding can be performed faster than when the intermediate root Qn is represented by a sum and carry, and the amount of circuitry can be reduced compared to when a separate circuit for converting the intermediate root Qn back to a normal binary number is provided. Furthermore, the size of the storage element, such as a register, that holds the intermediate root Qn can be made approximately the same as when it is represented by a sum and carry. This embodiment can also apply the "on-the-fly conversion" technique, which holds the intermediate root Qn as a normal binary number rather than as a sum and carry.

[0064] Fig. 2 shows an example of the operation of the arithmetic processing device 10 of Fig. 1. That is, Fig. 2 shows an example of an arithmetic processing method of the arithmetic processing device 10 for obtaining the square root of input data X by the arithmetic processing device 10. In the following explanation, it is assumed that data Xeven, whose exponent has been made even by the even number making circuit EXEVN of Fig. 1, is data X.

[0065] First, in step S10, the arithmetic processing device 10 sets a variable n to 0 and sets a variable m to an initial value (for example, 1). Next, in step S11, the arithmetic processing device 10 refers to table TBL1 to acquire an approximate value k (=approximate value of 1 / SQRT(X)) and an initial value Q0 of an intermediate root Qn (=approximate value of SQRT(X)). Furthermore, the arithmetic processing device 10 refers to table TBL1 based on the acquired approximate value k and initial value Q0 to acquire an initial value S0 of an intermediate variable Sn and an initial value T0 of a residual variable Tn.

[0066] Next, in step S12, the calculation processing device 10 generates a partial root qn that is a value close to Tn / 2 by dividing the residual variable Tn by 2 using the generation unit qnGEN. Next, in step S13, the calculation processing device 10 adds the intermediate root Qn and the partial root qn using the adder ADD2 to obtain the intermediate root Qn[n+1] to be used in the next iterative calculation.

[0067] The arithmetic processing device 10 also uses the multiplier MUL2 and the adder ADD3 to add the product k·qn of the approximate value k and the partial root qn to the intermediate variable Sn to obtain the intermediate variable S[n+1] to be used in the next iterative calculation. The arithmetic processing device 10 also uses the squaring circuit SQR, multipliers MUL3, MUL4, and adder ADD4 to obtain the product 2·qn·Sn and the product k·qn from the residual variable Tn. 2 and is subtracted to obtain the residual variable T[n+1] to be used in the next iterative calculation.

[0068] Next, in step S14, if the root of a predetermined number of digits (i.e., intermediate root Qn) is found, the arithmetic processing device 10 performs step S16, and if the root of a predetermined number of digits has not been found, the arithmetic processing device 10 performs step S15. In step S15, the arithmetic processing device 10 increments the variables n and m by 1, and returns to the operation of step S12.

[0069] In step S16, the arithmetic processing device 10 uses the rounding processing unit RND to perform post-processing on the intermediate root Qn for which a predetermined number of digits has been obtained. For example, in the post-processing, the arithmetic processing device 10 converts the intermediate root Qn input using the sum and carry into a normal binary number, and then performs rounding by referring to the sign of the residual variable Tn. Then, the arithmetic processing device 10 outputs the rounded value as the square root of the input data X (the calculation result), and ends the square root calculation process shown in FIG. 2.

[0070] As described above, in this embodiment, by repeatedly performing the square root extraction using the approximation k of the reciprocal of the square root of the input data X, the number of data bits used in the various calculations of the square root extraction can be reduced compared to the conventional technology, thereby enabling a smaller circuit scale of the arithmetic processing device 10. By using the reduced circuit delay resulting from the reduced circuit scale for other calculation elements, the number of bits of the partial root qn obtained in one iterative calculation can be increased. As a result, the square root extraction can be performed faster than the conventional technology. In other words, by increasing the number of bits of the partial root obtained in one iterative calculation while suppressing an increase in circuit scale, the square root extraction can be performed faster.

[0071] The generation unit qnGEN obtains the partial root qn by dividing the residual variable Tn obtained using the approximate value k by 2, so the partial root qn can be obtained using a simple bit shift circuit. Therefore, compared to obtaining the partial root qn using a table, the circuit size of the generation unit qnGEN can be reduced, and the time required to obtain the partial root qn can be shortened. Furthermore, by dividing only the significant upper bits of the residual variable Tn by 2, the circuit size can be further reduced.

[0072] The table TBL1 holds an approximation value of the square root of the input data X as the initial value Q0 of the intermediate root Qn, and therefore the accuracy of the initial value Q0 can be improved compared to when the initial value Q0 is fixed to 1, etc. In addition, the table TBL1 stores the product k·Q0 (=S0) of the approximation value k and the initial value Q0, and the product k·Q0 (=S0) of the approximation value k and the square of the initial value Q0. 2 and hold.

[0073] As a result, the adder ADD2 can accurately find the intermediate root Qn from the first iterative calculation. The adder ADD3 can accurately find the intermediate variable Sn from the first iterative calculation. The adder ADD1 can accurately find the initial value T0 of the residual variable Tn, and the generation unit qnGEN can accurately find the partial root qn from the first iterative calculation using the initial value T0.

[0074] The rounding unit RND performs rounding of the intermediate root Qn by referring to the sign of the residual variable Tn whose sign is the same as that of the residual Rn, instead of using the sign of the residual Rn. This eliminates the need for a circuit for calculating the residual Rn, thereby further reducing the circuit scale of the arithmetic processing device 10.

[0075] The various adders ADD and various multipliers MUL mounted on the arithmetic processing device 10 receive at least one of their inputs as a sum and a carry, and output the calculation result as a sum and a carry. This makes it possible to improve the calculation speed or reduce the circuit size compared to when the sum and carry are not used.

[0076] The inventors have studied the number of iterative calculations required to calculate the square root of the mantissa (24 bits) of single-precision floating-point number data using the arithmetic processing device 10 of Fig. 1 and the arithmetic processing device 20 of Fig. 5 (described later). As a result, the arithmetic processing device 20 of Fig. 5 calculated the partial root qn by 2 bits in each iteration, and thus calculated the square root after 14 iterations. In contrast, the arithmetic processing device 10 of Fig. 1 was found to be able to calculate the partial root qn by 6 bits in each iteration, and thus to calculate the square root after about six iterations.

[0077] Fig. 3 shows an example of a processing device according to another embodiment. Elements similar to those of the processing device 10 in Fig. 1 are given the same reference numerals, and detailed description thereof will be omitted. The processing device 10A shown in Fig. 3 separates the residual variable Tn of the processing device 10 in Fig. 1 into an intermediate variable Vn, which is a component of the squared term, and a residual variable Un, which is a component other than the squared term, and performs a decomposition of the calculation for updating the residual variable T[n+1]. The intermediate variable Vn is k·qn 2 and the residual variable Un is given by Tn-2·qn·Sn.

[0078] For this reason, the arithmetic processing device 10A is obtained by adding a register REG7, a selector SEL5, and an adder ADD5 that functions as a subtractor SUB to the arithmetic processing device 10 of FIG. 1. The arithmetic processing device 10A also has an adder ADD6 instead of the adder ADD4 of FIG. 1. The adder ADD6 functions as the subtractor SUB in the same way as the adder ADD4. The adder ADD6 is an example of an eighth arithmetic unit.

[0079] In other words, the arithmetic processing device 10A has adders ADD5 and ADD6 that share the function of the adder ADD4 in Fig. 1. As a result, the squaring circuit SQR and multiplier MUL4 are removed from the main path of the repeated calculation that loops between the register REG6 and the adder ADD6, and are relocated to the path that calculates the intermediate variable Vn.

[0080] The register REG6 that holds the residual variable Un may store either a positive or negative value, similar to the register REG6 that holds the residual variable Tn in Figure 1. On the other hand, the register REG7 that holds the intermediate variable Vn stores either zero or a positive value.

[0081] In Fig. 1, the path returning to register REG6 via register REG6, generator qnGEN, squaring circuit SQR, multiplier MUL4, and adder ADD4 is the delay bottleneck (critical path). In contrast, the critical path in Fig. 3 is the path returning to register REG6 via register REG6, generator qnGEN, multiplier MUL3, and adder ADD6, or the path returning to register REG6, generator qnGEN, squaring circuit SQR, and multiplier MUL4.

[0082] 1, the arithmetic processing device 10A can average out delays and reduce the amount of delay in the critical path. As a result, the speed of the circuit that performs repeated square root calculations can be increased, and the time required for the arithmetic processing device 10A to find the square root can be reduced compared to the time required for the arithmetic processing device 10 to find the square root.

[0083] In the first few iterations, the squared term k qn 2 Since the influence of is relatively large, the squared term k qn 2 If is ignored, the effect of is slightly larger than that of other error components, and the calculation may not be well balanced. This may require a circuit that calculates a larger number of bits.

[0084] In this case, for example, for the initial few iterations, perform one iteration in two cycles, and use the squared term k qn 2 It is possible to wait until it is reflected in the residual variable Un(Tn) before using it to calculate the partial root qn. Alternatively, as a way to deal with this, for example, in the first-order convergence method, a method can be combined in which the shift amount of the residual, etc. is reduced only for the initial iterative calculations in which the error is large, slowing down the convergence speed and allowing for the error.

[0085] The calculation processing device 10A calculates the intermediate variable Vn after calculating the residual variable Un. In other words, the calculation processing device 10A generates the intermediate variable Vn using the partial root qn obtained in one iteration of the square root extraction, and uses the generated intermediate variable Vn in the next iteration to calculate the next residual variable Un.

[0086] In the initial state in which the arithmetic processing device 10A executes the square root extraction command, the selector SEL5 selects the initial value V0 (=0) of the intermediate variable Vn, and then selects the intermediate variable V[n+1] (=k·qn 2 The register REG7 outputs the initial value V0 or the intermediate variable V[n+1] selected by the selector SEL5 to the adder ADD5 as the intermediate variable Vn.

[0087] The adder ADD1 converts the product k·X to the product k·Q0 2 The initial value U0 of the residual variable Un is calculated by subtracting the residual variable U from the sum of the initial value U0 and the residual variable U[n+1]. The initial value U0 is stored in the register REG6 via the selector SEL4. The register REG6 outputs the retained initial value U0 or the residual variable U[n+1] received from the adder ADD6 via the selector SEL4 as the residual variable Un to the generator qnGEN and the adder ADD5.

[0088] The generation unit qnGEN divides the residual variable Un received from the register REG6 by the value 2 to obtain the partial root qn. In other words, the generation unit qnGEN calculates the partial root qn using the residual variable Un that can be calculated first, rather than the residual variable Tn. This is because if the absolute value of the partial root qn is smaller than a certain value, the product k qn 2 This is because the absolute value of is small enough to be ignored compared to the residual variable Tn (i.e., the difference between the residual variables Tn and Un is small). This results in the product k qn which contributes little to generating the partial root qn in the next iterative calculation. 2 can be separated from the path from the generator qnGEN to the adder ADD6.

[0089] As the square root calculation continues, if the bits to be calculated for the intermediate root Qn reach the lower bits, or if accurate rounding is required, small values ​​that were negligible in the previous iteration can become a problem. 2 Although accurate calculation of the residual variable Tn including 2 can be ignored.

[0090] The calculation processing device 10A calculates the squared term k·qn so that the calculation of the residual variable U[n+1] does not become a critical path of the calculation cycle. 2 is stored in the register REG7 as V[n+1] during the calculation and carried over to the next calculation cycle. Then, the calculation processing device 10A continues the calculation using the adder ADD5 in parallel with the generation of the next partial root qn and other calculations, and calculates the squared term k qn 2 In the next calculation cycle, the variable n is incremented by 1, so the output of the adder ADD5 is expressed as Tn=Un-Vn (not T[n+1]=U[n+1]-V[n+1]).

[0091] The adder ADD5 converts the residual variable Un into the intermediate variable Vn (= k qn 2 ) to obtain a new residual variable Tn, and outputs the obtained residual variable Tn to the adder ADD4 and the rounding processor RND. That is, the adder ADD5 adds the residual variable Un and the intermediate variable Vn to generate the residual variable Tn. The adder ADD5 is an example of a seventh arithmetic unit.

[0092] The adder ADD6 subtracts the product 2·qn·Sn from the residual variable Tn received from the adder ADD5 to obtain a new residual variable U[n+1], and stores the obtained residual variable U[n+1] in the register REG6. Here, the intermediate variable Vn is the product k·qn 2 Therefore, the residual variable U[n+1] output by the adder ADD6 is equal to the residual variable T[n+1] output by the adder ADD4 in Fig. 1. Also, the residual variable Tn output by the adder ADD5 is equal to the residual variable T[n+1] output by the register REG6 in Fig. 1.

[0093] Fig. 4 shows an example of the operation of the arithmetic processing device 10A of Fig. 3. That is, Fig. 4 shows an example of an arithmetic processing method of the arithmetic processing device 10A for calculating the square root of input data X by the arithmetic processing device 10A. The same step numbers are used for operations similar to those of Fig. 2, and detailed descriptions thereof will be omitted. In Fig. 4, step S11A is performed instead of step S11 of Fig. 2, and step S13A is performed instead of step S13 of Fig. 2.

[0094] In step S11A, instead of acquiring the initial value T0 of the residual variable Tn in step S11 of Fig. 2, the calculation processing device 10A acquires the initial value U0 of the residual variable Un and sets the initial value V0 of the intermediate variable Vn to 0. Other operations in step S11A are the same as those in step S11 of Fig. 2.

[0095] In step S13A, the calculation processing device 10A calculates a residual variable Tn, a residual variable U[n+1], and an intermediate variable V[n+1], instead of calculating the residual variable T[n+1] in step S13 of FIG. 2. The residual variable Tn is calculated using the adder ADD5 of FIG. 3. The residual variable U[n+1] is calculated using the multiplier MUL3 and adder ADD6, utilizing the calculation result of the adder ADD5. The intermediate variable V[n+1] is calculated using the squaring circuit SQR and multiplier MUL4. Other operations in step S13A are similar to those in step S13 of FIG. 1.

[0096] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, by repeatedly calculating the square root using an approximation k of the reciprocal of the square root of the input data X, the number of bits of data used in the various calculations of the square root calculation can be reduced compared to the conventional method, and the circuit scale of the calculation processing device 10A can be made smaller. This allows the number of bits of the partial root qn obtained in one iterative calculation to be increased, and the square root calculation can be performed faster than the conventional method.

[0097] Furthermore, in this embodiment, the squaring circuit SQR and the multiplier MUL4 are removed from the main path of the iterative calculation loop between the register REG6 and the adder ADD6 and are relocated to the path for calculating the intermediate variable Vn. This allows the arithmetic processing device 10A to average out delays and reduce the amount of delay in the critical path compared to the arithmetic processing device 10 of FIG. 1. As a result, the circuit that performs the iterative square root calculation can be speeded up, and the time required for the arithmetic processing device 10A to calculate the square root can be shortened compared to the time required for the arithmetic processing device 10 to calculate the square root.

[0098] Fig. 5 shows an example of another arithmetic processing device. Elements similar to those of the arithmetic processing device 10 in Fig. 1 are given the same reference numerals and detailed description thereof will be omitted. The arithmetic processing device 20 shown in Fig. 3 does not use the approximate value k used in the arithmetic processing device 10 in Fig. 1, but instead finds the partial root qn by referring to table TBL2.

[0099] The arithmetic processing unit 20 includes a plurality of registers REG (REG1, REG2, REG4, REG5), an even numbering circuit EXEVN, and selectors SEL2 and SEL3. The arithmetic processing unit 20 also includes an initialization circuit INIT, a table TBL2 (qn determination circuit) used to determine the partial root qn, a multiplier MUL3, adders ADD2 and ADD4, and a rounding processing unit RND.

[0100] The functions of the registers REG1, REG2, REG4, and REG5 are the same as the functions of the registers REG1, REG2, REG4, and REG5 in Figure 1, respectively. The functions of the selectors SEL2 and SEL3 are the same as the functions of the selectors SEL2 and SEL3 in Figure 1, respectively. The function of the adder ADD2 is the same as the function of the adder ADD in Figure 1. The calculation of the above-mentioned equation (2) is realized by the adder ADD2.

[0101] The initialization circuit INIT sets the initial value Q0 of the intermediate root Qn and the initial value R0 of the residual Rn based on the data Xeven, which is output from the register REG2 and is obtained by making the exponent part of the data X even. Here, the initial values ​​Q0 and R0 are set as follows:2 +R0 and are set to values ​​that are easy to calculate. For example, the initialization circuit INIT sets Q0=1 and R0=X-1.

[0102] Table TBL2 outputs a partial root qn corresponding to the upper few bits of the intermediate root Qn output from register REG4 and the residual Rn output from register REG5. For example, when the radix B is 4, the qn determination circuit may obtain the partial root qn by processing a 17-bit input signal and searching 1024 entries included in table TBL2.

[0103] The multiplier MUL3 calculates the product 2·qn·Qn of the partial root qn and the double value of the intermediate root Qn, and outputs the result to the adder ADD4. The adder ADD4 functions as a subtractor SUB. The adder ADD4 calculates the product 2·qn·Qn and the square value qn of the partial root qn from the residual Rn calculated last time. 2 The new residual R[n+1] is calculated by subtracting the residual R[n+1] from the sum of the first and second inputs, and the calculated residual R[n+1] is stored in the register REG5 via the selector SEL3. The calculation of the above-mentioned equation (3) is realized by the multiplier MUL3, the squaring circuit SQR, and the adder ADD4.

[0104] To find the exact optimal partial root qn, a procedure similar to solving a quadratic equation is required. However, when finding the square root using hardware such as the arithmetic processing device 20, the partial root qn is often found by table lookup (combinational circuit). The arithmetic processing device 20 searches the table TBL2 using the residual Rn and intermediate root Qn as keys. Therefore, the table TBL2 has a two-dimensional structure that obtains the partial root qn based on two elements, the intermediate root Qn and the residual Rn.

[0105] Here, if all bits of the residual Rn and the intermediate root Qn are referenced, the circuit scale of table TBL2 increases, and the search time for table TBL2 also increases. For this reason, table TBL2 has a simple configuration that uses the most significant bits of each of the residual Rn and the intermediate root Qn. However, table TBL2 is designed so that the desired partial root qn does not deviate from the optimal partial root within a range that does not cause any problems.

[0106] Furthermore, increasing the resolution (precision) of table TBL2 to increase the number of options for partial root qn (i.e., increasing the radix B) also increases the circuit size of table TBL2. For this reason, in order to suppress the increase in circuit size, table TBL2 is designed so that the partial root qn obtained in one iterative calculation is on the order of several bits. In other words, it is difficult to obtain a partial root qn of, for example, 3 bits or more using a high-resolution table TBL2.

[0107] In the SRT method, the options for the partial roots qn are designed to have some margin (redundancy) so that even if the partial roots qn deviate from the optimal partial root, the intermediate roots Qn will be corrected in the next and subsequent iterative calculations. For example, in the SRT method, when the base B is 2, the options are set to (-1, 0, +1) rather than (0, 1).

[0108] During one of the multiple iterations, it is possible that 1 is obtained as the partial root qn for that digit when 0 is optimal. In this case, the residual Rn is oversubtracted when updating, leaving a negative residual Rn, and in the next iteration, -1 is obtained as the partial root qn. As a result, the unstable intermediate root Qn is recovered and corrected in the next iteration.

[0109] Fig. 6 is a flow diagram showing an example of the operation of the arithmetic processing device 20 of Fig. 5. Detailed description of the same operations as those of Fig. 2 will be omitted. The operations of steps S20, S24, S25, and S26 are the same as the operations of steps S10, S14, S15, and S16 of Fig. 2, respectively.

[0110] In step S21, the arithmetic processing unit 20 sets the initial values ​​Q0 and R0 by the initialization setting circuit INIT as follows: 2+R0. Next, in step S22, the arithmetic processing device 20 searches the table TBL2 to acquire the partial root qn. In the first iterative calculation, the arithmetic processing device 20 acquires the partial root qn using the upper few bits of the initial value Q0 and the initial value R0. In the second and subsequent iterative calculations, the arithmetic processing device 20 acquires the partial root qn using the upper few bits of the intermediate root Qn and the residual Rn.

[0111] Next, in step S23, the calculation processing device 20 performs calculation of equation (2) using the adder ADD2 to obtain the intermediate root Q[n+1] to be used in the next iterative calculation. The calculation processing device 20 also performs calculation of equation (3) using the multiplier MUL3, the squaring circuit SQR, and the adder ADD4 to obtain the residual R[n+1] to be used in the next iterative calculation. After step S23, the calculation processing device 20 then performs step S24.

[0112] 1 to 4, an approximation value k is used in the repeated calculations for updating the intermediate root Qn and the residual Rn in FIGS. 5 and 6. For example, in the embodiment shown in FIGS. 1 to 4, the intermediate variable Sn is set to k·Qn, the residual variable Tn (or Un) is set to k·Rn, and the square root is calculated by repeatedly updating the intermediate variable Sn and the residual variable Tn (or Un). To calculate the partial root qn, the residual variable Tn (or Un) is used instead of k·Rn. Also, instead of updating the residual Rn using the intermediate root Qn, the residual variable Tn (or Un) is updated using the intermediate variable Sn.

[0113] If the square root calculation process involves multiplication between multiple bits, a large-scale multiplier is required. However, in the embodiment shown in FIGS. 1 to 4, among the circuits that perform iterative calculations, the multiplication between multiple bits is performed only by multiplier MUL3, which calculates 2 qn Sn. Furthermore, only the intermediate variable Sn has a large number of bits in the multiplication by multiplier MUL3, and the partial root qn has a number of bits (for example, about 8 bits) that is desired to be calculated in one iteration.

[0114] A multiplier can be configured with a number of logic stages proportional to the logarithm of the number of digits in the multiplier or multiplicand, whichever is smaller. Therefore, the multiplier MUL3 that performs 2·qn·Sn only requires a circuit scale of a few logic stages. Furthermore, the circuit scale and delay can be adjusted by adjusting the number of bits required in one iterative calculation. Because multipliers MUL1, MUL2, and MUL4 perform multiplication of small numbers of bits, such as the approximate value k or the partial root qn, the circuit scale can be smaller than that of multiplier MUL3 that calculates 2·qn·Sn.

[0115] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0116] 10, 10A, 20 Processing unit ADD(ADD1, ADD2, ADD3, ADD4) adder ADD(ADD5, ADD6) adder EXEVN Even numbering circuit k approximation MUL(MUL1, MUL2, MUL3, MUL4) Multiplier Q0 initial value qn partial root Qn intermediate root qnGEN generator REG (REG1, REG2, REG3, REG4) registers REG (REG5, REG6, REG7) registers RND Rounding processor Rn residual SEL (SEL1, SEL2, SEL3, SEL4) Selector SQR squaring circuit Sn intermediate variable T0 initial value Tables TBL1 and TBL2 Tn residual variables Un residual variables Vn intermediate variable X Data

Claims

1. A processing device that calculates the square root of input data X by repeatedly calculating the square root so as to reduce a residual, which is the difference between the square value of an intermediate root obtained during the calculation and the input data, an acquisition unit that acquires an approximate value k by referring to a table that stores an approximate value k of the reciprocal of the square root of input data X; a first calculation unit that uses a residual variable Tn indicating a residual calculated based on an approximate value k to calculate a partial root qn that is a bit to be calculated among the square roots to be calculated; The product 2·qn·Sn of the doubled value of the intermediate variable Sn indicating the intermediate root obtained based on the approximate value k and the partial root qn, and the product k·qn of the approximate value k and the squared value of the partial root qn ２ a second calculation unit that calculates a new residual variable Tn by subtracting the above from the previously calculated residual variable Tn; a third calculation unit that calculates a new intermediate variable Sn by adding a product k·qn of an approximate value k and a partial root qn to a previously calculated intermediate variable Sn; a fourth calculation unit that calculates a new intermediate root Qn by adding the previously calculated intermediate root Qn and the partial root qn calculated by the first calculation unit, and outputs the calculated intermediate root Qn with a predetermined number of digits as the square root of the input data X; A processing unit having:

2. The first calculation unit divides a predetermined number of most significant bits of the residual variable Tn by 2 to obtain a partial root qn. The processor according to claim 1 .

3. The acquisition unit acquires an approximation value of the square root of the input data X as an initial value Q0 of the intermediate root Qn. The processing unit according to claim 1 or 2.

4. From the product k·X of the approximation value k and the input data X, the product k·Q0 of the approximation value k and the square of the initial value Q0 ２ a fifth calculation unit that calculates an initial value T0 of a residual variable Tn by subtracting the first calculation unit and the second calculation unit use an initial value T0 as a residual variable Tn calculated previously in a first calculation; the third calculation unit uses the product k·Q0 of the approximation value k and the initial value Q0 as the intermediate variable Sn calculated previously in the first calculation, In the first calculation, the fourth calculation unit uses the initial value Q0 as the intermediate root Qn obtained previously. The processor according to claim 3 .

5. a rounding processing unit that rounds the intermediate root Qn output as a square root by the fourth calculation unit using a residual variable Tn; The processor according to any one of claims 1 to 4.

6. The first calculation unit, the second calculation unit, the third calculation unit, and the fourth calculation unit perform calculations using values ​​expressed in binary numbers not including a carry when added and binary numbers indicating whether or not a carry is to be carried when added to the binary numbers, and output calculation results as values ​​expressed in binary numbers not including a carry when added and values ​​expressed in binary numbers indicating a carry when added. The processor according to any one of claims 1 to 5.

7. The second calculation unit The product k·qn of the approximate value k and the square value of the partial root qn calculated by the first calculation unit ２ a sixth calculation unit for calculating The residual variable Tn calculated last time and the product k·qn calculated by the sixth calculation unit ２ The difference between Tn-k and qn ２ a seventh calculation unit for calculating The product 2·qn·Sn of the partial root qn and the double value of the intermediate variable Sn is converted into the difference Tn−k·qn calculated by the seventh calculation unit. ２ an eighth calculation unit that subtracts from the residual variable Tn to obtain a new residual variable Tn; 5. The processor according to claim 1, further comprising:

8. A processing method for a processing device for repeatedly calculating the square root of input data X so as to reduce a residual, which is the difference between the square value of an intermediate root obtained during the calculation and the input data, comprising: an acquisition unit included in the arithmetic processing device acquires an approximate value k by referring to a table in which an approximate value k of a reciprocal of a square root of input data X is stored; a first calculation unit included in the calculation processing device uses a residual variable Tn indicating a residual calculated based on an approximate value k to calculate a partial root qn which is a bit to be calculated in the square root to be calculated; The second calculation unit of the calculation processing device calculates a product 2·qn·Sn of the partial root qn and a doubled value of the intermediate variable Sn indicating the intermediate root calculated based on the approximate value k, and a product k·qn of the partial root qn and a squared value of the approximate value k. ２ and subtract it from the previously calculated residual variable Tn to obtain a new residual variable Tn, a third calculation unit included in the calculation processing device adds a product k·qn of the approximation value k and the partial root qn to the previously calculated intermediate variable Sn to calculate a new intermediate variable Sn; A fourth calculation unit of the calculation processing device calculates a new intermediate root Qn by adding the intermediate root Qn calculated previously and the partial root qn calculated by the first calculation unit, and outputs the intermediate root Qn with a predetermined number of digits calculated as the square root of the input data X. Arithmetic processing method.

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