printed circuit board

Abstract

To provide a printed circuit board capable of performing die-to-die interconnection in a printed circuit board for mounting electronic components, semiconductor chips, etc., implementing the function of an element in addition to the die-to-die interconnection, and improving reliability.SOLUTION: A printed circuit board includes a substrate portion having a first insulating layer and a first wiring layer disposed on or inside the first insulating layer, and a connecting structure that is disposed on or inside the substrate portion, and includes a plurality of first dielectric layers, a first metal layer and a second metal layer disposed on the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer. Each of the plurality of first dielectric layers includes an organic material, and the distance between the first metal layer and the second metal layer is shorter than the distance between the first metal layer and the second wiring layer.SELECTED DRAWING: Figure 3a

Description

[Technical Field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, multi-chip packages containing memory chips such as high-bandwidth memory (HBM) and processor chips such as central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs) are being used to handle exponentially increasing data processing. In particular, as the number of CPU and GPU cores in server products has rapidly increased, die-splitting technology, which can effectively increase the number of cores, has become commonplace, creating a demand for die-to-die interconnection. Research is ongoing to design substrates that include interconnection structures for die-to-die interconnection, thereby simplifying substrate and package structures and improving the reliability of interconnection structures and increasing yields. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present disclosure is to provide a printed circuit board capable of providing die-to-die interconnections on a printed circuit board for mounting electronic components, semiconductor chips, and the like.

[0004] Another of several objects of the present disclosure is to provide a printed circuit board including interconnect structures that can perform device functions in addition to die-to-die interconnects.

[0005] Another of several objects of the present disclosure is to provide a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of several solutions proposed through the present disclosure is to provide a printed circuit board including a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a connecting structure disposed on or within the substrate portion, the connecting structure including a plurality of first dielectric layers, first and second metal layers disposed on the plurality of first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer, each of the plurality of first dielectric layers comprising an organic material, and the distance between the first metal layer and the second metal layer being closer than the distance between the first metal layer and the second wiring layer.

[0007] Another of several solutions proposed through the present disclosure is to provide a printed circuit board including a connecting structure including a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a capacitor portion disposed on or within the substrate portion and consisting of a first dielectric layer and a first metal layer disposed on or within the first dielectric layer, and a wiring portion consisting of a second insulating layer and a second wiring layer disposed on the second insulating layer, wherein the first metal layer of the capacitor portion includes a pair of metal plates facing each other, and the first dielectric layer of the capacitor portion includes an organic material. [Effects of the Invention]

[0008] Among the various advantages of the present disclosure, one advantage is that a printed circuit board capable of performing die-to-die interconnection on a printed circuit board for mounting electronic components, semiconductor chips, and the like can be provided.

[0009] Among other advantages of the present disclosure is the provision of a printed circuit board including interconnect structures that can perform device functions in addition to die-to-die interconnects.

[0010] Another advantage of the present disclosure is that it is possible to provide a printed circuit board that can improve reliability. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3a] FIG. 1 is a cross-sectional view of a printed circuit board according to an example. [Figure 3b] FIG. 1 is a cross-sectional view of a printed circuit board according to an example. [Figure 4] FIG. 10 is a cross-sectional view schematically illustrating a printed circuit board according to another example. [Figure 5] FIG. 10 is a cross-sectional view schematically showing a printed circuit board according to another example. [Figure 6a] 1 is a cross-sectional view schematically illustrating a connection structure of a printed circuit board according to an example. [Figure 6b] 1 is a perspective view schematically illustrating a capacitor portion of a connection structure of a printed circuit board according to an example; [Figure 7a] FIG. 10 is a cross-sectional view schematically showing a connection structure according to another example. [Figure 7b] FIG. 10 is a perspective view schematically illustrating a capacitor portion of a connecting structure according to another example. [Figure 8a] FIG. 10 is a cross-sectional view schematically showing a connection structure according to another example. [Figure 8b] FIG. 10 is a perspective view schematically showing a capacitor portion of a connecting structure according to another example. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present disclosure will be described below with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for clarity.

[0013] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0014] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components (described later) to form various signal lines 1090.

[0015] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with one another. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0016] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of numerous other wireless or wired standards or protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0017] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-firing ceramics (LTCC), electro-magnetic interference (EMI) filters, multi-layer ceramic capacitors (MLCC), etc. However, the other components 1040 may include, but are not limited to, passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0018] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0019] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0020] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0021] Referring to the drawing, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Furthermore, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-described chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0022] printed circuit board 3a and 3b are schematic cross-sectional views of a printed circuit board according to an example.

[0023] 3a, a printed circuit board according to an example includes a substrate unit 100 and a connecting structure 200. The substrate unit 100 is a part that realizes a signal path of the printed circuit board, and the connecting structure 200 corresponds to a part that connects components such as chips to each other. The connecting structure 200 is a part that realizes a fine signal path corresponding to an electronic component such as a fine chip, and multiple electronic components such as chips can be arranged across the connecting structure 200, corresponding to a part that interconnects electronic components such as chips and maintains an electrical signal path.

[0024] The substrate unit 100 may include a first insulating layer 110, a first wiring layer 120 disposed on or within the first insulating layer 110, and a cavity penetrating at least a portion of the first insulating layer 110. The substrate unit 100 may include a first via layer 130 penetrating at least a portion of the first insulating layer 110 to connect the first wiring layers 120 to each other.

[0025] The first insulating layer 110 may be composed of multiple insulating layers, and each first insulating layer 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the first insulating layer 110 may be, but is not limited to, insulating materials such as PPG (Prepreg) and RCC (Resin Coated Copper), and may also include ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, BT (Bismaleimide Triazine), and the like. However, the insulating material is not limited thereto, and other polymer materials with excellent rigidity may also be used as needed.

[0026] The first wiring layer 120 may be composed of multiple wiring layers, and each first wiring layer 120 may include a metal material. Metal materials include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each first wiring layer 120 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. Each first wiring layer 120 may perform various functions depending on the design of the corresponding layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as data signals. These patterns may include line patterns, plane patterns, and / or pad patterns.

[0027] The first via layer 130 may be composed of multiple via layers, and each first via layer 130 may include a microvia. The microvia may be a filled via that fills a via hole or a conformal via that is arranged along the wall surface of a via hole. The microvias may be arranged in a stacked and / or staggered manner. Each first via layer 130 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each connection via layer may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of the chemical copper as the electroless plating layer. The first via layer 130 may perform various functions depending on the design of the layer. For example, it may include a ground via, a power via, a signal via, etc. Here, the signal via may include a via for transmitting various signals, such as a data signal, excluding the ground via, the power via, etc.

[0028] Each first wiring layer 120 and each first via layer 130 may be formed integrally with each other, but is not limited to this. The first wiring layer 120 and / or the first via layer 130 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited to these, and any process that can form a circuit on a printed circuit board can be used without limitation.

[0029] The fact that the first wiring layer 120 is disposed on or within the first insulating layer 110 means that the first wiring layer 120 can be disposed on the first insulating layer 110 or disposed so as to be embedded within the first insulating layer 110, and may mean that the first wiring layer 120 can have a so-called coreless type substrate structure in which it is embedded within the first insulating layer 110. In particular, referring to FIG. 3 , the first wiring layer 120 disposed at the bottom may have a structure in which it is embedded within the first wiring layer 110.

[0030] 3a and 3b, the first insulating layer 110 is depicted as being composed of four layers, and as having a corresponding number of first wiring layers 120 and first via layers 130, but this is not limited thereto, and the number of first insulating layers 110, first wiring layers 120, and first via layers 130 can be changed according to the design. In particular, the first insulating layer 110 may further include a core insulating layer including a core, the first wiring layer 120 may include copper foil, and the first via layer 130 may also include a through via that penetrates the core insulating layer. As such, the first insulating layer 110, first wiring layer 120, and first via layer 130 of the printed circuit board according to one example may have a configuration that can be utilized by a person having ordinary skill in the technical field of printed circuit boards.

[0031] The cavity may penetrate at least a portion of the first insulating layer 110. The cavity may correspond to a position where the connection structure 200 is mounted. The cavity may penetrate at least a portion of the first insulating layer 110. This may mean that the cavity penetrates any continuous first insulating layer 110 among the plurality of first insulating layers 110, or may mean that the cavity penetrates only a portion of any first insulating layer 110, and is not limited thereto. It may also mean that the cavity penetrates any continuous first insulating layer 110 and also penetrates a portion of any other first insulating layer 110. Although not shown in FIGS. 3A and 3B, when the cavity penetrates only a portion of any first insulating layer 110, the top surface of the corresponding first insulating layer 110 may have a step.

[0032] The cavity may be formed by any known cavity forming method. For example, a mechanical drilling process such as laser processing or a blasting process may be used, but is not limited to these. A portion of the first wiring layer 120 disposed on the first insulating layer 110 may function as a stopper layer. Alternatively, a separate stopper layer may be previously disposed on the upper surface of the first insulating layer 110 and then removed by etching after the cavity is formed. If a stopper layer is formed, the stopper layer may be formed simultaneously with the first insulating layer 120. The wall surface of the cavity penetrating at least a portion of the first insulating layer 110 may be formed by the side surface of the first insulating layer 110, and the bottom surface of the cavity may be formed by the top surface of the first insulating layer 110. Although not shown in FIGS. 3A and 3B, the bottom surface of the cavity may also be formed by a stopper layer.

[0033] The printed circuit board according to an example includes a connection structure 200. The connection structure 200 may be disposed in a cavity, and may include a wiring portion 201 and a capacitor portion 202.

[0034] The wiring portion 201 of the connecting structure 200 may include a second insulating layer 210, a second wiring layer 220 disposed on or within the second insulating layer 210, and a second via layer 230 penetrating at least a portion of the second insulating layer 210 to connect the second wiring layer 220 to each other.

[0035] The capacitor unit 202 of the connecting structure 200 may include a plurality of first dielectric layers 240, a first metal layer 251 and a second metal layer 252 disposed on or within the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The capacitor unit 202 may include a first connection via 281 and a second connection via 282. The first connecting via 281 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261, and the second connecting via 282 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262. The second connecting via 282 may connect the second wiring layer 220 and the second metal plate 262 via the first connecting pad 271.

[0036] The wiring unit 201 of the connecting structure 200 may have a higher wiring density than the substrate unit 100. Higher wiring density is a relative concept, and may mean, for example, that the average pitch of the wiring included in the second wiring layer 220 may be smaller than the average pitch of the wiring included in the first wiring layer 120. The pitch may be measured by photographing a cross section of the printed circuit board using a scanning microscope, and the average pitch may be the average value of the pitches between the wiring measured at any five points. In addition, the average interlayer insulation distance between the second wiring layers 220 may be smaller than the average interlayer insulation distance between the plurality of first wiring layers 120. The interlayer insulation distance may also be measured by photographing a cross section of the printed circuit board using a scanning microscope, and the average interlayer insulation distance may be the average value of the insulation distances between adjacent wiring layers measured at any five points. In other words, the wiring included in the second wiring layer 220 may be a high-density circuit with a smaller L / S (line / space) than the wiring included in the first wiring layer 120. As a non-limiting example, the wiring included in the second wiring layer 220 may have a line / space of about 2 / 2 μm. Since the wiring portion 201 of the connection structure 200 has a higher density than the wiring of the substrate portion 100, it may be effective in interconnecting electronic components such as semiconductor chips. In other words, it may be effective for die-to-die interconnection.

[0037] For this reason, the thickness of the second insulating layer 210 may be thinner than the thickness of the first insulating layer 110, and the thickness of the second wiring layer 220 may be thinner than the thickness of the first wiring layer 120. The thickness of an insulating layer is a general concept and may refer to the vertical distance between the upper and lower surfaces of an insulating layer. The thickness of the second insulating layer 210 being thinner than the thickness of the first insulating layer 110 may mean, but is not limited to, that the thickness of any one second insulating layer 210 among the plurality of second insulating layers 210 is thinner than the thickness of any one first insulating layer 110 among the plurality of first insulating layers 110. The thicknesses of the first insulating layer 110 and the second insulating layer 210 may be measured by photographing a cross section of a printed circuit board using a scanning microscope, and may be the average value of the thicknesses of the insulating layers measured at any five points. The thickness of a wiring layer may be interpreted in the same sense as the thickness of an insulating layer.

[0038] Other configurations of the connecting structure will be described in detail later.

[0039] The printed circuit board according to an example may further include an adhesive layer 300. The connection structure 200 is disposed in a cavity of the substrate part 100, and the connection structure 200 may be attached to a bottom surface of the cavity via the adhesive layer 300. The adhesive layer 300 may be disposed to cover a bottom surface of the connection structure 200. The adhesive layer 300 may be an adhesive film such as a conventional die attach film (DAF), but is not limited thereto. Known tapes may also be used, and any means capable of attaching electronic components or other components such as the connection structure to the printed circuit board may be used without limitation.

[0040] 3b, a printed circuit board according to an example may include a first semiconductor chip 401 disposed on a portion of the substrate unit 100 and a portion of the connecting structure 200, and a second semiconductor chip 402 disposed on a portion of the substrate unit 100 and a portion of the connecting structure 200, and may include a connecting member 500 that connects the first semiconductor chip 401 and the second semiconductor chip 402 to the substrate unit 100 and the connecting structure 200, respectively. The first semiconductor chip 401 may be disposed to be electrically connected to a portion of the substrate unit 100 and a portion of the connecting structure 200, and the second semiconductor chip 402 may be electrically connected to a portion of the substrate unit 100 and a portion of the connecting structure 200, and may be electrically connected to the first semiconductor chip 401 via the connecting structure 200.

[0041] The first semiconductor chip 401 and the second semiconductor chip 402 may each include an integrated circuit (IC) die in which hundreds to millions of elements are integrated into a single chip. The integrated circuit may be, for example, a logic chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an application processor (e.g., AP), an analog-to-digital converter, or an application-specific IC (ASIC), but is not limited thereto. It may also be a memory chip such as a volatile memory (e.g., DRAM), a nonvolatile memory (e.g., ROM), a flash memory, or a high-bandwidth memory (HBM), or a power management IC (PMIC). For example, the first semiconductor chip 401 may include a logic chip such as a GPU, and the second semiconductor chip 402 may include a memory chip such as an HBM. Alternatively, the first semiconductor chip 401 and the second semiconductor chip 402 may be divided logic chips having different cores by die splitting.

[0042] The first semiconductor chip 401 and the second semiconductor chip 402 may each be formed based on an active wafer. In this case, the base material forming each body may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. Connection pads may be formed on each body, and the connection pads may include a conductive material such as aluminum (Al) or copper (Cu). The first semiconductor chip 401 and the second semiconductor chip 402 may be bare dies, in which case metal bumps may be disposed on the connection pads. Alternatively, the first semiconductor chip 401 and the second semiconductor chip 402 may be packaged dies, in which case a redistribution layer may be further formed on the connection pads, and metal bumps may be disposed on the redistribution layer.

[0043] The first semiconductor chip 401 and the second semiconductor chip 402 may be connected to the substrate unit 100 of the printed circuit board and the connecting structure 200 via the connecting member 500. The connecting member 500 may be formed of a low-melting point metal, for example, but not limited to, a solder such as tin (Sn)-aluminum (Al)-copper (Cu). The connecting member 500 may be formed in a multi-layer or single layer. If formed in a multi-layer, it may include copper pillars and solder, and if formed in a single layer, it may include, but is not limited to, tin-silver solder and copper. Alternatively, any means capable of serving as an intermediary for electrically connecting the semiconductor chips or electronic components to the substrate unit 100 and / or the connecting structure 200 may be used without limitation. Although FIG. 3B illustrates two semiconductor chips mounted on the substrate 100, this is not limiting and a greater number of semiconductor chips may be mounted and electrically connected by the connecting structure 200.

[0044] Meanwhile, the printed circuit board according to the example is not limited to the configurations shown in Figures 3a and 3b, and may further include general configurations of printed circuit boards other than those shown in Figures 3a and 3b, i.e., may further include configurations that can be utilized by a person having ordinary skill in the art.

[0045] FIG. 4 is a cross-sectional view schematically showing a printed circuit board according to another example.

[0046] 4, a connecting structure 200 of a printed circuit board according to another example may be disposed on a substrate unit 100. That is, the connecting structure 200 may be disposed on a first insulating layer 110 of the substrate unit 100, and the first insulating layer 110 may not include a cavity.

[0047] Meanwhile, among the configurations other than the arrangement of the connecting structure 200, the same configurations as those of the printed circuit board according to one example can also be applied to the printed circuit board according to another example, so redundant explanations regarding this will be omitted.

[0048] FIG. 5 is a cross-sectional view schematically showing a printed circuit board according to yet another example.

[0049] 5, a substrate part 100 of a printed circuit board according to another example may include a core insulating layer 111, and a connection structure 200 may be mounted in a cavity formed in the core insulating layer 111. The core insulating layer 111 may include an insulating material, and examples of the insulating material include, but are not limited to, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, a material in which these insulating resins are mixed with an inorganic filler such as silica, or a resin impregnated in a core material such as glass fiber (glass cloth, glass fabric) together with an inorganic filler, for example, an insulating material such as CCL (Copper Clad Laminate). The core insulating layer 111 may be thicker than each of the first insulating layers 110, but is not limited to this. In this case, a portion of the first wiring layer 120 may function as a stopper on the lower surface of the cavity formed in the core insulating layer 111, but is not limited to this.

[0050] Meanwhile, among the configurations other than the contents relating to the core insulating layer 111 of the substrate part 100 and the arrangement of the connecting structure 200, the same configurations as those of the printed circuit board according to one example can also be applied to the printed circuit board according to another example, and therefore, redundant explanations regarding this will be omitted.

[0051] FIG. 6a is a cross-sectional view schematically illustrating a connection structure of a printed circuit board according to an example, and FIG. 6b is a perspective view schematically illustrating a capacitor portion of the connection structure of a printed circuit board according to an example.

[0052] Referring to FIG. 6 a, the connection structure 200 may include a wiring portion 201 and a capacitor portion 202 .

[0053] The wiring portion 201 of the connecting structure 200 may include a second insulating layer 210, a second wiring layer 220 disposed on or within the second insulating layer 210, and a second via layer 230 penetrating at least a portion of the second insulating layer 210 to connect the second wiring layer 220 to each other.

[0054] The second insulating layer 210 may be composed of multiple insulating layers, and each second insulating layer 210 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The insulating material may be a photosensitive material and / or a non-photosensitive material. For example, the insulating material of the second insulating layer 210 may be, but is not limited to, insulating materials such as PPG (Prepreg) and RCC (Resin Coated Copper), and may also include ABF (Ajinomoto Build-up Film), PID (Photo Imageable Dielectric), FR-4, and BT (Bismaleimide Triazine). However, the insulating material is not limited thereto, and other polymer materials with excellent rigidity may also be used as needed. Meanwhile, the second insulating layer 210 may include an insulating material made of an organic material. That is, the connecting structure 200 may be an organic bridge. Therefore, even if the connecting structure 200 is disposed on the upper side of the substrate part 100, reliability problems due to a coefficient of thermal expansion (CTE) mismatch may hardly occur, unlike when the connecting structure 200 is a silicon bridge. In addition, when the connecting structure 200 includes an organic insulating material, the difficulty and cost of the formation process may be reduced. For forming fine circuits, the organic insulating material may be, but is not limited to, a photoimageable dielectric (PID).

[0055] The second wiring layer 220 may be composed of multiple wiring layers, and each second wiring layer 220 may include a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each second wiring layer 220 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. Each second wiring layer 220 may perform various functions depending on the design of the corresponding layer. For example, it may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern may include various signals other than the ground pattern, power pattern, etc., such as data signals. These patterns may include line patterns, plane patterns, and / or pad patterns. The second wiring layer 220 disposed on the uppermost side of the second wiring layers 220 may have a structure exposed from the second insulating layer 210, and may further include a surface treatment layer on the exposed surface.

[0056] The second via layer 230 may be composed of multiple via layers, and each second via layer 230 may include a microvia. The microvia may be a filled via that fills a via hole or a conformal via that is arranged along the wall surface of a via hole. The microvias may be arranged in a stacked and / or staggered manner. Each second via layer 230 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each second via layer 230 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of the chemical copper as the electroless plating layer. The second via layer 230 may perform various functions depending on the design of the layer. For example, the signal via may include a ground via, a power via, a signal via, etc. Here, the signal via may include a via for transmitting various signals, such as a data signal, excluding the ground via, the power via, etc.

[0057] Each second wiring layer 220 and each second via layer 230 may be formed integrally with each other, but is not limited to this. The second wiring layer 220 and / or the second via layer 230 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited to these, and any process that can form a circuit on a printed circuit board or a connection structure, etc., can be used without limitation.

[0058] 6A shows that the second wiring layer 220 is disposed on the second insulating layer 210, but is not limited thereto, and the second wiring layer 220 may be disposed within the second insulating layer 210 and embedded in the second insulating layer 210. In this case, although not shown in FIG. 6A, the wiring portion 201 of the connecting structure 200 may be a so-called coreless type wiring portion 201.

[0059] The capacitor unit 202 of the connecting structure 200 may include a plurality of first dielectric layers 240, a first metal layer 251 and a second metal layer 252 disposed on or within the plurality of first dielectric layers 240. The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The capacitor unit 202 may include a first connection via 281 and a second connection via. The first connecting via 281 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261, and the second connecting via 282 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262. The second connecting via 282 may connect the second wiring layer 220 and the second metal plate 262 via the first connecting pad 271.

[0060] The first dielectric layer 240 may include a dielectric material made of an organic substance. Examples of the dielectric material include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing such a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric). The dielectric material may be a photosensitive material and / or a non-photosensitive material. For example, the dielectric material of the first dielectric layer 240 may be an insulating material such as PPG (Prepreg) or RCC (Resin Coated Copper), or may also be Ajinomoto Build-up Film (ABF), Photo Imageable Dielectric (PID), FR-4, or BT (Bismaleimide Triazine). However, the dielectric material is not limited thereto, and other polymeric materials with excellent dielectric properties may also be used as needed. To realize fine circuits and perform fine processing, a photosensitive dielectric material (Photo Imageable Dielectric, PID), i.e., a photosensitive resin, can be used as an organic insulating material to form the thin first dielectric layer 240, but is not limited thereto. Any material can be used without limitation as long as it can be disposed between the first metal layer 251 and the second metal layer 252, which function as electrodes, and can function as a dielectric.

[0061] The first metal layer 251 and the second metal layer 252 may each include a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. The second wiring layer 220 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed instead of chemical copper as the electroless plating layer. If necessary, a copper foil may be further included. The first metal layer 251 and the second metal layer 252 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive process, but is not limited thereto. Any method for forming a metal layer may be used. The method for forming the metal layer is not limited, and the metal layer may be formed by printing a conductive paste containing a metal material on the green sheet.

[0062] Of the first metal layer 251 and the second metal layer 252, the first metal plate 261 and the second metal plate 262 may function as internal electrodes of the capacitor unit 202. That is, the first metal layer 251 and the second metal layer 252 may be charged with opposite polarities to each other, thereby providing capacitance. The first metal plate 261 and the second metal plate 262 are arranged to face each other as a pair, sandwiching the first dielectric layer 240 between them. By arranging the first metal plate 261 and the second metal plate 262 in this manner, each metal plate is charged with an electric charge, thereby functioning as a capacitor. The first metal plate 261 and the second metal plate 262 may have a rectangular plate shape, but are not limited thereto and may also have a polygonal or circular shape. The metal plates may also have grooves or a shape with many closely spaced patterns. As described above, the first metal plate 261 and the second metal plate 262 may have various shapes and other designs depending on the capacitance required in the design of the printed circuit board and the design of the connection structure 200.

[0063] The first connection pad 271 may be spaced apart from the first metal plate 261 and may be disposed at the same level as the first metal plate 261. The first connection pad 271 may serve as an intermediate body for connecting the second wiring layer 220 and the second metal layer 252. That is, the first connection pad 271 may serve as an intermediate body for preventing the second connection via 282, which is electrically connected to the second metal plate 262 disposed below the first metal plate 261, from penetrating all of the first dielectric layers 240. That is, since the first connection pad 271 is disposed on the first metal layer, it may be more convenient to form a through hole for forming the second connection via 282. At this time, since the first connection pad 271 is spaced apart from the first metal plate 261, the first metal plate 261 and the second metal plate 262 may not be directly connected to each other. On the other hand, if a second connection via can be formed penetrating all of the first dielectric layers 240, the first connection pad 271 may not be disposed.

[0064] The first connecting via 281 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the first metal plate 261 to each other, and the second connecting via 282 may penetrate at least a portion of the plurality of first dielectric layers 240 and / or at least a portion of the second insulating layer 210 to connect the second wiring layer 220 and the second metal plate 262 to each other. The second connecting via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other via the first connecting pad 271. The first connecting via 281 and the second connecting via 282 may each include a metal material. Examples of the metal material include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. The second wiring layer 220 may include, but is not limited to, an electroless plating layer (or chemical copper) as a seed layer and an electrolytic plating layer (or electrolytic copper) as a plating layer. A sputtering layer may be formed as the electroless plating layer instead of chemical copper. If necessary, a copper foil may be further included. The first connection via 281 and the second connection via 282 may be formed by any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a tenting (TT), or a subtractive method, but is not limited thereto. Any method for forming vias may be used. The second connection via 282 and the first connection pad 271 may be formed integrally, but is not limited thereto.

[0065] The distance d1 between the first metal layer 251 and the second metal layer 252 may be closer than the distance d2 between the first metal layer 251 and the second wiring layer 220. The distance d1 between the first metal layer 251 and the second metal layer 252 may be understood to mean the distance between the bottom surface of the first metal layer 251 and the top surface of the second metal layer 252, and more specifically, may mean the insulation distance between the first metal layer 251 and the second metal layer 252. The distance d1 between the first metal layer 251 and the second metal layer 252 may be measured by photographing a cross section of a printed circuit board or a connecting structure using a scanning microscope, and may be the average value of the distances d1 between the first metal layer 251 and the second metal layer 252 measured at any five points. The distance d2 between the first metal layer 251 and the second wiring layer 220 may be interpreted in a similar manner. The distance d2 between the first metal layer 251 and the second wiring layer 220 can refer to the distance between the first metal layer 251 and the closest second wiring layer 220.

[0066] By reducing the distance d1 between the first metal layer 251 and the second metal layer 252, the first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 can function as capacitor electrodes. The distance d1 between the first metal layer 251 and the second metal layer 252 can be 1 μm or less, and can be set to 0.33 μm or less if the first metal layer 251 and the second metal layer 252 can be further reduced. The distance between the first metal layer 251 and the second metal layer 252 can be freely designed depending on the capacitance required for the capacitor unit 202 of the connecting structure 200. However, to ensure capacitance, the first metal layer 251 and the second metal layer 252 must be positioned close to each other so that the distance is shorter than a certain value. However, the distance between the first metal layer 251 and the second metal layer 252 can also be greater than 0. This is because if the first metal layer 251 and the second metal layer 252 come into contact with each other, a short circuit occurs, preventing capacitance.

[0067] Similar to the distance d1 between the first metal layer 251 and the second metal layer 252 being closer than the distance d2 between the first metal layer 251 and the second wiring layer 220, the thickness of the first dielectric layer 240 may be formed thinner than the thickness of the second insulating layer 210. The fact that the thickness of the first dielectric layer 240 may be formed thinner than the thickness of the second insulating layer 210 may mean that the thickness of any one of the first dielectric layers 240 among the plurality of first dielectric layers 240 may be formed thinner than the thickness of any one of the second insulating layers 210 among the plurality of second insulating layers 210. The thickness of the first dielectric layer 240 is a general concept and may refer to the vertical distance between the upper and lower surfaces of the first dielectric layer 240. The thickness of the first dielectric layer 240 may be measured by photographing a cross section of a printed circuit board using a scanning microscope, and may be an average value of the thicknesses of the insulating layer measured at any five points. The thickness of the second insulating layer 210 can be understood in the same sense as the thickness of the first dielectric layer 240, which can be understood in the same sense as described above with respect to measuring the thickness of the first insulating layer 110.

[0068] Because the first dielectric layer 240 is thinner than the second insulating layer 210, the first dielectric layer 240 may be formed by spin coating an insulating material instead of laminating an insulating material formed from a film. Forming the first dielectric layer 240 by spin coating may shorten the insulating distance (d1) between the first metal layer 251 and the second metal layer 252 and facilitate adjustment of the insulating distance. However, the method or means for forming the first dielectric layer 240 is not limited thereto. Any method capable of forming an insulating material or dielectric on a printed circuit board may be used without limitation, and any method capable of easily adjusting the thickness and forming a thin layer may be used without limitation. For example, if an insulating film for use in the first dielectric layer 240 can be formed thinner, it may be formed by lamination.

[0069] The first dielectric layer 240 may include the same type of organic material as the second insulating layer 210. As described above, the first dielectric layer 240 may use a photoimageable dielectric (PID), i.e., a photosensitive resin, to form a thin dielectric layer, and the second insulating layer 210 may use a photosensitive insulating material to realize fine circuits. However, the materials of the first dielectric layer 240 and the second insulating layer 210 are not limited thereto and may include various types of organic materials as described above. Even if the first dielectric layer 240 includes an organic material, the capacitor unit 202 can have capacitance by closely arranging the first metal layer 251 and the second metal layer 252.

[0070] Referring to FIG. 6b, the capacitor unit 202 may include a pair of metal layers facing each other. The first metal plate 261 of the first metal layer 251 and the second metal plate 262 of the second metal layer 252 face each other. Because capacitance may occur over the effective area where the first metal plate 261 and the second metal plate 262 face each other, the first metal plate 261 and the second metal plate 262 may be designed to increase the effective area. In FIG. 6b, protrusions are formed on both ends of the metal plates, and the protrusions are shown as being connected to the first connection via 281 or the second connection via 282. However, this is merely an example of one of various designs for the first metal plate 261 and the second metal plate 262. The shape of the protrusions of the metal plates may be changed, and the position of the first connection pad 271 may also be changed, as needed.

[0071] 6b, the first metal plate 261 and the second metal plate 262 may include a first hole 291 and a second hole 292 disposed therein, respectively. The first hole 291 and the second hole 292 may correspond to degassing holes in a printed circuit board. The first hole 291 and the second hole 292 may be a degassing configuration and may be used as a path for ejecting and removing unnecessary moisture, gas, etc. generated during the manufacturing of the connection structure 200 and the manufacturing of the printed circuit board. In the case of a general printed circuit board or other connection structure, degassing holes are disposed at different positions on each layer to efficiently perform degassing. In the case of the printed circuit board connection structure 200 according to an example, the first hole 291 formed in the first metal plate 261 and the second hole 292 formed in the second metal plate 262 may be positioned corresponding to each other. That is, by forming the first hole 291 and the second hole 292 to correspond to each other, it is possible to more easily adjust the effective area of ​​the overlapping region of the first metal plate 261 and the second metal plate 262. Since the effective areas of the first metal plate 261 and the second metal plate 262 can be easily adjusted, it is possible to easily design the capacitor unit 202 to have the required capacitance. Meanwhile, although FIG. 6b illustrates the first hole 291 and the second hole 292 as being formed one by one, the size, number, and shape of the first hole 291 and the second hole 292 are not limited and may be changed according to the design.

[0072] 6a and 6b, the connecting structure 200 may have a buried pattern structure. For example, the upper surface of the second wiring layer 220 disposed on the uppermost side may be buried in the upper surface of the second insulating layer 210 and exposed at the upper surface of the second insulating layer 210. When the connecting structure 200 is formed in such a structure, a finer pitch wiring design may be possible. In addition, the cost of manufacturing the connecting structure 200 may be lower than that of a silicon bridge, and the manufacturing process may be simpler.

[0073] FIG. 7a is a cross-sectional view schematically showing a connection structure according to another example, and FIG. 7b is a perspective view schematically showing a capacitor portion of the connection structure according to another example.

[0074] 7a and 7b, a connecting structure according to another example may include a plurality of first metal layers 251 and a plurality of second metal layers 252. The first metal layers 251 and the second metal layers 252 may be alternately arranged with the first dielectric layer 240 interposed therebetween. That is, a structure may be formed in which the second metal layer is arranged between the first metal layers 251, and the first metal layers 251 may be arranged between the second metal layers 252.

[0075] The first metal layer 251 may include a first metal plate 261 and a first connection pad 271 spaced apart from the first metal plate 261, and the second metal layer 252 may include a second metal plate 262 and a second connection pad 272 spaced apart from the second metal plate 262. The first connection via 281 may connect the second wiring layer 220 and the first metal plate 261 to each other and may also connect to another first metal plate 261 through the second connection pad 272. The second connection via 282 may connect the second wiring layer 220 and the second metal plate 262 to each other and may also connect to another second metal plate 262 through the first connection pad 271. The second connection pad 272 is disposed spaced apart from the second metal plate 262 and may have similar properties to the first connection pad 271, so a redundant description will be omitted.

[0076] 7A and 7B, the first metal layer 251 and the second metal layer 252 are each composed of two metal layers, so that a total of four metal layers are disposed, but the number of metal layers is not limited to this and more metal layers may be disposed. That is, the number of metal layers may be variously designed depending on the capacitance of the capacitor unit 202.

[0077] Meanwhile, among the configurations other than the first metal layer 251 and the second metal layer 252, the configuration of the connecting structure according to one example can also be applied to the connecting structure according to another example, so redundant explanations regarding this will be omitted.

[0078] FIG. 8a is a cross-sectional view schematically showing a connection structure according to yet another example, and FIG. 8b is a perspective view schematically showing a capacitor portion of the connection structure according to yet another example.

[0079] 8a and 8b, in a connection structure according to another example, one first metal layer 251 and one second metal layer 252 may include a plurality of first metal plates 261 and a plurality of second metal plates 262, respectively. In this case, the first metal plates 261 may be spaced apart from each other, and the second metal plates 262 may be spaced apart from each other. That is, in a connection structure 200 according to another example, the capacitor units 202 may be arranged in parallel. Therefore, the design can be diversified to achieve a desired capacitance in the capacitor units 202.

[0080] 8a and 8b, the first metal layer 251 and the second metal layer 252 are each shown as being composed of two metal plates, but the number of metal plates is not limited thereto, and a greater number of metal plates may be arranged in parallel. Meanwhile, the first metal layer 251 and the second metal layer 252 are each shown as being composed of one metal layer, but they may be composed of a plurality of first metal layers 251 and a plurality of second metal layers 252. In other words, the number of metal plates and the number of metal layers may be variously designed depending on the capacitance of the capacitor unit 202.

[0081] In addition, among the configurations other than the first metal plate 261 and the second metal plate 262, the configuration of the connecting structure of one example can also be applied to the connecting structure of another example, so duplicate explanations regarding this will be omitted.

[0082] In the present disclosure, "cross section" can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and "planar" can refer to the shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0083] In this disclosure, for convenience, terms such as upper side, top, and top surface are used to refer to the direction toward the surface on which electronic components can be mounted based on the cross section of the drawing, and terms such as lower side, bottom, and bottom surface are used to refer to the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of such directions.

[0084] In this disclosure, the term "connected" encompasses not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" encompasses both physical connection and non-physical connection. Furthermore, terms such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0085] The term "one example" used in this disclosure does not mean the same embodiment as the other examples, but is provided to emphasize and describe the unique features that are different from each other. However, the above-described one example does not exclude being realized in combination with the features of another example. For example, even if a matter described in a particular example is not described in another example, it can be understood as being related to the other example unless there is a contrary or contradictory description with that matter in the other example.

[0086] The terms used in this disclosure are merely used to describe an example and are not intended to limit the disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0087] 100 Circuit board 110 First insulating layer 111 Core insulation layer 120 1st wiring layer 130 First via layer 200 linked structure 201 Wiring section 202 Capacitor section 210 Second insulating layer 220 2nd wiring layer 230 Second via layer 240 First dielectric layer 251 1st metal layer 252 2nd metal layer 261 1st metal plate 262 Second metal plate 271 First Linking Pad 272 Second Link Pad 281 First Connected Via 282 Second Connected Via 291 Hole 1 292 Hole 2 300 adhesive layer 401 First semiconductor chip 402 Second semiconductor chip 500 connecting members 1000 electronic equipment 1010 mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 camera module 1060 Antenna Module 1070 display 1080 battery 1090 signal line 1100 smartphone 1110 Smartphone Internal Main Board 1120 Smartphone internal electronic components 1121 Smartphone Internal Antenna Module 1130 Smartphone Internal Camera Module 1140 Smartphone Internal Speaker

Claims

1. a substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer; a connecting structure disposed on or within the substrate portion, the connecting structure including a plurality of first dielectric layers, a first metal layer disposed on the first dielectric layers, a second metal layer disposed on the first dielectric layers, a second insulating layer disposed on the plurality of first dielectric layers, and a second wiring layer disposed on the second insulating layer; each of the plurality of first dielectric layers includes an organic material; a distance between the first metal layer and the second metal layer is shorter than a distance between the first metal layer and the second wiring layer; The first metal layer and the second metal layer are disposed on opposite sides of the first dielectric layer to form a capacitor.

2. the first metal layer includes a first metal plate and a first connection pad spaced apart from the first metal plate; The printed circuit board of claim 1 , wherein the second metal layer comprises a second metal plate.

3. 3. The printed circuit board of claim 2, wherein the connecting structure includes a first connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate, and a second connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate.

4. The printed circuit board of claim 3 , wherein the second connecting via connects the second wiring layer and the second metal plate through the first connecting pad.

5. the first metal layer and the second metal layer are respectively composed of a plurality of first metal layers and a plurality of second metal layers; the second metal layer further includes a second connection pad spaced apart from the second metal plate, The printed circuit board of claim 2 , wherein the first metal layer and the second metal layer are alternately arranged with the first dielectric layer in between.

6. the connecting structure includes: a first connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate; and a second connecting via that penetrates at least a portion of the plurality of first dielectric layers and at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate, the first connection via connects the second wiring layer and the first metal plate through the second connection pad; The printed circuit board of claim 5 , wherein the second connecting via connects the second wiring layer and the second metal plate through the first connecting pad.

7. the first metal layer includes a plurality of first metal plates spaced apart from one another and a plurality of first connection pads spaced apart from the plurality of first metal plates; The printed circuit board of claim 1 , wherein the second metal layer includes a plurality of second metal plates spaced apart from one another.

8. the connecting structure includes: a first connecting via that penetrates at least a portion of the plurality of first dielectric layers and / or at least a portion of the second insulating layer to connect the second wiring layer and the first metal plate; and a second connecting via that penetrates at least a portion of the plurality of first dielectric layers and / or at least a portion of the second insulating layer to connect the second wiring layer and the second metal plate, The printed circuit board of claim 7 , wherein the second connecting vias connect the second wiring layer and the second metal plates, respectively, through the first connecting pads.

9. The printed circuit board of claim 1 , wherein the thickness of the first dielectric layer is less than the thickness of the second insulating layer.

10. The printed circuit board of claim 1 , wherein the first dielectric layer comprises a photosensitive resin.

11. The printed circuit board of claim 1 , wherein the first dielectric layer comprises the same type of organic material as the second insulating layer.

12. The printed circuit board of claim 1 , further comprising an adhesive layer disposed between the substrate portion and the connecting structure.

13. The printed circuit board according to claim 1 , wherein the wiring density of the second wiring layer is higher than the wiring density of the first wiring layer.

14. the first metal plate includes a first hole disposed therein; The printed circuit board according to claim 2 , wherein the second metal plate includes a second hole therein corresponding to the first hole.

15. a first electronic component connected to a portion of the substrate portion and a portion of the connecting structure; The printed circuit board of claim 1 , further comprising: a second electronic component connected to another portion of the substrate portion and another portion of the connecting structure.

16. a substrate portion including a first insulating layer and a first wiring layer disposed on or within the first insulating layer; a connecting structure including a capacitor portion disposed on or within the substrate portion, the capacitor portion including a dielectric layer and a first metal layer disposed on or within the dielectric layer, and a wiring portion including a second insulating layer and a second wiring layer disposed on the second insulating layer; the second insulating layer is disposed on the dielectric layer; the first metal layer includes a pair of metal plates facing each other, The printed circuit board, wherein the dielectric layer comprises an organic material.

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