How to ultra-thin wafers

Abstract

A semiconductor device and method for its manufacture are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer then undergoes device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding and the wafer is thinned. To thin the wafer, a silicon substrate layer having a starting first thickness is polished to a second thickness less than the first thickness. After polishing, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing to reduce the silicon thickness to a third thickness less than the second thickness.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to semiconductor devices. More particularly, embodiments of the present disclosure are directed to power rail architectures, 3D packaging, and methods of manufacturing semiconductor devices. [Background technology]

[0002]

[0002] The semiconductor processing industry continues to strive for higher production yields while increasing the uniformity of layers deposited on substrates with larger surface areas. These same factors, combined with new materials, also increase the integration of circuits per unit area of ​​the substrate. As circuit integration increases, the need for greater uniformity and process control over layer thickness increases. As a result, various techniques have been developed for depositing layers on substrates in a cost-effective manner while maintaining control over the layer's properties.

[0003]

[0003] Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric, conductive, and semiconducting layers of material on a semiconductor substrate and using lithography to pattern the various material layers to form circuit components and elements thereon. The conductive layers facilitate electrical wiring to various electrical components, including transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors, inductors, resistors, etc.

[0004]

[0004] Transistors are key components of most integrated circuits. Because a transistor's drive current, and therefore its speed, is proportional to its gate width, faster transistors generally require larger gate widths. As a result, there is a trade-off between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that significantly increases transistor size without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, FinFETs also have drawbacks.

[0005]

[0005] As transistor device feature sizes continue to shrink to achieve increased circuit density and higher performance, improved transistor device structures are needed to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure offers good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0006]

[0006] Connecting the semiconductor to the power rails is typically done on the front side of the cell, which requires a large cell area. Therefore, there is a need for semiconductor devices that connect to power rails using less cell area. Summary of the Invention

[0007] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming an etch stop layer on a top surface of a substrate having a first thickness, forming an epitaxial layer on the top surface of the etch stop layer, forming a wafer device on the top surface of the epitaxial layer, bonding the wafer device to a bonding wafer, polishing the substrate to form a substrate having a second thickness less than the first thickness, planarizing the substrate to form a substrate having a third thickness less than the second thickness, removing the etch stop layer to expose source / drain regions on the wafer device, and forming contacts electrically connected to the source / drain regions.

[0008]

[0008] Additional embodiments of the present disclosure are directed to a method of forming a semiconductor device. In one or more embodiments, the method of forming the semiconductor device includes forming an etch stop layer on a top surface of a substrate having a first thickness, forming an epitaxial layer on the top surface of the etch stop layer, forming a wafer device on the top surface of the epitaxial layer, bonding the wafer device to a bonding dummy wafer or a Cu wafer with a hybrid bond, polishing the substrate to form a substrate having a second thickness less than the first thickness, depositing a mask layer on a bottom surface of the etch stop layer, forming at least one via opening in the mask layer, selectively removing the etch stop layer, and removing the mask layer to expose the substrate having a fourth thickness less than the first thickness.

[0009]

[0009] So that the features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above will be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure is open to other equally effective embodiments, and therefore the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a process flow diagram of a method according to one or more embodiments. [Figure 1B]

[0011] 1B is a continuation of the process flow diagram of FIG. 1A illustrating a method according to one or more embodiments. [Figure 2A]

[0012] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2B]

[0013] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2C]

[0014] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2D]

[0015] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2E]

[0016] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2F]

[0017] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2G]

[0018] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2H]

[0019] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2I]

[0020] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2J]

[0021] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2K]

[0022] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2L]

[0023] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2M]

[0024] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2N]

[0025] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2O]

[0026] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2P]

[0027] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2Q]

[0028] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2R]

[0029] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2S]

[0030] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2T]

[0031] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 2U]

[0032] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 3]

[0033] 1 shows a process flow diagram of a method according to one or more embodiments. [Figure 4A]

[0034] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4B]

[0035] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4C]

[0036] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4D]

[0037] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 4E]

[0038] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5A]

[0039] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5B]

[0040] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5C]

[0041] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 5D]

[0042] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 6]

[0043] 1 shows a process flow diagram of a method according to one or more embodiments. [Figure 7A]

[0044] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 7B]

[0045] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 7C]

[0046] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 7D]

[0047] 1 illustrates a cross-sectional view of a device according to one or more embodiments. [Figure 8]

[0048] 1 illustrates a cluster tool in accordance with one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0049] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0012]

[0050] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013]

[0051] The term "substrate," as used herein and in the appended claims, refers to a surface or a portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate may refer to only a portion of a substrate unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed on its surface.

[0014]

[0052] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a manufacturing process. For example, substrate surfaces upon which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer is the substrate surface. What a given substrate surface comprises will depend on what film is being deposited and the particular chemistry used.

[0015]

[0053] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably and refer to any gas species capable of reacting with the substrate surface.

[0016]

[0054] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on the semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is located over a channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0017]

[0055] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. Conduction between the drain and source terminals is controlled by the electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), where carriers enter the channel, the drain (D), where carriers exit the channel, and the gate (G), which controls the conductivity of the channel. Conventionally, the current entering the channel from the source (S) is denoted IS, and the current entering the channel from the drain (D) is denoted ID. The voltage between the drain and source is denoted VDS. Applying a voltage to the gate (G) controls the current entering the channel at the drain (i.e., ID).

[0018]

[0056] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the gate determines the device's conductivity. This ability to change conductivity in response to an applied voltage is used to amplify or switch electronic signals. MOSFETs are based on modulation of charge concentration through a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but both are the same type, opposite the body region. The source and drain (unlike the body) are highly doped, and the doping type is indicated by a "+" symbol.

[0019]

[0057] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is n region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is so named because it is where the charge carriers exit the channel.

[0020]

[0058] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate where the gates are located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the collective name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0021]

[0059] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire, nanoslab, or nanosheet, a rod-shaped channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0022]

[0060] As used herein, the term "nanowire" refers to a wire measuring 1 nanometer (10 -9 Nanowires refer to nanostructures having diameters on the order of 1000 to 10000 nm. Nanowires can also be defined as having a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is constrained to tens of nanometers or less, but whose length is not. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0023]

[0061] Embodiments of the present disclosure are illustrated by diagrams that illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely exemplary of possible applications of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0024]

[0062] One or more embodiments of the present disclosure are described with reference to the figures. In one or more embodiment methods, a transistor, e.g., a gate-all-around transistor, is fabricated using a standard process flow. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, e.g., epitaxial silicon, is deposited. The wafer then undergoes device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, e.g., copper or oxide bonding, and then the wafer is advantageously thinned. Thinning the wafer provides the desired flatness and bonding for backside power rail implementation. To thin the wafer, a silicon substrate layer having a starting first thickness is polished to a second thickness less than the first thickness. After polishing, in some embodiments, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing to reduce the thickness of the silicon to a third thickness less than the second thickness. In one or more embodiments, the etching stops at the buried etch stop layer. The contacts are then pre-filled with metal and metallized.

[0025]

[0063] In alternative embodiments, transistors, e.g., gate-all-around transistors, are fabricated using standard process flows. In some embodiments, a silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. An epitaxial layer, e.g., epitaxial silicon, is deposited. The wafer then undergoes device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, e.g., bonding to copper or oxide, and then the wafer is advantageously thinned. Thinning the wafer provides the desired planarity and bonding for realizing backside power rails. To thin the wafer, a silicon substrate layer having a starting first thickness is polished down to a second thickness that is smaller than the first thickness. After polishing, a large mask is deposited and vias are formed in the mask. The wafer is then etched through the vias down to the buried etch stop layer, after which the etch stop layer is selectively removed and lift-off is performed.

[0026]

[0064] In one or more embodiment methods, transistors, e.g., gate-all-around transistors, are fabricated using a standard process flow. After the source / drain cavities are recessed, the dimensions of the source / drain cavities are expanded and a sacrificial fill is deposited. Fabrication continues with interior spacer formation, source / drain epitaxy, interlayer dielectric formation, replacement gate formation, CT and CG formation, and front-side metal line formation. The substrate is then flipped and planarized. An interlayer dielectric is deposited on the backside, backside power rail vias are patterned, and the interlayer dielectric is etched. A damascene trench is formed and the sacrificial fill is removed to form an opening. Metal is deposited in the opening to form the backside metal line. In one or more embodiments, the sacrificial fill is advantageously selective so that, upon etching, self-aligned trenches and / or vias are formed, thus avoiding misalignment.

[0027]

[0065] In one or more embodiment methods, transistors, e.g., gate-all-around transistors, are fabricated using a standard process flow. Deep vias are etched with a separate mask, or alternatively, with a regular contact or via mask. After the regular vias are etched, a mask is placed and power rail vias are etched to a depth below the device to facilitate backside connections. The standard and deep vias / contacts are simultaneously filled with titanium nitride / tungsten (TiN / W) or titanium nitride / ruthenium (TiN / Ru) or molybdenum (Mo) contact fill and then planarized. The wafer may optionally be thinner. On the backside, vias are etched to connect to the deep vias. Metallization then occurs.

[0028]

[0066] FIG. 1A illustrates a process flow diagram for Method 6 for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 1B is a continuation of the process flow diagram of FIG. 1A illustrating Method 6 according to one or more embodiments. FIGS. 2A-2U illustrate fabrication stages of a semiconductor structure according to some embodiments of the present disclosure. Method 6 is described below with respect to FIGS. 2A-2U. FIGS. 2A-2U are cross-sectional views of an electronic device (e.g., a GAA) according to one or more embodiments. Method 6 may be part of a multi-step fabrication process for a semiconductor device. Thus, Method 6 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the fabrication of semiconductor devices.

[0029]

[0067] 2A-2U are fabrication steps for steps 8-54 of FIGS. 1A-1B. Referring to FIG. 1A, method 6 of forming device 100 begins in step 8 by providing a substrate 102. In some embodiments, substrate 102 can be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate that is entirely made of a semiconductor material. A bulk semiconductor substrate can include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 102 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials that can form the substrate are described, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) can be constructed is within the spirit and scope of the present disclosure.

[0030]

[0068] In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to a well positive charge (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration that is greater than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0031]

[0069] Referring to FIG. 1A , in some non-illustrated embodiments, an etch stop layer may be formed on the top surface of the substrate in step 10. The etch stop layer may comprise any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer comprises silicon germanium (SiGe). In one or more embodiments, the etch stop layer has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without wishing to be bound by theory, it is believed that a germanium content in the range of 30% to 50% increases the selectivity of the etch stop layer and minimizes stress defects. In one or more embodiments, the etch stop layer has a thickness in the range of 5 nm to 30 nm. The etch stop layer may function as an etch stop for planarization (e.g., CMP), dry or wet etching during backside processing.

[0032]

[0070] In one or more non-illustrated embodiments, an epitaxial layer, such as epitaxial silicon, may be deposited on the etch stop layer in step 12. The epitaxial layer may have a thickness in the range of 20 nm to 100 nm.

[0033]

[0071] 1A and 2A, in one or more embodiments, at least one superlattice structure 101 is formed on the top surface of the substrate 102 or on the top surface of the etch stop layer and the epitaxial layer in step 14. The superlattice structure 101 includes a plurality of semiconductor material layers 106 and a corresponding plurality of horizontal channel layers 104, which are arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked layers includes silicon (Si) and silicon germanium (SiGe). In some embodiments, the plurality of semiconductor material layers 106 includes silicon germanium (SiGe) and the plurality of horizontal channel layers 104 includes silicon (Si). In other embodiments, the plurality of horizontal channel layers 104 includes silicon germanium (SiGe) and the plurality of semiconductor material layers 106 includes silicon (Si).

[0034]

[0072] In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 may include any number of pairs of lattice-matched materials suitable for forming a superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 include from about 2 to about 50 pairs of lattice-matched materials.

[0035]

[0073] In one or more embodiments, the thickness of the semiconductor material layers 106 and the horizontal channel layers 104 is in the range of about 2 nm to about 50 nm, in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0036] 1A and 2B, in one or more embodiments, in step 16, the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105. Patterning can be performed by any suitable means known to those skilled in the art. As used in this regard, the term "opening" refers to any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two sidewalls, and a bottom. The openings can have any suitable aspect ratio (ratio of feature width to feature depth). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater.

[0037]

[0074] 1A and 2C, in step 18, shallow trench isolation (STI) 110 is formed. As used herein, the term "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents electrical current from leaking. In one or more embodiments, the STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill the trench or opening 108 and removing the excess dielectric using a technique such as chemical mechanical planarization.

[0038]

[0075] 1A and 2D, in some embodiments, a replacement gate structure 113 (e.g., a dummy gate structure) is formed over and adjacent to the superlattice structure 101. The dummy gate structure 113 defines a channel region of the transistor device. The dummy gate structure 113 may be formed using any suitable conventional deposition and patterning process known in the art.

[0039]

[0076] In one or more embodiments, the dummy gate structure includes one or more of a gate 114 and a polysilicon layer 112. In one or more embodiments, the dummy gate structure includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

[0040]

[0077] 1A and 2E, in some embodiments, in step 22, sidewalls 116 are formed along the outer sidewalls of dummy gate structures 113 on superlattice 101. Sidewall spacers 116 may comprise any suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, etc. In some embodiments, the sidewall spacers are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition.

[0041]

[0078] 1A and 2F, in step 24, in one or more embodiments, source / drain trenches 118 are formed adjacent to (ie, on either side of) the superlattice structure 101.

[0042]

[0079] 1A and 2G, in step 26, in one or more embodiments, the source / drain trenches 118 are extended deeply to form cavities 119 beneath the superlattice structure 101. The cavities 119 may have any suitable depth and width. In one or more embodiments, the cavities 119 extend through the shallow trench isolation 110 into the substrate 102. In one or more embodiments, the etch and dummy fill of the cavities 119 extend beneath the shallow trench isolation 110 up to the silicon germanium (SiGe) etch stop layer, allowing for self-aligned contacts without touching the device.

[0043]

[0080] The cavity 119 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, a hard mask 117 is deposited to block non-Vss / Vdd source / drains. In one or more embodiments, the hard mask 117 may comprise any suitable material known to those skilled in the art. In some embodiments, the hard mask 117 is resist. Once the hard mask 117 is formed, the cavity 119 is formed by etching.

[0044]

[0081] The etching process of step 26 may include any suitable etching process that is selective to the source-drain trenches 118. In some embodiments, the etching process of step 26 may include one or more of a wet etching process or a dry etching process. The etching process may be a directional etch.

[0045]

[0082] In some embodiments, the dry etching process can include conventional plasma etching or a remote plasma-assisted dry etching process, such as the SiCoNi™ etch process available from Applied Materials, Inc., Santa Clara, California. In the SiCoNi™ etch process, the device is exposed to H, NF, and / or NH plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device can be subjected to simultaneous exposure to H, NF, and NH plasma. The SiCoNi™ etch process is performed in a SiCoNi™ Preclean chamber and can be integrated into one of various multi-processing platforms, including the Centura™, Dual ACP, Producer™ GT, and Endura™ platforms available from Applied Materials. The wet etching process can include a hydrofluoric (HF) acid last process, or the so-called "HF last" process. In this process, an HF etch of the surface is performed, leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process can be used. In some embodiments, the process includes sublimation etching to remove native oxide. The etching process can be plasma-based or thermal-based. The plasma process can be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0046]

[0083] 1A and 2H, in step 28, a sacrificial material 120 is deposited in the cavity 119. The sacrificial material may include any suitable material known to those skilled in the art. In some embodiments, the sacrificial material 120 includes silicon germanium (SiGe). In one or more embodiments, the sacrificial material 120 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without wishing to be bound by theory, it is believed that a germanium content in the range of 30% to 50% increases the selectivity of the sacrificial material and minimizes stress defects.

[0047]

[0084] In one or more embodiments, the sacrificial material 120 is doped with a dopant for lower contact resistance. In some embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorous (P), arsenic (As), other semiconductor dopants, or combinations thereof. In a specific embodiment, the sacrificial material 120 is silicon germanium doped with a dopant selected from one or more of boron (B), gallium (Ga), phosphorous (P), and arsenic (As), with a germanium content in the range of 30% to 50%.

[0048]

[0085] 1A and 2I, in step 30, an inner spacer layer 121 is formed on each of the horizontal channel layers 104. The inner spacer layer 121 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer layer 121 comprises a nitride material. In a specific embodiment, the inner spacer layer 121 comprises silicon nitride.

[0049]

[0086] 2J and 1A, in step 32, in some embodiments, buried source / drain regions 122 are formed in source / drain trenches 118. In some embodiments, source region 122 is formed adjacent a first end of superlattice structure 101, and drain region 122 is formed adjacent an opposite second end of the superlattice structure. In some embodiments, source region and / or drain region 122 are formed from any suitable semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphide (SiP), silicon arsenide (SiAs), etc. In some embodiments, source / drain regions 122 can be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, source / drain regions 122 are independently doped with one or more of phosphorous (P), arsenic (As), boron (B), and gallium (Ga).

[0050]

[0087] 1A and 2K, in step 34, an interlevel dielectric (ILD) layer 124 is blanket deposited on the substrate 102, including the source / drain regions 122, the dummy gate structure 113, and the sidewall spacers 116. Conventional chemical vapor deposition techniques (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition) may be used to deposit the ILD layer 124. In one or more embodiments, the ILD layer 124 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer 124 is then polished back using conventional chemical mechanical planarization to expose the top surface of the dummy gate structure 113. In some embodiments, the ILD layer 124 is polished back to expose the top surface of the dummy gate structure 113 and the top surfaces of the sidewall spacers 116.

[0051]

[0088] The dummy gate structure 113 may be removed to expose the channel region 108 of the superlattice structure 101. The ILD layer 124 protects the source / drain regions 122 during removal of the dummy gate structure 113. The dummy gate structure 113 may be removed using conventional etching methods, such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 comprises polysilicon, and the superlattice structure 101 comprises alternating layers of silicon (Si) and silicon germanium (SiGe).

[0052]

[0089] 1B and 2L, in step 38, formation of a semiconductor device, e.g., a GAA, continues according to conventional procedures involving nanosheet release and replacement metal gate formation. Specifically, in one or more non-illustrated embodiments, the semiconductor material layers 106 are selectively etched between the horizontal channel layers 104 in the superlattice structure 101. For example, if the superlattice structure 101 is composed of silicon (Si) and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The semiconductor material layers 106, e.g., silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the horizontal channel layers 104, where the etchant etches the semiconductor material layers 106 significantly faster than the horizontal channel layers 104. In some embodiments, a selective dry etching or wet etching process can be used. In some embodiments, when the horizontal channel layers 104 are silicon (Si) and the semiconductor material layers 106 are silicon germanium (SiGe), the silicon germanium layers can be selectively removed using a wet etchant, such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution. Removal of the semiconductor material layers 106 leaves voids between the horizontal channel layers 104. The voids between the horizontal channel layers 104 have a thickness of about 3 nm to about 20 nm. The remaining horizontal channel layers 104 form a vertical array of channel nanowires connected to the source / drain regions 122. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0053]

[0090] In one or more embodiments, a high-k dielectric is formed. The high-k dielectric may be any suitable high-k dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-k dielectric comprises hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-k dielectric to form the replacement metal gate 128. To ensure formation of a layer with a uniform thickness around each of the multiple channel layers, the conductive material may be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD).

[0054]

[0091] 1B and 2M, in step 38, a contact to transistor (CT) 132 and a contact to gate (CG) 134 are formed.

[0055]

[0092] 1B and 2N, in step 40, metal (M0) lines 142 are formed and electrically connected to vias (V1) 144. This is similar to conventional processing, except that the M0 lines do not have power rails, leaving enough space for signal lines.

[0056]

[0093] 2O, in step 42, device 100 is rotated or flipped 180 degrees so that substrate 102 is now at the top of the figure. Additionally, in one or more embodiments, substrate 102 is planarized. Planarization can be any suitable planarization process known to those skilled in the art, including but not limited to chemical mechanical planarization (CMP). In one or more embodiments, prior to rotation, the front side is bonded to copper (Cu) metallization in the final layer by hybrid bonding (oxide-to-oxide and Cu-to-Cu) or electrostatic dummy wafer bonding.

[0057]

[0094] 1B and 2P, in step 44, an interlayer dielectric 146 / 148 is deposited on the backside. The interlayer dielectric material 146 / 148 may be deposited by any suitable means known to those skilled in the art. The interlayer dielectric material 146 / 148 may include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric material 146 / 148 includes one or more of silicon nitride (SiN), carbide, or boron carbide to enable high aspect ratio etching and metallization.

[0058]

[0095] 2Q, in step 46, in one or more embodiments, backside power rail vias 152 are formed. The vias 152 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, the vias 152 may be formed by patterning and etching the interlayer dielectric material 146 / 148.

[0059]

[0096] 1B and 2R, in step 48, a damascene trench 154 is formed by extending the via 152 to the contacts 120, 122. Extending the via 152 to form the trench 154 at least doubles the size of the opening, allowing for self-alignment. In one or more embodiments, the via 152 has a starting size of about 16 nm by about 26 nm and is extended to form the trench 154 having a size of about 90 nm by about 74 nm.

[0060]

[0097] The damascene trench 154 stops at the contacts 120, 122. The damascene trench 154 can have any suitable aspect ratio known to those skilled in the art. In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater. In one or more embodiments, the critical dimensions of the damascene 154 are about 16 nm by about 26 nm, or about 10 nm by about 30 nm, or about 15 nm by about 30 nm. In one or more embodiments, the height of the backside via depends on the thickness of the original epitaxial layer deposited on the etch stop layer.

[0061]

[0098] 2S, in step 50, the sacrificial layer 120 is selectively removed to form openings 156 over the source / drains 122. In one or more embodiments, if the sacrificial layer 120 is doped with one or more of Ga, B, and P, the sacrificial layer 120 may be partially removed, leaving a portion behind. The partial removal of the sacrificial layer 120 allows for the formation of low resistance contacts to the remaining sacrificial layer 120 (e.g., SiGe).

[0062]

[0099] In step 52, as shown in FIG. 2T, a metal fill 156 is deposited in the opening 156 formed by the removal of the sacrificial layer 120. The metal fill 156 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the metal fill 156 is selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0063]

[0100] 1B and 2U, in step 54, backside metal lines (MO) 160 are formed. Without wishing to be bound by theory, it is believed that placing the power rails on the backside can increase the cell area by between 20% and 30%.

[0064]

[0101] FIG. 3 shows a process flow diagram of a method 60 for thinning a semiconductor wafer according to some embodiments of the present disclosure. FIGS. 4A-4E show stages of wafer thinning according to some embodiments of the present disclosure. Method 60 is described below with respect to FIGS. 4A-4E. FIGS. 4A-4E are cross-sectional views of an electronic device (e.g., a GAA) according to one or more embodiments. Method 60 may be part of a multi-step manufacturing process for semiconductor devices. Thus, method 60 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0065]

[0102] Figures 4A-4E illustrate the fabrication steps of steps 62-76 of Figure 3. Referring to Figure 3, a method 60 for thinning a device 400 begins with step 62. Referring to Figures 3 and 4A-4E, in one or more embodiment methods, a transistor, such as a gate-all-around transistor, is fabricated using a standard process flow.

[0066]

[0103] In some embodiments, a silicon wafer 402 is provided, and in step 62, a buried etch stop layer 404 is formed on the silicon wafer. The buried etch stop layer 404 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 comprises silicon germanium (SiGe). In one or more embodiments, the buried etch stop layer 404 has a high germanium (Ge) content. In one or more embodiments, the amount of germanium is in the range of 30% to 50%, including the range of 35% to 45%. Without wishing to be bound by theory, it is believed that a germanium content in the range of 30% to 50% increases the selectivity of the buried etch stop layer 404 and minimizes stress defects.

[0067]

[0104] In one or more non-illustrated embodiments, an epitaxial layer, such as epitaxial silicon, is deposited in step 64. The wafer then undergoes device and front-end processing in step 66. The front-end processing can be the processes described above with respect to method 6 as shown in Figures 1A-1B and in cross-sectional views in Figures 2A-2U.

[0068]

[0105] 3 and 4B, in one or more embodiments, after front-end processing, wafer 400 undergoes hybrid bonding, for example to copper or oxide, and then the wafer is advantageously thinned at step 68. Without wishing to be bound by theory, it is believed that thinning the wafer advantageously provides the desired planarity and bonding properties to allow for backside power rails.

[0069]

[0106] 3 and 4C , to thin the wafer, in step 70, a silicon substrate layer 402 having a starting first thickness t1 is polished to a second thickness t2 that is less than the first thickness. The silicon substrate layer 402 may be polished by any suitable means known to those skilled in the art. In some embodiments, the silicon substrate layer 402 is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon substrate layer 402 to a third thickness t3 that is less than the second thickness. In one or more embodiments, the first thickness is in the range of 500 μm to 1000 μm. In one or more embodiments, the second thickness is in the range of 20 μm to 100 μm. In one or more embodiments, the third thickness is in the range of 1 μm to 20 μm.

[0070]

[0107] 3 and 4D, in step 72, the buried etch stop layer 404 is selectively removed to expose the source / drain 408. Then, in step 74, the contacts 410 are pre-filled with a metal, followed by metallization, as shown in FIG. 4E. In one or more embodiments, the contacts 410 are pre-filled with a metal selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0071]

[0108] Figures 5A-5E illustrate alternative manufacturing steps to steps 78-80 of Figure 3. Referring to Figure 3, a method 60 for thinning a device 400 begins with step 62 and proceeds to step 70, as shown in detail in Figures 4A-4C.

[0072]

[0109] After silicon substrate 402 is thinned by silicon polishing in step 70, the method proceeds to step 78, where a large mask 502 is formed over buried etch stop layer 404. Mask 502 may comprise any suitable material known to those skilled in the art. In one or more embodiments, mask 502 is selected from one or more of carbide, boron carbide, and silicon nitride.

[0073]

[0110] In step 80, the mask 502 is etched to form a plurality of through-silicon vias (TSVs) 508, which extend down to the buried etch stop layer 404. The vias 508 may be formed by any suitable means known to those skilled in the art. In one or more embodiments, the vias 508 are formed by etching. The nanometer-sized TSVs allow for high-density packaging of the formed device or other chips connected to the device without the need for traditional large TSVs, which add cost and space in typical 3D packaging.

[0074]

[0111] 3 and 5C, in step 82, the buried etch stop layer 404 is selectively removed to form an opening 510. The buried etch stop layer 404 may be selectively removed by any suitable means known to those skilled in the art. In one or more embodiments, the buried etch stop layer 404 is selectively removed by etching the sides of the device.

[0075]

[0112] 3 and 5D, in step 84, the mask 502 with the vias 508 is lifted off from the device. Lift-off can be performed by any suitable means known to those skilled in the art. In one or more embodiments, lift-off can thin the wafer to a thickness in the range of 50 nm to 100 nm. In one or more embodiments, lift-off results in a thinned wafer that is substantially defect- and scratch-free in the device 500. In one or more embodiments, lift-off requires etching the sides of the sacrificial layer 120 across the wafer (an isotropic etch), which is achieved by a Selectra® etch.

[0076]

[0113] FIG. 6 shows a process flow diagram for a method 600 of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIGS. 7A-7D show stages of forming a deep via and a backside contact according to some embodiments of the present disclosure. Method 600 is described below with reference to FIGS. 7A-7D. FIGS. 7A-7D are cross-sectional views of an electronic device (e.g., a GAA) 700 according to one or more embodiments. Method 600 may be part of a multi-step manufacturing process of a semiconductor device. Thus, method 600 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in manufacturing semiconductor devices.

[0077]

[0114] 7A-7D illustrate the fabrication steps of steps 602-614 of FIG. 6. Referring to FIG. 6, a method 600 for forming deep vias and backside contacts begins at step 602. Referring to FIG. 6 and FIGS. 7A-7D, in one or more embodiments of the method 600, a transistor, such as a gate-all-around transistor, is fabricated at step 602 using a standard process flow. The device 700 may be formed according to the methods described with respect to FIGS. 1A-1B and 2A-2Q.

[0078]

[0115] 7A, in step 604, at least one deep via 702 is formed on the front side. The deep via 702 can have any suitable size or shape. The deep via 702 can have any suitable aspect ratio (ratio of feature depth to feature width). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1, or about 40:1 or greater. In one or more embodiments, the critical dimensions of the deep via 702 are about 16 nm by about 16 nm, or about 10 nm by about 10 nm, or about 15 nm by about 15 nm, or about 20 nm by about 20 nm.

[0079]

[0116] 6 and 7B, in step 606, deep via 702 may be filled with metal 704. Metal 704 may be any suitable metal known to those skilled in the art. In one or more embodiments, metal 704 is selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like.

[0080]

[0117] 6 and 7C, in step 608, a bonded wafer 706 is bonded to the front side. In step 610, the substrate 708 may optionally be thinned according to one or more methods described above with respect to FIG. 3. As shown in FIG. 7D, in step 612, contacts 710 are then formed and electrically connected to the metal 704 in the deep vias 702. The contacts 710 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the contacts 710 comprise a metal selected from one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), ruthenium (Ru), and the like. In step 614, metallization is performed, as shown in FIG. 7D.

[0081]

[0118] In some embodiments, the methods are integrated without breaking vacuum. In one or more embodiments, method 60 is a via etch (step 80), buried sacrificial layer removal (step 82), and substrate release lift-off (step 84), which can be integrated without breaking vacuum between steps.

[0082]

[0119] An additional embodiment of the present disclosure is directed to a processing tool 300 and described methods for forming GAA devices, as shown in FIG. 8. Various multi-processing platforms may be utilized, including Applied Materials' Reflexion® CMP, Selectra® Etch, Centura®, Dual ACP, Producer® GT, and Endura® platforms, as well as other processing systems. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move the robot blade and wafer to each of the multiple sides.

[0083]

[0120] The cluster tool 300 includes multiple processing chambers 308, 310, 312, also referred to as process stations, connected to a central transfer station. The various processing chambers provide distinct processing regions separate from adjacent processing stations. The processing chambers may be any suitable chamber, such as, but not limited to, a pre-clean chamber, a deposition chamber, an annealing chamber, an etch chamber, etc. The specific arrangement of processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure.

[0084]

[0121] 8, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a loading and unloading chamber 302 at the front 319 of the factory interface 318.

[0085]

[0122] The size and shape of the loading and unloading chambers 302 can vary depending on, for example, the substrates to be processed in the cluster tool 300. In the illustrated embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette with multiple wafers positioned within the cassette.

[0086]

[0123] The robot 304 resides within a factory interface 318 and can move between the loading chamber 302 and the unloading chamber 302. The robot 304 can transfer wafers from a cassette in the loading chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 can also transfer wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unloading chamber 302.

[0087]

[0124] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0088]

[0125] A system controller 357 is in communication with the robot 316 and the plurality of processing chambers 308, 310, 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and robot. For example, the system controller 357 can be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, appropriate circuitry 398, and storage.

[0089]

[0126] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0090]

[0127] In some embodiments, the system controller 357 is configured to control the rapid thermal processing chamber to crystallize the template material.

[0091]

[0128] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, including a template deposition chamber and a template crystallization chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move wafers between the process stations and to control the process performed at each of the process stations.

[0092]

[0129] In the context of describing the materials and methods discussed herein (particularly in the context of the claims that follow), the use of "a" and "an," "the," and similar referents should be construed to encompass both the singular and the plural unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not limit the scope unless specifically claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0093]

[0130] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "a particular embodiment," "in one embodiment," or "an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0094]

[0131] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure includes modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, the method comprising: forming an etch stop layer on a top surface of the substrate having a first thickness; forming an epitaxial layer on top of the etch stop layer; forming a wafer device on an upper surface of the epitaxial layer; bonding the wafer device to a bonded wafer; polishing the substrate to form a substrate having a second thickness less than the first thickness; planarizing the substrate to form a substrate having a third thickness less than the second thickness; removing the etch stop layer to expose source / drain regions on the wafer device; forming contacts electrically connected to the source / drain regions; Including, The method, wherein the etch stop layer comprises silicon germanium (SiGe) having a germanium (Ge) content in the range of 30% to 50%.

2. 1. A method of forming a semiconductor device, the method comprising: forming an etch stop layer on a top surface of the substrate having a first thickness; forming an epitaxial layer on top of the etch stop layer; forming a wafer device on an upper surface of the epitaxial layer; bonding the wafer device to a bonded wafer; polishing the substrate to form a substrate having a second thickness less than the first thickness; planarizing the substrate to form a substrate having a third thickness less than the second thickness; removing the etch stop layer to expose source / drain regions on the wafer device; forming contacts electrically connected to the source / drain regions; Including, the etch stop layer comprises silicon germanium (SiGe); The method, wherein the silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof.

3. The method of claim 1 or claim 2, wherein the first thickness is in the range of 500 μm to 1000 μm.

4. 3. The method of claim 1 or claim 2, wherein the second thickness is in the range of 20 μm to 100 μm.

5. The method of claim 1 or claim 2, wherein the third thickness is in the range of 1 μm to 20 μm.

6. forming the wafer device, forming a superlattice structure on top of the etch stop layer on the substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs; forming a gate structure on an upper surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches on the substrate adjacent to the superlattice structure; forming an inner spacer layer on each of the plurality of horizontal channel layers; forming source and drain regions; forming a replacement metal gate; forming a contact to a transistor (CT) and a contact to a gate (CG) in electrical contact with the source and drain regions; forming a first metal line; 3. The method of claim 1 or claim 2, comprising:

7. 7. The method of claim 6, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently comprise one or more of silicon germanium (SiGe) and silicon (Si).

8. The method of claim 6 , wherein forming the source and drain regions comprises growing an epitaxial layer thereon.

9. 7. The method of claim 6, wherein the source and drain regions are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

10. The method of claim 6 further comprising forming a dielectric layer over the gate structure and the superlattice structure.

11. 7. The method of claim 6, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-type doped polysilicon.

12. 1. A method of forming a semiconductor device, the method comprising: forming an etch stop layer on a top surface of the substrate having a first thickness; forming an epitaxial layer on top of the etch stop layer; forming a wafer device on an upper surface of the epitaxial layer; bonding the wafer device to a bonding dummy wafer or a Cu wafer by hybrid bonding; polishing the substrate to form a substrate having a second thickness less than the first thickness; depositing a mask layer over a bottom surface of the etch stop layer; forming at least one via opening in the mask layer; selectively removing the etch stop layer; removing the mask layer by lift-off to expose the substrate having a fourth thickness less than the second thickness; A method comprising:

13. The method of claim 12, wherein the first thickness is in the range of 500 μm to 1000 μm.

14. The method of claim 12 , wherein the fourth thickness is in the range of 50 nm to 100 nm.

15. The method of claim 12 , wherein the etch stop layer comprises silicon germanium (SiGe).

16. 16. The method of claim 15, wherein the silicon germanium (SiGe) has a germanium (Ge) content in the range of 30% to 50%.

17. 16. The method of claim 15, wherein the silicon germanium (SiGe) is doped with a dopant selected from the group consisting of boron (B), gallium (Ga), phosphorus (P), arsenic (As), and combinations thereof.

18. forming the wafer device, forming a superlattice structure on top of the etch stop layer on the substrate, the superlattice structure including a plurality of horizontal channel layers and a corresponding plurality of layers of semiconductor material arranged alternately in a plurality of stacked pairs; forming a gate structure on an upper surface of the superlattice structure; forming a plurality of source trenches and a plurality of drain trenches on the substrate adjacent to the superlattice structure; forming an inner spacer layer on each of the plurality of horizontal channel layers; forming source and drain regions; forming a replacement metal gate; forming a contact to a transistor (CT) and a contact to a gate (CG) in electrical contact with the source and drain regions; forming a first metal line; 13. The method of claim 12, comprising:

Images