Phase adjustment processing system, phase adjustment processing method, and phase adjustment processing method program

Abstract

To obtain a phasing processing system, etc., with which, while having the capability of suppressing a noise signal in either of orthogonal axis directions, it is possible to suppress a computing amount in adaptive phasing processing.SOLUTION: The present invention comprises: a subarray division processing device 10 that carries out the process of dividing a plurality of signals pertaining to the detection of a sensor array 200 which is composed by arraying a plurality of sensor 201 in a plurality of orthogonal axis directions and generating as a signal pertaining to the detection of a plurality of subarrays; an elevation phasing processing device 20 that carries out phasing processing on the basis of the signals processed by the subarray division processing device 10; and a horizontal phasing processing device 30 that carries out phasing processing on the basis of the results of phasing processing carried out by the elevation phasing processing device 20. The subarray division processing device 10 includes: a first subarray division processing unit 11 that divides a plurality of signals along some axis direction and generates a first subarray signal; and a second subarray division processing unit 12 that divides the first subarray signal into a plurality of second subarray signals and outputs these to the elevation phasing processing device 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This technology relates to a phasing processing system and method that performs phasing processing based on signals detected by multiple sensors, and a program that causes a computer to perform this method, particularly to improve the performance of phasing processing. [Background technology]

[0002] When processing vibration waves such as sound waves as signals, signal processing (phase-matching processing) is performed by arranging the phase of the signals received by a sensor array, which is a 2D (planar) or 3D (three-dimensional) arrangement of multiple sensors that receive the signals. Conventional beamforming (CBF) is a technique for phasing signals received from the desired elevation (height or vertical) and horizontal directions. CBF calculates the propagation delay between sensors when a signal arrives from the desired direction, and multiplies and adds (product-sum) the inverse filter coefficients of the delay to the signals detected by each sensor to extract signals from the desired direction and suppress signals from other directions.

[0003] In recent years, a type of phasing processing called adaptive phasing processing has been widely used. Adaptive phasing processing is a method of adaptively performing phasing processing based on information about the signal detected by the sensor and the signal that becomes noise (noise signal). Adaptive phasing processing makes it possible to suppress signals arriving from directions other than the desired direction while maintaining the sensitivity of the signal arriving from the desired direction.

[0004] Examples of adaptive phasing include Dominant Mode Rejection (DMR), Minimum Variance Distortionless Response (MVDR), and Eigenvector / Beam Association and Excision (EBAE) (see, for example, Non-Patent Document 1). All of these adaptive phasing methods are superior to CBF in their ability to suppress noise signals.

[0005] However, all adaptive phasing processes require a large amount of computation for real-time processing, such as estimating the covariance matrix and calculating the inverse matrix. Therefore, forming a three-dimensional directivity pattern using standard adaptive phasing processes, such as calculating the covariance matrix from the signals detected by all sensors, requires a huge amount of computation. Therefore, when performing three-dimensional phasing, we employ separated phasing processes that take advantage of the symmetry characteristics of the array to reduce the amount of computation. For example, when phasing a surface array with 6x6 sensors, separated adaptive phasing processes can process the signal with approximately 1 / 136 the amount of computation required for standard adaptive phasing processes. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Stephen M. Kogon, “Experimental results for passive sonar arrays with eigenvector-based adaptive beamformers”, Signal, Systems and Computers, 2002 Summary of the Invention [Problem to be solved by the invention]

[0007] The above-mentioned separate adaptive phasing processing provides high directivity and a high ability to suppress noise signals in the horizontal direction due to adaptive phasing. However, the directivity in the elevation direction is equivalent to CBF. As a result, the ability to suppress noise signals arriving from directions with the same horizontal azimuth but different elevation angles is low. If normal adaptive phasing processing is performed using signals from all sensors in an attempt to improve the ability to suppress noise signals in the elevation direction, the amount of calculation increases, and an extremely large number of computational resources are required to ensure real-time performance.

[0008] For these reasons, it has been desired to realize a phasing processing system that has the ability to suppress noise signals in both orthogonal axial directions while reducing the amount of calculation required for adaptive phasing processing. [Means for solving the problem]

[0009] The phasing processing system according to the present disclosure includes a subarray division processing device that divides a plurality of signals related to detection by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axial directions and processes the signals to generate signals related to detection by a plurality of subarrays, a front-stage phasing processing device that performs front-stage phasing processing based on the signals processed by the subarray division processing device, and a rear-stage phasing processing device that performs rear-stage phasing processing based on the processing result of the front-stage phasing processing performed by the front-stage phasing processing device, and the subarray division processing device has a first subarray division processing device that divides the plurality of signals along a certain axial direction to generate signals of a first subarray, and a second subarray division processing device that divides the signals of the first subarray into a plurality of second subarray signals and outputs them to the front-stage phasing processing device. The first subarray division processing unit generates first subarray signals for each frequency, and the second subarray division processing unit divides the first subarray signals selected so as to be the phasing center set for each frequency into a fixed number of second subarray signals. It is something.

[0010] The phasing method according to the present disclosure further comprises dividing, along a certain axis, a plurality of signals detected by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axis directions, For each frequency a first subarray division step of generating signals for the first subarray; The center of the phase was selected for each frequency. The signal of the first subarray A fixed number ofThe method includes a second subarray division step of dividing the signals into second subarray signals, a front-end phasing processing step of performing front-end phasing processing based on the divided second subarray signals, and a rear-end phasing processing step of performing rear-end phasing processing based on the processing results of the front-end phasing processing.

[0011] The program for the phasing method according to the present disclosure divides, along a certain axis, a plurality of signals detected by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axis directions, For each frequency a first subarray division step of generating signals for the first subarray; The center of the phase was selected for each frequency. The signal of the first subarray A fixed number of The computer is caused to perform a second subarray division step of dividing the signals into second subarray signals, a front-end phasing processing step of performing front-end phasing processing based on the divided second subarray signals, and a rear-end phasing processing step of performing rear-end phasing processing based on the processing results of the front-end phasing processing. [Effects of the Invention]

[0012] According to the disclosed phasing processing system, not only is the signal of the first subarray divided along a certain axial direction, but the signal of the first subarray is also divided along an axial direction different from the certain axial direction into signals of a plurality of second subarrays for phasing processing. As a result, in the subsequent phasing processing device, phasing processing can be performed based on the processing results along multiple orthogonal axial directions. Therefore, noise signals in multiple orthogonal axial directions can be suppressed, and the accuracy of extracting the target signal can be improved. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a diagram showing a configuration centered on a phasing processing system 100 according to a first embodiment. [Figure 2] 1 is a diagram illustrating a sensor array 200 according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing a coordinate system used for explanation in the embodiment. [Figure 4] 2 is a diagram illustrating an example of a hardware configuration of each device in the phasing processing system 100 according to the first embodiment. FIG. [Figure 5] 3 is a diagram illustrating a processing flow in the phasing processing system 100 according to the first embodiment. FIG. [Figure 6] 3 is a diagram illustrating an example of processing in the subarray division processing device 10 according to the first embodiment. FIG. [Figure 7] FIG. 1 is a diagram showing a configuration centered on a phasing processing system 100 according to a second embodiment. [Figure 8] FIG. 10 is a diagram illustrating an example of processing by a second frequency-by-frequency subarray division processing unit 13 according to the second embodiment. [Figure 9] FIG. 10 is a diagram illustrating another example of processing by the second frequency-based subarray division processing unit 13 according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] The following describes a phasing processing system according to an embodiment, with reference to the drawings. In the following drawings, components with the same reference numerals are identical or equivalent and are common throughout the following embodiments. The size relationships between components in the drawings may differ from those in reality. The configurations of components shown throughout the specification are merely examples and are not limited to the configurations described in the specification. Not all of the devices described in the specification may be included. In particular, the combinations of components are not limited to the combinations in each embodiment, and components described in other embodiments may be applied to other embodiments. Furthermore, when multiple similar devices are distinguished by subscripts, the reference numerals, subscripts, etc. may be omitted if there is no need to distinguish or identify them.

[0015] Embodiment 1 1 is a diagram showing a configuration centered around a phasing processing system 100 according to the first embodiment. The phasing processing system 100 in the first embodiment performs processing based on signals from a sensor array 200. The sensor array is, for example, a radar or a sonar.

[0016] FIG. 2 is a diagram illustrating a sensor array 200 according to the first embodiment. FIG. 3 is a diagram illustrating a coordinate system used for the purposes of explanation in the embodiments. In the following description, as shown in FIG. 3, the angle from the x-axis to the y-axis (the angle in the xy plane) is defined as the horizontal angle θ, and the angle from the xy plane to the z-axis is defined as the elevation angle φ. For example, in FIG. 3, for a point P in a three-dimensional orthogonal space consisting of the x-axis, y-axis, and z-axis, the angle xOp at point p when point P is projected onto the xy plane is the horizontal angle θ. The sensor array 200 shown in FIG. 2 has multiple receivers, sensors 201-(1×1) to 201-(N×M). Each sensor 201 sends a detected signal to the phasing processing system 100. Each sensor 201 sends a signal detected at the same time at a constant period. The sensor array 200 in FIG. 2 is a surface array composed of N stacks of sensors 201 in the z-axis direction and M staves of sensors 201 in the y-axis direction. Here, in the first embodiment, each sensor 201 will be described as detecting a signal related to reception of a sound wave.

[0017] The phasing processing system 100 shown in Fig. 1 is a system that divides and processes the signals output from each sensor 201 of the sensor array 200. The phasing processing system 100 performs phasing processing in the elevation direction and phasing processing in the horizontal direction on the signals from the sensor array 200 in two stages, a front stage and a rear stage. The phasing processing system 100 includes an input terminal k, a subarray division processing device 10, an elevation phasing processing device 20, a horizontal phasing processing device 30, and an output terminal R out The input terminal k receives signals sent from the sensors 201 of the sensor array 200. Here, the input terminal k has N×M terminals, namely, input terminal k-(1×1) to input terminal k-(N×M). Also, the output terminal R outis the three-dimensional phasing result y obtained by the horizontal phasing processor 30 performing phasing processing. θφ Here, if the signal from the sensor array 200 can be input in a time-division manner, the number of input terminals k does not need to be N×M.

[0018] The subarray division processing device 10 is a device that generates and processes N×M signals received by each sensor 201 of the sensor array 200 at a certain time as signals for a plurality of virtually configured subarrays by dividing the sensor array 200. The subarray division processing device 10 in the first embodiment has a first subarray division processing unit 11 and a second subarray division processing unit 12. The first subarray division processing unit 11 performs a first subarray division step of dividing a plurality of signals for each set first subarray. Here, the first subarray division processing unit 11 further performs processing such as division for each frequency (frequency includes a set frequency band) based on the divided signals to generate signals for each first subarray. Here, the first subarrays are set by dividing the sensors 201 of the sensor array 200 for each stave and grouping the sensors 201 aligned in the stacking direction as subarrays. Therefore, M first subarrays are generated. The second subarray division processing unit 12 performs a second subarray division step of dividing the signals of each first subarray for each set second subarray. The second subarrays are set by further dividing each first subarray into a plurality of groups. The division process performed by the subarray division processing device 10 will be described later. Hereinafter, the signals of the sensors 201 constituting the first subarray and the data in the signals may be referred to as the first subarray. Similarly, the signals of the sensors 201 constituting the second subarray and the data in the signals may be referred to as the second subarray.

[0019] The elevation phasing processor 20 is a front-end phasing processor that performs phasing processing related to the elevation direction on the front-end. The elevation phasing processor 20 has a subarray elevation phasing processor 21. The subarray elevation phasing processor 21 performs elevation phasing processing (front-end phasing processing step) based on the desired elevation azimuth for each second subarray generated by the subarray division processor 10.

[0020] The horizontal phasing processor 30 is a subsequent-stage phasing processor that performs phasing processing related to the horizontal direction on the subsequent stage. The horizontal phasing processor 30 performs horizontal phasing processing based on the horizontal azimuth (subsequent-stage phasing processing step) based on the processing result of the elevation phasing processor 20. The horizontal phasing processor 30 has a covariance matrix processor 31, a 3D adaptive weight calculation processor 32, and a product-sum processor 33. The covariance matrix processor 31 calculates a covariance matrix R related to the estimation between the divided signals based on the processing result of the elevation phasing processor 20. φ Furthermore, the steric adaptive weight calculation processor 32 calculates the covariance matrix R φ Then, the product-sum processor 33 performs calculations such as multiplying the processing result from the elevation phasing processor 20 by the stereo adaptive weight, and obtains the stereo phasing result y θφ The calculation process is performed.

[0021] FIG. 4 illustrates an example of the hardware configuration of each device in the phasing processing system 100 according to the first embodiment. The phasing processing system 100 is, for example, an information processing device including a computer. The phasing processing system 100 includes a storage unit 60 and a control unit 50. The storage unit 60 stores the results of the arithmetic processing performed by the control unit 50. The storage unit 60 is, for example, a recording device such as a hard disk drive (HDD) or a solid state drive (SSD). The control unit 50 includes a control processing device 51 such as a central processing unit (CPU) that executes processing according to a program. The control unit 50 also includes a memory 52 such as a read-only memory or random access memory that stores the program. The control unit 50 implements the processing performed by the subarray division processing device 10, the elevation phasing processing device 20, and the horizontal phasing processing device 30.

[0022] Here, some or all of the processing functions performed by each device in the phasing processing system 100 may be configured using dedicated circuits. The dedicated circuits may be a single circuit, a composite circuit, a programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or the like. The dedicated circuits may also be a combination of these circuits. By having the dedicated circuits perform some or all of the signal processing, it is possible to increase the speed of signal processing. Furthermore, the functions of each device and section of the phasing processing system 100 may be shared and processed by multiple information processing devices.

[0023] 5 is a diagram illustrating a processing flow in the phasing processing system 100 according to the first embodiment. In the phasing processing system 100, the first subarray division processing unit 11 of the subarray division processing device 10 performs a first subarray division step of dividing a signal from the sensor array 200 and generating first subarrays (step S1). Furthermore, the second subarray division processing unit 12 of the subarray division processing device 10 performs a second subarray division step of dividing the first subarray and generating second subarrays (step S2).

[0024] Further, the subarray elevation phasing processor 21 of the elevation phasing processor 20 performs an elevation phasing process, which is a front-stage phasing process, for each second subarray (step S3). The elevation phasing process is performed by CBF. Furthermore, the horizontal phasing processor 30 performs a horizontal phasing process, which is a rear-stage phasing process, based on the processing result of the elevation phasing processor 20 (step S4). The horizontal phasing process is performed by adaptive phasing. Finally, the horizontal phasing processor 30 outputs the phasing process result y, which is a result of phasing processes performed in the elevation and horizontal directions. φ is output (step S5) and the process ends.

[0025] FIG. 6 is a diagram illustrating an example of processing in the subarray division processing device 10 according to the first embodiment. Here, processing in each device of the phasing processing system 100 according to the first embodiment will be described. First, when the first subarray division processing unit 11 of the subarray division processing device 10 receives a signal from the sensor array 200 via the input terminal k, it divides the signal for each stage as described above to generate M first subarrays. The matrix x representing the i-th first subarray at a certain frequency divided into M subarrays is i is expressed by the following equation (1), where 1≦i≦M. Also, T represents transpose. Therefore, the matrix x i is a matrix with 1×N elements.

[0026]

number

[0027] As described above, in the first embodiment, the second subarray division processing unit 12 divides each first subarray to generate second subarrays. Here, the second subarray division processing unit 12 divides N signals in the first subarray into s signals each to generate second subarrays. By dividing the first subarrays, the number of second subarrays (the number of divisions) becomes L. In FIG. 6, the sensors 201 in the first subarray are grouped into three groups to generate two second subarrays. However, the number of second subarrays generated by the second subarray division processing unit 12 by dividing the first subarray is not limited to this. The number of second subarrays may be determined by a trade-off between the amount of computation required for phasing processing in the horizontal direction and the ability to remove noise signals in the elevation direction (including irregular signals such as interference signals that arrive from other directions and interfere with the detection of target signals). The second subarray division processing unit 12 may also generate second subarrays by overlapping signals in the direction in which the stacks are arranged (the z-axis direction). In this way, L×M second subarrays are generated in the entire subarray division processing device 10.

[0028] The matrix x represents the h-th second subarray, which is a subarray of the i-th first subarray divided into s subarrays. i,h is expressed by the following equation (2), where 1≦i≦M and 1≦h≦L. T represents transpose. Therefore, the matrix x i,h is a matrix having 1×s elements. The subarray division processing device 10 outputs L×M second subarrays to the elevation phasing processing device 20.

[0029]

number

[0030] The subarray elevation phasing processor 21 of the elevation phasing processor 20 performs elevation phasing processing for the desired elevation direction for each second subarray. The subarray elevation phasing processor 21 regards the s sensors 201 corresponding to the h-th second subarray as a line array in the z-axis direction ((x, y) = (0, 0)) and performs phasing processing. The steering vector w of the signal for the desired elevation direction is h is expressed by the following equation (3). Here, j represents a complex operator. Also, ω represents an angular frequency. τ represents a delay time when the sensor 201, which is the phasing center of the second subarray, is positioned at the position of the second subarray. Also, T represents a transpose. Therefore, the steering vector w h is a matrix with 1×s elements.

[0031]

number

[0032] Furthermore, the subarray tilt beam processing unit 21 converts the beam processing result y φ is calculated based on the following equation (4). Here, H represents the complex conjugate transpose of the matrix. Furthermore, T represents the transpose. The phase adjustment processor 20 calculates the phase adjustment result y φ is output to the horizontal phasing processor 30.

[0033]

number

[0034] The covariance matrix processing unit 31 of the horizontal phasing processing unit 30 calculates the covariance matrix R based on the following equation (5): φ Calculate the covariance matrix R at the elevation angle φ. φ is y φ y φ H where K is the covariance matrix R φ is the integration time. k is the time index.

[0035]

number

[0036] The 3D adaptive weight calculation processor 32 of the horizontal phasing processor 30 calculates the covariance matrix R calculated by the covariance matrix processor 31. φ The stereo adaptive weight calculation processor 32 defines the steering vector w" used to calculate the stereo adaptive weight as the following equation (6). Here, τ" in equation (6) is different from that in the prior art and is the delay time of the second subarray according to the desired horizontal and elevation azimuth directions.

[0037]

number

[0038] The horizontal phasing processor 30 treats the signals as signals from a surface array having M×L sensors 201, and performs the same processing as adaptive phasing processing for normal 3D phasing. For example, the 3D adaptive weight in adaptive phasing processing of the MVDR system is expressed by the following equation (7). Here, R φ -1 is the covariance matrix R φ represents the inverse matrix of

[0039]

number

[0040] The product-sum processing unit 33 of the horizontal phasing processor 30 calculates the phasing processing result y φ and the cubic adaptive weight calculated by the cubic adaptive weight calculation processor 32. The cubic adaptive weight calculation processor 33 calculates the cubic phasing result y θφ The horizontal phasing processor 30 calculates the three-dimensional phasing result y θφ A signal containing the data is sent to the output terminal R out Output from

[0041]

number

[0042] As described above, according to the phasing processing system 100 of the first embodiment, the subarray division processing device 10 includes the second subarray division processing unit 12 that divides the first subarray, which is obtained by dividing the sensor 201 for each stave, into multiple subarrays in the stacking direction to generate second subarrays. Furthermore, the elevation phasing processing device 20, which serves as the upstream phasing processing device, performs elevation phasing processing based on the desired elevation azimuth for each second subarray. Therefore, the downstream horizontal phasing processing device 30, which performs adaptive phasing processing, can perform phasing processing based on the results of two-dimensional processing along the y-axis and z-axis. This allows noise signals to be suppressed not only in the horizontal direction but also in the elevation direction, improving the accuracy of target signal extraction.

[0043] The order of the amount of calculation in the phasing processing system 100 of the first embodiment is expressed by the following equation (9). This means that when phasing a surface array in which 6 × 6 sensors 201 are arranged, the amount of calculation is about 1 / 23 of that in normal adaptive phasing processing. Although the amount of calculation is about six times that in separate adaptive phasing processing, it is possible to increase the directivity in the elevation direction while suppressing the amount of calculation, and to improve the accuracy of extracting the target signal. Here, O 21 , O 31 , O 32 and O 33are the orders of magnitude of the computational complexity of the subarray phase adjusting processor 21, the covariance matrix processor 31, the stereo adaptive weight calculation processor 32, and the product-sum processor 33, respectively.

[0044]

number

[0045] Embodiment 2 The subarray division processing device 10 of the phasing processing system 100 in the first embodiment includes a second subarray division processing unit 12 and generates second subarrays. Here, there is a possibility that processing is performed so that the spacing between the sensors 201 serving as the phasing centers of each second subarray in the stacking direction is wider than the spacing between the sensors 201 in the stave direction constituting the first subarray. If the spacing between the sensors 201 serving as the phasing centers of each second subarray is wider than the spacing between the sensors 201 in each first subarray, the spatial sampling theorem in the phasing processing performed by the horizontal phasing processing device 30 in the second (posterior) stage is no longer satisfied as the frequency increases. As a result, elevation azimuths from which noise signals cannot be removed are generated in the high-frequency band, and the accuracy of target signal extraction decreases. Therefore, the phasing processing system 100 in the second embodiment adjusts the spacing between the second subarrays by varying the number of second subarrays generated based on the frequency.

[0046] FIG. 7 is a diagram showing a configuration centered on a phasing processing system 100 according to the second embodiment. In FIG. 7, devices and the like denoted by the same reference numerals as in FIG. 1 are the same as those described in the first embodiment. As shown in FIG. 7, the subarray division processing device 10 according to the second embodiment has a frequency-based second subarray division processing unit 13. The frequency-based second subarray division processing unit 13 performs processing to divide each first subarray into a plurality of second subarray groups according to frequency. Furthermore, the elevation phasing processing device 20 according to the second embodiment has a frequency-based subarray elevation phasing processing unit 22. The frequency-based subarray elevation phasing processing unit 22 performs elevation phasing processing for a desired elevation azimuth for each second subarray.

[0047] FIG. 8 illustrates an example of processing by the frequency-specific second subarray division processor 13 according to the second embodiment. The frequency-specific second subarray division processor 13 divides the first subarray for each frequency so as to satisfy the sampling theorem, thereby generating second subarrays. For ease of explanation, FIG. 8 illustrates the first subarray, with one stave extracted for each frequency band. Here, there are three first subarrays with the same stave, for the high frequency band, the mid frequency band, and the low frequency band. The sensors 201 within the black frames are the sensors 201 that constitute the second subarrays. The sensor 201 enclosed by the dashed line indicates the sensor 201 that serves as the phasing center of the second subarray. The sensor 201 that serves as the phasing center of the second subarray is a conceptual sensor 201 that is considered to be the position of each second subarray when the frequency-specific subarray phasing processor 22 of the phasing processor 20 performs phasing processing. Therefore, the actual sensor 201 may not be located at the position that serves as the phasing center sensor 201. 8, the frequency-based second subarray division processing unit 13 performs division processing to generate second subarrays such that the interval between phasing centers used in phasing processing performed by the amplitude phasing processing unit 20 becomes narrower as the frequency increases. Specifically, for example, the second subarrays are generated so that the interval in the stack direction related to the second subarrays becomes narrower for each octave.

[0048] FIG. 9 is a diagram illustrating another example of processing by the frequency-based second subarray division processor 13 according to the second embodiment. In FIG. 9, in addition to frequencies in the high and low frequency bands, processing is performed for two frequencies in the mid-frequency band. In the example of FIG. 8, the frequency-based second subarray division processor 13 performs processing so that the number L of generated second subarrays increases as the frequency increases. Here, the frequency-based second subarray division processor 13 can perform division processing by fixing the number of second subarrays for each frequency and narrowing only the spacing. For example, as shown in FIG. 9, the frequency-based second subarray division processor 13 performs division processing so as to keep the number of second subarrays for each frequency used by the elevation phasing processor 20 for processing constant and shorten only the spacing of the sensor 201, which serves as the phasing center.

[0049] The frequency-specific subarray amplification phasing processor 22 of the amplification phasing processor 20 performs amplification phasing in the second subarray. When the division process of the frequency-specific second subarray division processor 13 shown in FIG. 9 is performed, the frequency-specific subarray amplification phasing processor 22 performs phasing with the sensor 201 enclosed by the dashed line in FIG. 9 as the phasing center. Therefore, the number of sensors in the stacking direction is smallest at low frequencies, and the number of sensors in the stacking direction increases as the frequency increases. As a result, phasing is performed at the position of the sensor 201 that serves as a phasing center that differs for each divided frequency. When the division process of the frequency-specific second subarray division processor 13 shown in FIG. 9 is performed, the frequency-specific subarray amplification phasing processor 22 can select and execute either CBF or adaptive phasing.

[0050] As described above, in the phasing processing system 100 according to the second embodiment, the subarray division processing device 10 includes the frequency-specific second subarray division processing unit 13. The frequency-specific second subarray division processing unit 13 performs division processing based on frequency to generate second subarrays. Therefore, the frequency-specific second subarray division processing unit 13 can send to the subsequent amplification phasing processing device 20 a signal that satisfies the sampling theorem in the phasing processing performed by the subsequent amplification phasing processing device 20. The frequency-specific subarray amplification phasing processing unit 22 of the amplification phasing processing device 20 can perform adaptive phasing at any frequency of the detected signal, while ensuring that the amplification phasing processing device 20 satisfies the sampling theorem and with a smaller amount of calculation than conventional adaptive phasing.

[0051] Furthermore, when the frequency-specific subarray amplification phasing processor 22 performs adaptive phasing, the covariance matrix R φ Dimensions of (covariance matrix R φ Therefore, the frequency-specific subarray amplification phasing processor 22 can calculate the covariance matrix R in a shorter time. φAs a result, the phasing processing system 100 can perform phasing processing in real time, and can improve the ability to suppress noise signals such as non-stationary arriving interference signals and improve the ability to track targets that move at high speed.

[0052] Furthermore, the effect of the phasing processing system 100 according to the second embodiment on the amount of calculation will be described. For example, in the first embodiment, it is assumed that calculations are performed based on three frequencies, frequency f1, frequency f2, and frequency f3, for the second subarray generated by the processing shown in Fig. 6. If the frequency-specific subarray amplification phasing processor 22 performs phasing processing using CBF, the amount of calculation O for each frequency will be f1 , computational complexity O f2 and the computational complexity O f3 can be calculated as follows:

[0053] For example, for the second subarray generated by dividing as shown in FIG. 8, the amount of calculation for frequency f1 is O f1 is expressed by the following equation (10): 22 is the order of the amount of calculation of the frequency-specific subarray amplification phasing processor 22.

[0054]

number

[0055] In addition, the amount of calculation for frequency f2 is f2 is expressed by the following equation (11).

[0056]

number

[0057] And the amount of calculation for frequency f3 is O f3 is expressed by the following equation (12).

[0058]

number

[0059] Therefore, the total amount of operations is O f1 +O f2 +O f3 =59748.

[0060] On the other hand, for comparison, when adaptive phasing is performed on signals from a 6-stack x 6-stave surface array, if calculations are performed based on three frequency bands, the order of the amount of calculations is 202464. Therefore, the processing of the phasing processing system 100 according to the second embodiment can perform approximately 1 / 2.5 times the amount of calculation processing.

[0061] 9, the amount of calculation is approximately the same as that of the phasing processing system 100 according to the first embodiment (approximately 1 / 23 of the amount of calculation required for normal adaptive phasing processing). Furthermore, the phasing processing system 100 according to the second embodiment can satisfy the spatial sampling theorem, and can solve the problem of elevation azimuths from which noise signals cannot be removed in the high frequency band.

[0062] Embodiment 3 In the above-described first and second embodiments, the sensor array 200 has been described as a surface array in which the sensors 201 are arranged in two dimensions (2D), but any array to which the decoupled adaptive phasing process can be applied may be used. For example, the sensor array 200 may be an array in which the sensors 201 are arranged in three dimensions (3D), such as a cylindrical array or a conformal array. In addition, in the above-described first and second embodiments, the sensor array 200 has been described as receiving sound waves to detect sound, but the present invention is not limited to this. The sensor array 200 may also be configured to detect other physical quantities, such as ultrasound or light.

[0063] Furthermore, the phasing processing system 100 of the first and second embodiments described above is a system in which the upstream phasing processor 20 performs phasing in the elevation direction and the downstream horizontal phasing processor 30 performs phasing in the horizontal direction in two stages. Therefore, the phasing processing system 100 performs phasing in the elevation direction in the upstream phasing processing step and phasing in the horizontal direction in the downstream phasing processing step, but this is not limited to this. For example, if the first subarray can be considered a line array, phasing in the horizontal direction can be performed in the upstream phasing processing step in the upstream phasing processor, and phasing in the elevation direction can be performed in the downstream phasing processing step in the downstream phasing processor.

[0064] Furthermore, the adaptive phasing processing performed by the phasing processing system 100 of the first and second embodiments has been described as performing adaptive phasing processing of the MVDR type, but this is not limited to this. For example, adaptive phasing processing of other types, such as the EBAE type, can also be applied.

[0065] In the above-described first and second embodiments, the first subarray division processing unit 11 performs division processing without overlapping the sensors 201 to generate the first subarrays, but this is not limited to this. The first subarray division processing unit 11 may also generate the first subarrays by overlapping the sensors 201. In this case, signals from the same sensor 201 will be included in multiple first subarrays.

[0066] In the first and second embodiments described above, first subarray division processing unit 11 performs the process of generating first subarrays for each frequency, but this is not limited to this. Second subarray division processing unit 12 or frequency-specific second subarray division processing unit 13 may perform the process for each frequency.

[0067] In the second embodiment described above, an example has been described in which the division process is performed so that the intervals between stacks in the second subarray are narrowed for each octave, but this is not limiting. As shown in Fig. 9, the second subarray can also be configured so that the number of stacks is fixed and only the stack intervals are narrowed.

[0068] In the phasing processing systems 100 of the first and second embodiments, the elevation phasing processor 20 performs phasing processing using CBF, and the horizontal phasing processor 30 performs adaptive phasing, but this is not limited to this. Depending on the trade-off between the performance of adaptive phasing processing in the elevation direction and the accompanying increased processing volume, both the front-stage phasing processor and the rear-stage phasing processor may perform adaptive phasing.

[0069] In the above-described first and second embodiments, the phasing processing system 100 is described as a combination of the subarray division processing device 10, the elevation phasing processing device 20, and the horizontal phasing processing device 30, but the present invention is not limited to this. The subarray division processing device 10, the elevation phasing processing device 20, and the horizontal phasing processing device 30 may be configured as a single device. In this case, a single computer may execute programs related to the processing of each device to realize the processing of the entire system. [Explanation of symbols]

[0070] 10 Subarray division processing device 11 First subarray division processing unit 12 Second subarray division processing unit 13 Second subarray division processing unit by frequency 20. Phase adjustment processing device 21 Subarray elevation and phasing processor 22 Frequency-specific subarray amplification and phasing processing unit 30 Horizontal phasing processing device 31 Covariance matrix processing section 32 Stereo adaptive weight calculation processing unit 33 Multiply-and-accumulate processing unit 50 control section 51 Control processing device 52 memory 60 Storage section 100 Phase Processing System 200 sensor array 201 Sensors

Claims

1. a subarray division processing device that divides a plurality of signals related to detection by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axial directions, and generates the signals related to detection by a plurality of subarrays; a front-stage phasing processing device that performs front-stage phasing processing based on the signals processed by the subarray division processing device; a subsequent-stage phasing processing device that performs subsequent-stage phasing processing based on a processing result of the previous-stage phasing processing performed by the previous-stage phasing processing device, The subarray division processing device comprises: a first subarray division processing unit that divides a plurality of signals along a certain axis to generate signals of a first subarray; a second subarray division processing unit that divides the signal of the first subarray into a plurality of second subarray signals and outputs the divided signals to the front-stage phasing processing unit; and the first subarray division processing unit generates signals of the first subarray for each frequency; the second subarray division processing unit divides the signals of the first subarray selected so as to be the phasing center set for each frequency into a fixed number of signals of the second subarray; Phase processing system.

2. A subarray division processing device that divides a plurality of signals related to detection by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axial directions, and processes the signals to be generated as signals related to detection by a plurality of subarrays; a front-stage phasing processing device that performs front-stage phasing processing based on the signals processed by the subarray division processing device; a subsequent-stage phasing processing device that performs subsequent-stage phasing processing based on a processing result of the previous-stage phasing processing performed by the previous-stage phasing processing device, The subarray division processing device comprises: a first subarray division processing unit that divides a plurality of signals along a certain axis to generate signals of a first subarray; a second subarray division processing unit that divides the signal of the first subarray into a plurality of second subarray signals and outputs the divided signals to the front-stage phasing processing unit; and the first subarray division processing unit generates signals of the first subarray for each frequency; the second subarray division processing unit divides the signals of the first subarray into a set number of signals of the second subarray based on the frequency; Phase processing system.

3. 3. The phasing processing system according to claim 2, wherein the second subarray division processing unit divides the signals of the second subarrays so that the number of the second subarrays at frequencies relatively higher than the low frequencies is greater than the number of the second subarrays at the low frequencies.

4. 4. The phasing processing system according to claim 1, wherein at least one of the upstream phasing processing device and the downstream phasing processing device performs adaptive phasing processing.

5. the certain axial direction is an elevation direction of the sensor array, The phasing processing system according to any one of claims 1 to 4, wherein the upstream phasing processing device performs phasing processing related to the elevation direction, and the downstream phasing processing device performs phasing processing related to the horizontal direction in the sensor array.

6. the certain axial direction is an elevation direction of the sensor array, The phasing processing system according to any one of claims 1 to 5, wherein the first subarray division processing unit converts multiple signals from the sensors arranged along the elevation direction into signals of the first subarray.

7. a first subarray division step of dividing a plurality of signals detected by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axial directions along a certain axial direction to generate first subarray signals for each frequency; a second subarray division step of dividing the signals of the first subarray selected so as to be the phasing center set for each frequency into a fixed number of signals of a second subarray; a front-end phasing processing step of performing front-end phasing processing based on the divided signals of the second subarray; a subsequent-stage phasing processing step of performing subsequent-stage phasing processing based on the processing result of the previous-stage phasing processing; A phasing processing method comprising:

8. a first subarray division step of dividing a plurality of signals detected by a sensor array configured by arranging a plurality of sensors in a plurality of orthogonal axial directions along a certain axial direction to generate first subarray signals for each frequency; a second subarray division step of dividing the signals of the first subarray selected so as to be the phasing center set for each frequency into a fixed number of signals of a second subarray; a front-end phasing processing step of performing front-end phasing processing based on the divided signals of the second subarray; a subsequent-stage phasing processing step of performing subsequent-stage phasing processing based on the processing result of the previous-stage phasing processing; A program for a phasing processing method that causes a computer to perform the above.

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