Surface mount piezoelectric oscillator

Abstract

To improve electrical characteristics by reducing adverse influences of floating capacitance caused by a wiring pattern of a surface-mounted piezoelectric oscillator.SOLUTION: The present invention relates to a surface-mounted piezoelectric oscillator comprising: an integrated circuit element 2 incorporating an amplifier for oscillation; a piezoelectric vibration element 3 connected to an input side and an output side of the integrated circuit element; and a base 1 of which the storage part consists of a ceramic substrate. A pair of wiring patterns for piezoelectric vibration element connecting the integrated circuit element and the piezoelectric vibration element is included in the storage part, and a wiring pattern for power supply and a wiring pattern for grounding are included in an intermediate layer between the storage part, and a bottom face of a sheath part. A superposing part superposing the wiring pattern for power supply and the wiring pattern for grounding with the pair of wiring patterns for piezoelectric vibration element entirely or partially in a planar view is included.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a surface-mount piezoelectric oscillator. [Background technology]

[0002] Piezoelectric oscillators using piezoelectric vibration elements such as quartz crystal plates can produce stable, highly accurate oscillation frequencies, and are therefore used in a wide range of fields as reference frequency sources for electronic devices, etc. Surface-mount piezoelectric oscillators use a ceramic multilayer substrate as an insulating base, with an integrated circuit element for the oscillation circuit placed in the housing of the base, a quartz crystal plate supported and fixed above the integrated circuit element, and hermetically sealed with a lid. This type of configuration has a relatively small number of parts due to the customization of the integrated circuit element, resulting in a simple configuration and contributing to low costs.

[0003] In such piezoelectric oscillators, after the package is hermetically sealed, the characteristics of the piezoelectric resonator element alone can be measured externally. To achieve this, a configuration has been considered in which the input / output electrodes of the piezoelectric resonator element are directly routed to the outside of the package through the ceramic base, as shown in Patent Document 1. Specifically, a metallized wiring pattern is formed on the ceramic base so as to connect to the input / output electrodes of the piezoelectric resonator element alone, and the metallized wiring pattern is routed to a castellated portion formed on a side edge of the ceramic base to form a measurement terminal. By making measurements while the measurement terminal of the piezoelectric oscillator configured in this manner is in contact with the contact probe of a piezoelectric resonator element characteristics measuring device, the characteristics of the piezoelectric resonator element can be measured, rather than the characteristics of the oscillator circuit as a whole, without the presence of other circuit components.

[0004] As shown in Patent Document 1, in recent surface-mount piezoelectric oscillators, it has become common to configure an oscillation circuit by mounting a one-chip integrated circuit device with an oscillation amplifier built into a ceramic base housing and a piezoelectric vibration element as an oscillation reference source. For example, as disclosed in Patent Document 1, the oscillation circuit configuration of an oscillation amplifier is such that capacitive elements (dividing capacitors C1 and C2) are connected in series to the input side (gate side) and output side (drain side) of the oscillation amplifier, respectively, and a piezoelectric vibration element and feedback resistor R1 are connected in parallel between the oscillation amplifier and the capacitive element. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Jpn. Appl. KOKAI Publication No. 5-65110 Summary of the Invention [Problem to be solved by the invention]

[0006] In such an oscillator circuit configuration with a built-in oscillation amplifier, the design of the wiring pattern of an external circuit, etc., on which the surface-mount piezoelectric oscillator will later be mounted, may result in the unintended formation of new stray capacitance due to the arrangement of the wiring pattern in close proximity to the wiring pattern of the surface-mount piezoelectric oscillator. In particular, if new stray capacitance is formed in the wiring pattern connecting the piezoelectric vibrating element and the oscillation amplifier, it directly affects the oscillator circuit characteristics, and there is concern that this may lead to variations in the oscillator circuit design associated with frequency determination.

[0007] To address this issue, the wiring pattern structure of the surface-mount piezoelectric oscillator described above generally does not take into consideration reducing the adverse effects of stray capacitance on the oscillation circuit configuration that includes the oscillation amplifier. In other words, the stray capacitance can change significantly depending on the connection arrangement between the terminals of the surface-mount piezoelectric oscillator.

[0008] In order to solve the above problems, the present invention aims to provide a more reliable surface-mount piezoelectric oscillator that can reduce the adverse effects of stray capacitance caused by the wiring pattern of a surface-mount piezoelectric oscillator having an oscillation circuit configuration with a built-in oscillation amplifier, eliminate variations in the oscillation circuit design, and improve the electrical characteristics. [Means for solving the problem]

[0009] In order to achieve the above object, the present invention provides: The device includes an integrated circuit element having a built-in oscillation amplifier, a piezoelectric vibration element on which a pair of excitation electrodes connected to the integrated circuit element are formed, and an insulating base in which a storage section and an exterior section are formed by stacking ceramic substrates, the insulating base having a plurality of wiring patterns formed in the storage section and external terminals formed on the bottom surface of the exterior section and connected to some of the wiring patterns, the upper surface of the storage section of the base being a first wiring pattern surface, the first wiring pattern surface having at least a pair of piezoelectric vibration element wiring patterns that connect terminals of the oscillation amplifier of the integrated circuit element to the excitation electrodes of the piezoelectric vibration element, a second wiring pattern surface being between the first wiring pattern surface and the bottom surface of the exterior section, the second wiring pattern surface having at least two DC wiring patterns with different functions, and an overlapping portion in which the two DC wiring patterns and all or part of the pair of piezoelectric vibration element wiring patterns overlap in a planar view. It is characterized by:

[0010] With the above configuration, by forming an overlapping portion in which at least two DC wiring patterns with different functions are overlapped in all or part of the pair of wiring patterns for the piezoelectric vibration element connected to the oscillation amplifier of the integrated circuit element, it is possible to form a structurally stable capacitance formation region formed by a predetermined gap dimension through the laminated surfaces of the ceramic substrate. This capacitance formation region can be an electrically stable region in which new stray capacitance is not formed and increased by the later placement of wiring patterns for external circuits or the like in unintended positions, and therefore can be an area in which stray capacitance does not change.

[0011] Furthermore, in the present invention, the wiring pattern on the second wiring pattern surface, which overlaps all or part of the piezoelectric vibration element wiring pattern on the first wiring pattern surface, is divided into at least two DC wiring patterns with different functions, thereby making it possible to easily form a wider capacitance formation region that is structurally stable without forming a complex wiring pattern.In particular, compared to when the capacitance formation region is formed using only one DC wiring pattern, the design freedom of the wiring pattern and wiring pattern shape of the two DC wiring patterns using the second wiring pattern surface is dramatically improved, making it easier to design connections to upper layer wiring patterns and lower layer external mounting terminal pads, and allowing for shorter connections.The impedance of wiring related to power supply and ground can also be reduced.

[0012] In other words, by using at least two DC wiring patterns with different functions, it is possible to configure a capacitance formation area with a wider range and higher design freedom, and it is possible to more efficiently stabilize the circuit characteristics of the entire oscillator circuit without forming complex wiring patterns. Furthermore, it is possible to suppress design variations associated with determining the frequency of the oscillator circuit of a surface-mount piezoelectric oscillator. By forming new stray capacitance, the frequency tuning amount and frequency tuning sensitivity of the voltage-controlled piezoelectric oscillator do not decrease, and it is possible to achieve good frequency tuning balance.

[0013] Furthermore, the two DC wiring patterns may be composed of a power supply wiring pattern and a ground wiring pattern. Power supply wiring patterns and ground wiring patterns are essential wiring patterns for piezoelectric oscillators, and generally, they are formed to occupy a relatively large area in the insulating base in order to reduce the impedance of the wiring, thereby stabilizing the characteristics. In this configuration, by effectively utilizing such wiring patterns, it is possible to form a capacitance formation region that is structurally stable and advantageous for miniaturization without unnecessarily expanding the area of ​​the wiring patterns. [Effects of the Invention]

[0014] According to the above invention, it is possible to provide a more reliable surface-mount piezoelectric oscillator that can reduce the adverse effects of stray capacitance caused by the wiring pattern of a surface-mount piezoelectric oscillator having an oscillation circuit configuration with a built-in oscillation amplifier, eliminate variations in the oscillation circuit design, and improve the electrical characteristics. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram showing an oscillation circuit applied to the present invention. [Figure 2] FIG. 2 is a plan view of a base on which a piezoelectric vibration element is mounted and before a lid is sealed, showing an embodiment of the present invention. [Figure 3] FIG. 3 is a plan view of the base before the integrated circuit element and the piezoelectric vibration element in FIG. 2 are mounted. [Figure 4] 3 is a plan view of a first intermediate substrate having a piezoelectric vibration element mounting surface, with the upper substrate of the base of FIG. 2 removed. [Figure 5] 3 is a plan view of a second intermediate substrate having an integrated circuit element mounting surface, excluding the upper substrate and first intermediate substrate of the base of FIG. 2. [Figure 6] 3 is a plan view of a lower substrate having a second wiring pattern surface, excluding the upper substrate, the first intermediate substrate, and the second intermediate substrate of the base of FIG. 2. [Figure 7] Bottom view of Figure 2 [Figure 8] 1 is a schematic cross-sectional view showing a state in which a piezoelectric vibration element is mounted and a lid is sealed, illustrating an embodiment of the present invention. [Figure 9] FIG. 2 is a bottom view of an integrated circuit element applied to the present invention. [Figure 10] FIG. 10 is a plan view of a lower substrate having a second wiring pattern surface, excluding an upper substrate, a first intermediate substrate, and a second intermediate substrate of a base, showing a modified embodiment of the embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

[0016]

[0023] The following describes preferred embodiments of the present invention, taking a surface-mount crystal oscillator (surface-mount piezoelectric oscillator) using a ceramic multilayer substrate as an example, with reference to the drawings. Fig. 1 is a diagram showing an oscillator circuit used in the surface-mount crystal oscillator of the present invention. Fig. 2 is a plan view of the base on which a piezoelectric vibration element is mounted and before the lid is sealed, showing an embodiment of the present invention. Fig. 3 is a plan view of the base on which the integrated circuit element and piezoelectric vibration element of Fig. 2 are mounted. Fig. 4 is a plan view of the first intermediate substrate having the piezoelectric vibration element mounting surface of Fig. 2, excluding the upper substrate of the base. Fig. 5 is a plan view of the second intermediate substrate having the integrated circuit element mounting surface of Fig. 2, excluding the upper substrate and first intermediate substrate of Fig. 2. Fig. 6 is a plan view of the lower substrate having the second wiring pattern surface of Fig. 2, excluding the upper substrate, first intermediate substrate, and second intermediate substrate of Fig. 2. Fig. 7 is a bottom view of Fig. 2. Fig. 8 is a schematic cross-sectional view of the piezoelectric vibration element mounted and the lid sealed, showing an embodiment of the present invention. Fig. 9 is a bottom view of the integrated circuit element used in the surface-mount crystal oscillator of the present invention.

[0017] In this embodiment, for example, the surface-mounted crystal oscillator 6 has a planar external size (planar external dimensions of the base 1) of approximately 3.2 mm (long side) x 2.5 mm (short side), and is composed of a base 1 (hereinafter referred to as the base) made of an insulating ceramic multilayer substrate having an open recess at the top, an integrated circuit element 2 housed in the base, a piezoelectric vibration element 3 also housed in the top of the base, and a lid 4 joined to the opening of the base.

[0018] In this surface mount crystal oscillator, a base 1 and a lid 4 are hermetically sealed by heat-melting them together using a sealing material 5, which will be described later, to form a surface mount crystal oscillator 6. Note that the planar outer dimensions of the surface mount crystal oscillator described above are just an example, and the present invention is also applicable to package sizes other than the outer dimensions described above. Below, an outline of each component constituting the surface mount crystal oscillator 6 will be described in detail.

[0019] The ceramic multilayer substrate has a base 1 that is a rectangular parallelepiped overall, and is composed of four layers: a bottom layer, lower substrate 11, which is a single plate made of a ceramic material such as alumina and rectangular in plan view; a second intermediate substrate 12, which is a single plate made of a ceramic material and rectangular in plan view, laminated on lower substrate 11; a first intermediate substrate 13, which is a frame-shaped plate made of a ceramic material and laminated on second intermediate substrate 12, and an upper substrate 14, which is a top layer made of a ceramic material and frame-shaped in plan view; and the four layers are formed into a box-like body having a recessed storage section 10 in cross section and an exterior covering that covers the storage section. Note that first intermediate substrate 13 and upper substrate 14, which form the storage area for integrated circuit element 2 and piezoelectric vibration element 3 (described later), are approximately 200 μm to 300 μm thick, with some allowance for the thickness of each element, and more specifically, 250 μm thick. In contrast, the lower substrate 11 and the second intermediate substrate 12 are areas where only the second wiring pattern described later is configured in the interlayer portion, so they are thinner than the first intermediate substrate 13 and the like, and are approximately 100 μm to 150 μm thick, which is about half the thickness of the first intermediate substrate 13 and the like, and more specifically, are configured to be 125 μm thick.

[0020] A first intermediate substrate 13 and an upper substrate 14 are formed around the periphery of the storage section 10, and the upper surface (edge ​​surface) of the upper substrate 14 is formed flat. The storage section 10 is composed of a lower storage section 10a and an upper storage section 10b, which store the integrated circuit element 2 and the piezoelectric vibration element 3, respectively. Note that the ceramic multilayer substrate is not limited to a four-layer base as in this embodiment, and may be a three-layer structure or a four-layer or more structure depending on the structure of the storage section of the base.

[0021] The upper surface (edge ​​surface) of the upper substrate 14, which is the top layer of the base 1 of the ceramic multilayer substrate, is flat and forms a bonding area (metal film) 14a with the lid 4, which will be described later. This bonding area 14a is composed of a metallization layer made of a metallization material such as tungsten or molybdenum, a nickel layer laminated on this metallization layer, and a gold layer laminated on this nickel layer. The tungsten or molybdenum is formed integrally during ceramic firing using metallization technology using thick film printing, and the nickel layer and gold layer are plated on the metallization layer in that order.

[0022] Multiple castellations C1 extending vertically are formed on the square outer peripheral wall of the base 1, and two castellations C2 extending vertically are formed on a portion of the outer peripheral wall of the base 1. The castellations are configured as arc-shaped or semi-elliptical cutouts formed vertically on the outer peripheral wall of the base. The bonding region 14a is electrically connected to a mounting external terminal pad GT2 (described later) formed on the bottom surface of the base via at least one of a conductive via V1 that vertically connects the first intermediate substrate 13 and the upper substrate 14 of the base and a wiring pattern (not shown) formed on the upper surface of the castellation C1. Connecting the external terminal pad GT2 for grounding allows a metal cover (described later) to be grounded via the bonding region 14a, the conductive via, and the wiring pattern on the upper surface of the castellation, thereby providing electromagnetic shielding for the surface-mount crystal oscillator.

[0023] Within the base 1, a lower storage section 10a is formed on the lower surface, which is made of the first intermediate substrate 13 and stores the integrated circuit element 2. A holder 10c protrudes upward from the bottom surface of the lower storage section and holds an end of a piezoelectric vibration element (described later), and a pillow section 10d is formed facing the holder across the lower storage section. Furthermore, an upper storage section 10b made of the upper substrate 14 is formed above the lower storage section 10a.

[0024] The wiring patterns formed on the upper surface of each substrate disposed below the upper substrate 14 will be described below with reference to the drawings.

[0025] 3 and 4, the mounting surface for the piezoelectric vibration element 3 is formed by the upper surface portion of the first intermediate substrate 13. A holder 10c for mounting the piezoelectric vibration element 3 (described later) is formed on the upper surface of the first intermediate substrate 13 (the bottom surface of the upper storage section 10b), and a pair of internal terminal pads NT and a wiring pattern H connected to the piezoelectric vibration element 3 (described later) are formed on the upper surface of the holder 10c. The holder 10c is formed by a part of the second intermediate substrate 14 protruding toward the storage section 10. The dotted lines in FIG. 4 represent the sealant 5 arranged on the top of the upper substrate 14, seen through.

[0026] On the upper surface of castellations C2 formed on part of the outer peripheral edge of a first intermediate substrate 13, which is an intermediate layer of base 1 of the ceramic multilayer substrate, first external terminal pads for measurement GT5 connected to the first internal terminal pads NT1 and second external terminal pads for measurement GT6 connected to the second internal terminal pads NT2 are formed. Note that in this embodiment, the castellations C2 and the first external terminal pads for measurement GT5, and the castellations C2 and the second external terminal pads for measurement GT6 are formed opposite each other in the central parts of the long-side banks (long-side sidewalls) of base 1, but the locations are not limited to this.

[0027] 4, the first internal terminal pad NT1 connected to one excitation electrode 31 of the piezoelectric vibration element 3 (described later) is electrically connected to the wiring pattern on the upper surface of the second intermediate substrate 12 (the lower layer) by a conductive via V2 that penetrates and connects the input wiring pattern H1 to the first intermediate substrate 13, and is also connected to the first external terminal pad for measurement GT5 and the input wiring pattern H1. The second internal terminal pad NT2 connected to the other excitation electrode 32 of the piezoelectric vibration element 3 (described later) is electrically connected to the wiring pattern on the upper surface of the second intermediate substrate 12 (the lower layer) by a conductive via V3 that penetrates and connects the output wiring pattern H2 to the first intermediate substrate 13, and is also connected to the second external terminal pad for measurement GT6 and the output wiring pattern H2. The characteristics of the piezoelectric vibration element 3 (described later) alone can be measured by contacting the pair of the first external terminal pad for measurement GT5 and the second external terminal pad for measurement GT6 with contact probes of a piezoelectric vibration element characteristic device.

[0028] In the present invention, the mounting surface connected to the integrated circuit element 2 is defined as the first wiring pattern surface, and as shown in Figures 4 and 5, it is configured by the upper surface portion of the second intermediate substrate 12. On the upper surface of the second intermediate substrate 12 (the bottom surface of the lower storage portion 10a), a plurality of internal terminal pads MT and wiring patterns I connected to the integrated circuit element 2 (described later) are formed side by side. Specifically, as shown in Figure 5, the internal terminal pads MT of the base include input internal terminal pads MT1 connected to input pads 21 (input terminals) of the integrated circuit element 2 (described later), output internal terminal pads MT2 connected to output pads 22 (output terminals) of the integrated circuit element 2 (described later), other function internal terminal pads MT3 connected to other function pads 23 of the integrated circuit element 2 (described later), grounding internal terminal pads MT4 connected to grounding pads 24 of the integrated circuit element 2 (described later), output internal terminal pads MT5 connected to output pads 25 of the integrated circuit element 2 (described later), and power supply internal terminal pads MT6 connected to power supply pads 26 of the integrated circuit element 2 (described later). The dotted line in FIG. 5 shows the inner peripheral frame edge of the first intermediate substrate 13, which forms the boundary with the storage section 10a, in a transparent manner.

[0029] In addition, the wiring pattern I of the base is formed with an input side wiring pattern I1 (wiring pattern for piezoelectric vibration elements) that connects the input side internal terminal pad MT1 and the first internal terminal pad NT1 together with the conductive via V2, an output side wiring pattern I2 (wiring pattern for piezoelectric vibration elements) that connects the output side internal terminal pad MT2 and the second internal terminal pad NT2 together with the conductive via V3, an other function wiring pattern I3 that connects the other function internal terminal pad MT3 and the other function mounting external terminal pad GT3 described later, a first grounding wiring pattern I4 that connects the grounding internal terminal pad MT4 and the grounding mounting external terminal pad GT2 described later, an output wiring pattern I5 that connects the output internal terminal pad MT5 and the output mounting external terminal pad GT1 described later, and a first power supply wiring pattern I6 that connects the power supply internal terminal pad MT6 and the power supply mounting external terminal pad GT4 described later.

[0030] The mounting surface for the integrated circuit element 2 and the bottom surface of the base 1 (the bottom surface of the exterior part) are formed by the flat side and bottom side of the laminate of the lower substrate 11 and the second intermediate substrate 12, with an interlayer portion between the lower substrate 11 and the second intermediate substrate 12. In the present invention, a portion of the surface corresponding to this interlayer portion is defined as a second wiring pattern surface corresponding to the first wiring pattern surface, and as shown in FIG. 6, this second wiring pattern surface is formed by the upper surface portion of the lower substrate 11. The present invention is characterized in that two wiring patterns J for grounding and power supply, which are connected to the integrated circuit element 2 via DC components (described later), are formed on the upper surface of the lower substrate 11 so as to occupy most of the area of ​​the upper surface of the lower substrate 11. By arranging the wiring pattern J consisting of such DC components opposite the area where the input-side internal terminal pads and the input-side wiring pattern are combined (hereinafter referred to as the input-side wiring part) and the area where the output-side internal terminal pads and the output-side wiring pattern are combined (hereinafter referred to as the output-side wiring part), it can be configured as a stable capacitance forming area without introducing unnecessary noise to these areas.

[0031] Specifically, as shown in FIG. 6 , a second ground wiring pattern J1 is formed, connected to the first ground wiring pattern I4 and a ground external mounting terminal pad GT2 (described later), and a second power supply wiring pattern J2 is formed, connected to the first power supply wiring pattern I6 and a power supply external mounting terminal pad GT4 (described later). In this embodiment, the wiring pattern J, which consists of a DC component for opposing the input and output wiring sections, is divided into two patterns, the second ground wiring pattern J1 and the second power supply wiring pattern J2. This allows for an easy and structurally stable capacitance formation area without forming complex wiring patterns. In particular, compared to forming only the second ground wiring pattern J1 or the second power supply wiring pattern J2, the design freedom for routing the two DC wiring patterns using the second wiring pattern surface and the wiring pattern shape is dramatically improved. This simplifies the design of connections to upper-layer wiring patterns and lower-layer external mounting terminal pads, and allows for shorter connections. The impedance of the wiring related to the power supply and ground can also be reduced.

[0032] The second ground wiring pattern J1 has a larger plane area than the first ground wiring pattern I4, and the second power supply wiring pattern J2 has a larger plane area than the first power supply wiring pattern I6. The dotted lines in FIG. 6 represent the internal terminal pads MT1-MT6 and the wiring patterns I1-I6 formed on the upper surface of the second intermediate substrate 12 in the upper layer, which are transparent. In this embodiment, the DC wiring pattern is composed of two wiring patterns J, one for grounding and one for power supply, but it may be composed of only grounding or only power supply. DC wiring patterns for other functions may also be combined or additionally arranged.

[0033] A plurality of mounting external terminal pads GT for connection to external components and devices are formed on the lower surface (bottom surface) of the lower substrate 11, which is the lowest layer of the base 1 of the ceramic multilayer substrate. Specifically, as shown in Fig. 7, mounting external terminal pads GT1, GT2, GT3, and GT4 are formed, and the mounting external terminal pads GT1 to GT4 are electrically connected to the above-mentioned wiring patterns I3 to I6, the second ground wiring pattern J1, and the second power supply wiring pattern J2 via external wiring patterns (not shown) formed on the castellation C1 of the base. The mounting external terminal pad GT1 serves as an external terminal for oscillation output, the mounting external terminal pad GT2 serves as an external terminal for grounding, the mounting external terminal pad GT3 serves as an external terminal for other DC functions such as an OE terminal (Output Enable) and a control voltage terminal (VCONT), and the mounting external terminal pad GT4 functions as an external power supply terminal.

[0034] The base having the above-described configuration is formed using well-known ceramic lamination techniques and metallization techniques, and the internal terminal pads, external terminal pads, and wiring patterns are configured by forming nickel-plated layers and gold-plated layers on the top surface of a metallization layer made of tungsten or molybdenum, etc., in the same manner as in the formation of the aforementioned bonding region 13a.

[0035] The present invention is characterized by the superimposition relationship, in plan view, of the second ground wiring pattern J1 and the second power supply wiring pattern J2 formed on the second wiring pattern surface with respect to the input-side internal terminal pads MT1 and the input-side wiring pattern I1 and the output-side internal terminal pads MT2 and the output-side wiring pattern I2 formed on the first wiring pattern surface. Specifically, as shown in the solid areas in Fig. 6, the portions where these wiring patterns overlap in plan view include an input-side overlapping portion K1 where the input-side internal terminal pads MT1 and the input-side wiring pattern I1 overlap with the second power supply wiring pattern J2 in plan view, a first output-side overlapping portion K2 where the output-side wiring pattern I2 overlaps with the second power supply wiring pattern J2 in plan view, and a second output-side overlapping portion K3 where the output-side internal terminal pads MT2 and the output-side wiring pattern I2 overlap with the second ground wiring pattern J1 in plan view. Of these, it is more desirable to form the input side overlapping portion K1 so that its area in a plan view is larger than the combined area in a plan view of the output side overlapping portions K2 and K3.

[0036] In this configuration, the planar area of ​​the input side overlapping portion K1 is made larger than the combined area of ​​the output side overlapping portion K2 and the output side overlapping portion K3, making it an electrically stable region where the stray capacitance does not change subsequently.As a result, new stray capacitance is less likely to form or increase in the input side internal terminal pad MT1 and input side wiring pattern I1 connected to the input side (gate side) of the oscillation amplifier of the integrated circuit element 2, making it more effective to prevent the stray capacitance from changing.

[0037] In this embodiment, 100% of the area of ​​the input wiring section, including the input internal terminal pads MT1 and the input wiring pattern I1, in a plan view is covered with the second power supply wiring pattern J2, etc., which is the most preferable embodiment in which the input internal terminal pads MT1 and the input wiring pattern I1 are not affected at all by the new stray capacitance. However, even if it is difficult to achieve such a configuration due to the basic wiring design, the influence of the new stray capacitance can be effectively eliminated if the ratio of the planar area of ​​the input overlapping section to the planar area of ​​all the input wiring sections can be ensured to be 50% or more.

[0038] Similarly, it is desirable to ensure that the ratio of the planar area of ​​the output-side overlapping portion to the planar area of ​​all output-side wiring portions is 50 percent or more in order to eliminate the influence of stray capacitance.

[0039] 10, the input-side internal terminal pads MT1 and the input-side wiring pattern I1, and the output-side internal terminal pads MT2 and the output-side wiring pattern I2 formed on the first wiring pattern surface may all be superimposed in plan view on the second ground wiring pattern J3 and the second power supply wiring pattern J4 formed on the second wiring pattern surface. That is, the pair of piezoelectric vibration element wiring patterns may all have an input-side overlapping portion K4 and an output-side overlapping portion K5 that are superimposed in plan view. Such a modification is desirable in order to further eliminate the influence of stray capacitance.

[0040] The integrated circuit element 2 mounted on the inner bottom surface of the lower storage section 10a is a one-chip integrated circuit element incorporating an oscillation amplifier, and together with the piezoelectric vibration element 3, constitutes an oscillation circuit. As shown in FIG. 9, an input pad 21 connected to the input side of the oscillation amplifier, an output pad 22 connected to the output side of the oscillation amplifier, and other pads 23-26 are formed on the bottom side. The integrated circuit element 2 is connected to the internal terminal pads MT1-MT6 formed on the base 1 via metal bumps C, such as gold, by, for example, FCB. Note that, although the present embodiment exemplifies a configuration in which bonding is performed using metal bumps, metal wires may also be used.

[0041] The integrated circuit element 2 used in this embodiment is not limited to an integrated circuit element for a so-called SPXO that has only an oscillation circuit section that amplifies the frequency signal of the piezoelectric vibration element 3, but may also be an integrated circuit element for a so-called VCXO that has a frequency adjustment circuit as an additional function, or an integrated circuit element for a so-called TCXO that has a temperature compensation function as an additional function, or may be an integrated circuit element that combines these. The integrated circuit element 2 may also be a bipolar element, bi-CMOS, or the like other than CMOS.

[0042] Above the integrated circuit element 2, a piezoelectric vibration element 3 is mounted at a predetermined interval in the upper storage section 10b, which is the same space as the storage section 10. The piezoelectric vibration element 3 is, for example, a rectangular AT-cut quartz crystal vibration plate, and a pair of rectangular excitation electrodes 31, 32 and their respective extraction electrodes are formed facing each other on its front and back surfaces. These electrodes are, for example, a laminated thin film composed of a chromium or nickel base electrode layer, a silver or gold intermediate electrode layer, and a chromium or nickel top electrode layer, or a laminated thin film composed of a chromium or nickel base electrode layer and a silver or gold top electrode layer. Each of these electrodes can be formed by thin film formation methods such as vacuum deposition or sputtering.

[0043] The piezoelectric vibration element 3 and the base 1 are bonded together using, for example, a silicone-based conductive resin adhesive (conductive bonding material) S, which is paste-like and contains minute metal particles such as silver filler. As shown in FIG. 2, the conductive resin adhesive S is applied to the upper surfaces of the first internal terminal pad NT1 and the second internal terminal pad NT2, and is then interposed between the piezoelectric vibration element 3 and the holder 10c and cured, thereby electrically and mechanically bonding them together. As a result, one end of the piezoelectric vibration element 3 is spaced from the bottom surface of the lower storage section 10a of the base 1, while the opposing other end of the piezoelectric vibration element 3 is bonded to the holder 10c of the base, thereby providing a cantilevered support. Note that while this embodiment uses a silicone-based conductive resin adhesive for bonding, other conductive resin adhesives, metal bumps, metal-plated bumps, brazing materials, etc. may also be used as the conductive bonding material.

[0044] The lid 4 that hermetically seals the base 1 is configured such that a metal brazing material (sealing material) is formed on a core material made of, for example, Kovar, and the sealing material 5 made of this metal brazing material is joined to the joining region (metal film) 13a of the base 1. The outer shape of the metal lid in a plan view is approximately the same as or slightly smaller than the outer shape of the ceramic base.

[0045] The bonding area 13a of the base 1, which stores the integrated circuit element 2 and the piezoelectric vibration element 3 in the storage section 10, is covered with the metal lid 4, and the sealing material 5 of the metal lid 4 and the bonding area 13a of the base are melted and hardened to form an airtight seal, thereby completing the surface-mounted crystal oscillator 6.

[0046] The oscillation circuit configuration of the C-MOS inverter in the surface mount crystal oscillator 6 configured as described above is shown in Figure 1. That is, capacitive elements (dividing capacitors C1 and C2) are connected in series to the input side (gate side G) and output side (drain side D) of the C-MOS inverter, respectively, and the piezoelectric vibration element 3 and feedback resistor R are connected in parallel between this C-MOS inverter and the capacitive element. Note that this oscillation circuit discloses measurement external terminals X1 and X2 for measuring the electrical characteristics of the piezoelectric vibration element 3 alone, and an on-board external terminal OUT for oscillation output, but other on-board external terminals (such as power supply) are not shown.

[0047] In the above embodiment, the input-side internal terminal pads MT1 and the input-side wiring pattern I1, which are connected to the input side of the oscillation amplifier of the integrated circuit element 2, form an input-side overlapping portion K1 that overlaps with the second power supply wiring pattern J2 in a planar view. The output-side internal terminal pads MT2 and the output-side wiring pattern I2, which are connected to the output side of the oscillation amplifier of the integrated circuit element 2, form a first output-side overlapping portion K2 that overlaps with the second power supply wiring pattern J2 in a planar view. The output-side internal terminal pads MT2 and the output-side wiring pattern I2 form a second output-side overlapping portion K3 that overlaps with the second grounding wiring pattern J1 in a planar view. These overlapping portions form a structurally stable capacitance formation region formed by a gap dimension of 125 μm in thickness of the second intermediate substrate 12 across the laminated surfaces of the ceramic substrates.

[0048] These capacitance-forming regions are electrically stable, preventing future changes in stray capacitance due to the later placement of wiring patterns for external circuits or other components. Furthermore, because the gap dimensions are greater than the thickness of a single ceramic laminate substrate, the capacitance-forming regions can be constructed with a distance greater than 50 μm for a given thickness. This allows the capacitance to be kept relatively small, minimizing its impact on the electrical characteristics of the oscillator circuit.

[0049] Furthermore, the wiring patterns on the second wiring pattern surface, which overlap with the input side internal terminal pad MT1 and input side wiring pattern I1 (wiring pattern for piezoelectric vibration element) and the output side internal terminal pad MT2 and output side wiring pattern I2 (wiring pattern for piezoelectric vibration element) on the first wiring pattern surface, are divided into two, a second grounding wiring pattern J1 and a second power supply wiring pattern J2, so that a wider capacitance formation area can be easily and structurally stable without forming complex wiring patterns.

[0050] In other words, the two DC wiring patterns, the second ground wiring pattern J1 and the second power supply wiring pattern J2, allow for the creation of a wider capacitance formation area with greater design freedom, and the circuit characteristics of the entire oscillator circuit can be more efficiently stabilized without forming complex wiring patterns. This also reduces design variations associated with determining the frequency of the oscillator circuit of the surface-mount piezoelectric oscillator 6. The formation of new stray capacitance prevents a decrease in the frequency tuning amount or frequency tuning sensitivity in the voltage-controlled piezoelectric oscillator, and also allows for a good frequency tuning balance.

[0051] This embodiment uses a single-structure package in which an oscillation amplifier and a piezoelectric vibrator element are housed in a single storage space. In such a single-structure package, the side wiring pattern connecting the oscillation amplifier and the excitation electrode of the piezoelectric vibrator element tends to be located relatively close to the external circuit board, making it susceptible to the effects of stray capacitance. However, by combining the characteristic configuration of the present invention with a single-structure package, these adverse effects can be eliminated, making it easier to benefit from the effects of the present invention.

[0052] In the above-described embodiment, an AT-cut quartz crystal plate is used as the piezoelectric vibrating element, but this is not limited to this and a tuning-fork type quartz crystal plate may also be used. Furthermore, while quartz crystal is used as the material for the piezoelectric vibrating element, this is not limited to this and piezoelectric single crystal materials such as piezoelectric ceramics and LiNbO3 may also be used. In other words, any piezoelectric vibrating element is applicable. Furthermore, while the piezoelectric vibrating element is held cantilevered in this example, it may also be held at both ends. Furthermore, although a silicone-based conductive resin adhesive is used as the conductive bonding material, other conductive resin adhesives may also be used, as well as bump materials for metal bumps or metal-plated bumps, brazing materials, etc.

[0053] In addition, in this embodiment, the electrical connection between the integrated circuit element and the base is disclosed as being joined by a flip-chip bonding method, but this is not limited to this, and wire bonding methods, etc. may also be adopted. Although an oscillator circuit configuration using a one-chip integrated circuit element with a built-in oscillation amplifier is exemplified, an oscillator circuit configuration including other oscillation amplifiers may also be used.

[0054] Furthermore, in this embodiment, sealing using a metal brazing material is used as an example, but this is not limited to this, and seam sealing, beam sealing (for example, laser beam, electron beam), glass sealing, etc. can also be applied.

[0055] In addition, in this embodiment, a single-structure package using a base with a recess that is open only at the top is used as an example, but the present invention can also be applied to a package with an H-shaped cross-section structure that has recesses on the top and bottom surfaces of the base.

[0056] The present invention can be embodied in various other forms without departing from its spirit or essential features. Therefore, the above-described embodiments are merely illustrative in all respects and should not be interpreted as limiting. The scope of the present invention is defined by the claims and is not limited to the text of the specification. Furthermore, all modifications and variations within the scope of the claims are within the scope of the present invention. [Industrial Applicability]

[0057] The present invention is applicable to a surface-mount type piezoelectric oscillator. [Explanation of symbols]

[0058] 1 base 2. Integrated circuit elements 3 Piezoelectric vibration element 4 Lid 5. Encapsulating material 6 Surface Mount Crystal Oscillators S Conductive resin adhesive (conductive bonding material) C Metal bump

Claims

1. an integrated circuit element incorporating an oscillation amplifier; a piezoelectric vibration element on which a pair of excitation electrodes connected to the integrated circuit element are formed; The ceramic substrates are laminated to form a housing section and an exterior section, an insulating base having a plurality of wiring patterns formed in the housing portion and external terminals formed on the bottom surface of the exterior portion and connected to some of the wiring patterns; an upper surface of the storage portion of the base is a first wiring pattern surface; The first wiring pattern surface has: a pair of wiring patterns for the piezoelectric vibration element that connects a terminal of the oscillation amplifier of the integrated circuit element and an excitation electrode of the piezoelectric vibration element; a second wiring pattern surface is located between the first wiring pattern surface and the bottom surface of the exterior part; The second wiring pattern surface has: The device has at least two DC wiring patterns with different functions, The two DC wiring patterns and the pair of piezoelectric vibration element wiring patterns have overlapping portions where they are all or partly overlapped in plan view.

1. A surface-mount piezoelectric oscillator comprising:

2. The two DC wiring patterns are a power supply wiring pattern and a ground wiring pattern.

2. The surface-mounted piezoelectric oscillator according to claim 1.

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