Computers and programs

Abstract

To provide a computer and a program for generating an optimal native code for a system which executes a bytecode.SOLUTION: A computer 100 includes a CPU and a storage device. The storage device stores; a bytecode; a system that cannot be optimized unless an extended ISA supported by the CPU is designated in a command line argument of the system for executing the bytecode; a correspondence table showing a correspondence between a value of an extension field indicating the extended ISA (Instruction Set Architecture) and the command line argument necessary for enabling optimization corresponding to the extended ISA in the system; and a program for implementing functions to cause the CPU to: acquire an ISA supported by the CPU; acquire the extended ISA from the ISA; refer to the correspondence table to automatically set the extended ISA in the command line argument of the system; and cause the extended ISA to generate an optimal native code.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a computer and a program that executes bytecodes. [Background technology]

[0002] A system is known in which a runtime compiler generates and optimizes native code from a set of bytecodes presented to a compiler.

[0003] In addition, there are known systems that cannot generate native code that is optimal for the extended instruction set architecture (ISA) supported by the CPU in the runtime compiler unless the extended ISA supported by the CPU is specified as a command line argument for the system that executes the bytecode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-40007 [Non-patent literature]

[0005] [Non-Patent Document 1] https: / / wiki.openjdk.org / display / RISCVPort Summary of the Invention [Problem to be solved by the invention]

[0006] In a system in which native code is generated and optimized in a runtime compiler from a set of bytecodes presented to the compiler, in a system in which optimization cannot be performed unless an extended ISA supported by the CPU is manually specified as a command line argument for the system that executes the bytecode, the runtime compiler cannot generate and optimize native code because there is no means to set the command line argument.

[0007] The problem to be solved by the present invention is to provide a computer and a program that can generate native code that is optimal for a system that executes bytecodes. [Means for solving the problem]

[0008] A computer according to an embodiment includes a CPU and a storage device. The storage device stores bytecode, a system that cannot perform optimization unless an extended ISA supported by the CPU is specified in a command line argument of the system that executes the bytecode, a correspondence table that indicates correspondence between values ​​of an extension field representing the extended ISA and command line arguments required to enable optimization corresponding to the extended ISA in the system, and a program that causes the CPU to acquire an ISA supported by the CPU, acquire the extended ISA from the ISA, automatically set the extended ISA in the command line argument of the system by referring to the correspondence table, and generate native code optimal for the extended ISA. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram illustrating a hardware configuration of a computer according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a software configuration of a computer according to an embodiment. [Figure 3] FIG. 2 is a diagram illustrating an ID register included in a CPU of a computer according to an embodiment. [Figure 4] FIG. 2 is a diagram showing a Base field of an ID register included in a CPU of a computer according to an embodiment. [Figure 5] FIG. 10 is a diagram showing an Extensions field of an ID register included in a CPU of a computer according to an embodiment. [Figure 6] FIG. 10 is a diagram showing an ISA-command line correspondence table in the computer according to the embodiment. [Figure 7]10 is a flowchart showing processing executed by a Java (registered trademark) virtual machine calling unit in the computer according to the embodiment. [Figure 8] FIG. 10 is a diagram showing an execution command of a Java virtual machine calling unit in the computer according to the embodiment. [Figure 9] FIG. 10 is a diagram showing an actual call command for a Java virtual machine in a computer according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Hardware configuration) First, the hardware configuration of a computer 100 according to the embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing the hardware configuration of the computer 100. The computer 100 is, for example, a computer. The computer may be a personal computer, a server computer, or the like.

[0011] The computer 100 includes a CPU 101, a bus 102, a RAM 103, a solid state drive (SSD) 104, an Ethernet (registered trademark) interface (I / F) 105, a keyboard 106, and a display 107. The computer 100 may include other devices in addition to these.

[0012] The CPU 101 is, for example, a RISC-V CPU. The RISC-V CPU has, for example, the ISA RV64IMAFDC, a base ISA RV64I, and an extended ISA MAFDC.

[0013] The relationship between RISC-V ISAs and the letters of the alphabet that represent them is described in "riscv-privileged.pdf" at "https: / / github.com / riscv / riscv-isa-manual / releases".

[0014] Here, we have given an example in which CPU 101 is a RISC-V CPU, but other CPUs may be used as long as they have optional instruction sets other than the basic instruction set, such as extended instruction sets or dedicated instruction sets, just like the RISC-V CPU.

[0015] The CPU 101, RAM 103, solid state drive 104, Ethernet interface 105, keyboard 106, and display 107 are electrically connected to one another via a bus 102, and exchange commands, programs, and data via the bus 102.

[0016] The CPU 101 is a hardware processor and controls the RAM 103 , the solid state drive 104 , the Ethernet interface 105 , the display 107 , and the keyboard 106 .

[0017] The RAM 103 is a main memory that temporarily stores programs and data required for processing executed by the CPU 101.

[0018] The solid state drive 104 is an auxiliary storage device that non-temporarily stores the programs and data that the RAM 103 temporarily stores.

[0019] The CPU 101 loads the programs and data from the solid state drive 104 into the RAM 103 and executes the programs to perform various functions.

[0020] The display 107 is an output device that outputs data and presents various information to the user.

[0021] The keyboard 106 is an input device that receives commands and data through user operations.

[0022] The Ethernet interface 105 is an interface for connecting to a network or other devices. For example, the computer 100 can be connected to a network or other devices via the Ethernet interface 105.

[0023] The bus 102, RAM 103, solid state drive 104, Ethernet interface 105, keyboard 106, and display 107 may be general-purpose devices.

[0024] (Software configuration) When the computer 100 starts up, it loads the operating system stored in the solid state drive 104 into the RAM 103 and runs the operating system. For example, the operating system is Linux (registered trademark). In the following, an example in which the operating system is Linux will be described, but the operating system is not limited to this, and other operating systems may also be used.

[0025] The software configuration of the computer 100 will be described below with reference to Fig. 2. Fig. 2 is a diagram showing the software configuration of the computer 100. In detail, Fig. 2 is a diagram showing the configuration of Linux 201 stored in the solid state drive 104.

[0026] The solid state drive 104 stores Linux 201. Linux 201 may be, for example, Debian GNU Linux running on a RISC-V CPU.

[0027] Linux 201 has a Java development environment 202. Java development environment 202 has a Java compiler 204. Linux 201 stores Java source code 203 prepared by the user. Java compiler 204 is a program that compiles Java source code 203 to generate Java bytecode 205. Java compiler 204 may be, for example, javac. Java bytecode 205 generated from Java source code 203 by Java compiler 204 is stored in Linux 201. Java bytecode 205 may be a class file, a jar archive, or the like.

[0028] The Java development environment 202 is a system in which a runtime compiler cannot generate native code that is optimal for an extended instruction set architecture (ISA) supported by the CPU 101 unless the extended ISA supported by the CPU 101 is specified in a command line argument of the system that executes the Java bytecode 205. An example of such a Java development environment 202 is OpenJDK, described in Non-Patent Document 1.

[0029] The Java development environment 202 also includes a Java virtual machine 208. The Java virtual machine 208 may be a java command included in the Java development environment 202. The Java virtual machine 208 includes an interpreter 209 and a dynamic compiler 210, and can internally generate native code 211. The native code 211 may be a machine language for a RISC-V CPU.

[0030] Linux 201 also has a Java virtual machine calling unit 206 and an ISA-command line correspondence table 207. Java virtual machine calling unit 206 has a program that references ISA-command line correspondence table 207 and automatically sets an extended ISA in the command line arguments of Java development environment 202. Details of Java virtual machine calling unit 206 and ISA-command line correspondence table 207 will be described later.

[0031] (CPU) Next, the CPU 101 (RISC-V CPU) will be described with reference to Figures 3 to 5. Figure 3 is a diagram showing the CPU ID register 300 included in the CPU 101 (RISC-V CPU). Figure 4 is a diagram showing the Base field of the CPU ID register 300 (mcpuid) shown in Figure 3. Figure 5 is a diagram showing the Extensions field of the CPU ID register 300 (mcpuid) shown in Figure 3.

[0032] The CPU 101 (RISC-V CPU) has a CPU ID register 300 shown in Figure 3. The CPU ID register 300 has a Base field 301 that represents the base ISA and an Extensions field 302 that represents the extended ISA.

[0033] The Base field 301, which indicates the basic ISA, is made up of 2 bits. As shown in Fig. 4, the Values ​​0, 1, 2, and 3 of the Base field 301 correspond to Descriptions RV32I, RV32E, RV64I, and RV128I, respectively.

[0034] The Extensions field 302, which represents the extended ISA, consists of 26 bits. As shown in FIG. 4, the least significant bit is 0 bit and the most significant bit is 25 bit. In other words, from the right, it is 0 bit, 1 bit, ..., 25 bit. Each bit takes on a value of 0 or 1. 0 bit, 1 bit, ..., 25 bit correspond to the letters A, B, ..., Z, respectively. Each letter A, B, ..., Z represents an extended ISA.

[0035] By executing the mcpuid machine instruction, the CPU 101 (RISC-V CPU) can obtain the value of the Base field 301, which represents the base ISA shown in FIG. 4, and the value of the Extensions field 302, which represents the extended ISA shown in FIG. 5.

[0036] (ISA-Command Line Compatibility Table) 6 is a diagram showing the ISA-command line correspondence table 207. The ISA-command line correspondence table 207 shows the correspondence between the value of the Extensions field 302, which indicates an extended ISA, and the command line arguments required to enable optimizations corresponding to the extended ISA in the Java virtual machine 208.

[0037] In the ISA-command line correspondence table 207, the extension ISA represents the character in the Extensions field 302, the value represents the bit position corresponding to the character, and the argument represents the command line argument corresponding to the character. That is, the ISA-command line correspondence table 207 indicates the following:

[0038] The extended ISAs that enable optimization in the Java virtual machine 208 are the letters C and V. That is, the letters C and V are flagged. Furthermore, the bit digit corresponding to the letter C of the extended ISA is 2, the value of the 2nd bit digit is 1, and the command line argument for the letter C of the extended ISA is -XX:+UseRVC. Furthermore, the bit digit corresponding to the letter V of the extended ISA is 21, the value of the 21st bit digit is 1, and the command line argument for the letter V of the extended ISA is -XX:+UseRVC.

[0039] (Java Virtual Machine Caller) The Java virtual machine call unit 206 is a program that enables the CPU 101 to acquire an ISA supported by the CPU 101, acquire an extended ISA from the acquired ISA, automatically set the extended ISA as a command line argument of the Java development environment 202 by referring to the ISA-command line correspondence table 207, and generate native code that is optimal for the extended ISA.

[0040] An example of the operation of Java virtual machine calling unit 206 will be described below with reference to Fig. 7 to Fig. 9. Fig. 7 is a flowchart showing the processing executed by Java virtual machine calling unit 206. Fig. 8 is a diagram showing an execution command of Java virtual machine calling unit 206. Fig. 9 is a diagram showing an example of a command for calling Java virtual machine 208.

[0041] In this operation example, the user executes the javawrap command representing the Java virtual machine call unit 206 from the command line with an argument 801 called sample, as shown in Fig. 8. Here, it is assumed that the Java bytecode 205 is sample.class, and the character string sample in the argument 801 indicates that sample.class is to be executed.

[0042] By executing the javawrap command, the Java virtual machine calling unit 206 causes the CPU 101 to perform the following processing.

[0043] In step S101 , the CPU 101 executes the mcpuid instruction to copy the value of the CPU ID register 300 to the RAM 103 .

[0044] In step S102, the CPU 101 copies the value of the Extensions field 302 included in the value of the CPU ID register 300 copied to the RAM 103 to a variable e.

[0045] In step S103, the CPU 101 sets the command line argument to the character string s.

[0046] In step S104, CPU 101 refers to ISA-command line correspondence table 207 and determines whether e&2=0. Here, e&2 represents a bit operation that checks whether a flag is set for character C corresponding to the 2-bit digit of variable e. In more detail, e&2 compares the 2-bit digit value of variable e with the 2-bit digit value of ISA-command line correspondence table 207, and returns 0 if either value is 0.

[0047] If the determination result in step S104 is No, that is, if e&2=0 is not true, then the value of the 2nd bit of variable e and the value of the 2nd bit of ISA-command line correspondence table 207 are both 1, indicating that the character C of the extended ISA corresponding to the 2nd bit is valid for optimization in the Java virtual machine 208. In this case, next, in step S105, the character string s is changed to -XX:+UseRVC+s. Then, the process proceeds to step S106.

[0048] If the determination result in step S104 is Yes, that is, if e&2=0, either the value of the 2nd bit of variable e or the value of the 2nd bit of ISA-command line correspondence table 207 is 0, which indicates that the character C of the extended ISA corresponding to the 2nd bit is not valid for optimization in the Java virtual machine 208. In this case, the process of step S105 is omitted and the process proceeds to step S106.

[0049] In step S106, CPU 101 refers to ISA-command line correspondence table 207 and determines whether e&21=0. Here, e&21 represents a bit operation that checks whether a flag is set for the character V corresponding to the 21st bit of variable e. In more detail, e&21 compares the value of the 21st bit of variable e with the value of the 21st bit of ISA-command line correspondence table 207, and returns 0 if either value is 0.

[0050] If the determination result in step S106 is No, that is, if e&21=0 is not true, then both the value of the 21st bit of variable e and the value of the 21st bit of ISA-command line correspondence table 207 are 1, indicating that the character V of the extended ISA corresponding to the 21st bit is valid for optimization in the Java virtual machine 208. In this case, next, in step S107, the character string s is changed to -XX:+UseRVV+s. Then, the process proceeds to step S108.

[0051] If the determination result in step S106 is Yes, that is, if e&21=0, either the value of the 21st bit of variable e or the value of the 21st bit of ISA-command line correspondence table 207 is 0, which indicates that the letter V of the extended ISA corresponding to the 21st bit is not valid for optimization in the Java virtual machine 208. In this case, the process of step S107 is omitted and the process proceeds to step S108.

[0052] In step S108, CPU 101 executes a java command representing Java virtual machine 208 with s as an argument. Fig. 9 is a diagram showing an example of a command that calls Java virtual machine 208. The command shown in Fig. 9 is a command in an example where the determination result in step S104 is No and the determination result in step S106 is Yes in the flowchart shown in Fig. 7. In this example, argument 801 of sample is assigned -XX:+UseRVC, which is a command line argument effective for optimization in Java virtual machine 208.

[0053] If the determination results of both steps S104 and S106 are Yes, the argument 801 of the java command will be "sample." If the determination results of both steps S104 and S106 are Yes and the determination results of both steps S106 are No, the argument 801 of the java command will be "-XX:+UseRVV sample." If the determination results of both steps S104 and S106 are No, the argument 801 of the java command will be "-XX:+UseRVV -XX:+UseRVC sample."

[0054] In this way, by executing the java command with arguments that are effective for optimization in the Java virtual machine 208, the Java development environment 202 can generate native code that is optimal for the extended ISA.

[0055] (effect) As can be seen from the above explanation, according to the embodiment, it becomes possible to generate native code that is optimal for an extended ISA on a computer that has a system that cannot perform optimization unless an extended ISA supported by the CPU is specified in the command line arguments of the system that executes the bytecode.

[0056] In the embodiment, an environment using Java is used as an example of a system in which optimization cannot be performed unless an extended ISA supported by the CPU is specified in the command line arguments of the system that executes the bytecode. However, the present invention is not limited to this and can also be applied to environments using other programming languages, such as Python.

[0057] The program according to this embodiment may be transferred in a state where it is stored in an electronic device, or in a state where it is not stored in an electronic device. In the latter case, the program may be transferred via a network, or in a state where it is stored in a storage medium. The storage medium is a non-transitory tangible medium. The storage medium is a computer-readable medium. The storage medium may be in any form, such as a CD-ROM or a memory card, as long as it is capable of storing the program and is computer-readable.

[0058] Although the embodiments of the present invention have been described, they are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0059] 100...computer, 101...CPU, 102...bus, 103...RAM, 104...solid state drive, 105...Ethernet interface, 106...keyboard, 107...display, 201...Linux, 202...Java development environment, 203...Java source code, 204...Java compiler, 205...Java bytecode, 206...Java virtual machine caller, 207...ISA-command line correspondence table, 208...Java virtual machine, 209...interpreter, 210...dynamic compiler, 211...native code, 300...CPU ID register, 301...Base field, 302...Extensions field, 801...command line arguments.

Claims

1. A CPU and a storage device storing a bytecode and a system that cannot perform optimization unless an extended ISA supported by the CPU is specified as a command line argument for the system that executes the bytecode; A computer having: The storage device includes: a correspondence table indicating correspondence between values ​​of an extension field representing the extended ISA and command line arguments required to enable optimizations corresponding to the extended ISA in the system; a program that causes the CPU to acquire an ISA supported by the CPU, acquire the extended ISA from the ISA, automatically set the extended ISA in a command line argument of the system by referring to the correspondence table, and generate a native code that is optimal for the extended ISA; calculator.

2. A computer having a system that cannot perform optimization unless an extended ISA supported by a CPU is specified as a command line argument of the system that executes bytecodes, A function for acquiring an ISA supported by the CPU; a function for acquiring an extended ISA from the ISA; a function of automatically setting the extended ISA as a command line argument of the system by referring to a correspondence table showing correspondence between the value of an extension field representing the extended ISA and a command line argument required to enable optimization corresponding to the extended ISA in the system; a function for generating native code that is optimal for the extended ISA; A program to make this happen.

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