Radio frequency low noise amplifier circuit and radio frequency chip

Abstract

The present invention provides a radio frequency low noise amplifier circuit and radio frequency chip, comprising a signal input terminal, an input matching circuit, an amplifier circuit, an output matching circuit and a signal output terminal connected in sequence, and further comprising a gain adjustment circuit connected in parallel with the amplifier circuit, the gain adjustment circuit including a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, a third resistor and a fourth capacitor, the source of the tenth transistor, the source of the eleventh transistor and the source of the twelfth transistor are connected to each other and grounded, the drain of the tenth transistor is connected to the first end of the first resistor, the drain of the eleventh transistor is connected to the first end of the second resistor, the drain of the twelfth transistor is connected to the first end of the third resistor, and the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are all connected to the first end of the fourth capacitor. The radio frequency low noise amplifier circuit and chip of the present invention have a flexible and adjustable gain and high safety.

Description

[Technical Field]

[0001] The present invention relates to the field of wireless communication technology, and in particular to a radio frequency low noise amplifier circuit and a radio frequency chip. [Background technology]

[0002] With the advent of the information age, wireless communication technologies such as mobile phones, wireless LANs, and Bluetooth® have rapidly developed and become indispensable for social life and development. The progress of wireless communication technology is inseparable from the development of radio frequency circuits and microwave technology. Currently, radio frequency amplifiers are one of the important components in wireless transmission and reception systems.

[0003] Conventional radio frequency low-noise amplifiers have fixed gain, and the gain of the radio frequency receiving link is adjusted by a downstream variable gain amplifier to adapt to input signals of different power levels. In the 5G NR (New Radio) radio frequency system platform, the front-end low-noise amplifier also needs to have adjustable gain to achieve a wider input dynamic range and at the same time reduce the complexity of the subsequent intermediate frequency amplifier circuit.

[0004] However, the prior art radio frequency low noise amplifier circuit has poor gain adjustment effect, low adaptability and narrow adaptability range. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above drawbacks in the prior art, the present invention provides a radio frequency low noise amplifier circuit and radio frequency chip with flexibly adjustable gain, small return loss, and high safety, in order to solve the above technical problems. [Means for solving the problem]

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions.

[0007] In a first aspect, an embodiment of the present invention provides a radio frequency low noise amplifier circuit, comprising a signal input terminal, an input matching circuit, an amplifier circuit, an output matching circuit, and a signal output terminal connected in sequence; the amplifier circuit further includes a gain adjustment circuit connected in parallel with the amplifier circuit, the gain adjustment circuit including a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, a third resistor, and a fourth capacitor; a source of the tenth transistor, a source of the eleventh transistor, and a source of the twelfth transistor are connected to each other and grounded, a drain of the tenth transistor is connected to a first end of the first resistor, a drain of the eleventh transistor is connected to a first end of the second resistor, and a drain of the twelfth transistor is connected to a first end of the third resistor; The second end of the first resistor, the second end of the second resistor, and the second end of the third resistor are all connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the amplifier circuit as an input end of the gain adjustment circuit.

[0008] Preferably, the amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a source of the first transistor, a source of the second transistor, and a source of the third transistor are connected to each other to form a common-source input structure and are connected to the input matching circuit; a drain of the first transistor, a drain of the second transistor, and a drain of the third transistor are connected to the source of the fourth transistor, the source of the fifth transistor, and the source of the sixth transistor, respectively; a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to each other and are connected to the input matching circuit; The drain of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are connected to each other, and then connected to the input end of the output matching circuit and the input end of the gain adjustment circuit, respectively.

[0009] Preferably, the amplifier circuit further includes a seventh transistor, the source of which is connected to the drain of the fourth transistor, and the drain of which is connected to the input terminal of the output matching circuit.

[0010] Preferably, the output matching circuit includes a first inductor, a first capacitor, and a second capacitor; a first end of the first inductor is connected to a power supply voltage, and a second end of the first inductor is connected to a drain of the seventh transistor as an input end of the output matching circuit; the first capacitor and the first inductor are connected in parallel; A first end of the second capacitor is connected to the second end of the first inductor, and a second end of the second capacitor is connected to the signal output terminal.

[0011] Preferably, the input matching circuit includes a first input matching network and a second input matching network, an input terminal of the first input matching network is connected to the signal input terminal, an output terminal of the first input matching network is connected to the gate of the first transistor, an output terminal of the second input matching network is grounded, and an input terminal of the second input matching network is connected to the source of the first transistor.

[0012] Preferably, the first input matching network includes a second inductor and a third capacitor, a first end of the second inductor is connected to the signal input end as an input end of the first input matching network, a second end of the second inductor is connected to a first end of the third capacitor, and a second end of the third capacitor is connected to the gate of the first transistor.

[0013] Preferably, the second input matching network includes an eighth transistor, a ninth transistor, a third inductor, and a fourth inductor, wherein a source of the eighth transistor and a source of the ninth transistor are connected to each other and grounded, a drain of the ninth transistor is connected to a first end of the third inductor, a drain of the eighth transistor is connected to a second end of the third inductor, a first end of the fourth inductor is connected to a second end of the third inductor, and a second end of the fourth inductor is connected to the source of the second transistor.

[0014] Preferably, the third inductor and the fourth inductor are connected in series to form a source inductor of the second transistor.

[0015] In a second aspect, an embodiment of the present invention further provides a radio frequency chip comprising the radio frequency low noise amplifier circuit described above. [Effects of the Invention]

[0016] Compared with the related art, in this embodiment of the present invention, an input signal input from a signal input terminal is input to an amplifier circuit through an input matching circuit, the input signal is amplified by an output matching circuit through the amplifier circuit, the amplified signal is output from the amplifier circuit through the output matching circuit, one end of a gain adjustment circuit is connected to the other end of the amplifier circuit and is used to adjust the gain of the amplified signal, the other end of the gain adjustment circuit is grounded, the sources of the tenth transistor, the eleventh transistor, and the twelfth transistor of the gain adjustment circuit are connected to each other and grounded, the drain of the tenth transistor is connected to a first end of the first resistor, the drain of the eleventh transistor is connected to a first end of the second resistor, the drain of the twelfth transistor is connected to a first end of the third resistor, the second end of the first resistor, the second end of the second resistor, and the second end of the third resistor are all connected to a first end of the fourth capacitor, and the second end of the fourth capacitor is connected to the amplifier circuit as an input end of the gain adjustment circuit. The input signal is amplified through the amplifier circuit, so the greater the total current, the higher the gain. The tenth, eleventh, and twelfth transistors of the gain adjustment circuit form attenuation branch circuits with the first, second, and third resistors, respectively, so the more conductive branch circuits, the lower the gain. This allows the gain of the radio frequency low-noise amplifier circuit to be adjustable, allowing the gain size to be adjusted to accommodate radio frequency input signals of different power levels. [Brief explanation of the drawings]

[0017] The present invention will now be described in detail with reference to the drawings. These and other aspects of the present invention will become more clear and easier to understand from the detailed description taken in conjunction with the following drawings. [Figure 1] 1 is a module diagram of a radio frequency low noise amplifier circuit according to an embodiment of the present invention; [Figure 2] 1 is a structural schematic diagram of a radio frequency low noise amplifier circuit according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains, and the terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit the application. The terms "comprise" and "have" and variations thereof in the specification and claims of this application, as well as the above description of the drawings, are intended to include a non-exclusive inclusion. Terms such as "first," "second," etc. in the specification and claims of this application, or the above drawings, do not describe a particular order but are used to distinguish between different objects.

[0019] References herein to an "embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. Appearances of this phrase in various places throughout the specification do not necessarily all refer to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will understand, either explicitly or implicitly, that the embodiments described herein may be combined with other embodiments.

[0020] The following clearly and completely describes the technical solutions of the embodiments of the present invention with reference to the accompanying drawings of the embodiments of the present invention. Of course, the embodiments described herein are only a part, not all, of the embodiments of the present invention. All other embodiments that those skilled in the art can obtain based on the embodiments of the present invention without creative work should fall within the protection scope of the present invention.

[0021] Example 1 As shown in FIGS. 1 and 2, the radio frequency low noise amplifier circuit 100 provided by the embodiment of the present invention includes a signal input terminal 1, an input matching circuit 2, an amplifier circuit 3, an output matching circuit 4, a gain adjustment circuit 5, and a signal output terminal 6, which are connected in sequence.

[0022] Signal input 1 is used to connect a single-ended input signal, The input matching circuit 2 has one end connected to the signal input terminal 1 and is used to match and output the input signal. The input matching circuit 2 performs matching processing on the received input signal to obtain a matched signal, and transmits the matched signal to one end of the amplifier circuit 3.

[0023] The amplifier circuit 3 has one end connected in series to the other end of the input matching circuit 2 and is used to amplify the input signal. The gain of the chip is increased by amplifying the matching signal output by the input matching circuit 2.

[0024] The output matching circuit 4 has one end connected to the other end of the amplifier circuit 3 and is used to output the amplified signal output by the amplifier circuit 3.

[0025] One end of the gain adjustment circuit 5 is connected to the other end of the amplifier circuit 3 and is used to adjust the gain attenuation of the amplified signal, and the other end of the gain adjustment circuit 5 is grounded. By connecting it to the other end of the amplifier circuit 3, the output amplified signal is attenuated and the gain is reduced, which can make it easier to adjust the gain size of the chip.

[0026] The signal output terminal 6 is connected to the other end of the output matching circuit 4 and is used to output a signal.

[0027] Specifically, the input signal input from signal input terminal 1 is matched through input matching circuit 2 and output to amplifier circuit 3, the input signal is amplified through amplifier circuit 3 to output matching circuit 4, one end of output matching circuit 4 is connected to the other end of amplifier circuit 3 to output the amplified signal, one end of gain adjustment circuit 5 is connected to the other end of amplifier circuit 3 to adjust the gain of the amplified signal, the other end of gain adjustment circuit 5 is grounded, and signal output terminal 6 is connected to the other end of output matching circuit 4 to output the signal. Since the input signal is amplified through amplifier circuit 3, the larger the total current, the higher the gain; and since gain adjustment circuit 5 forms an attenuation branch circuit for amplifier circuit 3, the lower the gain. Thus, the gain of radio frequency low noise amplifier circuit 100 is adjustable, and gain size configuration adjustment can be realized to adapt to radio frequency input signals of different power levels.

[0028] In this embodiment, the gain adjustment circuit 5 includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth capacitor C4. The drain of the tenth transistor M10 is connected to the first end of the first resistor R1, the drain of the eleventh transistor M11 is connected to the first end of the second resistor R2, and the drain of the twelfth transistor M12 is connected to the first end of the third resistor R3. The sources of the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are connected to each other and grounded. The second end of the first resistor R1, the second end of the second resistor R2, and the second end of the third resistor R3 are all connected to the first end of the fourth capacitor C4. The second end of the fourth capacitor C4 is connected to the amplifier circuit 3 as an input end of the gain adjustment circuit 5. The gates of the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are digitally controlled. theoryBy connecting the transistors M10, M11, and M12 to the logic circuit, the conduction or blocking of the transistors M10, M11, and M12 can be effectively controlled, and the gain size can be controlled with good control effect.

[0029] Specifically, by connecting the second end of the fourth capacitor C4 to the source of the seventh transistor M7, the second end of the fourth capacitor C4 is connected in series to the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 via the first resistor R1, the second resistor R2, and the third resistor R3, respectively, and is then connected to ground.When the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are conductive, a portion of the small-signal current is bypassed to ground, thereby reducing the gain.In this way, the gain can be adjusted by changing the number of amplifier tubes, the inductance value, and the resistance value.

[0030] In this embodiment, the amplifier circuit 3 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The source of the first transistor M1, the source of the second transistor M2, and the source of the third transistor M3 are connected to each other to form a common-source input structure and connected to the input matching circuit 2. The drain of the first transistor M1, the drain of the second transistor M2, and the drain of the third transistor M3 are connected in series to the source of the fourth transistor M4, the source of the fifth transistor M5, and the source of the sixth transistor M6, respectively. The gate of the first transistor M1, the gate of the second transistor M2, and the gate of the third transistor M3 are connected to each other and connected to the input matching circuit 2. The drain of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6 are connected to the input terminal of the output matching circuit 4 and the input terminal of the gain adjustment circuit 5, respectively.

[0031] Here, the first transistor M1, the second transistor M2, and the third transistor M3 are all common-input-source amplifying transistors, and the first transistor M1, the second transistor M2, and the third transistor M3 are controlled by the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, respectively, to adjust the amplifying branch circuit.

[0032] Specifically, the input signal output by the input matching circuit 2 is transmitted to the gates of the first transistor M1, the second transistor M2, and the third transistor M3. The first transistor M1, the second transistor M2, and the third transistor M3 amplify the three conducting branch circuit signals. The amplification is controlled by the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 connected to the first transistor M1, the second transistor M2, and the third transistor M3, respectively. The more conducting branch circuits there are, the larger the total current of the amplifier and the higher the gain.

[0033] Preferably, the above-mentioned conducting branch circuit can be not only a three-branch circuit, but also a single-branch circuit, a two-branch circuit, a four-branch circuit, etc. The more branches there are, the greater the total current of the amplifier and the higher the gain. The specific selection can be made according to the actual situation, so here we will not explain one by one.

[0034] In this embodiment, the amplifier circuit 3 further includes a seventh transistor M7, the source of which is connected to the drain of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6, respectively, and the drain of the seventh transistor M7 is connected to the input terminal of the output matching circuit 4.

[0035] Here, the seventh transistor M7 is an amplifier tube with a common gate configuration, and the source of the seventh transistor M7 is connected to the drain of the fourth transistor M4, the drain of the fifth transistor M5, and the drain of the sixth transistor M6, respectively, and the drain of the seventh transistor M7 is connected to one end of the output matching circuit 4, thereby performing the roles of voltage division and input / output isolation, and improving safety.

[0036] In this embodiment, the output matching circuit 4 includes a first inductor Ld, and a first capacitor C1 and a second capacitor C2 connected in parallel with the first inductor Ld, a second terminal of the first inductor Ld and the first capacitor C1 connected in parallel is connected to a power supply voltage VDD, one terminal of the first inductor Ld and the first capacitor C1 is connected to the drain of the seventh transistor M7, a first terminal of the second capacitor C2 is connected to the first terminal of the first capacitor C1, and a second terminal of the second capacitor C2 is connected to the signal output terminal 6.

[0037] Here, the first inductor Ld is a choke inductor used for filtering, oscillation, current stabilization, and electromagnetic interference suppression. The first inductor Ld and the first capacitor C1 are combined to form an LC filter circuit, which provides filtering and interference prevention effects.

[0038] Preferably, the output matching circuit 4 is used to match the output impedance of the amplifier to a 50 ohm matched load, and has strong anti-interference performance.

[0039] Specifically, the amplified signal is transmitted to the first terminal of the first inductor Ld and the first capacitor C1 via the seventh transistor M7. By connecting the first inductor Ld and the first capacitor C1 in parallel, the resonance of the first inductor Ld and the first capacitor C1 is within the operating frequency band, thereby achieving frequency selection. The second capacitor C2 is used to block the output DC signal, achieving a DC blocking effect.

[0040] In this embodiment, the input matching circuit 2 includes a first input matching network 21 and a second input matching network 22, the input terminal of the first input matching network 21 is connected to the signal input terminal 1, the output terminal of the first input matching network 21 is connected to the gate of the first transistor M1, the output terminal of the second input matching network 22 is grounded, and the input terminal of the second input matching network 22 is connected to the source of the first transistor M1. An input signal is matched to the amplifier circuit 3 through the first input matching network 21, and the second input matching network 22 is used to control the source switching of the first transistor M1, the second transistor M2, and the third transistor M3, which facilitates gain level switching.

[0041] In this embodiment, the first input matching network 21 includes a second inductor Lg and a third capacitor C3 connected in series with the second inductor Lg, a first end of the second inductor Lg is connected to the signal input terminal 1 as an input terminal of the first input matching network 21, a second end of the second inductor Lg is connected to a first end of the third capacitor C3, and a second end of the third capacitor C3 is connected to the gate of the first transistor M1. An input signal is input to the second inductor Lg via the signal input terminal 1 and output to the third capacitor C3 via the second inductor Lg. The third capacitor C3 isolates DC signals, and AC signals are output to the gates of the first transistor M1, the second transistor M2, and the third transistor M3. The input signal is amplified by the first transistor M1, the second transistor M2, and the third transistor M3, and output to the output matching circuit 4 from the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, respectively. At the same time, the second inductor Lg and the third capacitor at the gate of the first transistor M1 are connected in series, so that the first input matching network 21 resonates at the operating frequency point, realizing low-noise input matching of the amplifier.

[0042] In this embodiment, the second input matching network 22 includes an eighth transistor M8, a ninth transistor M9, a third inductor Ls1, and a fourth inductor Ls0, a source of the eighth transistor M8 and a source of the ninth transistor M9 are connected to each other and grounded, a drain of the ninth transistor M9 is connected to a first end of the third inductor Ls1, a drain of the eighth transistor M8 is connected to a second end of the third inductor Ls1 and then to a first end of the fourth inductor Ls0, and a second end of the fourth inductor Ls0 is connected to the source of the second transistor M2.

[0043] In this embodiment, the fourth inductor Ls0 and the third inductor Ls1 are source inductors.

[0044] Specifically, the fourth inductor Ls0 and the third inductor Ls1 are source inductors, providing the real impedance for input matching. At high gain levels, the eighth transistor M8 is turned on, the ninth transistor M9 is turned off, and only the fourth inductor Ls0 is active. At low gain levels, the eighth transistor M8 is turned off and the ninth transistor M9 is turned on. The total source inductance is the sum of the fourth inductor Ls0 and the third inductor Ls1 connected in series. This not only reduces gain but also compensates for the reduction in the real part of the input impedance caused by the reduced transconductance of the transistors at low gain levels, achieving the goal of achieving relatively good input return loss performance even at low gain levels. The gain level is flexible and adjustable, while maintaining high safety without deterioration in input or output return loss at each gain level.

[0045] <Example 2> An embodiment of the present invention also provides a radio frequency chip including the radio frequency low noise amplifier circuit 100 of the above-mentioned embodiment 1. According to the above-mentioned radio frequency low noise amplifier circuit 100, the chip can realize adaptive adjustment of gain size to adapt to radio frequency input signals of different power levels.

[0046] It should be noted that the embodiments described with reference to the accompanying drawings are used only to explain the present invention and do not limit the scope of the present invention. Those skilled in the art should understand that any modifications or equivalent replacements made to the present invention without departing from the spirit and scope of the present invention should be included within the scope of the present invention. Furthermore, unless otherwise required by context, words appearing in the singular include the plural, and vice versa. Furthermore, unless otherwise specified, all or a part of any embodiment can be used in combination with all or a part of any other embodiment. [Explanation of symbols]

[0047] 100 radio frequency low noise amplifier circuit, 1 signal input terminal, 2 input matching circuit, 21 first input matching network, 22 second input matching network, 3 amplifier circuit, 4 output matching circuit, 5 gain adjustment circuit, 6 signal output terminal.

Claims

1. A radio frequency low noise amplifier circuit comprising a signal input terminal, an input matching circuit, an amplifier circuit, an output matching circuit, and a signal output terminal, which are connected in this order, a gain adjustment circuit connected to the output of the amplifier circuit; the gain adjustment circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a first resistor, a second resistor, a third resistor, and a fourth capacitor; a source of the tenth transistor, a source of the eleventh transistor, and a source of the twelfth transistor are connected to each other and grounded, a drain of the tenth transistor is connected to a first end of the first resistor, a drain of the eleventh transistor is connected to a first end of the second resistor, and a drain of the twelfth transistor is connected to a first end of the third resistor; a second end of the first resistor, a second end of the second resistor, and a second end of the third resistor are all connected to a first end of the fourth capacitor, and the second end of the fourth capacitor is connected to an output of the amplifier circuit as an input end of the gain adjustment circuit; a gate of the tenth transistor, a gate of the eleventh transistor, and a gate of the twelfth transistor are connected to and controlled by a digital control logic circuit; the amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; a source of the first transistor, a source of the second transistor, and a source of the third transistor are connected to each other to form a common-source input structure and are connected to the input matching circuit; a drain of the first transistor, a drain of the second transistor, and a drain of the third transistor are connected to the source of the fourth transistor, the source of the fifth transistor, and the source of the sixth transistor, respectively; a gate of the first transistor, a gate of the second transistor, and a gate of the third transistor are connected to each other and are connected to the input matching circuit; the drain of the fourth transistor, the drain of the fifth transistor, and the drain of the sixth transistor are connected to each other and then connected to the input end of the output matching circuit and the input end of the gain adjustment circuit, respectively; the gate of the fourth transistor, the gate of the fifth transistor, and the gate of the sixth transistor are connected to and controlled by a digital control logic circuit, respectively; the input matching circuit includes a first input matching network and a second input matching network, an input terminal of the first input matching network is connected to the signal input terminal, an output terminal of the first input matching network is connected to the gate of the first transistor, an output terminal of the second input matching network is grounded, and an input terminal of the second input matching network is connected to the source of the first transistor; the second input matching network includes an eighth transistor, a ninth transistor, a third inductor, and a fourth inductor, a source of the eighth transistor and a source of the ninth transistor are connected to each other and grounded, a drain of the ninth transistor is connected to a first end of the third inductor, a drain of the eighth transistor is connected to a second end of the third inductor, a first end of the fourth inductor is connected to a second end of the third inductor, and a second end of the fourth inductor is connected to the source of the second transistor, and a gate of the eighth transistor and a gate of the ninth transistor are connected to and controlled by a digital control logic circuit.

2. 2. The radio frequency low noise amplifier circuit according to claim 1, wherein the amplifier circuit further comprises a seventh transistor, the drain of the fourth transistor is connected to the input terminal of the output matching circuit via the seventh transistor, the source of the seventh transistor is connected to the drain of the fourth transistor, the drain of the seventh transistor is connected to the input terminal of the output matching circuit, and the gate of the seventh transistor is connected to and controlled by a digital control logic circuit.

3. the output matching circuit includes a first inductor, a first capacitor, and a second capacitor; a first end of the first inductor is connected to a power supply voltage, and a second end of the first inductor is connected to a drain of the seventh transistor as an input end of the output matching circuit; the first capacitor and the first inductor are connected in parallel; 3. The radio frequency low noise amplifier circuit according to claim 2, wherein a first end of the second capacitor is connected to a second end of the first inductor, and a second end of the second capacitor is connected to the signal output terminal.

4. 2. The radio frequency low-noise amplifier circuit according to claim 1, wherein the first input matching network includes a second inductor and a third capacitor, a first end of the second inductor is connected to the signal input terminal as an input terminal of the first input matching network, a second end of the second inductor is connected to a first end of the third capacitor, and a second end of the third capacitor is connected to a gate of the first transistor.

5. 2. The radio frequency low noise amplifier circuit according to claim 1, wherein the third inductor and the fourth inductor are connected in series to form a source inductor of the second transistor.

6. A radio frequency chip comprising the radio frequency low noise amplifier circuit according to any one of claims 1 to 5.

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