Power management integrated circuit with field programmable array of voltage regulators

Abstract

A semiconductor device includes a plurality of voltage regulators arranged in a field programmable array and a power array controller coupled to the plurality of voltage regulators. The power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails, each power rail providing a respective rail current at a respective rail voltage. The power array controller is configured to: determine, for each of the plurality of power rails, a respective rail current associated with the respective power rail, select a subset of the voltage regulators according to at least the respective rail currents, and enable the subset of voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents.

Description

[Technical Field]

[0001] Related Applications

[0001] This application claims priority to U.S. Nonprovisional Patent Application No. 17 / 534,345, entitled "Power Management Integrated Circuit with a Field Programmable Array of Voltage Regulators," filed on November 23, 2021, which claims priority to U.S. Provisional Patent Application No. 63 / 143,732, entitled "Power Management Integrated Circuit with a Field Programmable Array of Voltage Regulators," filed on January 29, 2021. This application also claims priority to U.S. Nonprovisional Patent Application No. 17 / 534,362, entitled "Current Balancing for Voltage Regulator Units in Field Programmable Arrays," filed on November 23, 2021, which claims priority to U.S. Provisional Patent Application No. 63 / 143,734, entitled "Current Balancing for Voltage Regulator Units in Field Programmable Arrays," filed on January 29, 2021. Each of the above applications is incorporated herein by reference in its entirety.

[0002]

[0002] This application is related to PCT Patent Application No. __ (Attorney Docket No. 125533-5006-WO), entitled "Current Balancing for Voltage Regulator Units in Field Programmable Arrays," filed on November 24, 2021, the entire contents of which are incorporated herein by reference.

[0003] This application relates generally to electronic devices, including but not limited to devices and methods for adaptively driving power rails in electronic systems. [Background technology]

[0004]

[0004] Electronic devices often incorporate a system-on-chip (SoC) with a power management integrated circuit (PMIC), communication ports, external memory or storage, and other peripheral function modules on a main logic board. The SoC includes one or more microprocessors or central processing unit (CPU) cores, memory, input / output ports, and secondary storage in a single package. The PMIC is typically disposed adjacent to the SoC on the main logic board and provides multiple direct current (DC) power supply rails to the SoC through conductors formed on the main logic board. For each type of SoC, the PMIC and the conductors leading to the SoC need to be custom designed based on at least the microprocessor or CPU core included in that type of SoC. Customizing a PMIC for each SoC type is inefficient in many situations. It would be beneficial to provide an efficient, high-performance PMIC solution that is configurable to drive different types of SoCs. Summary of the Invention

[0005] To address the problems associated with custom-designed PMICs, it would be highly desirable to provide a semiconductor device or system with a general-purpose PMIC that can adaptively support a variety of different types of SoCs having different microprocessors or CPU cores, particularly a general-purpose PMIC that utilizes voltage regulators that are individually and mutually balanced to enable high performance of the general-purpose PMIC.

[0006] Various embodiments of systems, methods, and devices within the scope of the appended claims each have several aspects, no single aspect of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and particularly the section entitled "Detailed Description of the Invention," those skilled in the art will understand how aspects of the various embodiments can be used to provide a semiconductor device configured to provide multiple power rails to power one or more clusters of processors of an SoC. The semiconductor device includes multiple voltage regulators arranged in a field programmable array and controlled to output power to the multiple power rails of the SoC based on load information associated with one or more clusters of processors coupled to the power rails. In other words, the same semiconductor device can be configured to drive different types of SoCs based on their load information, resulting in a universal SoC power supply solution.

[0007] In some embodiments, for each power rail, in each active voltage regulator driving the respective power rail, intra- and / or inter-regulator current balancing mechanisms are applied internally such that path currents in different current paths of each active voltage regulator are balanced and output currents in different active voltage regulators driving the respective power rail are balanced. These balancing mechanisms are efficiently implemented for each individual voltage regulator (e.g., in a general-purpose PMIC circuit) without input or control from other separate voltage regulators. Furthermore, voltage regulators in a field programmable array can be electrically isolated from multiple power rails and become redundant voltage regulators without being completely powered down when a bypass unit is used to disable the feedback path between the output interface and input of the redundant voltage regulator.

[0008]

[0008] In particular, in one aspect, an integrated semiconductor device includes a plurality of voltage regulators and a power array controller. The plurality of voltage regulators are arranged in a field programmable array. The power array controller is coupled to the plurality of voltage regulators and configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a respective rail current at a respective rail voltage. For each of the plurality of power rails, the power array controller determines a respective rail current associated with the respective power rail, selects a subset of the voltage regulators according to at least the respective rail current, and enables the subset of voltage regulators to generate the respective rail voltage and collectively provide the respective rail current. In some embodiments, the power array controller includes one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the processors to control a plurality of voltage regulators to output power to a plurality of power rails.

[0009] In some embodiments, the power array controller is configured to determine a control value based on at least the respective rail voltages, and to enable a subset of the voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents in accordance with the determined control value. Further, in some embodiments, enabling the subset of voltage regulators further comprises providing the control value to the subset of voltage regulators. The subset of voltage regulators are controlled by the control value to generate the respective rail voltages and collectively provide the respective rail currents. Further, in some embodiments, enabling the subset of voltage regulators further comprises providing an operation enable signal to the selected subset of voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents.

[0010] In some embodiments, the power array controller is configured to determine a respective rail current associated with each power rail according to load information corresponding to an expected or actual load on the respective power rail. Further, in some embodiments, the load information corresponds to processor load information for one or more clusters of processors coupled to the respective power rail.

[0011] In some embodiments, the integrated semiconductor device further includes one or more direct current (DC) power supply interfaces, each configured to receive a distinct DC supply voltage, and each voltage regulator coupled to a respective subset of the one or more DC power supply interfaces, powered by a corresponding DC supply voltage, and configured to generate a respective rail voltage from the corresponding DC supply voltage.

[0012] In some embodiments, at each time, at least one of the multiple voltage regulators is redundant and not coupled to any of the multiple power rails.

[0013]

[0013] In some embodiments, selecting the subset of voltage regulators for each power rail further includes uniquely associating each of the subset of voltage regulators with a respective power rail at a respective time.

[0014] In some embodiments, for each power rail, the respective rail current is a maximum rail current I RLM Each of the subset of voltage regulators has a maximum regulator current I RGM A subset of voltage regulators are configured to provide currents up to the maximum rail current I RLM and the maximum regulator current I RGM Further, in some embodiments, the first power rails are configured to reach their respective rail voltages within a transient load response time at each startup of the first power rails, the transient load response time being less than or equal to a maximum regulator current I RGMThe first number is determined based on a transient load response time. Furthermore, the second power rail reaches its respective rail voltage within the transient load response time at each start-up of the second power rail and draws a maximum rail current I during normal operation. RLM The transient load response time is set to the maximum rail current I RLM In some embodiments, the power array controller is configured to, for each power rail, determine an instant rail current for the respective power rail and enable all of the subset of voltage regulators to collectively provide the instant rail current for the respective power rail. In some embodiments, the power array controller is configured to, for each power rail, determine an instant rail current for the respective power rail and enable all of the subset of voltage regulators to collectively provide the instant rail current for the respective power rail. In some embodiments, the power array controller is configured to, for each power rail, determine an instant rail current for the respective power rail and enable all of the subset of voltage regulators to collectively provide the instant rail current for the respective power rail. RGM , disabling one or more voltage regulators in the subset of voltage regulators, and allowing the remainder of the subset of voltage regulators to collectively provide the instantaneous rail current for the respective power rail.

[0015]

[0015] In some embodiments, the multiple voltage regulators are identical to each other.

[0016] In some embodiments, each of the plurality of voltage regulators corresponds to a respective voltage regulator type selected from a plurality of predefined voltage regulator types, and for each power rail, a subset of voltage regulators corresponds to each voltage regulator type, and selecting the subset of voltage regulators includes determining the respective voltage regulator type based on at least one performance criterion.

[0017] In some embodiments, for each power rail, each of the subset of voltage regulators further includes an output interface, one or more drive paths, and a voltage regulator controller. The output interface is coupled to the respective power rail and configured to provide a rail voltage and deliver a respective rail current to the respective power rail. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path, and is configured to control the one or more drive paths.

[0018] In some embodiments, for each power rail, each of the subset of voltage regulators further includes a bypass unit coupled to one or more drive paths and the voltage regulator controller. The bypass unit is configured to provide a dummy load component. Each voltage regulator has a standby / redundancy mode in which the bypass unit is enabled to bypass a feedback path from the output interface to an input of the voltage regulator controller, thereby disabling the respective voltage regulator from contributing to the respective rail current.

[0019] In some embodiments, for each power rail, each voltage regulator in the subset of voltage regulators is configured to provide a portion of the respective rail current and further includes an output interface electrically coupled to the respective power rail, a plurality of drive paths, and at least one of an intra-regulator balancing circuit and an inter-regulator balancing circuit. Each drive path is coupled to the output interface and configured to provide a respective path current to the respective power rail. The intra-regulator balancing circuit is coupled to the plurality of drive paths and configured to balance the respective path currents of the plurality of drive paths, and the inter-regulator balancing circuit is coupled to the output interface and configured to balance a portion of the respective rail current provided by each voltage regulator with at least another portion of the respective rail current provided by a separate voltage regulator in the subset of voltage regulators. Furthermore, in some embodiments, for each power rail, each voltage regulator in the subset of voltage regulators includes both an intra-regulator balancing circuit and an inter-regulator balancing circuit.

[0020] In another aspect, an integrated semiconductor device includes a power rail and a plurality of voltage regulators electrically coupled to the power rail. The power rail is configured to provide a rail voltage, and the plurality of voltage regulators are configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, a first drive path, a second drive path, and an in-regulator balancing circuit. The output interface is electrically coupled to the power rail. The first drive path is coupled to the output interface and configured to operate at an operating frequency during a first phase to provide a first path current to the power rail. The second drive path is coupled to the output interface and configured to operate at an operating frequency during a second phase to provide a second path current to the power rail. The second drive path is electrically coupled in parallel with the first drive path. The balancing circuit within the regulator is coupled to the first and second drive paths and configured to sense the first and second path currents and generate a first control signal for controlling a first duty cycle of the first phase and / or a second duty cycle of the second phase based on a difference between the first and second path currents.

[0021] In some embodiments, each of the plurality of voltage regulators further includes a voltage regulator controller having a feedback input coupled to the output interface. The feedback input of the voltage regulator controller is configured to receive the output voltage of the output interface. Each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The inter-regulator balancing circuit is configured to sense an output current of the respective voltage regulator and apply an offset to a control input of the voltage regulator controller, where the offset is determined based on the sensed output current of the respective voltage regulator.

[0022]

[0022] In some embodiments, the balancing circuit within the regulator is configured to determine that a difference between the first and second path currents does not satisfy a path current balancing criterion, and, in accordance with the determination that the difference between the first and second path currents does not satisfy the path current balancing criterion and the determination that the first path current is greater than the second path current, implement one or both of reducing the first duty cycle of the first phase and increasing the second duty cycle of the second phase until the difference between the first and second path currents satisfies the path current balancing criterion.

[0023]

[0023] In some embodiments, each of the plurality of voltage regulators further includes a voltage regulator controller having a feedback input coupled to the output interface, the feedback input of the voltage regulator controller configured to receive the output voltage of the output interface. Further, in some embodiments, each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The inter-regulator balancing circuit is configured to sense an output current of the respective voltage regulator and apply an offset to a control input of the voltage regulator controller. The offset is determined based on the sensed output current of the respective voltage regulator. Further, in some embodiments, the voltage regulator controller includes an error amplifier configured to receive the control input and apply an offset between the feedback input and a control value defining the rail voltage. In some embodiments, each of the plurality of voltage regulators further includes an inter-regulator balancing circuit coupled to the output interface and the voltage regulator controller. The inter-regulator balancing circuit is configured to sense one of the first and second path currents of each voltage regulator and apply an offset to the control input received by the voltage regulator controller, the offset being based on the sensed one of the first and second path currents.

[0024] In some embodiments, each of the first and second drive paths is connected to an input supply voltage V in and a switching component coupled to the output interface, and a driver coupled to the switching component and configured to enable the switching component at the operating frequency during a respective one of the first and second phases, thereby enabling the respective one of the first and second path currents to be provided to the power rail.

[0025] In some embodiments, a first duty cycle of the first phase is equal to a second duty cycle of the second phase, and the second phase is offset from the first phase.

[0026] In some embodiments, the first control signal is generated to control the second duty cycle of the second phase based on a difference between the first and second path currents. Each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during the third phase to provide a third path current to the power rail, the third drive path being electrically coupled in parallel with the first and second drive paths. The in-regulator balancing circuit is coupled to the third drive path and configured to sense the third path current and generate a second control signal to control the third duty cycle of the third phase based on the difference between the first and third path currents.

[0027] In some embodiments, each of the plurality of voltage regulators further includes a third drive path coupled to the output interface and configured to operate at the operating frequency during the third phase to provide a third path current to the power rail, the third drive path being electrically coupled in parallel with the first and second drive paths. The in-regulator balancing circuit is coupled to the third drive path and configured to sense the third path current and generate a first control signal for controlling the first duty cycle of the first phase based on a difference between the first and second path currents and based on a difference between the first and third path currents.

[0028]

[0028] In some embodiments, the multiple voltage regulators and one or more additional voltage regulators are arranged in a field programmable array, and the multiple voltage regulators are selected from the field programmable array to drive the power rails based on load information corresponding to expected or actual loads on the power rails.

[0029]

[0029] In yet another aspect, an integrated semiconductor device includes a power rail and a plurality of voltage regulators coupled to the power rail. The power rail is configured to provide a rail voltage, and the plurality of voltage regulators are configured to collectively provide the rail voltage. Each of the plurality of voltage regulators includes an output interface, one or more drive paths, a voltage regulator controller, and a bypass unit. The output interface is coupled to the power rail and configured to provide the rail voltage and deliver up to a predefined regulator current to the power rail. The one or more drive paths are coupled to the output interface and configured to operate at an operating frequency. The voltage regulator controller has an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path and is configured to control the one or more drive paths. The bypass unit is coupled to the one or more drive paths and the voltage regulator controller and configured to provide a dummy load component. Each voltage regulator has a standby / redundant mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller.

[0030]

[0030] Other embodiments and advantages will be apparent to those skilled in the art in light of the description and drawings herein. [Brief explanation of the drawings]

[0031] [Figure 1]

[0031] A block diagram of exemplary system modules in a typical electronic device, according to some embodiments. [Figure 2]

[0032] 1 is a block diagram of a power management system according to some embodiments. [Figure 3]

[0033] 1 is a cross-sectional view of an integrated semiconductor device according to some embodiments. [Figure 4A]

[0034] 1 is a diagram of a field programmable array of voltage regulators according to some embodiments. [Figure 4B] 4B is a diagram of a basic cluster of voltage regulators in the field programmable array shown in FIG. 4A, according to some embodiments. [Figure 5]

[0035] 5 is a schematic diagram of a power management system including the field programmable array of voltage regulators shown in FIG. 4, according to some embodiments. [Figure 6]

[0036] 1 is a simplified block diagram of an integrated semiconductor device including multiple voltage regulators for providing one or more power rails to an SoC, according to some embodiments. [Figure 7A]

[0037] FIG. 2 illustrates a process for providing a rail current IR at a rail voltage VR using a subset of voltage regulators according to some embodiments. [Figure 7B] 1 illustrates a process for providing a rail current IR at a rail voltage VR based on one or more redundant voltage regulators, according to some embodiments. [Figure 8A]

[0038] FIG. 1 is a block diagram of a voltage regulator used as a basic unit to form a field programmable array, according to some embodiments. [Figure 8B]

[0039] 1 is a block diagram of a voltage regulator using current balancing and / or redundancy control according to some embodiments. [Figure 9]

[0040] 8 is a circuit diagram of a voltage regulator having multiple drive paths 804, according to some embodiments. [Figure 10A]

[0041] 1 is a circuit diagram of a voltage regulator having two drive paths balanced by an in-regulator balancing circuit, according to some embodiments. [Figure 10B]

[0042] 1 is a circuit diagram of a voltage regulator having more than two (e.g., three) drive paths balanced by an in-regulator balancing circuit, according to some embodiments. [Figure 10C]

[0043] 1 is a circuit diagram of a voltage regulator balanced drive path with a differential amplifier according to some embodiments. [Figure 11A]

[0044] 3 is an equivalent circuit diagram of a power rail driven by two voltage regulators in a field programmable array of voltage regulators, according to some embodiments. [Figure 11B]

[0045] 1 is an equivalent circuit diagram of a single voltage regulator using a low pass filter (LPF) for inter-regulator current balancing, according to some embodiments. [Figure 12A]

[0046] 1 is a circuit diagram of a voltage regulator controlled by an inter-regulator balancing circuit according to some embodiments. [Figure 12B] 1 is a circuit diagram of a voltage regulator controlled by an inter-regulator balancing circuit according to some embodiments. [Figure 13]

[0047] 1 is a circuit diagram of a voltage regulator of a field programmable array of voltage regulators having an auxiliary loop to control redundancy, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0032]

[0048] Like reference numbers refer to corresponding parts throughout the drawings.

[0033]

[0049] Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth to aid in understanding the subject matter presented herein. However, it will be apparent to those skilled in the art that various alternatives may be used without departing from the scope of the claims and that the subject matter may be practiced without these specific details. For example, it will be apparent to those skilled in the art that the subject matter presented herein may be implemented on many types of electronic devices with power management capabilities.

[0034]

[0050] Previously, for each type of SoC, the PMIC and the conductors leading to the SoC had to be custom designed based on at least the microprocessor or CPU core included in that type of SoC. Customizing the PMIC for each SoC type was inefficient in many situations. Furthermore, in some situations, voltage regulators in the same PMIC were not balanced, impairing the performance of the PMIC. In various embodiments of the present application, an integrated semiconductor device is configured to provide multiple power rails to power one or more clusters of processors of the SoC. The semiconductor device includes multiple voltage regulators arranged in a field programmable array and controlled to output power to the multiple power rails of the SoC based on load information associated with the one or more clusters of processors coupled to the power rails. The same integrated semiconductor device is tuned to power different types of SoCs. Furthermore, in some embodiments, for each power rail, in each active voltage regulator driving the respective power rail, an intra-regulator and / or inter-regulator current balancing mechanism is internally applied, such that the path currents in different current paths of each active voltage regulator are balanced and the output currents in different active voltage regulators driving the respective power rail are balanced. By these means, the present application provides an efficient and high-performance PMIC solution with highly balanced voltage regulators and capable of adaptively driving different types of SoCs.

[0035]

[0051] 1 is a block diagram of an exemplary system module 100 in a typical electronic device, according to some embodiments. The system module 100 in this electronic device includes at least a system-on-chip (SoC) 102, a memory module 104 for storing programs, instructions, and data, an input / output (I / O) controller 106, one or more communication interfaces, such as a network interface 108, and one or more communication buses 150 for interconnecting these components. In some embodiments, the I / O controller 106 enables the SoC 102 to communicate with I / O devices (e.g., a keyboard, a mouse, or a touchscreen) via a Universal Serial Bus interface. In some embodiments, the network interface 108 includes one or more interfaces for Wi-Fi, Ethernet, and Bluetooth networks, each of which allows the electronic device to exchange data with an external source, e.g., a server or another electronic device. In some embodiments, the communication bus 150 includes circuitry (sometimes referred to as a chipset) that interconnects and controls communications between the various system components included in the system module 100.

[0036]

[0052] In some embodiments, memory module 104 includes high-speed random-access memory, such as DRAM, SRAM, DDR RAM, or other random-access solid-state memory devices. In some embodiments, memory module 104 includes non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. In some embodiments, memory module 104, or alternatively, the non-volatile memory devices within memory module 104, include a non-transitory computer-readable storage medium. In some embodiments, a memory slot is reserved on system module 100 to accept memory module 104. When inserted into the memory slot, memory module 104 is integrated into system module 100.

[0037]

[0053] In some embodiments, the system module 100 further includes one or more components selected from the following: a memory controller 110 that controls communication between the SoC 102 and memory components, including the memory module 104, in the electronic device; A solid-state drive (SSD) 112, which applies integrated circuit assemblies for storing data in electronic devices, and in many embodiments is based on NAND or NOR memory configurations; hard drive 114, a conventional data storage device based on electromechanical magnetic disks used to store and retrieve digital information; a power supply connector 116 including one or more direct current (DC) power supply interfaces each configured to receive a separate DC supply voltage; a power management integrated circuit (PMIC) 118 that modulates the separate DC supply voltage received via the DC power supply interface to other desired internal supply voltages, e.g., 5V, 3.3V, or 1.8V, as required by various components or circuits within the electronic device (e.g., processor cores in the SoC 102); a graphics module 120 that generates an output image feed to one or more display devices according to a desired image / video format; and A sound module 122 that facilitates the input and output of audio signals to and from electronic devices under the control of a computer program.

[0038]

[0054] Also, note that communication bus 150 interconnects and controls communications between various system components, including components 110-122.

[0039]

[0055] Furthermore, those skilled in the art will appreciate that other non-transitory computer-readable storage media may be used as new data storage technologies are developed for storing information on non-transitory computer-readable storage media in memory module 104 and in SSD 112. These new non-transitory computer-readable storage media include, but are not limited to, those made from biological materials, nanowires, carbon nanotubes, and individual molecules, although each of these data storage technologies is currently under development and has not yet been commercialized.

[0040]

[0056] In some embodiments, the SoC 102 is implemented in a semiconductor package containing one or more integrated circuits, each incorporating a subset of one or more microprocessors or CPU cores, memory, input / output ports, and secondary storage on a single substrate. The PMIC 118 is also implemented in a semiconductor package containing one or more integrated circuits, each formed on a single substrate. The SoC 102 is configured to receive one or more internal supply voltages (also referred to as rail voltages) provided by the PMIC 118 via one or more power rails. In some embodiments, both the SoC 102 and the PMIC 118 are mounted on a main logic board, e.g., on two separate areas of the main logic board, and are electrically coupled to each other via conductors formed in the main logic board. This arrangement introduces parasitic effects and electrical noise that can impair the performance of the SoC, for example, causing voltage drops in the internal supply voltages. Alternatively, according to various embodiments described below, the semiconductor dies of the SoC 102 and the PMIC 118 are vertically packaged in an integrated semiconductor device such that they are electrically coupled to each other via electrical connections not formed in the main logic board. Such a vertical arrangement of the semiconductor dies of the SoC 102 and the PMIC 118 can reduce the length of the electrical connections between the SoC 102 and the PMIC 118 and avoid performance degradation caused by routing conductors on the main logic board.

[0041]

[0057] It should be noted that in some embodiments, vertical placement of the semiconductor dies of the SoC 102 and the PMIC 118 is facilitated in part by the incorporation of thin-film inductors in the limited space between the dies of the SoC 102 and the PMIC 118. The thin-film inductors are formed and incorporated on the substrate of the PMIC 118 so that they can fit into the limited space between the semiconductor dies of the SoC 102 and the PMIC 118, and have an inductor height controlled to be smaller than the height of the limited space. When the thin-film inductors are formed on the substrate of the PMIC 118, the thin-film inductors can be directly connected to internal or output nodes of the PMIC 118, and traces of the main logic board are not used to connect the thin-film inductors to the internal or output nodes of the PMIC 118.

[0042]

[0058] In various embodiments of the present application, the general-purpose PMIC 118 is configured to drive different types of SoCs 102 in different types of electronic devices 100. Whether the PMIC 118 and SoCs 102 are arranged side-by-side or vertically, the PMIC 118 occupies the same footprint on the main circuit board, while the SoCs 102 may have separate footprints based on the electronic modules incorporated therein. The PMIC 118 includes multiple voltage regulator units arranged in a field-programmable array. The multiple voltage regulator units may be identical to one another or may include two or more types of voltage regulator units. In a particular electronic device, control signals are determined based on the rail voltages and rail currents of the power rails, if any, required to power the SoCs 102 and other electronic modules. For each of these power rails, the corresponding control signal is used to select a subset of voltage regulator units in the field-programmable array of the PMIC 118, and the selected voltage regulator units collectively provide the rail current at the rail voltage for the respective power rail. Thus, the PMIC 118 is reconfigured by these control signals to provide rail voltages and currents to the power rails of the SoC 102, and each voltage regulator unit in the multiple configurable voltage regulators in the PMIC 118 is redundant or selected to drive one of the power rails by one of the control signals.

[0043]

[0059] 2 is a block diagram of a power management system 200 configured to provide power to one or more power rails 206 of an SoC, such as SoC 102, in accordance with some embodiments. Power management system 200 receives one or more input DC supply voltages 202 and digital power control signals 204, converts the input DC supply voltages 202 to one or more rail voltages, which are output by one or more power rails 206A, 206B, through 206N and provided to SoC 102. Power management system 200 includes a power management interface 208, one or more DC-DC converters 210 (e.g., DC-DC converters 210A, 210B, . . . 210N), and one or more output filters 212 (e.g., output filters 212A, 212B, . . . 212N). Power management interface 208 receives the input DC supply voltages 202 and the digital power control signals 204. In some embodiments, the power management interface 208 is controlled by a master power management interface of a central processor unit (e.g., on the SoC 102) and is configured to receive digital power control signals 204 from the SoC 102. The DC-DC converter 210 is coupled to the power management interface 208 and to the power rails 206 and is controlled by the digital power control signals 204 to generate one or more rail voltages provided on the power rails 206 from the input DC supply voltage 202. The output filter 212 is coupled to the DC-DC converter 210 and is configured to reduce noise in and maintain stability of the power rails 206 provided to the SoC 102. In some embodiments, the output filter (e.g., any of 212A, 212B, ... 212N) includes one or more respective output resistors 214 and one or more output capacitors 216 (e.g., 216A, 216B, ... 216N). In some embodiments, the output filter (eg, 212B) includes an inductor 218 and one or more output capacitors (eg, capacitor 216B).

[0044]

[0060] In some embodiments, power management system 200 is implemented on one or more PMIC dies 220 (corresponding to PMIC 118 of FIG. 1 ), with each PMIC die having a single substrate. In some embodiments, power management interface 208 and DC-DC converter 210 are formed on the substrate of a single PMIC die 220, e.g., reside on the same integrated circuit fabricated on the substrate of PMIC die 220. Conversely, in some embodiments, power management interface 208 and DC-DC converter 210 are formed on multiple substrates of multiple PMIC dies 220. In some embodiments, in addition to power management interface 208 and DC-DC converter 210, each PMIC die 220 further includes multiple thin-film inductors fabricated on or attached to the top surface of the substrate of PMIC die 220. In some cases, the multiple thin-film inductors include one or more inductors 218 used in output filter 212. In some cases, the multiple thin-film inductors include one or more inductors 218′ used in DC-DC converter 210. In some embodiments, in addition to the interface 208 , the converter 210 , and the inductor 218 / 218 ′, the PMIC die 220 further incorporates a subset of the output resistors 214 and capacitors 216 of the output filter 212 .

[0045]

[0061] In some embodiments, power management system 200 includes a field-programmable array of voltage regulator units, an output filter 212, one or more output resistors 214, one or more output capacitors 216, and one or more inductors 218. Digital power control signals 204 are determined, for example, by SoC 102, based on target power capabilities (e.g., rail voltages and rail currents) required for power rails 206. For example, each power rail is configured to power a CPU cluster, cache, or functional block of SoC 102, with respective power demands used by SoC 102 to indicate the target power capacity of the respective power rail. According to control signals 204, voltage regulator units in the field-programmable array are partitioned and configured to form one or more DC-DC converters 210, e.g., DC-DC converters 210A, 210B, ... 210N, to drive power rails 206 with the target power capabilities. For each DC-DC converter 210, additional components 212-218 may also be selected and controlled by a respective subset of control signals 204 to enable desired noise performance for the corresponding power rail 206.

[0046]

[0062] 3 is a cross-sectional view of an integrated semiconductor device 300 according to some embodiments. The semiconductor device 300 incorporates at least one SoC die 302 and at least one PMIC die 220 in a semiconductor package and includes at least a package substrate 304 having a first side 304A and a second side 304B opposite the first side 304A. The SoC die 302 is disposed on the first side 304A of the package substrate 304, and the PMIC die 220 is mechanically coupled to the second side 304B of the package substrate 304.

[0047]

[0063] The package substrate 304 further includes a plurality of first via interconnects 306 that pass through the body of the package substrate 304 and are exposed on both the first side 304A and the second side 304B. The PMIC die 220 is electrically coupled to the SoC die 302 through the plurality of first via interconnects 306 of the package substrate 304. In particular, the PMIC die 220 includes a plurality of DC connections 308 configured to output a plurality of rail voltages provided to the power rails 206 ( FIG. 2 ). When the PMIC die 220 is mounted on the second side 304B of the package substrate 304, the DC connections 308 are electrically coupled to the plurality of first via interconnects 306 of the package substrate 304. In some embodiments, the SoC die 302 includes a plurality of power connections 312 configured to receive a plurality of rail voltages. When the SoC die 302 is mounted on the first surface 304A of the package substrate 304, the power connections 312 are electrically coupled to the plurality of first via interconnects 306 of the package substrate 304. Thus, the PMIC die 220 is configured to provide DC power (i.e., the rail voltage and rail current of the power rails 206) to the SoC die 302 via the DC connections 308 of the PMIC die 220, the power connections 312 of the SoC die 302, and the first via interconnects 306 of the package substrate 304. Furthermore, by using the extremely low impedance DC connections 308, the quality of the PMIC die 220 providing DC power to the SoC die 302 is significantly improved relative to a system in which the PMIC die 220 and the SoC die 302 are packaged separately and placed side-by-side on a main circuit board.

[0048]

[0064] In some embodiments, the power management interface 208 on the PMIC die 220 is controlled by the master power management interface of the SoC die 302 and is configured to receive the digital power control signals 204 from the SoC die 302. A subset of the first via interconnects 306 is configured to transfer the digital power control signals 204 from the SoC die 302 to the PMIC die 220.

[0049]

[0065] The SoC die 302 has a first footprint on the package substrate 304, and the PMIC 220 has a second footprint on the package substrate 304. The first and second footprints at least partially overlap for the purpose of directly coupling the DC connections 308 of the PMIC die 220 to the power connections 312 of the SoC die 302 using a plurality of first via interconnects 306. In some situations, the first footprint of the SoC die 302 is larger than and completely surrounds the second footprint of the PMIC die 220. Alternatively, in some situations, the first footprint of the SoC die 302 is offset from but at least partially overlaps with the second footprint of the PMIC die 220. The DC connection 308 of the PMIC die 220, the power connection 312 of the SoC die 302, and the first via interconnect 306 of the package substrate 304 are aligned and surrounded in the overlap area of ​​the first and second footprints.

[0050]

[0066] Further, the PMIC die 220 includes a plurality of thin-film inductors 218 corresponding to the plurality of DC connections 308. The plurality of thin-film inductors 218 are located adjacent to or opposite the second side 304B of the package substrate 304, for example, on the top surface of the PMIC die 220 facing the second side 304B of the package substrate 304. In other words, the plurality of thin-film inductors 218 are disposed between the top surface of the PMIC die 220 and the second side 304B of the package substrate 304. In some embodiments, the PMIC die 220 is mechanically coupled to the package substrate 304, for example, via an adhesive. The height of the plurality of thin-film inductors 218 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) to maintain robustness of the mechanical coupling between the PMIC die 220 and the package substrate 304.

[0051]

[0067] In some embodiments, the integrated semiconductor device 300 further includes a cover 314 coupled to the first surface 304A of the package substrate 304. The cover 314 is configured to conceal the SoC die 302 and at least a portion of the first surface 304A of the package substrate 304, thereby protecting the SoC die 302 and at least a portion of the first surface 304A. Additionally, in some embodiments, the cover 314 is made from a conductive material and is configured to be grounded to provide electrostatic shielding to the SoC die 302 and any other circuitry on the first surface 304A when fully concealed by the cover 314, or to provide electrostatic shielding to the portion of the first surface 304A concealed by the cover 314 when the first surface 304A is only partially concealed by the cover 314. In some circumstances, the cover 314 is made from a thermally conductive material configured to dissipate heat generated by the SoC die 302. In some embodiments, a heat spreader 316, or layer of heat spreader, is used to couple the SoC die 302 to the inner surface of the cover 314 to uniformly spread heat generated by the SoC die 302 from the SoC die 302 to the cover 314.

[0052]

[0068] In some embodiments, the semiconductor device 300 further includes a socket substrate 318. The socket substrate 318 has a third surface 318A opposite the second surface 304B of the package substrate 304. The package substrate 304 is electrically coupled to the socket substrate 318 via a plurality of electrical connectors 320. In particular, the second surface 304B of the package substrate 304 includes a first area (e.g., a central area) to which the PMIC die 220 is mechanically coupled and a second area (e.g., a peripheral area) in which the plurality of electrical connectors 320 are located. In one example, the second area is adjacent to or surrounds the first area. Note that under some circumstances, the semiconductor device 300 is provided with the socket substrate 318. However, under some circumstances, the socket substrate 318 is fixed onto the circuit board of the electronic device of FIG. 1 and is not part of the integrated semiconductor device 300. Instead, semiconductor device 300 is an interchangeable part that provides for the proposed functionality of the PMIC die 220 and SoC die 302 combination.

[0053]

[0069] In some embodiments, the third surface 318A of the socket substrate 318 is substantially flat, and the PMIC die 220 is disposed between the second surface 304B of the package substrate 304 and the third surface 318A of the socket substrate 318. The height of the plurality of thin-film inductors 218 is less than a predetermined threshold height (e.g., 1 mm, 100 μm) determined by the difference between the length of the electrical connector 320 and the thickness of the PMIC die 220. Alternatively, in some embodiments, the socket substrate 318 includes a recessed portion 322 formed on the third surface 318A and configured to receive the PMIC die 220 when the PMIC die 220 is mechanically and electrically coupled to the second surface 304B of the package substrate 304. The depth of the recessed portion 322 is less than the thickness of the socket substrate 318. In some circumstances, the PMIC die 220 is suspended in the recessed portion 322, i.e., separated from a bottom surface of the recessed portion 322 by an air gap. Alternatively, in some situations, the PMIC die 220 contacts the bottom surface of the concave portion 322 either directly or through an intermediate layer (e.g., an adhesive layer, a heat spreader layer, or a layer that is both an adhesive and a heat spreader).

[0054]

[0070] 3, the depth of recessed portion 322 is equal to the thickness of socket substrate 318, and recessed portion 322 is an opening or cutoff in socket substrate 318. When socket substrate 318 is mounted on a circuit board (e.g., a main logic board), PMIC die 220 is suspended in recessed portion 322 (also called an opening or cutoff) and is at least partially surrounded by package substrate 304, socket substrate 318, and the circuit board.

[0055]

[0071] In some embodiments, the power connections 312 of the SoC die 302 are not directly coupled to the first via interconnects 306 of the package substrate 304. Instead, a first interposer 324 is disposed between the SoC die 302 and the first side 304A of the package substrate 304. The first interposer 324 further includes a plurality of second via interconnects 326 configured to at least electrically couple the power connections 312 of the SoC die 302 to the first via interconnects 306 of the package substrate 304. Similarly, in some embodiments, the DC connections 308 of the PMIC die 220 are not directly coupled to the first via interconnects 306 of the package substrate 304. Instead, a second interposer 328 is disposed between the PMIC die 220 and the second side 304B of the package substrate 304. The second interposer 328 further includes a plurality of third via interconnects configured to at least electrically couple the DC connection 308 of the PMIC die 220 and the first via interconnect 306 of the package substrate 304. Thus, the power rail 206 of the SoC 102 includes at least the power connection 312 of the SoC die 302, the first via interconnect 306 of the package substrate 304, and the DC connection 308 of the PMIC die 220, and in some circumstances further includes the second via interconnect 326 of the first interposer 324 and / or the third via interconnect 332 of the second interposer 328.

[0056]

[0072] In some embodiments, the semiconductor device 300 further includes one or more discrete electronic modules 330 (e.g., resistors, capacitors, inductors, transistors, and logic chips). The discrete electronic modules 330 may be electrically coupled in an input / output interface circuit of the SoC die 302 to control input / output coupling of the SoC die 302. In some cases, a subset of the discrete electronic modules 330 (e.g., components 330A) are disposed on the first side 304A of the package substrate 304. Each component 330A may be contained within the cover 314 or located outside the cover 314. In some cases, a subset of the discrete electronic modules 330 (e.g., components 330B) are mechanically coupled to the second side 304B of the package substrate 304. If each component 330B has a low profile (e.g., thinner than the length of the electrical connector 320), the component 330B may fit into the gap between the second side 304B of the package substrate 304 and the third side 318A of the socket substrate 318. Otherwise, if the components 330B do not have a low profile (e.g., are thicker than the length of the electrical connector 320), each component 330B may be received by the recessed portion 322 of the socket substrate 318 and disposed adjacent to the PMIC die 220.

[0057]

[0073] The SoC die 302 and the PMIC die 220 are arranged vertically in the semiconductor device 300. The power connections 312 of the SoC die 302 and the DC connections 308 of the PMIC die 220 are aligned and located close to each other, thereby reducing parasitic resistance and capacitance coupled to each power rail 206 that provides rail voltages to the SoC die 302. Note that in some implementations, multiple PMIC dies 220 may be disposed in a recessed portion 322 of the socket substrate 318 and electrically coupled to one or more SoC dies 302 disposed on the first side 304A of the package substrate 304. For example, two PMIC dies 220 are disposed in the recessed portion 322 of the socket substrate 318 to collectively power four SoC dies 302. One of the SoC dies 302, as the case may be, corresponds to a microprocessor or CPU core or a cluster of microprocessors or CPU cores.

[0058]

[0074] Additionally, in some embodiments of the present application, the PMIC die 220 includes a field-programmable array of voltage regulators that are configurable by control signals to drive different types of SoC die 302. In some situations, the same PMIC die 220, package substrate 304, and socket substrate 318 are used to support different types of SoC die 302. The recessed portion 322 formed on the socket substrate 318 has a fixed size to accommodate the same PMIC die 220, and the first via interconnects 306 passing through the body of the package substrate 304 have fixed locations. Alternatively, in some situations, the footprint sizes of the package substrate 304 and the socket substrate 318 are different for different types of SoC die, but the same PMIC die 220 allows the recessed portion 322 and the first via interconnects 306 of the package substrate 304 to remain constant, thereby avoiding custom-designing the PMIC die 220 and the entire package for each individual type of SoC die 302. Therefore, the application of a field programmable array of voltage regulators in the PMIC die 220 simplifies the assembly process of the semiconductor device 300 and improves cost efficiency.

[0059]

[0075] FIG. 4A is a diagram of a field programmable array 400 of voltage regulators 402 according to some embodiments, and FIG. 4B is a diagram of a basic cluster 420 of voltage regulators 402 in the field programmable array 400 shown in FIG. 4A according to some embodiments. The field programmable array 400 of voltage regulators 402 is used to establish a power management system 200 and is configured to provide one or more power rails 206 to an SoC, such as SoC 102. In the field programmable array 400, the voltage regulators 402 correspond to one or more voltage regulator types and are organized into multiple rows and multiple columns (e.g., 16 rows and 15 columns in FIG. 4A ). When only one type of voltage regulator is used, the voltage regulators 402 of the field programmable array 400 are identical to one another (e.g., have identical circuitry but may be configured differently). In some implementations, the field programmable array 400 includes a single cluster 420 of voltage regulators. In some implementations, the field programmable array 400 includes multiple basic clusters 420 of voltage regulators, e.g., six basic clusters 420 arranged in two rows and three columns in FIG. 4A . The multiple basic clusters 420 in the field programmable array 400 may be identical to one another. Alternatively, the multiple basic clusters 420 may be unrelated to one another, with each basic cluster 420 including a respective sub-array of voltage regulators 402 including a single type of voltage regulator or two or more types of voltage regulators. In some implementations, each basic cluster 420 is formed on a separate substrate and includes a standalone semiconductor chip. Alternatively, in some implementations, two or more basic clusters 420 are formed on the same substrate. Whether the basic clusters 420 of the field programmable array 400 are formed on a single substrate or two or more substrates, these basic clusters 420 are coupled to one another and configured to together implement the power management system 200.

[0060]

[0076] 2, the power management system 200 includes a power management interface 208 having a power array controller (e.g., power array controller 602 of FIG. 6). The power array controller is coupled to and configured to control the field-programmable array of voltage regulators 400. In some embodiments, the power array controller further includes multiple circuit modules, e.g., an analog-to-digital converter (ADC) 404, an analog register 406, an oscillator 408, a static random access memory (SRAM) array 410, a phase-locked loop (PLL) circuit 412, and / or a low-dropout regulator (LDO) 414. The power array controller 602 optionally includes one or more processors (e.g., microcontroller 508, FIG. 5), non-volatile memory (NVM) 506 (e.g., read-only memory, one-time programmable (OTP) memory), registers 506, and one or more finite state machines (e.g., 532). In some implementations, each circuit module in the plurality of circuit modules is disposed between two adjacent rows of voltage regulators 402 in the field programmable array 400. In some implementations, the memory of the power array controller stores one or more programs having instructions that, when executed by one or more processors, cause the processors to control the voltage regulators 402 in the field programmable array 400 to output power.

[0061]

[0077] The multiple voltage regulators 402 are controlled by a power array controller of the power management interface 208 to output power to multiple power rails 206. Each power rail 206 has a respective rail voltage V R In each rail current I R The power array controller is required to provide, for each power rail, at least the respective rail current I R, and is configured to select a respective subset of voltage regulators 402 in field programmable array 400 according to the voltage regulators 402 selected in the clusters 420. In some embodiments, for each power rail 206, the selection of voltage regulators 402 is implemented at the package or board level of power management system 200 and may include voltage regulators 402 in different clusters 420 distributed throughout field programmable array 400. The voltage regulators selected for each power rail 206 need not be limited to voltage regulators in a single cluster 420, or a limited number of clusters 420. In one example, first power rail 206-1 is configured to be powered by ten voltage regulators 402 located on the same cluster 420A. In another example, second power rail 206-2 is configured to be powered by ten voltage regulators 402 located in two or more separate clusters (e.g., 420B, 420C, and 420D) formed on two or more separate semiconductor chips.

[0062]

[0078] For each of the plurality of power rails 206 (e.g., power rail 206-1 or 206-2), the voltage regulators 402 in the respective subset of voltage regulators 402 selected for that power rail are controlled to share the corresponding load on the respective power rail in a substantially equal manner. Each voltage regulator 402 in the respective subset, when activated to power the respective power rail, supplies a respective rail voltage V R and the respective rail currents I R For example, the first power rail 206-1 is controlled to provide a first rail voltage V R1 and the first rail current I R1 and ten voltage regulators 402 configured to power the first power rail 206-1, each having an output coupled to the first power rail 206-1 and providing a first rail voltage V R1 and 1 / 10 of the first rail current (i.e., 0.1 I R1) In some implementations, first power rail 206-1 is associated with one or more inter-regulator balancing circuits coupled between the ten voltage regulators 402 to evenly (or substantially evenly) balance the load on each power rail among the ten voltage regulators 402. Conversely, in some implementations, no inter-regulator balancing circuits are coupled between any two of the corresponding ten voltage regulators 402 configured to power first power rail 206-1. Each voltage regulator 402 is individually and independently controlled, for example, based on its respective output current, to power its respective portion of the load balanced with other portions of the load powered by the other voltage regulators 402.

[0063]

[0079] One or more clusters 420 of voltage regulators are formed on the same substrate using one or more layers of interconnects 416. In some embodiments, pairs of adjacent layers of the one or more layers of interconnects 416 are electrically coupled through electrical contacts and / or vias. Each voltage regulator 402 in the one or more clusters 420 may be electrically coupled to a respective power rail 206 via the interconnects 416. Each voltage regulator 402 may also be coupled to and controlled by multiple circuit modules of the power array controller via the interconnects 416. In some implementations, multiple DC connections 308 are formed and exposed on the top surface of the substrate of the one or more clusters 420 of voltage regulators. The multiple DC connections 308 are electrically coupled to a subset of the interconnects 416 and are part of one or more power rails 206 of the SoC die 302. The DC connections 308 connect one or more rail voltages V output by the voltage regulators 402. R 3 and 4B , the cluster 420 of voltage regulators in the PMIC die 220 receives DC power (i.e., the rail voltage V output by the voltage regulator 402) through the DC connection 308 of the PMIC die 220, the power connection 312 of the SoC die 302, and the first via interconnect 306 of the package substrate 304. Rand current I R and ) to the SoC die 302. In one example, each DC connection 308 of the PMIC die 220 includes a conductive bump (e.g., a solder, gold, or copper bump).

[0064]

[0080] The field programmable array of voltage regulators 400 can be configured to accommodate the power requirements of different types of SoC 302 (e.g., rail voltage V R , rail current I R ) are scalable with the power rails 206. For example, the field programmable array 400 includes a plurality of voltage regulators 402 organized into clusters. When the field programmable array 400 is configured to drive a first SoC 302, a first group of the voltage regulators 402 is activated to power a first plurality of power rails 206. When the field programmable array 400 is configured to drive a second SoC die 302, a second group of the voltage regulators 402 is activated to power a second plurality of power rails 206. The first SoC die 302 is separate from the second SoC die 302, and the first plurality of power rails 206 is separate from the second plurality of power rails 206. The first and second groups of voltage regulators 402 are determined based on the power requirements of the power rails 206 of the first SoC die 302 and the second SoC die 302, respectively. Although the first and second groups of voltage regulators 402 are separate from one another, the same field programmable array 400 is applied to drive the first SoC die 302 and the second SoC die 302. Thus, the field programmable array 400 scales with the power requirements of the power rails 206 of the first SoC die 302 and the second SoC die 302.

[0065]

[0081] FIG. 5 is a schematic diagram of a power management system 500 including the field programmable array 400 of voltage regulators 402 shown in FIG. 4 , according to some embodiments. The field programmable array 400 includes a plurality of voltage regulators 402 configured to be controlled by a plurality of circuit modules. In some implementations, the plurality of circuit modules are disposed between rows of the plurality of voltage regulators 402 on the field programmable array 400. These circuit modules belong to a power management interface 208. In some implementations, the power management system 500 is controlled by a master power management interface of a central processor unit (e.g., the SoC 102) and is configured to receive one or more power control signals 204 from the SoC 102 via the SoC interface 502. The power control signals 204 may include information about a plurality of power rails 206 of the corresponding SoC 102 (e.g., configuration information such as voltage and current requirements), e.g., rail voltages V of the power rails 206, and the like. R and rail current I R The SoC 102 stores information about the power rails 206 in registers 506. The information about the power rails 206 is then extracted from registers 506, and the microcontroller 508 is configured to select a subset of the voltage regulators 402 in the plurality of voltage regulators 402 to drive each power rail 206 of the corresponding SoC die 302 based on the information about the power rails 206 in registers 506.

[0066]

[0082] The power management system 500 further includes one or more of the ADC 404, the analog register 406, the oscillator 408, the SRAM array 410, the PLL circuit 412, and the LDO 414. The oscillator 408 is configured to generate an internal clock signal 510. The clock select signal 514 is used to determine whether the internal clock signal 510 or the external clock signal 512 is selected to serve as a system clock 516. The microcontroller 508 is configured to operate under the control of the system clock 516. The PLL 412 is configured to receive the system clock 516 and generate a multi-phase clock 518 with or without a divider 520. Each voltage regulator 402 includes one or more switching-mode drive paths configured to operate at the frequency of the multi-phase clock 518. The frequency of the one or more switching-mode drive paths is equal to or a multiple of the frequency of the system clock 516.

[0067]

[0083] Furthermore, in some embodiments, the LDO 414 is applied to generate an additional rail voltage 522 from the input DC supply voltage 202, where the additional rail voltage 522 is separate from the rail voltage 206 provided by the voltage regulator 402. The additional rail voltage 522 is fairly stable with line and load variations, is not affected by changes in ambient temperature, and is stable over time. Even with changes in the input DC supply voltage 202 (within a predefined range), the variation of the additional rail voltage 522 is fairly small, e.g., less than a threshold dropout voltage. For example, if the input DC supply voltage 202 is 1.8 V or less, the additional rail voltage 522 remains substantially stable at 0.9 V (e.g., with a variation of less than ±50 mV) even when the input DC supply voltage 202 drops to 1.1 V.

[0068]

[0084] In some embodiments, power management system 500 further includes a reference generator 524 configured to provide one or more reference voltages to one or more of LDO 414, voltage regulator 402, fuse 526, and ADC 404. ADC 404 includes a track and hold circuit and an analog input multiplexer that allows conversion of up to nine different inputs (e.g., one or more reference voltages, input DC supply voltage 202, rail voltage 206, control and data extracted from register 506).

[0069]

[0085] In some embodiments, the power management system 500 further includes a thermal shutdown module 528 configured to monitor the temperature of the SoC die 302 coupled to the power management system 500 or the temperature of the power management system 500 itself, and to control (e.g., disable) outputting a rail voltage to the power rail 206 based on the temperature of the SoC die 302 or the power management system 500. In one example, when the temperature of the SoC die 302 exceeds a predefined SoC threshold temperature (e.g., 85° C.), the thermal shutdown module 526 disables outputting a rail voltage V R to allow the temperature of the SoC die 302 to drop below the SoC threshold temperature.

[0070]

[0086] 6 is a simplified block diagram of an integrated semiconductor device 600 including multiple voltage regulators 402 for providing one or more power rails 206 to an SoC 102, according to some embodiments. The multiple voltage regulators 402 are arranged in a field programmable array 400. A power array controller 602 includes multiple electronic modules (e.g., one or more of the SoC interface 502, oscillator 408, microcontroller 508, LDO 414, and reference generator 524 of FIG. 5) and is coupled to the multiple voltage regulators 402. The power array controller 602 is configured to control the multiple voltage regulators 402 to output power to the multiple power rails 206. Each power rail 206 has a respective rail voltage VR In each rail current I R 6, a field programmable array 400 of voltage regulators 402 feeds four power rails 206-1, 206-2, 206-3, and 206-4, each providing a rail voltage V R1 , V R2 , V R3 , and V R4 In the rail current I R1 , I R2 , I R3 , and I R4 For each of the plurality of power rails 206, the power array controller 602 provides a respective rail current I associated with the respective power rail 206. R and determine at least the respective rail current I R and selecting a subset of voltage regulators 402 according to R and generate the respective rail currents I R Thus, power array controller 602 and voltage regulator 502 implement a power management system for SOC 102 on one or more PMIC dies 220 (corresponding to PMIC 118 of FIG. 1).

[0071]

[0087] The SoC 102 includes multiple electronic components, such as one or more microprocessors or CPU cores 604, memory 606, a communications module 608, timing sources, peripherals (e.g., clocks, counter timers), analog interfaces, input / output ports, and / or secondary storage. The microprocessors or CPU cores 604 are sometimes arranged in clusters. The SoC 102 is implemented by one or more integrated circuits (e.g., SoC die 302) disposed on the same package substrate 304. Each SoC die 302 incorporates a subset of the electronic modules of the SoC 102 on its respective semiconductor substrate. In one example, the SoC 102 has a main SoC die including one or more processor cores 604 and a companion SoC die including the memory 606, analog interfaces, or other components separate from the processor cores 604.

[0072]

[0088] For each power rail 206, the respective rail voltage V R is determined by the operation of each subset of electronic components of the SOC 102. The power array controller 602 controls at least each rail voltage V R and providing the determined control values ​​610 to a subset of voltage regulators 402 corresponding to each power rail 206, such that the subset of voltage regulators 402 regulates the respective rail voltage V R and generate the respective rail currents I R Additionally, in some embodiments, the power array controller 602 is configured to enable collectively providing each rail voltage V R and generate the respective rail currents I R , provides an operational enable signal 612 to a selected subset of the voltage regulators corresponding to each power rail 206 to collectively provide

[0073]

[0089] In some embodiments, power array controller 602 includes one or more processors and memory storing instructions that, when executed by the one or more processors, cause the processors to control voltage regulators 402 to output power to multiple rails 206. In some situations, a VRU grouping configuration is stored in memory of power array controller 602 (e.g., non-volatile memory 506, FIG. 5 ), in off-chip non-volatile memory (NVM) of system module 100, or in the basic input / output system (BIOS) of system module 100 to associate control values ​​610 and enable signals 612 with a subset of voltage regulators for each of power rails 206. In some situations, the VRU grouping configuration is loaded and implemented by power array controller 602 when PMIC 220 is powered on.

[0074]

[0090] Each of the multiple power rails 206 is configured to power a subset of the electronic modules of the SOC 102, which are loads for the respective power rail 206. For each power rail 206, the power array controller 602 determines load information 614 corresponding to the expected or actual load for the respective power rail 206 and calculates a respective rail current I associated with the respective power rail according to the load information 614. RIn some embodiments, a power rail 206 is coupled to a main SoC die having one or more processor cores 604 arranged in clusters, and the load information 614 for that power rail 206 corresponds to processor load information for one or more clusters of processors 604 of the main SoC die coupled to that power rail 206. Examples of processor load information include the total number of operations to be performed by one or more clusters of processors 604, and the type of operation. Conversely, in some embodiments, one of the power rails 206 is coupled to a companion SoC die having memory 606 and is configured to power write and read operations on the memory 606. The load information for that power rail 206 corresponds to memory load information for memory accesses of the memory 606 on the companion SoC die. Examples of memory load information include the memory type of the memory 606, the frequency of memory write operations, and the frequency of memory read operations. Thus, the rail current I for each power rail 206 is R is adaptively determined based on the load information 614 (eg, processor or memory load information) of the respective power rail 206.

[0075]

[0091] Furthermore, in some embodiments, each of the plurality of voltage regulators 402 in the field programmable array 400 corresponds to a respective voltage regulator type selected from a plurality of predefined voltage regulator types. For each power rail 206, the selected subset of voltage regulators 402 meets at least one performance criterion (e.g., maximum rail current I RLM , maximum regulator current I RGM , output ripple voltage, power supply rejection ratio, load transient response, output noise, and power efficiency).

[0076]

[0092] 6, after a respective subset of voltage regulators 402 is selected for each power rail 206, each voltage regulator 402 in the subset is uniquely associated with a respective power rail 206 at a time. For example, at a first time, power rails 206-1, 206-2, 206-3, and 206-4 are associated with four separate sets of voltage regulators 402 as shown in FIG. 6. Each voltage regulator 402 in a first row is uniquely associated with power rail 206-1 at a first time and may not be associated with any of power rails 206-2, 206-3, or 206-4 at the same first time. However, at a second time, distinct from the first time, the voltage regulators 402 in the field programmable array 400 may be reconfigured to power separate power rails 206. Each voltage regulator 402 in a first row is uniquely associated with power rail 206-1 at a first time, but can be reconfigured to drive any of power rails 206-2, 206-3, and 206-4 at a second time. More generally, in some embodiments, at least a plurality of voltage regulators 402 in the field programmable array 400 can be configured to provide power to selected power rails 206 of a plurality of power rails at any one time. Thus, in some embodiments, a subset of the voltage regulators 402 are permanently assigned to some power rails 206, while others are configurable as to which power rails 206 they are connected to. In some other embodiments, all of the voltage regulators 402 in the field programmable array 400 are configurable as to which power rails 206 they are connected to.

[0077]

[0093] In some situations, one or more voltage regulators 402 (e.g., 402RA-402RD) in field programmable array 400 are redundant at a first time. However, redundant voltage regulators 402RA-402RD are not coupled to any of power rails 206 at the first time. At a second time after the first time, each of these redundant voltage regulators 402RA-402RD can be reconfigured to provide power to a respective power rail 206. In some embodiments, a voltage regulator 402 is completely powered down when it is configured as a redundant voltage regulator 402 that is not used to power any power rails 206. Conversely, in some embodiments, voltage regulator 402 includes a bypass unit configured to provide a dummy load component. In the standby / redundant mode, the bypass unit (e.g., under control of operation enable signal 612) bypasses the feedback path from the output interface to the input of voltage regulator 402, thereby preventing each voltage regulator 402 from sourcing any rail current I via the output interface. R Further details regarding standby / redundant mode are provided below with reference to FIG.

[0078]

[0094] In some embodiments, the semiconductor device 600 further includes one or more direct current (DC) power supply interfaces 616. Each DC power supply interface 616 receives a separate DC supply voltage V IN 202. Each voltage regulator 402 is coupled to a respective subset of one or more DC power supply interfaces 616 and configured to receive a corresponding DC supply voltage V IN 202 and the corresponding DC supply voltage V IN 202 to the respective rail voltage V R The method is configured to generate:

[0079]

[0095] FIG. 7A illustrates a voltage regulator using a subset of voltage regulators 402 to regulate a rail voltage V R In the rail current IR , and FIG. 7B illustrates a process 700 for providing a rail voltage V based on one or more redundant voltage regulators 402, according to some embodiments. R In the rail current I R 7 shows a process 750 for providing a rail current I R is 0 and the maximum rail current I RLM Each of the subset of voltage regulators 402 can vary between a maximum regulator current I RGM A subset of voltage regulators 402 is configured to provide a regulator current up to a maximum rail current I RLM and the maximum regulator current I RGM For example, in FIG. 6, the first power rail 206-1 has a maximum rail current I RLM , and each voltage regulator 402 is required to output a maximum regulator current I RGM Each regulator can provide a maximum rail current I RLM (for example, 0.6A) and the maximum regulator current I RGM (for example, 80mA) and the eight voltage regulators supply the maximum rail current I RLM Rail current I up to R are required to provide.

[0080]

[0096] In some embodiments, the maximum rail current I RLM is the rail voltage V within the transient load response time. R , and the power rail 206 then reaches a maximum rail current I RLM The power rail 206 operates at an operating current less than the rail voltage V within the transient load response time at each power-up of the power rail 206. R The rail voltage V R Providing enough power to the power rails to reach the maximum regulator current I during startup RGM and maximum rail current I RLMand thus the first number of voltage regulators is determined in part based on the transient load response time required for start-up of the power rails 206. However, in some embodiments, when ramping up the voltage on each power rail 206 at power rail start-up, the current provided by power management system 500 is significantly less than the maximum rail current for that power rail to reduce system stress, avoid overshoot, etc.

[0081]

[0097] During operation (sometimes referred to herein as normal operation, as opposed to startup) of the power rail 206, the operating current I R varies, and the maximum rail current I RLM Conversely, in some embodiments, the rail current I R When is used, the maximum rail current I RLM is reached at least occasionally during normal operation of the power rail 206. The operating current is between 0 and the maximum rail current I RLM In contrast to power rail 206 startup, during normal operation, the first number of voltage regulators is determined based on the operating current of the power rail 206, rather than the transient load response time of the power rail 206 at each startup. The transient load response time of the power rail 206 is determined based on the maximum rail current I RLM This can be achieved with a transient rail current less than

[0082]

[0098] Referring to FIG. 7A, at each time, regardless of whether each time corresponds to startup or normal operation of the power rail 206, the power rail 206 experiences an instantaneous rail current I R In some embodiments, the power array controller 602 may be configured to adjust the instantaneous rail current I of the power rail 206 when all of the subset of voltage regulators 402 are in a R In other words, the instantaneous rail I R is 0 and the maximum rail current I RLMFor example, first power rail 206-1 (FIG. 6) may fluctuate between 0.5 I and 1.5 I at a time, and none of the subsets of voltage regulators 402 operate in standby / redundant mode. RLM The instantaneous rail current I is equal to R and the maximum rail current I RLM All eight voltage regulators configured to provide 0.5I RLM 4. The voltage regulators 402 are enabled while being controlled by the power array controller 602 to collectively provide only a portion of the power capability of each voltage regulator 402. Thus, in this example, only a portion of the power capability of each voltage regulator 402 is utilized. In some situations, the instantaneous rail current I R The rail voltage V R is the maximum rail current I RLM The rail voltage V R The power array controller 602 and / or the voltage regulator 402 may vary the first rail voltage error by a rail drift tolerance V RT The device is configured to maintain (e.g., limit or control) the amount of data that is available within the device.

[0083]

[0099] Furthermore, in some embodiments, a subset of voltage regulators 402 may be configured to substantially equally distribute the instantaneous rail current I R For example, each voltage regulator 402 is controlled to contribute its portion to the instantaneous rail current I R , which varies by less than 5% (or 10%, 20%, or other predefined margin) between voltage regulators 402 configured to provide power to the same power rail 206. Each voltage regulator 402 provides a respective rail current I provided by the respective voltage regulator 402. R , by dividing a portion of each rail current I provided by a separate voltage regulator 402 in the subset of voltage regulators 402. R In some implementations, an inter-regulator balancing circuit (e.g., 826 in FIG. 8B ) is internal to each voltage regulator 402 and balances the respective rail current I provided by each voltage regulator 402. Rportion of the respective rail current I R Use it as negative feedback to control the part.

[0084]

[0100] 7B , in some embodiments, one or more voltage regulators 402 are disabled in a subset of voltage regulators 402 and operate in a standby / redundant mode, e.g., under control of operation enable signal 612, while the remainder of the subset of voltage regulators 402 operate in a standby / redundant mode, while the remainder of the subset of voltage regulators 402 operate in a standby / redundant mode, e.g., under control of operation enable signal 612, and the instantaneous rail current I of the corresponding power rail is R The one or more voltage regulators 402 may have a second number of voltage regulators 402, the second number being capable of collectively providing an instantaneous rail current I R and the maximum regulator current I RGM or equivalently, the instantaneous rail current I R and maximum rail current I RLM For example, the subset of voltage regulators 402 has eight voltage regulators, and the second number is equal to a value between 1 and 8. The instantaneous rail current I R is the first range, e.g.,

[0085]

number

[0086] If the voltage is within the range of 10 V, the first voltage regulator 402A reduces the instantaneous rail current I R The instantaneous rail current I R increases at each time,

[0087]

number

[0088] ,

[0089]

number

[0090] ,

[0091]

number

[0092] ,

[0093]

number

[0094] ,

[0095]

number

[0096] ,

[0097]

number

[0098] , and

[0099]

number

[0100] exceeding the instantaneous rail current I R Within a corresponding range of rail currents, the second number of voltage regulators 402 are enabled (e.g., enabled progressively or continuously). Further, in some embodiments, while the second number of voltage regulators 402 are operating in standby / redundancy mode, the remainder of the subset of voltage regulators 402 are enabled to provide substantially equal instantaneous rail currents I R, for example, each enabled voltage regulator 402 contributes a respective portion of the instantaneous rail current I that varies by less than 5% (or 10%, 20%, or other predefined margin) between voltage regulators 402 associated with the same power rail 206. R Provided to.

[0101] In some circumstances, when one or more voltage regulators 402 operate in standby / redundant mode, the instantaneous rail current I R The rail voltage V R is the maximum rail current I RLM The rail voltage V R The second rail voltage error differs from the rail drift tolerance V RT The rail current I R When is provided with at least one redundant regulator (FIG. 7B) or without a redundant regulator (FIG. 7A), the second rail voltage error is smaller than the first rail voltage error, and the involvement of redundant regulator 402 allows for more complex regulator control to be used to obtain a more accurate rail voltage V R is provided.

[0102] In some embodiments, each voltage regulator 402 in the field programmable array 400 is 100 V. FIG. 8A is a block diagram of a voltage regulator 402, which is one of the voltage regulators in the field programmable array 400, according to some embodiments. In the field programmable array 400, the power rails 206 are connected to the corresponding rail voltage V R , and a plurality of voltage regulators 402 configured to collectively provide a rail voltage V. Each voltage regulator 402 includes an output interface 802, one or more drive paths 804, and a voltage regulator controller 806. The output interface 802 provides a rail voltage V ROne or more drive paths 804 are coupled in parallel between the voltage regulator controller 806 and the output interface 802, with each drive path 804 providing a respective path current I to the power rail 206. P Each of the phases is configured to operate at an operating frequency to provide a respective path current I P is the rail current I induced in the power rail 206 R The voltage regulator controller 806 is configured to receive the control value 610 and the operation enable signal 612 from the power array controller 602 and generate a path control signal 808 to control one or more drive paths 804.

[0103]

[0103] Voltage regulator 402 includes a feedback path 822 coupling output interface 802 to voltage regulator controller 806. That said, voltage regulator controller 806 has a feedback input 840 configured to receive the output voltage of output interface 802. Voltage regulator controller 806 dynamically adjusts path control signal 808 based on the output voltage of output interface 802 to regulate rail voltage V as defined by control value 610. R In particular, in some embodiments, the path control signal 808 is configured to generate a rail voltage V defined by the control value 610. R 8. The output voltage of the output interface 802 is compared to the duty cycle of the voltage regulator controller 806 .

[0104]

[0104] The voltage regulator 402 includes a buck converter, i.e., a DC-DC switch-mode converter, that operates based on an embedded switch. Each drive path 804 includes a switching component 810 and a pulse width modulation (PWM) driver 812. The PWM driver 812 is coupled between the voltage regulator controller 806 and the switching component 810. The PWM driver 812 receives a clock signal 814 (e.g., multi-phase clock 518) and a path control signal 808 to control the switching component 810. In particular, the path control signal 808 defines a duty cycle, and the clock signal 814 has a frequency equal to the operating frequency of one or more drive paths 804. The PWM driver 812 is configured to modify the clock signal 814 with the path control signal 808 to generate a switching signal 816. The switching component 810 is controlled by the switching signal 816 to be turned on and off according to the duty cycle at the operating frequency. The switching component 810 is also coupled to the DC power supply interface 616 and provides a corresponding DC supply voltage V IN , which is thereby output at the switched output 818 of the switching component 810 at the operating frequency according to the duty cycle. The switched output 818 of the switching component 810 is connected to the rail voltage V R The rail voltage is further conditioned (e.g., filtered) by a passive load component 820 (e.g., a series inductor) to generate the rail voltage V. The rail voltage is output to the power rail 206 via the output interface 802. In some implementations, the rail voltage V R is substantially constant (e.g., has an output ripple voltage that is less than the ripple tolerance) and the DC supply voltage V IN and has an average magnitude equal to the product of the duty cycle and the conversion efficiency of the switching component 810.

[0105] 8B is a block diagram of a voltage regulator 402 using current balancing and / or redundancy control, according to some embodiments. In some embodiments, the voltage regulator 402 further includes one or more of an intra-regulator balancing circuit 824, an inter-regulator balancing circuit 826, and a bypass unit 828. The intra-regulator balancing circuit 824, the inter-regulator balancing circuit 826, and the bypass unit 828 are internal to the voltage regulator 402. In some embodiments, each individual voltage regulator 402 can independently disable current outputs, balance currents internally, and / or control the rail current I R , can be balanced with other voltage regulators driving the same power rail 206. In particular, in some embodiments, when voltage regulator 402 includes multiple drive paths 804, in-regulator balancing circuit 824 is coupled between the passive load components 820 of drive paths 804 and at least one of the PWM drivers 812 of drive paths 804. In-regulator balancing circuit 824 is configured to monitor drive paths 804 (e.g., monitor current passing through switching components 810 and passive load components 820), adjust the duty cycle of at least one of drive paths 804, and control at least one of PWM drivers 812 to dynamically balance the path currents of each of drive paths 804.

[0106] In some embodiments, voltage regulator 402 includes one or more drive paths 804, and an inter-regulator balancing circuit 826 is coupled from the passive load components 820 and the output interface 802 to the voltage regulator controller 806. For each voltage regulator 402, the inter-regulator balancing circuit 826 may, for example, balance the respective rail current I provided by the respective voltage regulator itself. R , the respective rail current I provided by each voltage regulator 402 based on a portion of R , a portion of each rail current I provided by a distinct voltage regulator 402 in the subset of voltage regulators 402 selected to power the same power rail 206. RIn particular, in some embodiments, the inter-regulator balancing circuit 826 is configured to balance at least another portion of the respective rail current I R and monitors a portion of each rail current I R For each voltage regulator 402, the respective rail current I passing through the switching component 810 and the passive load component 820 is configured to control the path control signal 808 based on a portion of the voltage regulator 402. R is monitored by inter-regulator balancing circuit 826. In some situations, when the fraction of each rail current provided by each voltage regulator is relatively large, control path control signal 808 may adjust the fraction of each rail current I R If the fraction of each rail current provided by each voltage regulator is relatively small, the control path control signal 808 reduces the duty cycle of the drive path 804 (of its respective voltage regulator) to suppress the fraction of each rail current I R To boost a portion of the output, the duty cycle of drive path 804 is increased.

[0107] Conversely, in some embodiments now shown, inter-regulator balancing circuit 826 of first voltage regulator 402 is also coupled to passive load components 820 and output interface 802 of a second voltage regulator 402 that is separate from first voltage regulator 402 and feeds the same power rail 206 together with first voltage regulator 402. Inter-regulator balancing circuit 826 balances the rail current I provided by the first and second voltage regulators. R According to a comparison of the portions, the respective rail currents I provided by the first voltage regulator 402 are R , and the respective rail current I provided by the second voltage regulator 402. R The ion exchanger is configured to balance the ion exchanger with the ion exchanger.

[0108]

[0108] The bypass unit 828 prevents the voltage regulator 402 from reducing the rail current I R6 ) is applied to drive a power rail 206 or when no voltage regulator 402 (e.g., 402RA-402RD in FIG. 6 ) is applied to drive any of the power rails 206. Bypass unit 828 is coupled to one or more drive paths 804 and to voltage regulator controller 806 and configured to provide a dummy load component (e.g., including a passive RC filter) in place of a load coupled to a power rail 206. In the standby / redundant mode, bypass unit 828 bypasses feedback path 822 from output interface 802 to the input of voltage regulator controller 806, thereby preventing each voltage regulator 402 from contributing to the respective rail current I R 8B , switch 830A is turned off and inserted in feedback path 822, and switch 830B is turned off and inserted in the interconnect carrying switching signal 816 in each drive path 804. In some implementations, switches 830A and 830B each include a multiplexer () and are controlled by an operation enable signal 612 received by voltage regulator 402. Bypass unit 828 is coupled between switch 830A and switch 830B of each drive path 804 and configured to intercept the switching signal 816 and isolate power rail 206 and feedback path 822 from voltage regulator controller 806. Thus, bypass unit 828 allows auxiliary path 832 to bypass feedback path 822 in standby / redundancy mode. An example implementation of bypass unit 828 is shown in FIG. 13 , described below.

[0109] 9 is a circuit diagram of a voltage regulator 402 having multiple drive paths 804, according to some embodiments. A voltage regulator controller 806 is coupled to each of the drive paths 804A-804N and provides a path control signal 808 thereto. A feedback path 822 connects the output interface 802 of the drive paths 804A-804N to a feedback input 840 of the voltage regulator controller 806. In some embodiments, the voltage regulator controller 806 includes a digital-to-analog converter (DAC) 902, an error amplifier 904, and an amplifier feedback circuit, and is configured to enable pulse width modulation for the drive paths 804A-804N. A control value 610 is applied by the DAC 902 to generate a reference voltage 906 received at the input of the error amplifier 904. The amplifier feedback circuit and feedback path 822 adjust the rail voltage V output at the output interface 802 to match the reference voltage 906. R In particular, the path control signal 808 dynamically controls the rail voltage V R and a reference voltage 906. In some situations, the power array controller 602 also controls the duty cycles of the drive paths 804A-804N to match the respective rail voltages V R and the respective rail currents I R and provides an operation enable signal 612 to each voltage regulator 402 to enable it to generate the error amplifier 904 and the DAC 902. The operation enable signal 612 is applied to control (e.g., enable and disable) the error amplifier 904 and / or the DAC 902, as the case may be.

[0110] Each of the drive paths 804A-804N further includes a passive load component 820 coupled to the output interface 802, a PWM driver 812, and a switching component 810. The PWM driver 812 is configured to receive a clock signal 814 having an operating frequency and to modulate the clock signal 814 to provide a phase to a switching signal 816. The power switching component 810 is coupled between the PWM driver 812 and the passive load component 820 and is configured to couple the passive load component 820 to one or more DC supply voltages V under the control of the switching signal 816. IN In some embodiments, the switching components 810 are configured to couple the passive load components 820 to the DC supply voltage V IN and ground.

[0111] 10A is a circuit diagram of a voltage regulator 402 having two drive paths 804A and 804B balanced by an in-regulator balancing circuit 824, according to some embodiments. The voltage regulator 402 is electrically coupled to the power rail 206 and supplies the power rail 206 with a rail voltage V R The voltage regulator 402 is one of a plurality of voltage regulators 402 configured to collectively provide a first path current I to the power rail 206. The voltage regulator 402 is coupled to the output interface 802 and provides a first path current I to the power rail 206. P1 The second drive path 804 is coupled to the output interface 802 and provides a second path current I to the power rail 206. P2The second drive path 804B is configured to operate at an operating frequency during the second phase to provide a second drive path 804B. The second drive path 804B is electrically coupled in parallel with the first drive path 804A. In some situations, the first phase and the second phase are equivalent and have the same duty cycle. In some situations, the first phase and the second phase are distinct from one another. The first duty cycle of the first phase is equal to but offset from the second duty cycle of the second phase. The first duty cycle of the first phase partially overlaps with or is fully offset from the second duty cycle of the second phase.

[0112]

[0112] The regulator balancing circuit 824 is coupled to the first and second drive paths 804A and 804B and controls the first and second path currents I P1 and I P2 and detects the first and second path currents I P1 and I P2 For example, the regulator balancing circuit 824 may be configured to generate a control signal 1002 for controlling a first duty cycle of the first phase, a second duty cycle of the second phase, or both, based on a difference between the first path current I P1 is the second path current I P2 If it is determined that the first path current I P1 or controlling the PWM driver 812A of the first drive path 804A to decrease the first duty cycle to reduce the second path current I P2 In some embodiments, the in-regulator balancing circuit 824 balances the path current I between the two drive paths 804A and 804B. P1 and I P2 In some embodiments, the in-regulator balancing circuit 824 periodically or in response to a command received from the SoC 102, balances the path current I between the two drive paths 804A and 804B. P1 and IP2 is allowed to balance.

[0113] In some embodiments, the regulator balancing circuit 824 balances the first and second path currents I P1 and I P2 The voltage regulator 402 determines that the difference between the first and second path currents I does not satisfy the path current balance criterion. In one example, the path current balance criterion requires that the absolute value of the difference does not exceed a current threshold (e.g., 0.1 mA) or a percentage threshold (e.g., 5%). In accordance with the determination that the difference between the first and second path currents does not satisfy the path current balance criterion and the determination that the first path current is greater than the second path current, the voltage regulator 402 implements one or both of reducing the first duty cycle of the first phase and increasing the second duty cycle of the second phase until the difference between the first and second path currents I satisfies the path current balance criterion. Alternatively, under some circumstances, the path current balance criterion may require that the absolute value of the difference does not exceed a current threshold (e.g., 0.1 mA) or a percentage threshold (e.g., 5%). P1 and I P2 are equal (i.e., their difference is 0), and the voltage regulator 402 regulates the path current I P1 and I P2 Whenever θ and θ are not equal, the first phase of drive path 804A and / or the second phase of drive path 804B are adjusted.

[0114] First and second path currents I P1 and I P2 The difference in the first and second drive paths 804A and 804B is caused by a variety of factors, including mismatches in the PWM drivers 812, switching components 810, or passive load components 820 of the corresponding drive paths 804. The in-regulator balancing circuit 824 enables an internal analog current balancing loop within each voltage regulator 402 to correct for mismatches in the first and second drive paths 804A and 804B without requiring digital signal processing or summing incoming and outgoing signals. In one example, the analog current balancing loop enabled by the in-regulator balancing circuit 824 includes an overall loop.

[0115] 10B is a circuit diagram of a voltage regulator 402 having three or more (e.g., three) drive paths 804 balanced by an in-regulator balancing circuit 824, according to some embodiments. Like drive paths 804A and 804B, at least a third drive path 804C is coupled to the output interface 802 and provides a third path current I to the power rail 206 along with the first drive path 804A and the second drive path 804B. P3 The third drive path 804C is configured to operate at the operating frequency of the drive paths 804A and 804B during the third phase to provide a third drive path 804C electrically coupled in parallel with the first and second drive paths 804A and 804B. In some embodiments, the control signal 1002 controls the first and second path currents I P1 and I P2 The internal regulator balancing circuit 824 is coupled to the third drive path 804C and includes a first control signal 1002A generated to control a second duty cycle of the second phase based on the difference between the first and second drive paths. P3 and detects the first and third path currents I P1 and I P3 and generating a second control signal 1002B for controlling the third duty cycle of the third phase based on the difference between the first and second path currents I. P1 is used as a reference, and each of the other drive paths 804 calculates its path current relative to the first path current I P1 is adjusted to match the

[0116] Alternatively, in some embodiments, the internal regulator balancing circuit 824 is coupled to the third drive path 804C, and the third path current I P3 and detects the first and second path currents I P1 and I P2 and the first and third path currents I P2 and I P3 and generating a control signal 1002 for controlling a first duty cycle of the first phase based on the difference between the first path current I P1 is the path current I P1~I P3 To reduce the variation between the second and third path currents I P2 and I P3 In some situations, the smallest difference corresponding to the first pair of drive paths 804 is identified among the differences between any pair of drive paths 804A-C, and the duty cycles of the remaining drive paths 804A-C are adjusted to a value between the duty cycles of the drive paths in the first pair. Thus, the path current I P1 , I P2 and I P3 To improve the balance between the duty cycles of only one of the three drive paths 804A-804C is adjusted.

[0117] FIG. 10C is a circuit diagram of a voltage regulator 402 that balances drive paths 804 using differential amplifiers 1006, according to some embodiments. The regulator balancing circuit 824 includes one or more differential amplifiers 1006. Each differential amplifier 1006 is coupled to two of the drive paths 804. In particular, the switch outputs 818A and 818B of drive paths 804A and 804B are filtered by low-pass filters 1008A and 1008B coupled to the differential inputs of the amplifiers 1006 to remove high-frequency noise in the switch outputs 818A and 818B. The differential amplifiers 1006 generate a control signal 1002 for controlling a first duty cycle of a first phase, a second duty cycle of a second phase, or both, based on the switch outputs 818A and 818B. The control signal 1002 is, as the case may be, a single-ended or differential signal. Thus, when activated, the differential amplifiers 1006 control the path current I P1 and I P2 is not balanced, the first phase of drive path 804A and / or the second phase of drive path 804B can be adjusted.

[0118] FIG. 11A is an equivalent circuit diagram 1100 of a power rail 206 driven by two voltage regulators 402 in a field-programmable array of voltage regulators 400, according to some embodiments. For inter-regulator current balancing, each voltage regulator 402 is simplified and corresponds to a voltage source 1110 according to a voltage source model. The power rails 206 powered by these voltage regulators 402 are configured to power a subset of the SoC 102. For each voltage regulator 402, the output interface 802 is connected to the power rail 206 via a first interconnect 1102 that is physically located within the footprint of the respective voltage regulator 402 and has a resistance Rline1 that potentially includes the parasitic resistance of the first interconnect 1102. In some circumstances, the first interconnects 1102 of the voltage regulators 402 are merged to form the power rail 206 at a regulator joint 1104, e.g., DC connection 308 in FIG. 4B . In some situations, the first interconnections 1102 of three or more voltage regulators 402 are merged to form a power rail 206 at two or more regulator joints 1104. In some cases, two or more regulator joints 1104 are used with additional interconnections connecting these two or more regulator joints 1104. In some cases, the common regulator joint 1104 is determined by adjusting the equivalent resistance of the first interconnections 1102 of the voltage regulators 402 that feed the power rail 206. The power rail 206 is routed from the regulator joint 1104 with a distributed resistance Rline2, which may include the parasitic resistance of the power rail 206. Each voltage regulator 402 has an output impedance R o It has 1106.

[0119] In some embodiments, the mismatch between the two voltage regulators 402 corresponds to an internal error in one or more of the voltage regulators 402, for example, caused by a reference voltage error in the DAC 902 and / or an offset voltage of the error amplifier 904 of the voltage regulator controller 806. The resistance Rline1 of the first interconnect 1102 is negligible. The distributed resistance Rline2 of the power rail 206 does not affect the mismatch between the two voltage regulators 402. In some embodiments, the output current of each voltage regulator 402 is sensed and used to control the offset input of the error amplifier 904, thereby canceling the offset voltage of the error amplifier 904. In some implementations, a modulator 1108 is incorporated in each voltage regulator 402 to compensate for the internal error of the respective voltage regulator 402. For example, the modulator 1108 is implemented as the inter-regulator balancing circuit 826 in FIG. 8B, 12A, or 12B.

[0120] In some embodiments, the modulator 1108 includes a low pass filter (LPF) 1112. Figure 11B is an equivalent circuit diagram 1150 of a single voltage regulator 402 using the LPF 1112 for inter-regulator current balancing, according to some embodiments. The output impedance R of the voltage regulator 402 o The voltage drop at 1106 is proportional to the output current of the voltage regulator 402, i.e., the rail current I contributed by the voltage regulator 402. R , which corresponds to a portion of the voltage drop. The voltage drop is extracted, filtered by LPF 1112 to reduce high frequency noise, and applied to the voltage regulator controller 806 (e.g., error amplifier 904) with a scale factor (e.g., 1). LPF 1112 allows negative feedback to cancel and compensate for internal errors of the voltage regulator 402. This current balancing configuration is implemented internally within the voltage regulator 402 without requiring any input or control from other voltage regulators 402 driving the same power rails 206 or power array controller 602.

[0121] 12A and 12B are circuit diagrams of voltage regulators 402 controlled by an inter-regulator balancing circuit 826, according to some embodiments. The inter-regulator balancing circuit 826 is coupled to the output interface 802 and the voltage regulator controller 806 and is configured to sense the output current of each voltage regulator 402 and apply an offset 1202 to a control input of the voltage regulator controller 806. The offset 1202 is determined based on the sensed output current of the voltage regulator 402. In some embodiments, the voltage regulator controller 806 includes an error amplifier 904 configured to receive the control input and apply the offset 1202 between the feedback input 840 and a control value defining the rail voltage of the power rail 206 powered by the voltage regulator 402.

[0122] 12A , in some embodiments, the inter-regulator balancing circuit 826 is coupled to the output inductor 1204 of the passive load component 820 coupled at the output interface 802. The inter-regulator balancing circuit 826 is configured to sense the output current of the voltage regulator 402 based on the voltage drop across the output inductor 1204. Alternatively, in some embodiments, an output resistor 1206 having a fairly small resistance (e.g., less than a threshold resistance) is coupled in series at the output interface 802. The inter-regulator balancing circuit 826 is coupled to the output interface 802 via the output resistor 1204, and the output current of the voltage regulator 402 is sensed from the voltage drop across the output resistor 1204. Thus, the inter-regulator balancing circuit 826 is configured to sense the output current of the voltage regulator 402 and apply an offset 1202 to the control input received by the voltage regulator controller 806. The offset 1202 is determined directly based on the output current of the voltage regulator 402 , specifically based on the voltage drop across the output inductor 1204 or the output resistor 1206 .

[0123] 12B, in some embodiments, the voltage regulator 402 includes multiple drive paths 804 with path currents that are optionally balanced with each other. In some embodiments, an inter-regulator balancing circuit 826 is coupled to a path inductor 1208 of a passive load component 820 in one of the drive paths 804. The inter-regulator balancing circuit 826 balances the multiple path currents I of the voltage regulator 402 based on the voltage drop across the path inductor 1208. P Alternatively, in some embodiments, a path resistor 1210 having a fairly small resistance (e.g., less than a threshold resistance) is coupled in series in one of the multiple drive paths 804. An inter-regulator balancing circuit 826 is coupled to the path resistor 1210, and the output current of the voltage regulator 402 is sensed and determined indirectly from the voltage drop across the path resistor 1210. That said, the inter-regulator balancing circuit 826 may sense one of the multiple path currents I of the voltage regulator 402. P and applies an offset 1202 to the control input received by the voltage regulator controller 806. The offset 1202 is configured to sense one of the multiple path currents I P , in particular based on the voltage drop across the path inductor 1208 or the path resistance 1210.

[0124] In some embodiments, the inter-regulator balancing circuit 826 includes two LPFs respectively coupled to two ends of one of the output inductor 1204, the output resistor 1206, the path inductor 1208, and the path resistor 1210. The offset 1202 is determined based on the DC and low frequency portions of the output current of the voltage regulator 402.

[0125] In some embodiments, the voltage regulator 402 regulates the path current I P1 and I P2 12B ) and an internal regulator balancing circuit 824 configured to balance the output current of the voltage regulator 402, i.e., the rail current I provided to the power rail 206 associated with the voltage regulator 402.R In some embodiments, voltage regulator 402 includes only one of intra-regulator balancing circuit 824 and inter-regulator balancing circuit 826.

[0126] 13 is a circuit diagram of a voltage regulator 402 of a field programmable array of voltage regulators 400 having an auxiliary loop 1302 to control redundancy, according to some embodiments. As explained above, a voltage regulator 402 may be configured to operate in a manner such that a voltage regulator 402 (e.g., 402RA-402RD) is not enabled to power any power rail 206, or a voltage regulator 402 (e.g., 402H in FIG. 7B) is used to drive a power rail 206 but does not drive the corresponding rail current I of the power rail 206. R 13. In some embodiments, regardless of whether voltage regulator 402 is coupled to any power rail 206, voltage regulator 402 includes an output interface 802, one or more drive paths 804, a voltage regulator controller 806, and a bypass unit 828. Voltage regulator controller 806 has an output coupled to one or more drive paths 804 and a feedback input 840 coupled to output interface 802 by a feedback path 822. Bypass unit 828 is coupled to one or more drive paths 804 and voltage regulator controller 806 and configured to provide a dummy load component 1304. In the standby / redundant mode, when bypass unit 828 is enabled, auxiliary loop 1302 bypasses feedback path 822 from output interface 802 to the input of voltage regulator controller 806 and drives dummy load component 1304 with one or more switching components 1306. Therefore, auxiliary loop 1302 includes bypass unit 828 such that, in standby / redundant mode, voltage regulator 402 reduces the corresponding rail current I of power rail 206. R , is enabled instead of the feedback path 822 to disable it from contributing to the

[0127] In the standby / redundancy mode, the bypass unit 828 is enabled to bypass the switching component 810 and the passive load component 820 of each drive path 804. Each drive path 804 further includes a multiplexer or switch 830B coupled to the PWM driver 812, the switching component 810, and the bypass unit 828. The multiplexer or switch 830B is configured to select the bypass unit 828, deselect the switching component 810, and electrically couple the PWM driver 812 to the bypass unit 828 in the standby / redundancy mode. The voltage regulator 402 further includes a multiplexer or switch 830A coupled between the feedback input 840 of the voltage regulator controller 806 and the output interface 802. The multiplexer or switch 830A is configured to operate simultaneously with the multiplexer or switch 830B of each drive path 804 to select the bypass unit and deselect the output interface 802 for the input of the voltage regulator controller 806. In some embodiments, an operational enable signal 612 is used to simultaneously control multiplexer or switch 830A, multiplexer or switch 830B, and dummy load components 1304 to enable standby / redundant mode. By these means, in standby / redundant mode, the switching components 810 and passive load components 820 of each drive path 804 are disabled, while the voltage regulator controller 806 and PWM driver 812 of each drive path 804 operate with the dummy load components 1304 and switching components 1306.

[0128] In summary, when voltage regulator 402 is in standby / redundant mode, auxiliary loop 1302 is applied to isolate output interface 802 without completely shutting down voltage regulator 402. Voltage regulator controller 806 and PWM driver 812 of drive path 804 are operational, thereby enabling voltage regulator 402 to wake up promptly and maintain a desirable transient response time when it recovers from standby / redundant mode. Moreover, switching component 810 of drive path 804 is isolated and disabled, and dummy load component 1304 and switching component 1306 are designed to consume less power than switching component 810 and load component 820 of drive path 804. This effectively saves power consumption of voltage regulator 402 in standby / redundant mode. Conversely, when auxiliary loop 1302 is not used to enable standby / redundant mode of voltage regulator 402, voltage regulator controller 806 and PWM driver 812 of drive path 804 are disabled to enable standby / redundant mode. Voltage regulator 402 is completely shut down in standby / redundant mode, and the corresponding rail current I of power rail 206 that needs to be powered by voltage regulator 402 is R In order to contribute to the recovery, voltage regulator 402 must be restarted each time it recovers from standby / redundant mode. The restart process is often slow and impairs the transient response time of voltage regulator 402 when it recovers from standby / redundant mode.

[0129]

[0129] The terms used in the description of the various described implementations herein are for the purpose of describing particular implementations only and are not intended to be limiting. As used in the description of the various described implementations and in the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will also be understood that, although terms such as "first," "second," and the like, may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0130]

[0130] The term "if" as used herein is to be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" or "in accordance with a determination that," as the case may be, depending on the context. Similarly, the phrase "if it is determined that" or "if a 'stated condition or event' is detected" is to be interpreted to mean "upon determining" or "in response to determining" or "upon detecting the 'stated condition or event'" or "in response to detecting the 'stated condition or event'" or "in accordance with a determination that a 'stated condition or event' has been detected," as the case may be, depending on the context.

[0131]

[0131] The above description has been provided with respect to specific implementations. However, the above exemplary description is not intended to be exhaustive or to be limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The implementations have been chosen and described to best explain the disclosed principles and their practical applications, thereby enabling others to best utilize the present disclosure and various implementations with various modifications suited to the particular uses contemplated. The inventions described in the claims of the present application as originally filed are set forth below. [C1] a plurality of voltage regulators arranged in a field programmable array; a power array controller coupled to the plurality of voltage regulators, wherein the power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails, each of the plurality of power rails providing a respective rail current at a respective rail voltage, and for each of the power rails in the plurality of power rails, the power array controller: determining the respective rail currents associated with the respective power rails; and selecting a subset of voltage regulators according to at least the respective rail currents; enabling the subset of voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents; An integrated semiconductor device configured to perform the following: [C2] 10. The integrated semiconductor device of claim 1, wherein the power array controller is configured to determine a control value based on at least the respective rail voltages, and to enable the subset of voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents in accordance with the determined control value. [C3] 3. The integrated semiconductor device of claim 2, wherein enabling the subset of voltage regulators includes providing the control values ​​to the subset of voltage regulators, wherein the subset of voltage regulators are controlled by the control values ​​to generate the respective rail voltages and collectively provide the respective rail currents. [C4] 3. The integrated semiconductor device of claim 2, wherein enabling the subset of voltage regulators further comprises providing an operational enable signal to the selected subset of voltage regulators to generate the respective rail voltages and collectively provide the respective rail currents. [C5] 5. The integrated semiconductor device of any of C1 to 4, wherein the power array controller is configured to determine the respective rail currents associated with the respective power rails according to load information corresponding to expected or actual loads on the respective power rail loads. [C6] The integrated semiconductor device of C5, wherein the load information corresponds to processor load information for one or more clusters of processors coupled to the respective power rails. [C7] further comprising one or more direct current (DC) power supply interfaces, each DC power supply interface configured to receive a distinct DC supply voltage, and each voltage regulator coupled to a respective subset of the one or more DC power supply interfaces, powered by a corresponding DC supply voltage, and configured to generate the respective rail voltage from the corresponding DC supply voltage; An integrated semiconductor device according to any one of C1 to C6. [C8] 8. An integrated semiconductor device as described in any of C1 to 7, wherein at each time, at least one of the plurality of voltage regulators is redundant and is not coupled to any of the plurality of power rails. [C9] selecting the subset of voltage regulators for each power rail; uniquely associating each of said subset of voltage regulators with said respective power rail at each time. The integrated semiconductor device according to any one of C1 to C8, further comprising: [C10] For each power rail: The rail current for each of the above is the maximum rail current IRLM and Each of said subset of voltage regulators has a maximum regulator current I RGM configured to provide a regulator current up to The subset of voltage regulators is configured to RLM and the maximum regulator current I RGM and a first number of voltage regulators corresponding to a ratio of An integrated semiconductor device according to any one of C1 to C9. [C11] a first power rail configured to reach the respective rail voltage within a transient load response time at each start-up of the first power rail; The transient load response time is the maximum regulator current I RGM made possible by the first number is determined based on the transient load response time; The integrated semiconductor device according to C10. [C12] a second power rail reaches the respective rail voltage within a transient load response time at each start-up of the second power rail, and the maximum rail current I RLM and the transient load response time is greater than or equal to the maximum rail current I RLM The integrated semiconductor device of claim 10, wherein the integrated semiconductor device is enabled by a transient load current less than or equal to 100 mA. [C13] The power array controller, for each power rail: determining an instantaneous rail current for each of the power rails; enabling all of the subset of voltage regulators to collectively provide the instantaneous rail current for the respective power rail; The integrated semiconductor device according to C10, configured to perform the following: [C14] The power array controller, for each power rail: determining an instantaneous rail current for each of the power rails; The instantaneous rail current and the maximum regulator current I RGM and comparing disabling one or more voltage regulators in the subset of voltage regulators; and enabling the remainder of the subset of voltage regulators to collectively provide the instantaneous rail current for the respective power rail. The integrated semiconductor device according to C10, configured to perform the following: [C15] 15. An integrated semiconductor device according to any one of C1 to C14, wherein the plurality of voltage regulators are identical to one another. [C16] each of the plurality of voltage regulators corresponds to a respective voltage regulator type selected from a plurality of predefined voltage regulator types; for each power rail, the subset of voltage regulators corresponds to a respective voltage regulator type, and selecting the subset of voltage regulators includes determining the respective voltage regulator type based on at least one performance criterion; An integrated semiconductor device according to any one of C1 to 15. [C17] For each power rail, each of the subset of voltage regulators an output interface coupled to the respective power rail and configured to provide the rail voltage and deliver the respective rail current to the respective power rail; one or more drive paths coupled to the output interface and configured to operate at an operating frequency; a voltage regulator controller having an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path, the voltage regulator controller configured to control the one or more drive paths; a bypass unit coupled to the one or more drive paths and the voltage regulator controller, the bypass unit configured to provide a dummy load component, wherein the respective voltage regulators have a standby / redundant mode in which the bypass unit is enabled to bypass the feedback path from the output interface to the input of the voltage regulator controller, thereby disabling the respective voltage regulators from contributing to the respective rail current; 17. The integrated semiconductor device of any one of C1 to C16, further comprising: [C18] for each power rail, each voltage regulator in the subset of voltage regulators is configured to provide a portion of the respective rail current; an output interface electrically coupled to each of the power rails; a plurality of drive paths, each coupled to the output interface and configured to provide a respective path current to the respective power rail; At least one of an intra-regulator balancing circuit and an inter-regulator balancing circuit further comprising wherein the in-regulator balancing circuit is coupled to the plurality of drive paths and configured to balance the respective path currents of the plurality of drive paths; and wherein the inter-regulator balancing circuit is coupled to the output interface and configured to balance the portion of the respective rail current provided by the respective voltage regulator with at least another portion of the respective rail current provided by a separate voltage regulator in the subset of voltage regulators. An integrated semiconductor device according to any one of C1 to 17.

Claims

1. a plurality of voltage regulators arranged in a field programmable array, said plurality of voltage regulators being organized into a plurality of rows and a plurality of columns; a power array controller coupled to the plurality of voltage regulators, wherein the power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails, each of the plurality of power rails having a respective rail voltage (V Ｒ ) at each rail current (I Ｒ ), and for each of the power rails in the plurality of power rails, the power array controller The respective rail current (I) associated with the respective power rail is calculated according to load information corresponding to an expected or actual load on the respective power rail. Ｒ ) and At least the respective rail current (I Ｒ selecting a subset of voltage regulators according to The subset of voltage regulators may be configured to supply the respective rail voltages (V Ｒ ), and the respective rail currents (I Ｒ ) collectively available and An integrated semiconductor device configured to perform the following:

2. The power array controller controls at least the respective rail voltage (V Ｒ ), and the subset of voltage regulators adjusts the respective rail voltages (V Ｒ ), and the respective rail currents (I Ｒ 10. The integrated semiconductor device of claim 1, configured to collectively provide:

3. Enabling the subset of voltage regulators includes providing the control values ​​to the subset of voltage regulators, wherein the subset of voltage regulators control the respective rail voltages (V Ｒ ), and the respective rail currents (I Ｒ 3. The integrated semiconductor device of claim 2, wherein the control values ​​collectively provide:

4. Enabling the subset of voltage regulators comprises: Ｒ ), and the respective rail currents (I Ｒ 4. The integrated semiconductor device of claim 3, further comprising providing an operational enable signal to the selected subset of voltage regulators to collectively provide a 5. The integrated semiconductor device of claim 1, wherein the load information corresponds to processor load information for one or more clusters of processors coupled to the respective power rails.

6. The power supply may further include one or more direct current (DC) power supply interfaces, each DC power supply interface configured to receive a distinct DC supply voltage, and each voltage regulator is coupled to a respective subset of the one or more DC power supply interfaces, powered by a corresponding DC supply voltage, and configured to convert the voltage regulator into a respective rail voltage (V Ｒ ), 6. An integrated semiconductor device according to claim 1.

7. An integrated semiconductor device as described in any of claims 1 to 6, wherein at least one of the plurality of voltage regulators is redundant and is not coupled to any of the plurality of power rails.

8. selecting a subset of the voltage regulators for each power rail; uniquely associating each of the subset of voltage regulators with the respective power rail. The integrated semiconductor device according to claim 1 , further comprising:

9. For each power rail: The respective rail currents (I Ｒ ) is the maximum rail current (I RLM ) Each of the subset of voltage regulators has a maximum regulator current (I RGM ) and configured to provide a regulator current of up to The subset of voltage regulators may be configured to operate at a maximum rail current (I RLM ) and the maximum regulator current (I RGM ) a first number of voltage regulators corresponding to a ratio of 9. An integrated semiconductor device according to claim 1.

10. A first power rail is configured to generate a voltage drop of the respective rail voltage (V) within a transient load response time at each start-up of the first power rail. Ｒ ) The transient load response time is the maximum regulator current (I RGM ) is made possible by the first number is determined based on the transient load response time; 10. The integrated semiconductor device of claim 9.

11. a second power rail is configured to generate a second power rail voltage (V Ｒ ) and the maximum rail current (I RLM )of and the transient load response time is greater than or equal to the maximum rail current (I RLM )twist 10. The integrated semiconductor device of claim 9, wherein the power array controller is configured to: determine, for each power rail, an instantaneous rail current for the respective power rail; and enable all of the subset of voltage regulators to collectively provide the instantaneous rail current for the respective power rail.

12. The power array controller, for each power rail: determining an instantaneous rail current for each of the power rails; The instantaneous rail current and the maximum regulator current (I RGM ) and disabling one or more voltage regulators in the subset of voltage regulators; enabling the remainder of the subset of voltage regulators to collectively provide the instantaneous rail current for the respective power rail; and 10. The integrated semiconductor device of claim 9 configured to:

13. each of the plurality of voltage regulators corresponds to a respective voltage regulator type selected from a plurality of predefined voltage regulator types; for each power rail, the subset of voltage regulators corresponds to a respective voltage regulator type, and selecting the subset of voltage regulators includes determining the respective voltage regulator type based on at least one performance criterion; 13. An integrated semiconductor device according to any one of claims 1 to 12.

14. For each power rail, each of the subset of voltage regulators coupled to the respective power rails, and Ｒ ), and providing the respective rail currents (I Ｒ ) to the respective power rail; and one or more drive paths coupled to the output interface and configured to operate at an operating frequency; a voltage regulator controller having an output coupled to the one or more drive paths and an input coupled to the output interface by a feedback path, the voltage regulator controller configured to control the one or more drive paths; a bypass unit coupled to the one or more drive paths and the voltage regulator controller, the bypass unit configured to provide a dummy load component, wherein the respective voltage regulator is configured to: bypass the feedback path from the output interface to the input of the voltage regulator controller, thereby allowing the respective voltage regulator to reduce the respective rail current (I Ｒ ) a standby / redundant mode that allows the user to disable the contribution of the 14. The integrated semiconductor device according to claim 1, further comprising:

15. For each power rail, each voltage regulator in the subset of voltage regulators controls the respective rail current (I Ｒ ) configured to provide a portion of an output interface electrically coupled to each of the power rails; a plurality of drive paths, each coupled to the output interface and configured to provide a respective path current to the respective power rail; At least one of an intra-regulator balancing circuit and an inter-regulator balancing circuit further comprising wherein the in-regulator balancing circuit is coupled to the plurality of drive paths and configured to balance the respective path currents of the plurality of drive paths; and wherein the inter-regulator balancing circuit is coupled to the output interface and adjusts the respective rail currents (I Ｒ ) provided by a separate voltage regulator in the subset of voltage regulators, Ｒ ) configured to counterbalance at least another portion of 15. An integrated semiconductor device according to any one of claims 1 to 14.

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