semiconductor memory device

Abstract

A semiconductor memory device including a plurality of semiconductor dies stacked on top of one another, the semiconductor memory device having a novel configuration different from conventional semiconductor memory devices, is provided. [Solution] A semiconductor memory device includes memory dies 1-1 and 1-2 stacked on top of each other. The memory dies 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between the memory dies 1-1 and 1-2. Each of the memory dies 1-1 and 1-2 has a front surface and a back surface facing each other, and a plurality of first terminals arranged on the front surface. In each of the memory dies 1-1 and 1-2, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane perpendicular to the front surface and the back surface. The memory dies 1-1 and 1-2 are stacked so that the front surface of the memory die 1-1 is in contact with the front surface of the memory die 1-2, and the plurality of first terminals of the memory die 1-1 are connected to the plurality of first terminals of the memory die 1-2.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] In recent years, along with the improvement in the performance of GPUs (Graphics Processing Units) and CPUs (Central Processing Units), there has been a significant increase in the demand for semiconductor memory devices with large capacities and high performance. However, in order to satisfy the limitations on the power supply and / or thermal management of the entire system, low power consumption is also required in addition to high performance.

[0003] As a solution to these problems, semiconductor memory devices that stack semiconductor dies three-dimensionally have been proposed. The Joint Electron Device Engineering Council (JEDEC) has also standardized the HBM (High Bandwidth Memory) series, and actual products are being supplied to the market.

[0004] For example, Patent Document 1 discloses a semiconductor memory device including multiple semiconductor dies stacked one above the other. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-166147 Summary of the Invention [Problem to be solved by the invention]

[0006] According to the semiconductor memory device of Patent Document 1, multiple semiconductor dies are stacked by repeatedly connecting the back surface of one semiconductor die to the front surface of another semiconductor die. Hereinafter, in this specification, such connection of semiconductor dies is referred to as "F2B (face to back) connection."

[0007] In order to provide a large-capacity, high-performance, and low-power-consumption three-dimensional memory at a low price, semiconductor memory devices with various configurations, not limited to F2B connections, are required.

[0008] An object of the present disclosure is to provide a semiconductor memory device that includes a plurality of semiconductor dies stacked on top of each other and has a novel configuration that differs from conventional semiconductor memory devices. [Means for solving the problem]

[0009] A semiconductor memory device according to one aspect of the present disclosure includes: 1. A semiconductor memory device including a plurality of semiconductor dies stacked on top of one another, the plurality of semiconductor dies include circuit elements and wiring arranged in the same layout among the plurality of semiconductor dies; Each of the plurality of semiconductor dies has first and second surfaces facing each other and a plurality of first terminals disposed on the first surface; In each of the plurality of semiconductor dies, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first and second surfaces; the plurality of semiconductor dies includes first and second semiconductor dies; The first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the plurality of first terminals of the first semiconductor die are connected to the plurality of first terminals of the second semiconductor die. [Effects of the Invention]

[0010] According to one aspect of the present disclosure, it is possible to provide a semiconductor memory device having a novel configuration that differs from conventional F2B connections. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing the terminal layout of memory dies 1-1 and 1-2 of the semiconductor memory device according to the first embodiment. [Figure 2] 1 is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a first embodiment. [Figure 3] 1 is a plan view showing the terminal layout of memory dies 2-1 and 2-2 of a semiconductor memory device according to a first comparative example. FIG. [Figure 4] 1 is a vertical cross-sectional view showing a configuration of a semiconductor memory device according to a first comparative example. [Figure 5] FIG. 10 is a plan view showing the terminal layout of memory dies 3-1 and 3-2 of a semiconductor memory device according to a second comparative example. [Figure 6] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a second comparative example. [Figure 7] FIG. 4 is a vertical cross-sectional view showing another configuration of the semiconductor memory device according to the first embodiment. [Figure 8] FIG. 10 is a plan view showing the terminal layout of memory dies 4-1 to 4-4 of a semiconductor memory device according to a second embodiment. [Figure 9] FIG. 9 is a vertical cross-sectional view showing the wiring layout of the memory die 4-1 of FIG. 8. [Figure 10] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a second embodiment. [Figure 11] FIG. 1 is a diagram illustrating a multi-drop connection of semiconductor memory devices. [Figure 12] FIG. 1 is a diagram showing a spiral connection of a semiconductor memory device. [Figure 13] 11A to 11C are diagrams illustrating a manufacturing process of the semiconductor memory device of FIG. [Figure 14] 10A to 10C are diagrams illustrating a manufacturing process of a semiconductor memory device according to a third comparative example. [Figure 15]FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a third comparative example. [Figure 16] FIG. 10 is a plan view showing the terminal layout of memory dies 7-1 to 7-4 of a semiconductor memory device according to a modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, semiconductor memory devices according to embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same reference numerals denote similar components.

[0013] [First embodiment] Fig. 1 is a plan view showing the terminal layout of memory dies 1-1 and 1-2 of a semiconductor memory device according to the first embodiment. Fig. 2 is a vertical cross-sectional view showing the configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device of Figs. 1 and 2 includes memory dies 1-1 and 1-2 stacked on top of each other.

[0014] 1 and 2, Xa, Ya, and Za indicate the local coordinate system of the memory die 1-1, and Xb, Yb, and Zb indicate the local coordinate system of the memory die 1-2. X, (Y,)Z indicate the global coordinate system of the semiconductor memory device. Local and global coordinate systems are similarly referenced in other figures.

[0015] The memory dies 1-1 and 1-2 are examples of semiconductor dies that include memory circuit elements formed on a semiconductor substrate. The memory dies 1-1 and 1-2 generally have the same structure as each other. At least, the memory dies 1-1 and 1-2 include circuit elements and wiring that are arranged in the same layout between the memory dies 1-1 and 1-2.

[0016] 1, the memory die 1-1 has a front surface 10a-1 and a back surface 10b-1 facing each other of a semiconductor substrate. The memory die 1-1 further has terminals 21-1 to 28-1 arranged on the front surface 10a-1 and terminals 31-1 to 38-1 arranged on the back surface 10b-1. The terminals 21-1 to 28-1 are arranged in mirror symmetry with respect to a plane of symmetry perpendicular to the front surface 10a-1 and the back surface 10b-1. Similarly, the terminals 31-1 to 38-1 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0017] Similarly, the memory die 1-2 has a front surface 10a-2 and a back surface 10b-2 facing each other of the semiconductor substrate. The memory die 1-2 has terminals 21-2 to 28-2 arranged on the front surface 10a-2 and terminals 31-2 to 38-2 arranged on the back surface 10b-2. The terminals 21-2 to 28-2 are arranged in mirror symmetry with respect to a plane of symmetry that is perpendicular to the front surface 10a-2 and the back surface 10b-2. Similarly, the terminals 31-2 to 38-2 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0018] In this specification, the front surface of a semiconductor substrate is also referred to as the “first surface,” and the back surface is also referred to as the “second surface.” Furthermore, in this specification, a terminal arranged on the front surface of a semiconductor substrate is also referred to as the “first terminal,” and a terminal arranged on the back surface of a semiconductor substrate is also referred to as the “second terminal.”

[0019] The memory die 1-1 includes circuit elements 11-1 to 14-1 formed in an internal layer of a semiconductor substrate. The circuit elements 11-1 to 14-1 are associated with predetermined functions of the semiconductor memory device and include, for example, memory elements, input / output circuits, address (e.g., row address) decoders, command decoders, power supplies, etc. The circuit element 11-1 is connected to terminals 21-1, 22-1, 31-1, and 32-1. The circuit element 12-1 is connected to terminals 23-1, 24-1, 33-1, and 34-1. The circuit element 13-1 is connected to terminals 25-1, 26-1, 35-1, and 36-1. The circuit element 14-1 is connected to terminals 27-1, 28-1, 37-1, and 38-1.

[0020] Similarly, memory die 1-2 includes circuit elements 11-2 to 14-2 formed in an inner layer of the semiconductor substrate. Circuit elements 11-2 to 14-2 are associated with predetermined functions of the semiconductor memory device. Circuit element 11-2 is connected to terminals 21-2, 22-2, 31-2, and 32-2. Circuit element 12-2 is connected to terminals 23-2, 24-2, 33-2, and 34-2. Circuit element 13-2 is connected to terminals 25-2, 26-2, 35-2, and 36-2. Circuit element 14-2 is connected to terminals 27-2, 28-2, 37-2, and 38-2.

[0021] As shown in FIG. 2, the memory dies 1-1 and 1-2 are stacked such that the surface 10a-2 of the memory die 1-2 is in contact with the surface 10a-1 of the memory die 1-1. As a result, the terminals 21-2 to 28-2 of the memory die 1-2 are connected to the terminals 21-1 to 28-1 of the memory die 1-1. Hereinafter, this type of connection between the memory dies is referred to as a "face-to-face (F2F) connection." When the memory dies 1-1 and 1-2 are stacked in this manner, each pair of terminals designated by the same reference symbols A to H in FIG. 1 is connected to each other. The terminal 21-1 of the memory die 1-1 is connected to the terminal 24-2 of the memory die 1-2 (reference symbol A), the terminal 22-1 of the memory die 1-1 is connected to the terminal 23-2 of the memory die 1-2 (reference symbol B), and so on. The terminal 28-1 of the memory die 1-1 is connected to the terminal 25-2 of the memory die 1-2 (reference symbol H).

[0022] In FIG. 1 and other figures, thick dashed lines indicate that two memory dies are stacked so that their front or back surfaces contact each other.

[0023] The memory die 1-1 includes wiring formed in an internal layer of the semiconductor substrate 10-1, the wiring layer 41-1, the wiring via 42-1, and the TSV (through silicon via) 43-1. The terminal 21-1 is connected to the circuit element 11-1 of the memory die 1-1 via the wiring layer 41-1, the wiring via 42-1, and the TSV 43-1. Similarly, the memory die 1-2 includes wiring formed in an internal layer of the semiconductor substrate 10-2, the wiring layer 41-2, the wiring via 42-2, and the TSV 43-2. ​​The terminal 24-2 is connected to the circuit element 12-2 of the memory die 1-2 via the wiring layer 41-2, the wiring via 42-2, and the TSV 43-2. ​​By connecting the terminals 21-1 and 24-2 to each other, the wiring and the circuit elements of the different memory dies 1-1 and 1-2 are connected to each other. For simplicity of illustration, FIG. 2 shows only the portions related to terminals 21-1 and 24-2, but the remaining terminals are similarly connected to the wiring and circuit elements of memory dies 1-1 and 1-2.

[0024] 1, among the terminals 21-1 to 28-1 of the memory die 1-1, each pair of terminals arranged in mirror symmetry with respect to the symmetry plane is connected to wiring associated with the same function. Similarly, among the terminals 21-2 to 28-2 of the memory die 1-2, each pair of terminals arranged in mirror symmetry with respect to the symmetry plane is connected to wiring associated with the same function. Here, the wiring includes data signal lines, address signal lines, command signal lines, power supply lines, etc.

[0025] For example, assume that circuit elements 11-1 to 14-1 of memory die 1-1 and circuit elements 11-2 to 14-2 of memory die 1-2 form a memory array. In this case, terminals 21-1 and 22-1 of memory die 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 11-1, respectively. Terminals 23-1 and 24-1 of memory die 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 12-1, respectively. Terminals 25-1 and 26-1 of memory die 1-1 are connected to the address signal line RA0 and data signal line DQ0 of circuit element 13-1, respectively. Terminals 27-1 and 28-1 of memory die 1-1 are connected to the data signal line DQ0 and address signal line RA0 of circuit element 14-1, respectively. Similarly, the terminals 21-2 to 28-2 of the memory die 1-2 are also connected to the address signal lines and data signal lines of the circuit elements 11-2 to 14-2.

[0026] When the memory dies 1-1 and 1-2 are stacked using F2F connection, as described above, the terminal 21-1 of the memory die 1-1 is connected to the terminal 24-2 of the memory die 1-2. In this case, both the terminals 21-1 and 24-2 are connected to the address signal line RA0 of the memory array, so that addresses are transmitted normally via the terminals 21-1 and 24-2 and the wiring connected thereto. Similarly, addresses and data are transmitted normally via the other pairs of terminals of the memory dies 1-1 and 1-2 that are connected to each other and the wiring connected thereto.

[0027] In this way, in each of the memory dies 1-1 and 1-2, the terminals connected to the wiring associated with the same function are arranged in mirror symmetry with respect to the symmetry plane. Therefore, each pair of terminals connected to each other on the memory dies 1-1 and 1-2, i.e., each pair of terminals assigned the same reference symbols A to H in FIG. 1, is connected to the wiring associated with the same function.

[0028] Although the terminals of the memory dies 1-1 and 1-2 are arranged in mirror symmetry with respect to the plane of symmetry, other components of the memory dies 1-1 and 1-2, such as circuit elements and wiring, do not necessarily have to be arranged in mirror symmetry.

[0029] The memory dies 1-1 and 1-2 include circuit elements and wiring arranged in the same layout between them. Therefore, the memory dies 1-1 and 1-2 can be manufactured using substantially the same mask set. Here, "substantially the same mask set" refers to the mask set for forming each layer of the memory die being entirely or partially identical. Even if the masks are partially different in entirely or partially in layers unrelated to the features of this embodiment, the masks are included in the "substantially the same mask set."

[0030] Now, a semiconductor memory device according to a comparative example will be described with reference to FIGS.

[0031] Fig. 3 is a plan view showing the terminal layout of memory dies 2-1 and 2-2 of a semiconductor memory device according to a first comparative example. Fig. 4 is a vertical cross-sectional view showing the configuration of the semiconductor memory device according to the first comparative example. The semiconductor memory device of Figs. 3 and 4 includes memory dies 2-1 and 2-2 stacked on top of each other.

[0032] The memory dies 2-1 and 2-2 generally have the same structure as each other.

[0033] Referring to FIG. 3, the memory die 2-1 has a front surface 10a-1 and a back surface 10b-1. The memory die 2-1 also has terminals 21-1 to 24-1 arranged on the front surface 10a-1 and terminals 31-1 to 34-1 arranged on the back surface 10b-1. The memory die 2-1 also has circuit elements 11-1 and 12-1. Similarly, the memory die 2-2 has a front surface 10a-2 and a back surface 10b-2. The memory die 2-2 also has terminals 21-2 to 24-2 arranged on the front surface 10a-2 and terminals 31-2 to 34-2 arranged on the back surface 10b-2. The memory die 2-2 also has circuit elements 11-2 and 12-2.

[0034] 4, the memory dies 2-1 and 2-2 are stacked in an F2B connection such that the back surface 10b-2 of the memory die 2-2 is in contact with the front surface 10a-1 of the memory die 2-1. As a result, the terminals 31-2 to 34-2 of the memory die 2-2 are connected to the terminals 21-1 to 24-1 of the memory die 2-1. When the memory dies 2-1 and 2-2 are stacked in this manner, each pair of terminals designated by the same reference symbols A to D in FIG. 3 is connected to each other.

[0035] According to the semiconductor memory device of FIGS. 3 and 4, by stacking the memory dies 2-1 and 2-2 having the same structure by F2B connection, the corresponding terminals of the memory dies 2-1 and 2-2 can be easily connected.

[0036] Fig. 5 is a plan view showing the terminal layout of memory dies 3-1 and 3-2 of a semiconductor memory device according to a second comparative example. Fig. 6 is a vertical cross-sectional view showing the configuration of the semiconductor memory device according to the second comparative example. The semiconductor memory device of Figs. 5 and 6 includes memory dies 3-1 and 3-2 stacked on top of each other.

[0037] Referring to FIG. 5, the memory die 3-1 has a front surface 10a-1 and a back surface 10b-1. The memory die 3-1 also has terminals 21-1 to 24-1 arranged on the front surface 10a-1 and terminals 31-1 to 34-1 arranged on the back surface 10b-1. The memory die 3-1 also includes circuit elements 11-1 and 12-1. Similarly, the memory die 3-2 has a front surface 10a-2 and a back surface 10b-2. The memory die 3-2 also includes terminals 21-2 to 24-2 arranged on the front surface 10a-2 and terminals 31-2 to 34-2 arranged on the back surface 10b-2. The memory die 3-2 also includes circuit elements 11-2 and 12-2.

[0038] 6, the memory dies 3-1 and 3-2 are stacked using F2F connection so that the surface 10a-2 of the memory die 3-2 is in contact with the surface 10a-1 of the memory die 3-1. As a result, the terminals 21-2 to 24-2 of the memory die 3-2 are connected to the terminals 21-1 to 24-1 of the memory die 3-1. When the memory dies 3-1 and 3-2 are stacked in this manner, each pair of terminals designated by the same reference symbols A to D in FIG. 5 is connected to each other.

[0039] 5 and 6, in order to stack the memory dies 3-1 and 3-2 using F2F connection and connect the corresponding terminals of the memory dies 2-1 and 2-2, the memory dies 3-1 and 3-2 must have terminals arranged in different layouts. Therefore, two mask sets with different parts related to the terminals are required, which increases manufacturing costs.

[0040] 1 and 2, memory dies 1-1 and 1-2 having terminals arranged in mirror symmetry with respect to a plane of symmetry are stacked by F2F connection, thereby providing a semiconductor memory device having a novel configuration different from the conventional F2B connection and the conventional F2F connection. According to the semiconductor memory device of the first embodiment, the memory dies 1-1 and 1-2 can be manufactured using substantially the same mask set, thereby reducing manufacturing costs compared to the semiconductor memory device of FIGS. 5 and 6. Therefore, according to the semiconductor memory device of the first embodiment, a semiconductor memory device with large capacity, high performance, and low power consumption can be provided at a low price.

[0041] Next, other connections of the terminals and wiring of the memory die will be described.

[0042] In each of the memory dies 1-1 and 1-2, each pair of terminals arranged in mirror symmetry with respect to the symmetry plane may not necessarily be connected to wiring associated with the same function, but may be connected to wiring associated with different functions. In this case, in each of the memory dies 1-1 and 1-2, the multiple terminals on the surface 10a-1 include first and second terminal groups, which are arranged in mirror symmetry with respect to the symmetry plane. The first and second terminal groups are connected to multiple wiring associated with the same functional group. Here, a "functional group" refers to, for example, multiple bits of address, command, or data, and "multiple wiring associated with the same functional group" refers to multiple signal lines transmitting multiple bits of address, command, or data.

[0043] 1, the terminals 21-1 to 28-1 of the memory die 1-1 include, for example, first terminal groups 21-1 and 22-1 and second terminal groups 23-1 and 24-1, which are arranged in mirror symmetry with respect to a plane of symmetry. In this case, the first terminal groups 21-1 and 22-1 may be connected to address signal lines RA0 and RA1 of the circuit element 11-1, respectively, and the second terminal groups 23-1 and 24-1 may be connected to address signal lines RA0 and RA1 of the circuit element 12-1, respectively. In other words, the first terminal groups 21-1 and 22-1 and the second terminal groups 23-1 and 24-1 are connected to multiple wirings associated with the same functional group. A pair of terminals 21-1 and 24-1 arranged in mirror symmetry with respect to the symmetry plane are included in the same functional group but are connected to wiring associated with different functions, i.e., address signal lines RA0 and RA1, respectively. Similarly, a pair of terminals 22-1 and 23-1 arranged in mirror symmetry with respect to the symmetry plane are included in the same functional group but are connected to wiring associated with different functions, i.e., address signal lines RA1 and RA0, respectively.

[0044] Similarly, the terminals 21-2 to 28-2 of the memory die 1-2 may also include first and second groups of terminals arranged in mirror symmetry with respect to the plane of symmetry, and connected to multiple wirings associated with the same functional group.

[0045] Each pair of terminals arranged in mirror symmetry with respect to the plane of symmetry is connected to a signal line transmitting a different bit of the address, but the first and second groups of terminals are connected as a whole to a plurality of wires associated with the same plurality of bits of the address, and the address is transmitted normally via the entire first and second groups of terminals and the wires connected thereto.

[0046] However, if the address, command, or data signals do not have a pattern that applies appropriate noise or stress to the memory array when testing the memory array, defects in the memory array may not be detected. In consideration of this, the first and second terminal groups may be selected so as to apply appropriate noise or stress to the memory array when testing the memory array.

[0047] Next, another configuration of the semiconductor memory device according to the first embodiment will be described.

[0048] 7 is a vertical cross-sectional view showing another configuration of the semiconductor memory device according to the first embodiment. The semiconductor memory device in FIG. 7 includes memory dies 1-1 to 1-4 stacked on top of each other.

[0049] The memory dies 1-1 and 1-2 in FIG. 7 are configured similarly to the memory dies 1-1 and 1-2 in FIGS.

[0050] The memory dies 1-3 and 1-4 are configured similarly to the memory dies 1-1 and 1-2 in Figures 1 and 2. The memory dies 1-3 and 1-4 are stacked so that the surface of the memory die 1-4 is in contact with the surface of the memory die 1-3, i.e., F2F connection. As a result, the terminals on the surface of the memory die 1-4 are connected to the terminals on the surface of the memory die 1-3.

[0051] The memory dies 1-2 and 1-3 are stacked so that the back surface of the memory die 1-3 is in contact with the back surface of the memory die 1-2. This connects the terminals on the back surface of the memory die 1-3 to the terminals on the back surface of the memory die 1-2. Hereinafter, in this specification, this type of connection between memory dies is referred to as a "B2B (back to back) connection."

[0052] In each of the memory dies 1-1 to 1-4, among the plurality of terminals arranged on the back surface of the memory die, each pair of terminals arranged in mirror symmetry with respect to the symmetry plane may be connected to wiring associated with the same function. Also, in each of the memory dies 1-1 to 1-4, the plurality of terminals arranged on the back surface of the memory die may include third and fourth terminal groups arranged in mirror symmetry with respect to the symmetry plane, the third and fourth terminal groups being connected to a plurality of wiring associated with the same function group. The third and fourth terminal groups may be selected so as to apply appropriate noise or stress to the memory array when testing the memory array.

[0053] 7, memory dies 1-1 to 1-4 are stacked alternately with F2F connection and B2B connection. Similarly, more than four memory dies may be stacked alternately with F2F connection and B2B connection.

[0054] [Second embodiment] In the second embodiment, a description will be given of an improvement in signal transmission speed by reducing the load on the signal lines connected to the terminals of the memory die.

[0055] FIG. 8 is a plan view showing the terminal layout of memory dies 4-1 to 4-4 of the semiconductor memory device according to the second embodiment.

[0056] The memory dies 4-1 to 4-4 generally have the same structure as one another, and at least include circuit elements and wiring that are arranged in the same layout among the memory dies 4-1 to 4-4.

[0057] The memory die 4-1 has a front surface 10a-1 and a back surface 10b-1. The memory die 4-1 further has terminals 21-1 to 28-1 arranged on the front surface 10a-1 and terminals 31-1 to 38-1 arranged on the back surface 10b-1. The terminals 21-1 to 28-1 are arranged in mirror symmetry with respect to a plane of symmetry that is perpendicular to the front surface 10a-1 and the back surface 10b-1. Similarly, the terminals 31-1 to 38-1 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0058] The memory die 4-2 has a front surface 10a-2 and a back surface 10b-2. The memory die 4-2 has terminals 21-2 to 28-2 arranged on the front surface 10a-2 and terminals 31-2 to 38-2 arranged on the back surface 10b-2. The terminals 21-2 to 28-2 are arranged in mirror symmetry with respect to a plane of symmetry that is perpendicular to the front surface 10a-2 and the back surface 10b-2. Similarly, the terminals 31-2 to 38-2 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0059] The memory die 4-3 has a front surface 10a-3 and a back surface 10b-3. The memory die 4-3 further has terminals 21-3 to 28-3 arranged on the front surface 10a-3 and terminals 31-3 to 38-3 arranged on the back surface 10b-3. The terminals 21-3 to 28-3 are arranged in mirror symmetry with respect to a plane of symmetry perpendicular to the front surface 10a-3 and the back surface 10b-3. Similarly, the terminals 31-3 to 38-3 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0060] The memory die 4-4 has a front surface 10a-4 and a back surface 10b-4. The memory die 4-4 further has terminals 21-4 to 28-4 arranged on the front surface 10a-4 and terminals 31-4 to 38-4 arranged on the back surface 10b-4. The terminals 21-4 to 28-4 are arranged in mirror symmetry with respect to a plane of symmetry perpendicular to the front surface 10a-4 and the back surface 10b-4. Similarly, the terminals 31-4 to 38-4 are also arranged in mirror symmetry with respect to the same plane of symmetry.

[0061] The memory die 4-1 includes circuit elements 11-1 and 12-1 formed in an inner layer of a semiconductor substrate. The circuit element 11-1 is connected to terminals 22-1 and 31-1. The circuit element 12-1 is connected to terminals 28-1 and 37-1.

[0062] The memory die 4-2 includes circuit elements 11-2 and 12-2 formed in an inner layer of a semiconductor substrate. The circuit element 11-2 is connected to terminals 22-2 and 31-2. The circuit element 12-2 is connected to terminals 28-2 and 37-2.

[0063] The memory die 4-3 includes circuit elements 11-3 and 12-3 formed in an inner layer of a semiconductor substrate. The circuit element 11-3 is connected to terminals 22-3 and 31-3. The circuit element 12-3 is connected to terminals 28-3 and 37-3.

[0064] The memory die 4-4 includes circuit elements 11-4 and 12-4 formed in an inner layer of a semiconductor substrate. The circuit element 11-4 is connected to terminals 22-4 and 31-4. The circuit element 12-4 is connected to terminals 28-4 and 37-4.

[0065] 9 is a vertical cross-sectional view showing the wiring layout of the memory die 4-1 of FIG. 8. The memory die 4-1 has wiring formed in an internal layer of the semiconductor substrate 10-1, the wiring layer 41 including wiring vias 42 and TSVs 43. The terminals 21-1 to 28-1 on the front surface 10a-1 are connected to the middle wiring layer 41 via the wiring vias 42. The middle wiring layer 41 is connected to the terminals 31-1 to 38-1 on the back surface 10b-1 via the TSVs 43. The wiring vias 42 and the TSVs 43 are connected to the wiring layer 41 at different positions shifted horizontally.

[0066] The terminals 21-1 to 28-1 on the front surface 10a-1 include first terminal groups 21-1 to 24-1 and second terminal groups 25-1 to 28-1, and the first and second terminal groups are arranged in mirror symmetry with respect to the plane of symmetry. The terminals 31-1 to 38-1 on the back surface 10b-1 include third terminal groups 31-1 to 34-1 and fourth terminal groups 35-1 to 38-1, and the third and fourth terminal groups are arranged in mirror symmetry with respect to the plane of symmetry. The first terminal groups 21-1 to 24-1 and the third terminal groups 31-1 to 34-1 are arranged on the same side (left side in FIG. 9) with respect to the plane of symmetry. The second terminal groups 25-1 to 28-1 and the fourth terminal groups 35-1 to 38-1 are also arranged on the same side (right side in FIG. 9) with respect to the plane of symmetry.

[0067] The first terminal group 21-1 to 24-1 and the third terminal group 31-1 to 34-1 are connected to each other via a first wiring group. Specifically, the terminals 21-1 to 24-1 are connected to terminals 34-1, 31-1, 32-1, and 33-1, respectively. The second terminal group 25-1 to 28-1 and the fourth terminal group 35-1 to 38-1 are connected to each other via a second wiring group. Specifically, the terminals 25-1 to 28-1 are connected to terminals 38-1, 35-1, 36-1, and 37-1, respectively.

[0068] The first and second wiring groups have layouts that are asymmetric with respect to the plane of symmetry. For example, as shown in Figure 9, the second wiring group may have a layout that is a translational shift of the first wiring group, i.e., a layout that is translationally symmetric with respect to the first wiring group.

[0069] As described above, circuit element 11-1 is connected to terminals 22-1 and 31-1, and circuit element 12-1 is connected to terminals 28-1 and 37-1. Therefore, only one wire in the first wiring group, i.e., the wire connecting terminals 22-1 and 31-1, is connected to circuit element 11-1, and the remaining wires in the first wiring group are not connected to any circuit element. Also, only one wire in the second wiring group, i.e., the wire connecting terminals 28-1 and 37-1, is connected to circuit element 12-1, and the remaining wires in the second wiring group are not connected to any circuit element. In memory die 4-1, the wires not connected to either circuit element 11-1 or 11-2 are connected to one of circuit elements 11-2 to 11-4 of other memory dies 4-2 and 4-3, as described below.

[0070] The memory dies 4-2 to 4-4 in FIG. 8 are configured similarly to the memory die 4-1 in FIG.

[0071] Fig. 10 is a vertical cross-sectional view showing the configuration of a semiconductor memory device according to a second embodiment. Fig. 10 shows a simplified version of the wiring in Fig. 9. The semiconductor memory device in Fig. 10 includes memory dies 4-1 to 4-4 stacked alternately with F2F connection and B2B connection, as in Fig. 7. When the memory dies 4-1 to 4-4 are stacked in this manner, terminals denoted by the same reference characters A to H in Fig. 8 are connected to each other directly or via the wiring of each memory dies 4-1 to 4-4.

[0072] 10, only the circuit element 11-1 is connected to the terminals marked with the symbol A and the wiring connecting them, and no other circuit elements are connected to them. Furthermore, only the circuit element 11-2 is connected to the terminals marked with the symbol B and the wiring connecting them, and no other circuit elements are connected to them. Furthermore, only the circuit element 11-3 is connected to the terminals marked with the symbol C and the wiring connecting them, and no other circuit elements are connected to them. Furthermore, only the circuit element 11-4 is connected to the terminals marked with the symbol D and the wiring connecting them, and no other circuit elements are connected to them. In this way, the semiconductor memory device of FIG. 10 connects the circuit elements 11-1 to 11-4 to the wiring of each memory die 4-1 to 4-4 in a spiral manner.

[0073] FIG. 11 is a diagram illustrating a multi-drop connection of a semiconductor memory device. The semiconductor memory device of FIG. 11 includes memory dies 5-1 to 5-4 stacked on top of each other. Symbols A to D indicate signal lines extending across the multiple memory dies 5-1 to 5-4, including terminals of each memory die 5-1 to 5-4 and wiring connecting the terminals to each other. The memory die 5-1 includes four circuit elements 11-1 to 14-1, and the other memory dies 5-2 to 5-3 also include four circuit elements each. These circuit elements are, for example, transmission / reception circuits for signals transmitted via the signal lines. Four circuit elements 11-1 to 11-4 are connected to signal line A, and four circuit elements each are also connected to the other signal lines B to D. FIG. 11 illustrates a "multi-drop connection" in which multiple circuit elements of the multiple memory dies 5-1 to 5-4 are connected to each signal line. For example, when a controller (not shown) of a semiconductor memory device communicates with circuit element 11-1 via signal line A, circuit elements 11-2 to 11-4 connected to the same signal line A become inactive and stop sending and receiving signals. However, even when circuit elements 11-2 to 11-4 are inactive, they still act as loads on circuit element 11-1. Therefore, a multi-drop connection is not suitable for high-speed signal transmission.

[0074] FIG. 12 is a diagram illustrating a spiral connection of a semiconductor memory device. FIG. 12 shows an equivalent configuration of the semiconductor memory device of FIG. 10. As shown in FIG. 12, only circuit element 11-1 is connected to signal line A, and no other circuit elements are connected. Furthermore, only circuit element 11-2 is connected to signal line B, and no other circuit elements are connected. Furthermore, only circuit element 11-3 is connected to signal line C, and no other circuit elements are connected. Furthermore, only circuit element 11-4 is connected to signal line D, and no other circuit elements are connected. FIG. 12 illustrates a "spiral connection" in which the connection points of the signal lines and circuit elements shift as the memory die is moved. Circuit elements 11-1 to 11-4 can operate in parallel or simultaneously. Since no circuit elements that would be an extra load are connected to signal lines A to D, this configuration is suitable for high-speed signal transmission.

[0075] The memory dies 4-1 to 4-4 include circuit elements and wirings arranged in the same layout among the memory dies 4-1 to 4-4, and therefore can be manufactured using substantially the same mask set.

[0076] FIG. 13 is a diagram illustrating a manufacturing process of the semiconductor memory device of FIG. 10. Referring to FIG. 13, it will be described how a spiral connection is realized by alternately stacking memory dies 4-1 to 4-4 with F2F and B2B connections. As described above, the memory dies 4-1 to 4-4 generally have the same structure as one another, and therefore the memory dies 4-1 and 4-2 in FIG. 13 also have the same structure as one another. Since the terminal groups of the memory dies 4-1 and 4-2 are arranged in mirror symmetry with respect to the symmetry plane and the wiring groups of the memory dies 4-1 and 4-2 have layouts that are translationally symmetrical with one another, the memory die 4-2 rotated 180 degrees has substantially the same structure as before the rotation. By alternately stacking the memory dies 4-1 to 4-4 with F2F and B2B connections, the semiconductor memory device of FIG. 10 is obtained, and a spiral connection is realized.

[0077] FIG. 14 is a diagram illustrating a manufacturing process of a semiconductor memory device according to a third comparative example. FIG. 15 is a vertical cross-sectional view illustrating the configuration of the semiconductor memory device according to the third comparative example. The semiconductor memory device of FIGS. 14 and 15 includes memory dies 6-1 to 6-4 stacked on top of each other. Each of the memory dies 6-1 to 6-4 has two sets of wiring groups that are mirror-symmetric with respect to the symmetry plane. In this case, terminals 31-2 to 38-2 on the back surface 10b-2 of the memory die 6-2 (middle row in FIG. 14), which is rotated 180 degrees, are connected to terminals 31-1 to 38-1 on the back surface 10b-2 of the memory die 6-1, respectively, via wiring. As a result, as shown in FIG. 15, it can be seen that a spiral connection cannot be achieved even if the memory dies 6-1 to 6-4 are alternately stacked in the F2F connection and the B2B connection.

[0078] When circuit elements 11-1 to 11-4 are connected to the wiring of each memory die 4-1 to 4-4 in a spiral manner, the wiring included in the first and second wiring groups in each memory die 4-1 to 4-4 may be associated with the same function group. Also, in each memory die 4-1 to 4-4, the wiring included in the first wiring group may be associated with at least two functions, and the wiring included in the second wiring group may be associated with at least two functions.

[0079] For example, referring to FIG. 10, on the surfaces 10a-1 to 10a-4 of each of the memory dies 4-1 to 4-4, odd-numbered terminals (e.g., terminals 21-1 and 23-1) on the left side of the symmetry plane must have the same function as even-numbered terminals (e.g., terminals 26-1 and 28-1) on the right side of the symmetry plane. Similarly, even-numbered terminals (e.g., terminals 22-1 and 24-1) on the left side of the symmetry plane must have the same function as odd-numbered terminals (e.g., terminals 25-1 and 27-1) on the right side of the symmetry plane. In other combinations, terminals for signals of different functions and / or power supplies of different levels may be arranged in mirror symmetry. Assume that terminal 31-1 of memory die 4-1 is connected to an address decoder, and terminal 38-1, located at its mirror image, is connected to an input / output circuit. In this case, terminal 28-2 of memory die 4-2 is connected to a signal line different from that of terminal 31-1, and therefore addresses and data are transmitted normally even though they are not associated with the same function. The terminal 21-3 of the memory die 4-3 has the same coordinates in the XY plane as the terminal 21-1 of the memory die 4-1. Therefore, the terminal 21-3 is connected to an address decoder. Similarly, the terminal 28-4 of the memory die 4-4 is connected to a signal line different from the terminal 31-1, so that addresses and data are transmitted normally even though they are not associated with the same function.

[0080] According to the semiconductor memory device of the second embodiment shown in FIGS. 8 to 10, memory dies 4-1 to 4-4, each having terminals arranged in mirror symmetry with respect to the plane of symmetry, can be alternately stacked using F2F and B2B connections. Furthermore, according to the semiconductor memory device of the second embodiment, by including a group of terminals arranged in mirror symmetry with respect to the plane of symmetry and a group of wirings that are translationally symmetric, the memory dies 4-1 to 4-4 can be alternately stacked using F2F and B2B connections to achieve a spiral connection. This makes it possible to provide a semiconductor memory device with a novel configuration that differs from conventional F2B and F2F connections. According to the semiconductor memory device of the second embodiment, the memory dies 4-1 to 4-4 can be manufactured using substantially the same mask set, thereby reducing manufacturing costs. Therefore, according to the semiconductor memory device of the second embodiment, a semiconductor memory device with large capacity, high performance, and low power consumption can be provided at a low price.

[0081] Here, the spiral connection does not necessarily require the wiring to have a physical spiral shape, as long as the connection points of the signal lines and circuit elements shift logically as the memory die is moved.

[0082] 16 is a plan view showing the terminal layout of memory dies 7-1 to 7-4 of a semiconductor memory device according to a modification of the second embodiment. The memory dies 7-1 to 7-4 generally have the same structure. At least the memory dies 7-1 to 7-4 include circuit elements and wiring arranged in the same layout among the memory dies 7-1 to 7-4. The memory dies 7-1 to 7-4 have terminals arranged in a layout different from that in FIG. 8. As with the semiconductor memory devices of FIGS. 8 to 10, the semiconductor memory device of FIG. 16 can also achieve a spiral connection by alternately stacking the memory dies 7-1 to 7-4 in F2F and B2B connections.

[0083] [Other embodiments] The semiconductor memory device may include more than four memory dies.

[0084] The semiconductor memory device may have a different terminal layout than that described.

[0085] When using F2F connection and / or B2B connection, the layout of the terminals on the front surface of each memory die may be different from the layout of the terminals on the back surface.

[0086] [Summary of the embodiment] A semiconductor memory device according to a first aspect of the present disclosure includes: 1. A semiconductor memory device including a plurality of semiconductor dies stacked on top of one another, the plurality of semiconductor dies include circuit elements and wiring arranged in the same layout among the plurality of semiconductor dies; Each of the plurality of semiconductor dies has first and second surfaces facing each other and a plurality of first terminals disposed on the first surface; In each of the plurality of semiconductor dies, the plurality of first terminals are arranged in mirror symmetry with respect to a symmetry plane orthogonal to the first and second surfaces; the plurality of semiconductor dies includes first and second semiconductor dies; The first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the plurality of first terminals of the first semiconductor die are connected to the plurality of first terminals of the second semiconductor die.

[0087] According to the semiconductor memory device according to the second aspect of the present disclosure, in the semiconductor memory device according to the first aspect, In each of the plurality of semiconductor dies, each pair of first terminals arranged in mirror symmetry with respect to the plane of symmetry is connected to wiring associated with the same function.

[0088] According to the semiconductor memory device according to the third aspect of the present disclosure, in the semiconductor memory device according to the first aspect, In each of the plurality of semiconductor dies, the plurality of first terminals include first and second terminal groups, the first and second terminal groups being arranged in mirror symmetry with respect to the plane of symmetry, and the first and second terminal groups being connected to a plurality of wirings associated with the same functional group.

[0089] According to a semiconductor memory device according to a fourth aspect of the present disclosure, in the semiconductor memory device according to one of the first to third aspects, each of the plurality of semiconductor dies further having a plurality of second terminals disposed on the second surface; In each of the plurality of semiconductor dies, the plurality of second terminals are arranged in mirror symmetry with respect to the plane of symmetry; the plurality of semiconductor dies includes a third and a fourth semiconductor die; the third and fourth semiconductor dies are stacked such that the first surface of the third semiconductor die is in contact with the first surface of the fourth semiconductor die, and the plurality of first terminals of the third semiconductor die are connected to the plurality of first terminals of the fourth semiconductor die; The second and third semiconductor dies are stacked such that the second surface of the second semiconductor die is in contact with the second surface of the third semiconductor die, and the plurality of second terminals of the second semiconductor die are connected to the plurality of second terminals of the third semiconductor die.

[0090] According to the semiconductor memory device according to the fifth aspect of the present disclosure, in the semiconductor memory device according to the fourth aspect, In each of the plurality of semiconductor dies, each pair of second terminals arranged in mirror symmetry with respect to the plane of symmetry is connected to wiring associated with the same function.

[0091] According to the semiconductor memory device according to the sixth aspect of the present disclosure, in the semiconductor memory device according to the fourth aspect, In each of the plurality of semiconductor dies, the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups being arranged in mirror symmetry with respect to the plane of symmetry, and the third and fourth terminal groups being connected to a group of wiring associated with the same functional group.

[0092] According to a seventh aspect of the present disclosure, in the semiconductor memory device according to any one of the fourth to sixth aspects, in each of the plurality of semiconductor dies: the plurality of first terminals include first and second terminal groups, the first and second terminal groups being arranged in mirror symmetry with respect to the plane of symmetry; the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups being arranged in mirror symmetry with respect to the plane of symmetry; the first and third terminal groups are arranged on the same side with respect to the plane of symmetry; the first and third terminal groups are connected to each other via a first wiring group; the second and fourth terminal groups are connected to each other via a second wiring group; The first and second wiring groups have layouts that are asymmetric with respect to the plane of symmetry.

[0093] According to the semiconductor memory device according to the eighth aspect of the present disclosure, in the semiconductor memory device according to the seventh aspect, In each of the plurality of semiconductor dies, the second wiring group is It has a translationally symmetric layout with respect to

[0094] According to a semiconductor memory device according to a ninth aspect of the present disclosure, in the semiconductor memory device according to the seventh or eighth aspect, In each of the plurality of semiconductor dies, Only one wiring in the first wiring group is connected to a circuit element, and the remaining wirings in the first wiring group are not connected to a circuit element; Only one wire in the second wiring group is connected to a circuit element, and the remaining wires in the second wiring group are not connected to a circuit element.

[0095] According to a semiconductor memory device according to a tenth aspect of the present disclosure, in the semiconductor memory device according to one of the seventh to ninth aspects, In each of the plurality of semiconductor dies, the wires included in the first and second wire groups are associated with the same functional group.

[0096] According to a semiconductor memory device according to a tenth aspect of the present disclosure, in the semiconductor memory device according to one of the seventh to ninth aspects, In each of the plurality of semiconductor dies, The wiring included in the first wiring group is associated with at least two functions; The wires included in the second group of wires are associated with the at least two functions. [Industrial Applicability]

[0097] According to one aspect of the present disclosure, a semiconductor memory device having a novel configuration different from conventional F2B connections is provided. [Explanation of symbols]

[0098] 1-1~1-4, 4-1, 4-4, 7-1~7-4 Memory die 10-1~10-4 Semiconductor substrate 10a-1 to 10a-4 Surface of semiconductor substrate 10b-1 to 10b-4 Back surface of semiconductor substrate 11-1 to 11-4 Circuit elements 21-1~28-4 Surface terminals 31-1~38-4 Surface terminals 41,41-1~41-4 Wiring layer 42, 42-1 to 42-4 Wiring via 43,43-1~43-4 TSV(through silicon via)

Claims

1. 1. A semiconductor memory device including a plurality of semiconductor dies stacked on top of one another, the plurality of semiconductor dies include circuit elements and wiring arranged in the same layout among the plurality of semiconductor dies; Each of the plurality of semiconductor dies has first and second surfaces facing each other, a plurality of first terminals disposed on the first surface, and a plurality of second terminals disposed on the second surface; In each of the plurality of semiconductor dies, the plurality of first terminals are arranged in mirror symmetry with respect to a plane of symmetry orthogonal to the first and second faces, and the plurality of second terminals are arranged in mirror symmetry with respect to the plane of symmetry; the plurality of semiconductor dies include first through fourth semiconductor dies; the first and second semiconductor dies are stacked such that the first surface of the first semiconductor die is in contact with the first surface of the second semiconductor die, and the first terminals of the first semiconductor die are connected to the first terminals of the second semiconductor die; the third and fourth semiconductor dies are stacked such that the first surface of the third semiconductor die is in contact with the first surface of the fourth semiconductor die, and the plurality of first terminals of the third semiconductor die are connected to the plurality of first terminals of the fourth semiconductor die; the second and third semiconductor dies are stacked such that the second surface of the second semiconductor die is in contact with the second surface of the third semiconductor die, and the plurality of second terminals of the second semiconductor die are connected to the plurality of second terminals of the third semiconductor die. Semiconductor memory device.

2. In each of the plurality of semiconductor dies, each pair of first terminals arranged in mirror symmetry with respect to the symmetry plane are connected to wiring associated with the same function.

2. The semiconductor memory device according to claim 1.

3. In each of the plurality of semiconductor dies, the plurality of first terminals include first and second terminal groups, the first and second terminal groups being arranged in mirror symmetry with respect to the symmetry plane, and the first and second terminal groups being connected to a plurality of wirings associated with the same functional group.

2. The semiconductor memory device according to claim 1.

4. In each of the plurality of semiconductor dies, each pair of second terminals arranged in mirror symmetry with respect to the symmetry plane are connected to wiring associated with the same function.

2. The semiconductor memory device according to claim 1.

5. In each of the plurality of semiconductor dies, the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups being arranged in mirror symmetry with respect to the symmetry plane, and the third and fourth terminal groups being connected to a group of wirings associated with the same functional group.

2. The semiconductor memory device according to claim 1.

6. In each of the plurality of semiconductor dies, the plurality of first terminals include first and second terminal groups, the first and second terminal groups being arranged in mirror symmetry with respect to the plane of symmetry; the plurality of second terminals include third and fourth terminal groups, the third and fourth terminal groups being arranged in mirror symmetry with respect to the plane of symmetry; the first and third terminal groups are arranged on the same side with respect to the plane of symmetry; the first and third terminal groups are connected to each other via a first wiring group; the second and fourth terminal groups are connected to each other via a second wiring group; the first and second wiring groups have asymmetric layouts with respect to the plane of symmetry; 2. The semiconductor memory device according to claim 1.

7. In each of the plurality of semiconductor dies, the second wiring group has a layout that is translationally symmetric with respect to the first wiring group.

7. The semiconductor memory device according to claim 6.

8. In each of the plurality of semiconductor dies, Only one wiring in the first wiring group is connected to a circuit element, and the remaining wirings in the first wiring group are not connected to a circuit element; Only one wiring in the second wiring group is connected to a circuit element, and the remaining wirings in the second wiring group are not connected to a circuit element.

8. The semiconductor memory device according to claim 7.

9. In each of the plurality of semiconductor dies, the wiring included in the first and second wiring groups are associated with the same functional group.

9. The semiconductor memory device according to claim 8.

10. In each of the plurality of semiconductor dies, The wiring included in the first wiring group is associated with at least two functions; the wiring included in the second wiring group is associated with the at least two functions; 9. The semiconductor memory device according to claim 8.

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