SoC Module

Abstract

To suppress degrading of access efficiency in an SoC module.SOLUTION: An SoC module 1000 includes: arithmetic operation devices 110, 120, and 130; an address region determination unit 200 which determines a write destination logical address and issues an access request; and an address generation unit 330 which generates a data address and an error correction code address by using the write destination logical address, the address generation unit selectively realizing, according to necessary / unnecessary of error correction for write data and data length, either arranging the write data and the error correction code in a physical address space so that they are contained in a minimum access unit of a semiconductor memory device, or arranging the write data and the error correction code in a physical address space so that they are apart from the minimum access unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an SoC module. [Background technology]

[0002] There is a system-on-chip (SoC) module that includes a dynamic random access memory (DRAM) as a semiconductor memory device and a memory controller with an error check and correct (ECC) function, and performs error detection and correction processing on data using an error correction code generated corresponding to the data (Patent Document 1). Planar format and packed format are known as methods for storing data and error correction codes in semiconductor memory devices. In the planar format, the data and error correction code are arranged in different areas. In the packed format, the data and error correction code are arranged so that they fit within the minimum access unit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-139764 Summary of the Invention [Problem to be solved by the invention]

[0004] In the Planar format, data and error correction codes are arranged in different areas. Therefore, when reading data and error correction codes, due to the constraints of the minimum access unit, other unnecessary error correction codes must also be read. This reduces access efficiency when reading data with a small data length. On the other hand, in the Packed format, data and error correction codes are arranged so that they fit within the minimum access unit. Therefore, even for data with a small data length, only the required data and error correction codes can be read. However, even if reading the error correction codes is not necessary, the error correction codes are always read along with the data. This makes it impossible to suppress a decrease in access efficiency even when accessing only data.

[0005] For these reasons, the planar format is generally advantageous when accessing data with a large data length, and the packed format is advantageous when accessing data with a small data length. However, the SoC module described in Patent Document 1 does not offer both of these advantages, and access efficiency may decrease depending on the amount of data to be accessed and whether an error correction code is required. [Means for solving the problem]

[0006] The present disclosure can be realized in the following forms.

[0007] According to one embodiment of the present disclosure, there is provided an SoC module (1000) that reads and writes data from and to a semiconductor memory device (2000) and selectively performs error correction on the data when reading the data, and includes an arithmetic unit (110, 120, 130) that issues write data to the semiconductor memory device, an address area determination unit (200) that receives the write data, determines a destination logical address that is a logical address to which the write data is to be written depending on whether the error correction is required for the write data and the data length, and issues an access request including the write data and the destination logical address, and a physical address of the semiconductor memory device using the destination logical address. an address generation unit (330) that generates a data address in the physical address space to which the write data is written and an error correction code address to which an error correction code used when executing the error correction on the write data is written, and the address generation unit selectively realizes either arranging the write data and the error correction code in the physical address space so that they are both included in a minimum access unit of the semiconductor memory device, or arranging the write data and the error correction code in the physical address space so that they are spaced apart from each other by more than the minimum access unit, depending on whether the error correction of the write data is necessary and the data length of the write data. and an address area determination unit (320) that receives the access request and determines to which area the destination logical address belongs: a first logical address area in a logical address space corresponding to the physical address space, or a second logical address area in the logical address space that is different from the first logical address area. The address generation unit has a first address generation unit (331) and a second address generation unit (332) that use the destination logical address to generate the data address and the error correction code address according to the result of the determination by the address area determination unit. The first logical address area is a continuous area in the logical address space that is preset as an area for storing data that requires the error correction and has a data length that is equal to or less than a predetermined first threshold. The second logical address area is a continuous area in the logical address space that is preset as an area for storing data that requires the error correction and has a data length that is equal to or less than a predetermined second threshold that is equal to or greater than the first threshold, and data that does not require the error correction. the address area determination unit determines which logical address of the first logical address area or the second logical address area to assign to the logical address space as the destination logical address of the write data; the first address generation unit, when it is determined by the address area determination unit that the destination logical address belongs to the first logical address area, uses the destination logical address received from the address area determination unit to generate the data address and the error correction code address so that the write data and the error correction code are both stored in a storage area included in the minimum access unit; and the second address generation unit, when it is determined by the address area determination unit that the destination logical address belongs to the second logical address area, uses the destination logical address received from the address area determination unit to generate the data address and the error correction code address so that the write data and the error correction code are stored in storage areas that are farther apart from each other than the minimum access unit.

[0008] According to this type of SoC module, when writing data to a semiconductor memory device, it is possible to determine whether to allocate the data and error correction code in the physical address space so that they are included within the minimum access unit, or to allocate them so that they are separated from each other by more than the minimum access unit, depending on whether error correction is required for the write data and the data length.As a result, when reading data with a small data length, only the required data and error correction code are read, and when reading data that does not require error correction, only the data is read, thereby preventing a decrease in the access efficiency of the SoC module. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram illustrating a schematic configuration of an SoC module according to an embodiment of the present invention. [Figure 2] FIG. 1 is an explanatory diagram showing the arrangement of data and error correction codes in a packed format. [Figure 3] FIG. 2 is an explanatory diagram showing the arrangement of data and error correction codes in a planar format. [Figure 4] FIG. 2 is an explanatory diagram illustrating a schematic configuration of a physical address space according to the present embodiment. [Figure 5] 10 is a flowchart illustrating a procedure for a data writing process according to the present embodiment. [Figure 6] FIG. 10 is an explanatory diagram showing the procedure of steps S510 to S532 in the data writing process. [Figure 7] 10 is a flowchart illustrating a procedure for a write destination logical address determination process according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] A. Implementation: A1. System Configuration: As shown in Fig. 1, the SoC module 1000 of this embodiment includes arithmetic units 110 to 130, an address area determination unit 200, and a memory controller 300. The SoC module 1000 is connected to a semiconductor memory device 2000 via a bus 600. The semiconductor memory device 2000 is configured to be able to read and write data from and to any storage unit specified by a command issued by the SoC module 1000. The semiconductor memory device 2000 of this embodiment is a DRAM.

[0011] The SoC module 1000 generates a command in response to a data write request or data read request issued by the arithmetic devices 110 to 130, and issues the command to the semiconductor memory device 2000. The SoC module 1000 also has an error correction function, and is configured to be able to detect and correct data errors when reading data from the semiconductor memory device 2000, using an error correction code generated when writing data to the semiconductor memory device 2000. In this embodiment, error correction can be selectively performed depending on whether or not error correction is required, which is set for each piece of data.

[0012] The arithmetic devices 110 to 130 correspond to, for example, a CPU or a GPU (Graphics Processing Unit). The arithmetic devices 110 to 130 issue write data when requesting writing of data to the semiconductor memory device 2000. In this embodiment, the arithmetic devices 110 to 130 issue information indicating whether the write data requires error correction when read (hereinafter also referred to as "error correction necessity information") together with the write data. Note that the number of arithmetic devices included in the SoC module 1000 is not limited to multiple, and may be one.

[0013] The address area determination unit 200 is connected to the arithmetic units 110 to 130 via a bus 400. The address area determination unit 200 receives write data issued by the arithmetic units 110 to 130, and determines to which of the first logical address area and the second logical address area a logical address to which the write data is to be assigned (hereinafter also referred to as "destination logical address AL"), depending on whether error correction is required for the write data and the data length. In this embodiment, the destination logical address AL is a 32-bit bit string expressed in binary. Note that the destination logical address AL is not limited to 32 bits, and may be expressed using any number of bits depending on the type of data to be read or written.

[0014] The first logical address area and the second logical address area are consecutive but different areas in a logical address space corresponding to the physical address space of the semiconductor memory device 2000. In this embodiment, the first logical address area is an area in the logical address space that includes a storage area with a logical address of 0, and the second logical address area is an area in the logical address space excluding the first logical address area. A logical address that indicates the boundary between the first logical address area and the second logical address area and is the starting point of the second logical address area (hereinafter also referred to as a "boundary logical address") is set in advance as a logical address corresponding to a first boundary physical address APb1, which will be described later. How the destination logical address AL is assigned will be described in the destination logical address determination process, which will be described later. The address area determination unit 200 issues an access request that includes at least the write data and the destination logical address AL. In this embodiment, the access request further includes the error correction necessity information described above.

[0015] The memory controller 300 is connected to the address area determination unit 200 via a bus 500. The memory controller 300 receives an access request issued by the address area determination unit 200 and generates a command according to the type of access request. The memory controller 300 issues the generated command to the semiconductor memory device 2000. The memory controller 300 includes an error correction processing unit 310, an address area determination unit 320, an address generation unit 330, and a memory access unit 340.

[0016] When writing data to the semiconductor memory device 2000, the error correction processor 310 generates an error correction code corresponding to the write data included in the access request. In this embodiment, the error correction processor 310 generates an 8-bit error correction code for 64-bit data. The error correction processor 310 issues the generated error correction code and the write data. When reading data from the semiconductor memory device 2000, the error correction processor 310 performs error detection and correction on the read data using the error correction code read together with the read data.

[0017] The address area determination unit 320 determines whether the destination logical address AL in the access request belongs to the first logical address area or the second logical address area. The address area determination unit 320 issues the destination logical address AL and the determination result to the address generation unit 330.

[0018] The address generation unit 330 includes a first address generation unit 331 and a second address generation unit 332. The first address generation unit 331 and the second address generation unit 332 use the destination logical address AL issued by the address area determination unit 320 according to the result of the determination by the address area determination unit 320 to generate an address in the physical address space of the semiconductor memory device 2000 to which the write data is written (hereinafter also referred to as a "data address APd") and an address to which the above-mentioned error correction code is written (hereinafter also referred to as an "error correction code address APe").

[0019] In this embodiment, the data address APd and the error correction code address APe are arranged to conform to either a packed format or a planar format. The packed format refers to an arrangement method in which the write data and the error correction code are both stored in a storage area included in the minimum access unit of the semiconductor memory device 2000. The planar format refers to an arrangement method in which the write data and the error correction code are stored in storage areas that are further apart from each other than the minimum access unit. The minimum access unit is determined by the specifications of the semiconductor memory device 2000. In this embodiment, the minimum access unit of the semiconductor memory device 2000 is 512 bits.

[0020] The access block ABa shown in FIG. 2 is data obtained by dividing the write data and error correction codes arranged in accordance with the packed format into the minimum access units of the semiconductor memory device 2000. The access block ABa consists of seven data blocks DB0 to DB6 and seven error correction codes EC0 to EC6 corresponding to each of the data blocks DB0 to DB6. Data blocks and error correction codes assigned the same number correspond to each other. In this embodiment, each data block consists of eight 8-bit data DTs, and each data DT occupies one physical address. Thus, in the packed format, the write data and error correction codes are arranged so as to be included in the common access block ABa. Note that the hatched physical addresses are unused physical addresses due to the ratio between the data and error correction codes and the minimum access unit, and are not used in this embodiment.

[0021] The access block ABb shown in FIG. 3 is data obtained by dividing the data portion of the write data and error correction codes arranged in accordance with the packed format into the minimum access units of the semiconductor memory device 2000. The access block ABb is made up of eight data blocks DB10 to DB17. The access block ABc is data obtained by dividing the error correction code portion of the write data and error correction codes arranged in accordance with the packed format into the minimum access units of the semiconductor memory device 2000. The access block ABc is made up of 64 error correction codes. In FIG. 3, only the error correction codes EC10 to EC17 corresponding to the data blocks DB10 to DB17 are indicated by symbols. As such, in the planar format, the data and error correction codes are separately arranged in the access block ABb and the access block ABc. In this embodiment, the data blocks and the corresponding error correction codes are arranged so as to be stored in different pages in the semiconductor memory device 2000. Note that the data blocks and the corresponding error correction codes may be arranged so as to be stored in the same page in the semiconductor memory device 2000.

[0022] 4, in this embodiment, the physical address space is divided into a first physical address area and a second physical address area. In this embodiment, the physical address space is divided so that the first physical address area includes a storage area in the physical address space whose physical address is 0. The first physical address area is made up of a plurality of access blocks ABa.

[0023] The second physical address area consists of a data storage area and an error correction code storage area. The data storage area consists of a plurality of access blocks ABb. The error correction code storage area consists of a plurality of access blocks ABc. A first boundary physical address APb1, which is the start point of the second physical address area and is indicated by hatching, is set in advance in the second address generation unit 332 as a variable that can be set arbitrarily. Furthermore, a second boundary physical address APb2, which is the start point of the error correction code storage area and is indicated by cross-hatching, is set in advance in the second address generation unit 332 as a variable that can be set arbitrarily.

[0024] When the address area determination unit 320 determines that the destination logical address AL belongs to the first logical address area, the first address generation unit 331 generates a data address APd and an error correction code address APe using the destination logical address AL issued by the address area determination unit 320 so that the write data and the error correction code are arranged in the first physical address area. A specific method for generating the data address APd and the error correction code address APe will be described in the data write process described later.

[0025] When the address area determination unit 320 determines that the destination logical address AL belongs to the second logical address area, the second address generation unit 332 generates a data address APd and an error correction code address APe using the destination logical address AL issued by the address area determination unit 320 so that the write data and the error correction code are arranged in the second physical address area. A specific method for generating the data address APd and the error correction code address APe will be described in the data write process described later.

[0026] The memory access unit 340 generates a command to be issued to the semiconductor memory device 2000, which command includes the write data and error correction code issued by the error correction processing unit 310, and the data address APd and error correction code address APe issued by the first address generation unit 331 or the second address generation unit 332. More specifically, the memory access unit 340 generates a command to instruct writing data to the data address APd (hereinafter also referred to as a "data write command"), and a command to instruct writing an error correction code to the error correction code address APe (hereinafter also referred to as an "error correction code write command"). The memory access unit 340 issues the generated data write command and error correction code write command to the semiconductor memory device 2000.

[0027] A2.Memory access processing: 5 and 6 when writing data to the semiconductor memory device 2000. Note that the processing when the SoC module 1000 reads data from the semiconductor memory device 2000 is similar to the processing generally performed in an SoC module having an error correction function, and therefore a description thereof will be omitted.

[0028] In step S100 of FIG. 5, one of the arithmetic devices 110 to 130 issues write data and error correction necessity information.

[0029] In step S200, the address area determination unit 200 executes the destination logical address determination process shown in Fig. 7. As described above, the destination logical address determination process is a process for determining to which of the first logical address area and the second logical address area the destination logical address AL should be assigned, depending on whether error correction is required for the write data and the data length.

[0030] 7, the address area determination unit 200 determines whether the write data is data that requires error correction when read. This determination is made according to the error correction necessity information added to the write data. If the write data is data that does not require error correction when read (step S310: No), the address area determination unit 200 assigns the write destination logical address AL to the second logical address area (step S352) and ends the write destination logical address determination process.

[0031] If the write data is data that requires error correction when read (step S310: Yes), the address area determination unit 200 determines whether the data length of the write data is equal to or less than a preset first threshold (step S320). In this embodiment, the first threshold is 1024 bits. Note that the first threshold is not limited to 1024 bits and may be set to any value. If the data length of the write data is equal to or less than the first threshold (step S320: Yes), the address area determination unit 200 assigns the write destination logical address AL to the first logical address area (step S350) and ends the write destination logical address determination process.

[0032] If the data length of the write data is greater than the first threshold (step S320: No), the address area determination unit 200 determines whether the data length of the write data is greater than or equal to a preset second threshold (step S330). In this embodiment, the second threshold is 2048 bits. The second threshold is not limited to 2048 bits, and any value greater than or equal to the first threshold may be set. If the data length of the write data is greater than or equal to the second threshold (step S330: Yes), the address area determination unit 200 assigns the write destination logical address AL to the second logical address area (step S352) and ends the write destination logical address determination process.

[0033] If the data length of the write data is smaller than the second threshold (step S330: No), the address area determination unit 200 determines whether the first logical address area has more free space than the second logical address area (step S340). If the first logical address area has more free space (step S340: Yes), the address area determination unit 200 assigns the write destination logical address AL to the first logical address area (step S350) and ends the write destination logical address determination process. If the second logical address area has more free space (step S340: No), the address area determination unit 200 assigns the write destination logical address AL to the second logical address area (step S352) and ends the write destination logical address determination process. This concludes the description of the write destination logical address determination process.

[0034] 5, the address area determination unit 200 issues an access request to the memory controller 300. As described above, the access request includes write data, a write destination logical address AL, and error correction necessity information.

[0035] In step S400, the error correction processor 310 generates an error correction code corresponding to the write data in the access request and issues it together with the write data. Note that if the write data does not require error correction, this step may be omitted.

[0036] 6, in parallel with step 400, the address area determination unit 320 determines whether the destination logical address AL of the access request belongs to the first logical address area or the second logical address area. If the destination logical address AL is smaller than the boundary logical address described above, the address area determination unit 320 determines that the destination logical address AL belongs to the first logical address area. On the other hand, if the destination logical address AL is equal to or greater than the boundary logical address, the address area determination unit 320 determines that the destination logical address AL belongs to the second logical address area.

[0037] If it is determined in step S510 that the destination logical address AL belongs to the first area, the address area determination unit 320 issues the destination logical address AL to the first address generation unit 331 (step S520).

[0038] In step S530, the first address generation unit 331 generates a data address APd and an error correction code address APe from the destination logical address AL.

[0039] In the first address generating unit 331, the data address APd is calculated by the following equations (1) to (3).

[0040] APd[31:6]={AL[31:3] / 7}…(1) APd[5:3]=AL[31:3]%7…(2) APd=APd[31:6]×64+APd[5:3]×8…(3)

[0041] In formula (1), "AL[31:3]" means removing the lowest 3 bits of the destination logical address AL, which is expressed as a 32-bit bit string. This process corresponds to dividing the destination logical address AL by 8. As described above, one data block contains 8 data items, so this process determines the ordinal number of the data block in the first logical address area that is the data block immediately before the data block to which data address APd belongs (hereinafter also referred to as the "associated data block"). Furthermore, this is divided by 7, and the integer part of the quotient is obtained. As one access block contains 7 data blocks, this process determines the ordinal number of the access block immediately before the access block to which data address APd belongs (hereinafter also referred to as the "associated access block") in the first logical address area.

[0042] Equation (2) means that the quotient of the destination logical address AL divided by 8 is further divided by 7 to obtain the remainder. The integer part of the remainder indicates the ordinal number of the data block immediately before the data block to which the data block belongs in the access block to which the data block belongs.

[0043] The minimum access unit is 512 bits, or 64 bytes, so multiplying "APd[31:6]" by 64 gives the total number of physical addresses up to the associated access block. Also, since a data block is 64 bits, or 8 bytes, multiplying "APd[5:3]" by 8 gives the total number of physical addresses up to the data address APd in ​​the associated access block. Therefore, adding these together in equation (3) gives the data address APd.

[0044] In the first address generation unit 331, the error correction code address APe is calculated by the following equation (4).

[0045] APe=(AL[31:3]+1)×64-8+{AL[31:3]%7}…(4)

[0046] In equation (4), as mentioned above, "AL[31:3]" indicates the ordinal number of the data block immediately preceding the associated data block in the first logical address area. Therefore, "(AL[31:3]+1)×64" corresponds to the physical address of the start point of the access block following the associated access block. Since the error correction code occupies the last eight physical addresses of the access block, the address obtained by subtracting 8 from this address corresponds to the physical address where the first error correction code is located in the associated access block. Therefore, by adding "{AL[31:3]%7}" to this address, an offset corresponding to the ordinal number of the associated data block in the associated access block is added, and the error correction code address APe is obtained.

[0047] On the other hand, if it is determined in step S510 that the destination logical address AL belongs to the second area, the address area determination unit 320 issues the destination logical address AL to the second address generation unit 332 (step S522).

[0048] In step S532, the second address generation unit 332 generates a data address APd and an error correction code address APe from the destination logical address AL.

[0049] In the second address generating unit 332, the data address APd is calculated by the following equation (5).

[0050] APd = AL + APb1 / 8…(5)

[0051] As described above, the first boundary physical address APb1 refers to the physical address that is the starting point of the second physical address area, and its size corresponds to the total number of physical addresses belonging to the first physical address area. In the first logical address area, the ratio of data to error correction codes is 8:1 as described above, so "APb1 / 8" corresponds to the total number of physical addresses to which error correction codes are assigned in the first logical address area. Therefore, the data address APd can be obtained by adding "APb1 / 8" to the destination logical address AL.

[0052] In the second address generation unit 332, the error correction code address APe is calculated by the following equation (6).

[0053] APe=APb2+{(AL-APb1×7 / 8)[31:3]}…(6)

[0054] As described above, since the ratio of data to error correction codes in the first logical address area is 8:1, "APb1×7 / 8" corresponds to the total number of physical addresses to which data is assigned in the first logical address area. In other words, "AL-APb1×7 / 8" indicates the total number of data allocated to the second physical address area up to data address APd. Furthermore, by obtaining the integer part of the quotient obtained by dividing this total number of data by 8, the ordinal number of the data block to which the data block belongs in the second physical address area can be determined. Therefore, by adding "{(AL-APb1×7 / 8)[31:3]}" to the second boundary physical address APb2, an offset corresponding to the ordinal number of the data block to which the data block belongs in the second physical address area can be added, and the error correction code address APe can be determined.

[0055] After step S400 and step S530 or step S532 are completed, in other words, after the write data, error correction code, data address APd, and error correction code address APe are generated, the memory access unit 340 generates the above-mentioned data write command and error correction code write command and issues them to the semiconductor memory device 2000 (step S600). After this step is completed, the SoC module 1000 ends the data write process.

[0056] According to the SoC module 1000 of the embodiment described above, it is possible to determine whether to arrange the data and error correction code in the physical address space in the packed format or the planar format depending on the data length and whether error correction is required for the write data when writing data to the semiconductor memory device 2000. As a result, when reading data with a small data length, only the required data and error correction code are read, and when reading data that does not require error correction, only the data is read, thereby preventing a decrease in the access efficiency of the SoC module 1000.

[0057] B. Other Embodiments: (B1) In the above embodiment, the arithmetic device 110 and the address range determination unit 200 are independent functional units, but the present disclosure is not limited to this. The arithmetic device may also include a functional unit equivalent to the address range determination unit 200.

[0058] (B2) In the above embodiment, the SoC module 1000 includes the address area determination unit 320, which determines whether the destination logical address AL belongs to the first logical address area or the second logical address area. However, the present disclosure is not limited to this. The SoC module 1000 does not necessarily have to include the address area determination unit 320. In such an embodiment, for example, the address area determination unit 200 may issue an access request including information regarding whether the destination logical address AL belongs to the first logical address area or the second logical address area (hereinafter also referred to as "destination logical address affiliation information"). The address generation unit 330 may receive the access request and use the destination logical address affiliation information to determine whether the first address generation unit 331 or the second address generation unit 332 will generate the data address APd and the error correction code address APe. According to this embodiment, it is not necessary to make a determination regarding the destination logical address AL, and therefore it is possible to suppress a decrease in the processing performance of the SoC module 1000.

[0059] (B3) In the above embodiment, the first logical address area includes a storage area in the logical address space whose logical address is 0, but the present disclosure is not limited to this. The second logical address area may include a storage area in the logical address space whose logical address is 0.

[0060] (B4) In the above embodiment, the physical address space is divided so that the first physical address area includes a storage area in the physical address space whose physical address is 0, but the present disclosure is not limited to this. The physical address space may be divided so that the second physical address area includes a storage area in the physical address space whose physical address is 0.

[0061] (B5) In the above embodiment, the first threshold and the second threshold are set to different values, but the present disclosure is not limited to this. The first threshold and the second threshold may be set to the same value. In other words, a single threshold may be used to determine whether the destination logical address AL is assigned to the first logical address area or the second logical address area. According to this embodiment, the number of times data length determination is performed can be reduced, thereby suppressing a decrease in the processing performance of the SoC module 1000.

[0062] (B6) In the above embodiment, the address area determination unit 200 determines whether the first logical address area has more free space than the second logical address area in step S340 of the destination logical address determination process, but the present disclosure is not limited to this. For example, if the data length is greater than the first threshold and less than the second threshold, the address area determination unit 200 may assign the destination logical address AL to the first logical address without performing the determination in step S340. According to this embodiment, there is no need to check the free space in the first logical address area and the second logical address area, and therefore a decrease in the processing performance of the SoC module 1000 can be suppressed.

[0063] The present disclosure is not limited to the above-described embodiments and can be realized in various configurations without departing from the spirit thereof. For example, the technical features in each embodiment corresponding to the technical features in the form described in the Summary of the Invention section can be appropriately replaced or combined to solve some or all of the above-described problems or achieve some or all of the above-described effects. Furthermore, if a technical feature is not described as essential in this specification, it can be appropriately deleted.

[0064] The controller and the method described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the controller and the method described herein may be implemented by a special-purpose computer configured with a processor configured with one or more dedicated hardware logic circuits. Alternatively, the controller and the method described herein may be implemented by one or more special-purpose computers configured with a processor and memory programmed to perform one or more functions in combination with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory tangible storage medium. [Explanation of symbols]

[0065] 110... arithmetic unit, 200... address area determination unit, 330... address generation unit, 1000... SoC module, 2000... semiconductor memory device

Claims

1. An SoC module (1000) that reads and writes data from and to a semiconductor memory device (2000) and selectively performs error correction on the data when reading the data, an arithmetic unit (110, 120, 130) that issues write data to the semiconductor memory device; an address area determination unit (200) that receives the write data, determines a destination logical address, which is a logical address to which the write data is to be written, depending on whether the error correction for the write data is necessary and the data length, and issues an access request including the write data and the destination logical address; an address generation unit (330) that uses the write destination logical address to generate, in a physical address space of the semiconductor memory device, a data address to which the write data is written and an error correction code address to which an error correction code used when executing the error correction on the write data is written, and that selectively realizes, depending on whether the error correction of the write data is necessary and the data length, either arranging the write data and the error correction code in the physical address space so that they are both included in a minimum access unit of the semiconductor memory device, or arranging the write data and the error correction code in the physical address space so that they are spaced apart from each other by more than the minimum access unit; Equipped with an address area determination unit (320) that receives the access request and determines whether the destination logical address belongs to a first logical address area in a logical address space corresponding to the physical address space or a second logical address area in the logical address space that is different from the first logical address area; the address generation unit has a first address generation unit (331) and a second address generation unit (332) that generate the data address and the error correction code address by using the write destination logical address according to the result of the determination by the address area determination unit; the first logical address area is a continuous area in the logical address space, and is an area that is preset as an area for storing data that requires the error correction and has a data length that is equal to or less than a preset first threshold value; the second logical address area is a continuous area in the logical address space, and is preset as an area for storing data that requires the error correction and has a data length equal to or greater than a second threshold value that is equal to or greater than the first threshold value, and data that does not require the error correction, the address area determination unit determines which logical address of the first logical address area or the second logical address area is to be allocated to the logical address space as the write destination logical address of the write data; when the address area determination unit determines that the write destination logical address belongs to the first logical address area, the first address generation unit uses the write destination logical address received from the address area determination unit to generate the data address and the error correction code address so that both the write data and the error correction code are stored in a storage area included in the minimum access unit; when the address area determination unit determines that the write destination logical address belongs to the second logical address area, the second address generation unit uses the write destination logical address received from the address area determination unit to generate the data address and the error correction code address so that the write data and the error correction code are stored in storage areas that are farther apart from each other than the minimum access unit. SoC module.

2. 2. The SoC module of claim 1, the first logical address area is a continuous area in the logical address space that includes a storage area whose logical address is 0, the second logical address area is an area of ​​the logical address space excluding the first logical address area; SoC module.

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