Circuit and method for processing a data stream

Abstract

A circuit for processing a data stream is described, the circuit comprising: a burst phase detector configured to receive a data input signal, a clock circuit coupled to the burst phase detector, the clock circuit configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal, and a programmable clock generator configured to receive a plurality of clock signals, a selected one of the plurality of clock signals being generated by the programmable clock generator and provided to the burst phase detector and the clock circuit.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate generally to circuits and methods for processing data streams, and more particularly to phase detectors for processing data streams in burst data systems. [Background technology]

[0002] A burst data system includes several transmitters that communicate with a single receiver over a shared medium using time division techniques. In a burst data system, different transmitters are provided with different time slots during which they can exclusively communicate with the receiver. Transmitters in a conventional burst data system transmit data at the same frequency but with different phases. For a receiver to accurately process the data being transmitted by the transmitters, the receiver must quickly detect the phase of the data stream in order to accurately sample data from the data stream. Acquiring the phase of the data stream allows the receiver to sample data from the data stream at a point in time when the signal representing the data stream is more reliable (because it may be less affected by local noise). The time it takes for a receiver to detect the phase of the data stream and begin accurately sampling data using the detected phase, relative to the start of data sampling, is called the locking time. The goal of phase detection in a burst data system is to minimize locking.

[0003] However, as technology improves and faster burst clock and data recovery units (BCDRs) become available, the most a telecommunications carrier can do is upgrade the BCDR to a higher line rate if all clients simultaneously upgrade their optical network units (ONUs) to the new technology.

[0004] Therefore, there is a need to allow the BCDR to operate using multiple different clock signals. Summary of the Invention

[0005] A circuit for processing a data stream is described that may include: a burst phase detector configured to receive a data input signal; a clock circuit coupled to the burst phase detector, the clock circuit configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals, a selected one of the plurality of clock signals generated by the programmable clock generator and provided to the burst phase detector and the clock circuit.

[0006] A method of processing a data stream is also described that may include configuring a burst phase detector to receive a data input signal, coupling a clock circuit to the burst phase detector, the clock circuit configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal, and configuring a programmable clock generator to receive a plurality of clock signals, a selected clock signal of the plurality of clock signals being generated by the programmable clock generator and provided to the burst phase detector and the clock circuit.

[0007] The drawings illustrate the design and utility of the embodiments, and like elements are referred to by common reference numerals. The drawings are not necessarily to scale. For a better understanding of how the above and other advantages and objects are obtained, a more particular description of the embodiments will be given and is shown in the accompanying drawings. These drawings depict only exemplary embodiments and therefore should not be considered as limiting the scope thereof. [Brief explanation of the drawings]

[0008] [Figure 1] 1 illustrates an example of a burst data system. [Figure 2] 1 illustrates exemplary phase profiles of different clients of a burst data system. [Figure 3] 1 illustrates an example of a receiver for a burst data system. [Figure 4] 2 illustrates another example of a receiver for a burst data system. [Figure 5] 1 shows a receiver and its application in a burst data system. [Figure 6] The behavior of the PLL in FIG. [Figure 7] 5 is a graph illustrating the behavior of the receiver of FIG. 4. [Figure 8] 5 shows a detailed diagram of the voltage controlled oscillator VCO1 of the burst phase detector of FIG. 4. [Figure 9] 5 shows a detailed diagram of the voltage controlled oscillator VCO2 of the PLL of FIG. [Figure 10] 5 shows a detailed diagram of the controlled oscillator VCO2 of the PLL of FIG. 4 that supports fractional relationships. [Figure 11] 1 shows a flowchart of a technique for performing data stream sampling using a burst data system. [Figure 12] 1 shows a flowchart illustrating a method for processing a data stream. DETAILED DESCRIPTION OF THE INVENTION

[0009] Passive Optical Networking (PON) is a type of burst data system commonly used in last-mile technology to deliver Internet data to users' homes. Compared to other technologies, such as cable using the DOCSIS standard, PON offers advantages. For example, the external cabinets for PONs are generally passive and therefore less prone to failure. Furthermore, fiber does not impose bandwidth limitations. Rather, the bandwidth limitations arise solely from the electronics, which are not present in the external cabinets. This represents only upstream data transmission from clients to the central office (CO). Each client transmits to the CO during its own time slot, and only one client is active at any given time. The availability of slots is governed by the CO runtime, giving telecommunications carriers the ability to allocate upstream bandwidth according to clients or even runtime.

[0010] Over time, as technology improves and faster BCDRs become available, operators must ask all clients to upgrade their ONUs to the new technology in order to upgrade their BCDRs. According to one implementation, clients can upgrade their ONUs as soon as they want to benefit from an increased upstream line rate. However, if a client does not need to transmit data at a different rate, they can simply use their original ONU. To enable this network to operate correctly, a multi-rate BCDR is required. The circuits and methods described below describe a new BCDR architecture that can receive packets at different line rates. That is, the line rate can change for each packet from the upstream transmitter.

[0011] The circuit and method architecture described below can support several line rates (including different line rates for different clients) within the same network, without the line rates needing to be related by integer multiples. This is significant when compared to other implementations that simply use clock gating to change the line rate by an integer factor. The case of Ethernet Passive Optical Networks (EPONs) (i.e., 1.25G and 10.31 5Gbit / s) is a typical example where the rates do not have integer ratios. Furthermore, the line rates are likely to have non-integer ratios due to the presence of forward error correction (FEC).

[0012] The circuit and method described below can be extended to any application requiring a receiver that operates in bursts, where each burst can have its own phase and frequency. The solution can be further extended to incorporate a modified NCO structure. That is, in addition to receivers that support different line rates, the circuit and method can support fractional rates with an integer CENTER_FREQUENCY. As described in some implementations, all fractional rates can be implemented independently with a CENTER_FREQUENCY that is either fractional or integer. In other implementations, the CENTER_FREQUENCY signal can be latched by the PREAMBLE_DETECT signal before being loaded into the second controlled oscillator.

[0013] Thus, the circuits and methods described below include many novel circuits that support rates that are not limited to integer multiples of each other, including rates that change on a packet-by-packet basis. The circuits are fully synchronous and may use a single system clock regardless of the number of rates they support. As such, they are well suited to being implemented in available digital logic, field programmable gate arrays (FPGAs), or application specific integrated circuits (ASICs), for example.

[0014] Various embodiment features are described below with reference to the figures. Note that the figures are not necessarily to scale, and elements of similar structure or function are represented by like reference numerals throughout the figures. Note that the figures are intended only to facilitate the description of the embodiments. They are not intended as an exhaustive description of the claimed invention or as limiting the scope of the claimed invention. Additionally, the illustrated embodiments need not possess all of the illustrated aspects or advantages. Aspects or advantages discussed in connection with a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other embodiment, even if not so illustrated or explicitly described. Also, throughout this specification, references to "some embodiments" or "other embodiments" mean that a particular feature, structure, material, or characteristic discussed in connection with an embodiment is included in at least one embodiment. Thus, the appearance of the phrase "some embodiments" or "other embodiments" in various places throughout this specification does not necessarily refer to the same embodiment or embodiments.

[0015] 1 is a block diagram illustrating an exemplary burst data system 100. The burst data system includes several transmitters 101 that communicate with a single receiver 103 over a shared medium 105 using time division techniques. In the burst data system, different transmitters 101 are provided with different time slots in which they can communicate exclusively with the receiver 103, which may include, for example, a BCDR. The transmitters 101 in the burst data system may transmit data at different frequencies and different phases.

[0016] In order for the receiver 103 to accurately process the data stream being transmitted by the transmitter 101, the receiver 103 must quickly detect the phase of the data stream in order to accurately sample data from the data stream. Acquiring the phase of the data stream enables the receiver 103 to sample data from the data stream at a point in time when the signal representing the data stream is more reliable (e.g., less affected by local noise). The time it takes for the receiver 103, relative to the start of data sampling, to detect the phase of the data stream and begin accurately sampling data using the detected phase is called the locking time. The goal of phase detection in a burst data system is to minimize locking.

[0017] For data systems that are non-bursty in nature (e.g., one-to-one correspondence between transmitter and receiver), a phase-locked loop (PLL) may be used at the receiver to perform phase detection on the incoming data. The PLL includes a phase detector that compares the incoming data stream with the phase information output by a controlled oscillator to generate an error phase of the data relative to the phase information output by the controlled oscillator. The error phase is returned to the controlled oscillator, which updates its phase information to compensate for the error. This process continues until the phase information output by the voltage-controlled oscillator is synchronized with the data stream. While reference is made generally to a controlled oscillator, it should be understood that the controlled oscillator may be a voltage-controlled oscillator or a numerically controlled oscillator, or an oscillator controlled by some other quantity or value.

[0018] One technique for using a PLL in a burst data system involves adding a preamble to the beginning of a data stream transmitted from a transmitter to a receiver. The preamble can be a fixed number of bits used by the receiver to perform phase detection before sampling the data stream. The PLL uses the preamble to eventually detect the phase of the data stream, but this occurs very slowly, and therefore a long preamble length is necessary to ensure that the phase of the data stream is accurately detected before sampling the data stream. This technique is undesirable for use in burst data systems because it requires a long preamble length, which results in inefficient use of bandwidth and long locking times. Furthermore, this technique does not take into account that each transmitter is assigned only a fixed time segment during which it needs to sample its transmitted data stream, and a long preamble would cause too many time segments to be used for phase detection.

[0019] Another technique involves using a dedicated custom circuit in combination with a PLL to perform phase detection. A data stream is first transmitted from a transmitter to a receiver with a preamble containing a fixed pattern prepended to the data stream. The dedicated custom circuit at the receiver is used to perform phase detection on the preamble and steer the voltage-controlled oscillator of the PLL to accurately sample the data stream. The size of the preamble is determined by the speed of the dedicated custom circuit. Increasing the speed of the dedicated custom circuit can reduce the time it takes to detect the phase from the preamble. Even if this technique reduces the locking time, it still requires the use of a dedicated custom circuit that operates at a very high speed, which can be very expensive. Furthermore, even if the preamble length can be reduced, a positive locking time may still be required to accurately sample the data stream.

[0020] Another technique involves using a zero preamble length to perform phase detection on the data stream, but requires the transmitter to communicate with the receiver in a predictable, periodic manner. The circuit and method described below allows for rate changes on a packet-by-packet basis and supports rates that are not limited to integer multiples of each other. The circuit is fully synchronous and may use a single system clock regardless of the number of rates it supports.

[0021] FIG. 2 illustrates exemplary phase profiles of different transmitters 101 in a burst data system. As shown in FIG. 2, transmitters 1 and 3 transmit signals at Rate 2 during their designated time slots, while transmitters 2 and N transmit their data at Rate 1. According to the example in FIG. 2, the data transmitted by transmitters 1 through N are transmitted at different phases φ1, φ2, φ3, and φN as shown. FIG. 2 represents only upstream data transmission from clients to the receiver at the CO. Each client transmits to the CO during its own time slot, and at a given time, only one client is active. Slot availability can be managed by the CO runtime, giving the telecommunications carrier the ability to allocate upstream bandwidth depending on the client or even the runtime. Client orchestration occurs in the downstream direction, as shown in FIG. 1.

[0022] As shown in Figure 2, each transmitter 101 communicates exclusively with the receiver during a given period during which data is transmitted at a given phase. The example in Figure 2 represents a network in which only two clients (Transmitter 1 and Transmitter N) have upgraded their ONUs. At the physical layer, the BCDR of the receiver is important because it must quickly lock onto the incoming data organized in bursts, and in each burst, the data phase can change arbitrarily and each client may transmit at its own phase.

[0023] 3 shows a receiver 300 with a programmable clock generator that allows the receiver rate to be changed on a packet-by-packet basis. The receiver 300 includes a burst phase detector 302 configured to receive a data input (Data In) signal and provide a preamble phase and preamble detect signal to a clock circuit 304, as described in more detail below. The data input signal is also provided to a delay component 306, which supplies a delayed data input signal to the clock circuit. A programmable clock generator 308 provides a selected clock signal to the burst phase detector 302 and a delayed clock signal to the clock circuit 304, as described in more detail with reference to FIG. 4.

[0024] 4 shows a receiver 400 for a burst data system. The burst phase detector 302 performs phase detection on the incoming data stream and presets the phase of the PLL 403 to align with the data stream before sampling by the sample selector 426. In this manner, the receiver 400 of FIG. 4 can perform phase detection with zero or negative locking time, as will be described in further detail below. Optionally, the incoming data stream may include a preamble segment and a data segment.

[0025] The receiver 400 includes an upper branch (first branch) and a lower branch (second branch). The upper branch includes a controlled oscillator (CO1) 404, which may be implemented as a numerically controlled oscillator or a voltage controlled oscillator, for example, a phase detector PD1 402, a sample selector 406, a summer 408, and a signal stream detector 410. A numerically controlled oscillator may be implemented within the burst phase detector 302 and the clock circuit 304, for example, although it should be understood that a voltage controlled oscillator or an oscillator controlled according to some other value may also be used. The lower branch includes a delay component 306 configured to provide a delayed data input signal to the clock circuit 304.

[0026] Phase detector PD1 of burst phase detector 302 includes a first input coupled to receive the incoming data stream, a second input coupled to the output of a controlled oscillator, shown here by way of example as controlled oscillator CO1 404 of burst phase detector 302, and an output coupled to summer 408. Phase detector PD1 402 of burst phase detector 302 is configured to generate a phase error (shown as A) at its output. The phase error is based on a comparison of the phase of the data input signal to the CO1 phase output by voltage controlled oscillator CO1 of burst phase detector 302. As described below, controlled oscillator CO1 of burst phase detector 302 is fixed and generates a fixed CO1 phase. Thus, the phase error generated by phase detector PD1 of burst phase detector 302 is fixed. If the incoming data stream includes both a preamble segment and a data segment, phase detector PD1 402 of burst phase detector 302 may be configured to generate a phase error based on a comparison of the phase of the preamble segment to the CO1 phase generated by controlled oscillator CO1 of burst phase detector 302. In other embodiments, phase detector PD1 402 of burst phase detector 302 may be configured to generate a phase error based on a comparison of the phase of the data segment to the phase generated by controlled oscillator CO1 of burst phase detector 302.

[0027] The controlled oscillator CO1 of burst phase detector 302 is free-running, and therefore its input is tied to a fixed value (shown here as an example as "0"). The output of the controlled oscillator CO1 of burst phase detector 302 is coupled to summer 408. The controlled oscillator CO1 of burst phase detector 302 is configured to generate a fixed CO1 phase at its output based on the fixed value tied to its input.

[0028] The adder includes a first input coupled to the output of the controlled oscillator CO1 of the burst phase detector 302 (e.g., a fixed CO1 phase) and a second input coupled to the output of the phase detector PD1 of the burst phase detector 302 (e.g., a fixed phase error). The adder 408 combines the CO1 phase and the phase error to generate the runtime phase of the incoming data stream at its output. If the incoming data stream includes both a preamble segment and a data segment, the runtime phase generated by the adder may be the runtime phase of the preamble segment. In other embodiments, the runtime phase generated by the adder may be the runtime phase of the data segment.

[0029] The sample selector 406 of the burst phase detector 302 includes a first input coupled to the output of the summer 408, a second input coupled to receive the incoming data stream, and an output coupled to the signal stream detector 410. The sample selector 406 is configured to sample the incoming data stream using the runtime phase (e.g., the combined CO1 phase and phase error) of the incoming data stream to generate data stream samples at its output. If the incoming data stream includes both a preamble segment and a data segment, the data stream samples may be samples of the preamble segment. In some cases, the data stream samples may be samples of the data segment.

[0030] The signal stream detector 410 of the burst phase detector 302 includes a first input coupled to the output of the summer 408 and a second input coupled to the output of the sample selector 406. The signal stream detector 410 is configured to use the runtime phase (e.g., the combined CO1 phase and phase error) of the incoming data stream and the data stream samples to generate a data stream phase at a first output and a data stream detect signal at a second output. The data stream phase is the phase of the incoming data stream. The data stream detect signal indicates the start of incoming data from a new transmitter. If the incoming data stream includes both a preamble segment and a data segment, the data stream phase may be the preamble segment phase, and the data stream detect signal may be the preamble segment detect signal. In other cases, the data stream phase may be the data segment phase. Optionally, the preamble segment may be used to trigger the data stream detect signal.

[0031] The controlled oscillator 404 is also configured to receive a clock signal having a user-selectable frequency, which allows the rate to be changed on a packet-by-packet basis and supports rates not limited to integer multiples of each other. More specifically, the programmable clock generator 308 includes a selection circuit 412 configured to receive multiple clock signals having different frequencies to establish a receiver line rate, illustratively designated CENTER_F1 through CENTER_FN. The selection circuit 412 may include a multiplexer configured to receive a rate selection signal to select one of the clock signals provided to the multiplexer. The selected clock signal generated at output 414 is provided to the controlled oscillator CO1 to define the frequency of the output signal supplied to the summer 408. That is, the controlled oscillator generates an output signal having a frequency based on the selected center frequency of the clock signal output by the selection circuit 412. The delay component 416 may also be used to delay the coupling of the selected clock signal to the controlled oscillator CO2 of the PLL 403. Delay component 416 provides a delayed clock signal that is received by PLL 403 at the same time that the delayed data input signal is provided to PLL 403 .

[0032] Delay component 306 stores the incoming data stream while the upper branch performs phase detection. Once the phase of the incoming data stream is detected by the upper branch, the delay component releases the incoming data stream to PLL 403 and data sample detector 426. The clock signal generated by clock generator 308 maintains the clock signal to precisely time the clock signal provided to controlled oscillator CO2 of PLL 403. Delay component 306 is configured to store the data input signal for a period based on the data stream phase and the processing time for generating the data stream detect signal, and delay component 416 is configured to provide PLL 403 with a selected clock signal at the appropriate time to precisely sample the delayed input data.

[0033] During operation, an incoming data stream enters receiver 400 and flows into the upper branch as well as the lower branch. In the upper branch, the incoming data stream is detected and the phase of the incoming data stream is determined. The time it takes to detect the incoming data stream and determine the phase of the incoming data stream is the processing time. In the lower branch, the incoming data stream is stored in delay component 306 until the upper branch detects the incoming data stream and determines its phase. Optionally, the delay component may store the data stream for a period equal to the processing time. In other embodiments, the delay component stores the data stream for a period longer than the processing time.

[0034] When the signal stream detector of the burst phase detector 302 detects the phase of the incoming data stream, the signal stream detector injects that phase into the controlled oscillator CO2 of the PLL 403, so that the CO2 phase generated by the controlled oscillator CO2 of the PLL 403 is aligned with the phase of the incoming data stream.

[0035] The PLL 403 includes a phase detector PD2 420, a low pass filter LPF 422, and a controlled oscillator CO2 424.

[0036] Phase detector PD2 420 of PLL 403 includes a first input coupled to the output of the delay (e.g., the delayed incoming data stream) and a second input coupled to the output of controlled oscillator CO2 of PLL 403. Phase detector PD2 420 of PLL 403 is configured to generate a phase error at its output.

[0037] Low pass filter LPF 422 includes an input coupled to the output of phase detector PD2 420 and an output coupled to the input of controlled oscillator 424, which may be a voltage controlled oscillator VCO2 or a numerically controlled oscillator NCO2. Low pass filter LPF 422 is configured to remove local noise associated with the output of the phase detector.

[0038] The controlled oscillator CO2 of the PLL 403 includes a first input coupled to the low pass filter LPF, a second input coupled to the data stream phase signal generated by the signal stream detector 410, a third input coupled to receive the data stream detect signal generated by the signal stream detector 410, and an output coupled to the phase detector PD2 and the data sample selector of the PLL 403. The controlled oscillator CO2 424 of the PLL 403 generates the CO2 phase at its output, which is coupled to the second input of the phase detector PD2 and the data sample selector of the PLL 403. The controlled oscillator CO2 of the PLL 403 generates the CO2 phase at its output based on the output of the low pass filter LPF 422 (e.g., phase error filtered to remove local noise), the data stream phase, and the data stream detect signal, as described in more detail below.

[0039] As described above, when the signal stream detector in the upper branch detects the phase of the incoming data stream, the signal stream detector injects this phase into the controlled oscillator CO2 of the PLL 403, so that the CO2 phase generated by the controlled oscillator CO2 of the PLL 403 is aligned with the phase of the incoming data stream. Therefore, when the phase detector PD2 of the PLL 403 compares the phase of the incoming data stream with the CO2 phase generated by the controlled oscillator CO2 of the PLL 403, a minimum phase error is generated. This minimum phase error is passed to the low-pass filter LPF 422, which removes local noise before being received by the controlled oscillator CO2 of the PLL 403. Because the low-pass filtered phase error is minimal, the controlled oscillator CO2 of the PLL 403 continues to generate a CO2 phase that is aligned with the phase of the incoming data.

[0040] Data sample selector 426 receives the incoming data stream from the output of delay component 306 at the same time that PLL 403 receives it. The data sample selector is also coupled to the output of controlled oscillator CO2 of PLL 403 and samples the incoming data stream using the CO2 phase generated by controlled oscillator CO2. The CO2 phase generated by controlled oscillator CO2 of PLL 403 is aligned with the phase of the incoming data stream at the time the data sample selector begins receiving it, ensuring that the incoming data stream is sampled without data loss.

[0041] 5 shows a receiver 500 and its application in a burst data system. The receiver 500 includes a phase-locked loop (PLL) 501 and a sample selector. The PLL 501 includes a phase detector PD 502, a low-pass filter LPF 504, and a controlled oscillator CO1 506.

[0042] Phase detector PD502 includes a first input coupled to receive the incoming data stream and a second input coupled to the output of controlled oscillator CO1. Phase detector PD502 is configured to generate a phase error at its output.

[0043] Low pass filter LPF 504 includes an input coupled to the output of phase detector PD and an output coupled to the input of controlled oscillator CO1 506. Low pass filter LPF 504 is configured to remove local noise (e.g., phase error) associated with the output of phase detector PD.

[0044] The controlled oscillator CO includes an input coupled to the low pass filter LPF and an output coupled to the phase detector PD and the sample selector, and generates a CO phase at its output.

[0045] Initially, the incoming data stream is received at a first input of the phase detector PD 502 of the PLL 501. The controlled oscillator CO1 generates a random CO1 phase that is received at a second input of the phase detector PD of the PLL 501. The phase detector PD compares the phase of the incoming data stream with the CO1 phase generated by the controlled oscillator CO to generate a phase error. The phase error is passed to a low-pass filter LPF, which removes local noise before being received by the controlled oscillator CO. The controlled oscillator CO1 generates an adjusted CO1 phase based on the received, low-pass filtered phase error. This continues until the CO1 phase generated at the output of the controlled oscillator CO1 is aligned with the phase of the incoming data stream.

[0046] Figure 6 shows the behavior of the PLL at measurement point A in Figure 4. Figure 6 shows the behavior of two different incoming data streams (i.e., Packet 1 and Packet 2) with different phases. Measurement point A shows the phase error at the output of phase detector PD over time. As can be seen, when the incoming data stream is first received, a large phase error is generated by the phase detector due to a mismatch between the CO1 phase generated at the output of controlled oscillator CO1 and the phase of the incoming data stream. As the CO1 phase is adjusted, the phase error decreases until the CO1 phase is aligned with the phase of the incoming data stream (at which point there is no error at measurement point A).

[0047] While PLL 501 is performing phase detection on the incoming data stream, the incoming data stream is simultaneously being received by the sample selector. The CO1 phase generated by voltage-controlled oscillator CO1 is sent to the sample selector to sample the incoming data stream and generate data stream samples at its output. Because the CO1 phase is not initially aligned with the phase of the incoming data stream, the sampling of the input data by the sample selector is uncertain, and much of the incoming data stream is lost. Sampling of the incoming data stream is uncertain until controlled oscillator CO1 generates a CO1 phase that is aligned with the phase of the incoming data stream. In other words, receiver 500 has a positive locking time (i.e., the time between the start of data stream sampling and the time the phase of the data stream is detected is positive), and therefore, incoming data is lost due to delays in detecting the phase.

[0048] FIG. 7 is a graph illustrating the behavior of the receiver 400 of FIG. 4. As soon as the incoming data stream enters the upper branch, its phase is compared with the CO1 phase generated by the controlled oscillator CO1 of the burst phase detector 302 to generate a phase error at measurement point A in FIG. 4. This phase error is shown in FIG. 4. As mentioned above, the CO1 phase is fixed, so is the phase error. The phase error is combined with the CO1 phase in the summer to generate the runtime phase of the incoming data stream at the summer's output, as shown in FIG. 4. The assumed processing time corresponds to preamble detection (probe C). Probe D (the error phase of the data relative to CO2) is shown as a straight line (i.e., does not change). The processing time in FIG. 7 matches the delay in FIG. 4. Probe D appears flat in FIG. 7 because the upper branch (during processing time) calculated the correct phase of the incoming data and injected it into CO2. In this case, CO2 has already been adjusted to be in the same phase as the next incoming packet, and the PD detects no error (i.e., probe D is equal to 0).

[0049] As described above, the sample selector of burst phase detector 302 is configured to sample the incoming data stream using the run-time phase of the incoming data (e.g., the combined VCO phase and phase error) to generate data stream samples at its output. The signal stream detector of burst phase detector 302 is configured to use the combined VCO phase and phase error (i.e., the run-time phase of the incoming data stream) and the data stream samples to generate a data stream phase at a first output and a data stream detect signal at a second output (i.e., measurement point B), as described above. The data stream detect signal at measurement point B is shown in Figure 4. When the incoming data stream includes a preamble segment and a data segment, the data stream detect signal is a signal indicating that a preamble segment, rather than a data segment, has been detected.

[0050] The data stream phase and data stream detect signals are outputs to PLL 403 that align the CO2 phase generated by controlled oscillator CO2 of PLL 403 with the phase of the incoming data stream. Therefore, when the incoming data stream is output from the delay component of the lower branch to phase detector PD2 of PLL 403, the phase error generated by the output of phase detector PD2 of PLL 403 at measurement point C is minimized, as shown in FIG. 7. This is because the time at which receiver 400 detects the phase of the incoming data stream occurs before the data sample selector begins sampling data. In other words, the locking of receiver 400 is zero or negative. This is in contrast to the phase error output by the phase detector of PLL 403 of FIG. 4, which includes a positive locking time.

[0051] Therefore, the receiver 400 of FIG. 4 has the ability to perform phase detection with zero or negative locking time, thus ensuring that no data is lost during sampling. In addition, the receiver 400 of FIG. 4 can be implemented with standard electronics without any speed requirements. Rather than dedicating costly custom electronics that operate at high speeds to perform phase detection, standard electronics that operate at any speed can be used. This reduces costs and allows for flexible operation of the receiver 400. Furthermore, the receiver 400 of FIG. 4 can be configured to perform phase detection on an incoming data stream with or without a preamble segment. This provides flexible operation of the receiver and can reduce bandwidth consumption in situations where the incoming data stream does not include a preamble segment. The preamble segment is not constrained to a specific length and can be adjusted depending on the particular application.

[0052] 8 shows a detailed diagram of the controlled oscillator CO1 of the burst phase detector 302 of FIG. 4. The controlled oscillator CO1 includes a register 802 and an adder 804. An input of the register is coupled to an output of the adder, and the output of the register is coupled to a first input of the adder. The adder also includes a second input coupled to receive a control signal and a third input coupled to receive a center frequency signal.

[0053] The control signal received by the controlled oscillator CO1 is shown in FIG. 4. In FIG. 4, the control signal received by the controlled oscillator VCO1 is a fixed value (e.g., 0). The center frequency signal is not shown in FIG. 4 and is an internally set value based on the operating frequency of the transmitter that time-shares the receiver, such as programmable clock generator 308. The controlled oscillator CO1 generates a CO1 phase at its output based on the center frequency signal, the control signal, and the output of a register. The CO1 phase generated by the controlled oscillator CO1 changes as the control signal received by the summer changes. However, because the controlled oscillator CO1 of the burst phase detector 302 in FIG. 4 is controlled by a fixed value control signal, the CO1 phase generated at the output of the voltage-controlled oscillator VCO1 remains fixed as long as the center frequency does not change.

[0054] 9 shows a detailed diagram of the controlled oscillator CO2 of the PLL 403 of FIG. 4. The controlled oscillator CO2 includes a register 902, a multiplexer 904, and an adder 906. An input of the register is coupled to an output of the multiplexer 904, and the output of the register is coupled to a first input of the adder. A first input of the multiplexer 904 is coupled to receive the data stream phase signal generated by the signal stream detector of the burst phase detector 302, a second input of the multiplexer 904 is coupled to the output of the adder, and a control input of the multiplexer 904 is coupled to receive the data stream detection signal generated by the signal stream detector of the burst phase detector 302. The adder also includes a second input coupled to receive the control signal and a third input coupled to receive the center frequency signal.

[0055] The control signal received by the controlled oscillator CO2 is shown in FIG. 4, i.e., the output of the low-pass filter LPF (e.g., noise-filtered phase error). The center frequency signal is not shown in FIG. 4 and is an internally set value based on the operating frequency of the transmitter that time-shares the receiver. When the signal stream detector in the burst phase detector 302 generates a data stream detect signal, it causes the multiplexer 904 of the controlled oscillator CO2 of the PLL2 to select the data stream phase, and therefore the controlled oscillator CO2 generates a CO2 phase at its output that is aligned with the phase of the incoming data stream. The CO2 phase generated at the output of the controlled oscillator CO2 of the PLL 403 remains aligned with the phase of the incoming data stream until a different data stream detect signal is received by the controlled oscillator CO2 of the PLL 403.

[0056] As already mentioned above, the receiver 400 of FIG. 4 has several advantages over other techniques for processing bursty data systems. The receiver 400 of FIG. 4 has the ability to perform phase detection with zero or negative locking time, thus ensuring no data loss during sampling. In addition, the receiver 400 of FIG. 4 can be implemented with standard electronics without any speed requirements. Rather than dedicating costly custom electronics that operate at high speeds to perform phase detection, standard electronics operating at any speed can be used. This reduces costs and allows for flexible receiver operation. Furthermore, the receiver 400 of FIG. 4 can be configured to perform phase detection on an incoming data stream with or without a preamble segment. This provides flexible receiver operation and can reduce bandwidth consumption in situations where the incoming data stream does not include a preamble segment. The preamble segment is not constrained to a specific length and can be adjusted depending on the particular application.

[0057] Receiver 400 for burst data systems also supports fractional relationships. Burst phase detector 302 performs phase detection on the incoming data stream as described above with respect to burst phase detector 302. To support the fractional relationship between the reference clock frequency and the output frequency, clock circuit 304 has a different configuration and functionality than described with reference to clock circuit 304.

[0058] In particular, the controlled oscillator (CO2) of clock circuit 304 is disconnected from the low pass filter (LPF) and phase detector (PD2). This allows the controlled oscillator CO2 to operate independently of the low pass filter LPF and / or phase detector PD2 of clock circuit 304, thereby allowing the controlled oscillator CO2 to operate at frequencies not supported by clock circuit 304 shown in FIG. 4. Because the controlled oscillator CO2 does not receive input from the low pass filter LPF or provide an output to the phase detector PD2, the configuration and operation of the controlled oscillator CO2 in clock circuit 304 differs from the configuration and operation of the controlled oscillator CO2 in clock circuit 304. An example of a controlled oscillator CO2 for clock circuit 304 is described with reference to FIG. 10 below.

[0059] In some embodiments, clock circuit 304 may have additional or fewer circuits. For example, clock circuit 304 may include only controlled oscillator C02 to achieve a smaller total semiconductor substrate footprint. In such cases, phase detector PD2 and low-pass filter LPF may be considered separate from clock circuit 304. In other embodiments, clock circuit 304 may optionally include circuitry that allows the feedback path of clock circuit 304 to be enabled and disabled as circumstances dictate. For example, clock circuit 304 may include switching circuitry for managing the interconnections of components within clock circuit 304. Furthermore, in other cases, clock circuit 304 may include switching circuitry that enables or disables voltage sources connected to phase detector PD2 and low-pass filter LPF, thereby reducing power consumption and disabling components.

[0060] In some cases, the controlled oscillator CO2 may support a non-fractional mode (using the phase detector PD2 and the low-pass filter LPF as shown in FIG. 4) as well as a fractional mode. In such a multi-mode scenario, the control signal may be 0 in a mode supporting a fractional relationship between the reference frequency and the output frequency of the controllable oscillator, or the output of the low-pass filter LPF in a mode supporting an integer relationship between the reference frequency and the output frequency. In such a case, the controlled oscillator CO2 of the clock circuit 304 may be configured to selectively couple to the low-pass filter LPF. This may be achieved by switching between various permutations of disconnecting the low-pass filter LPF, pulling down the control input, or disabling the low-pass filter LPF. In one technique, to conserve energy and avoid generating unnecessary noise and heat within the circuit, unused components (e.g., the phase detector PD2 and the low-pass filter LPF) may be disabled when in a mode supporting a fractional relationship, for example, by power-gating, i.e., disconnecting, their inputs and / or outputs. In other cases, the controlled oscillator CO2 may only support a fractional relationship between the reference frequency and the output frequency. In such a case, the controlled oscillator CO2 may be completely disconnected from the low pass filter LPF, and the operation of the controlled oscillator CO2 does not depend on the output from the low pass filter LPF.

[0061] 10 illustrates the voltage-controlled oscillator VCO2 of the clock circuit 304 of FIG. 4, which supports a fractional relationship. The controlled oscillator VCO2 includes a register (register 0), a multiplexer 1001, and a first adder 1002. An input of the register is coupled to receive the output from the multiplexer 1001, and the output of the register is configured to provide an input to a first input of the first adder 1002. A first input of the multiplexer 1001 is configured to receive the data stream phase signal generated by the signal stream detector of the burst phase detector 302, a second input of the multiplexer 1001 is configured to receive the output of the first adder 1002, and a control input of the multiplexer 1001 is coupled to receive the data stream detection signal generated by the signal stream detector of the burst phase detector 302. The first adder 1002 also includes a second input configured to receive a control signal and a third input configured to receive a center frequency signal.

[0062] The control signal is a signal for selectively connecting and disconnecting the controlled oscillator CO2 from the low-pass filter LPF during different operating modes. As previously described, during a mode that supports a fractional relationship between the controllable oscillator's reference frequency and output frequency, the controlled oscillator CO2 is disconnected from the low-pass filter LPF. This disconnects the controlled oscillator CO2 from the feedback loop within the clock circuit 304. If the controlled oscillator CO2 is not disconnected from the feedback loop, the clock circuit 304 attempts to adjust the fractional component or remainder from the output of the controlled oscillator CO2, preventing the clock circuit 903 from supporting the fractional relationship. During a mode that supports an integer relationship, the controlled oscillator CO2 is connected to the low-pass filter LPF. In some cases, the control signal may be provided from a separate module (e.g., circuit).

[0063] The voltage controlled oscillator CO2 of Figure 10 is similar to that described with reference to Figure 7, except that it is provided with additional circuitry including a sigma-delta circuit 1003 and a second summer 1004. The additional circuitry allows the controlled oscillator CO2 of Figure 10 to support a fractional relationship between the output frequency and the reference frequency.

[0064] The sigma-delta circuit 1003 includes an adder 1006 (e.g., a third adder), a modulus circuit 1008, a register (register 1), and a comparator 1005. The adder 1006 has a first input configured to receive a remainder and a second input configured to receive an output of register 1. The modulus circuit 1008 has a first input configured to receive an output from the adder 1006 and a second input configured to receive an ordinal. The input of register 1 and the input of the comparator 1005 are configured to receive the output of the modulus circuit 1008. The comparator 1005 may be configured to receive the remainder and may have memory (e.g., a storage component) for storing the remainder. In other cases, the comparator 1005 may have an input coupled to receive the remainder. In some embodiments, register 0 is an n-bit register and register 1 is an m-bit register.

[0065] In the embodiment described with reference to Figure 4, the center frequency is an integer value that remains the same for the duration of each data stream. In contrast, the sigma-delta circuit 1003 of Figure 10 can modulate the center frequency by 1 or 0. In essence, the sigma-delta circuit 1003 provides the fractional component of the frequency relationship, where center frequency = Fout / Frefclk, which can be expressed according to the Euclidean division algorithm as center frequency = Fout / Frefclk = quotient + remainder / divisor, where the quotient is equal to the integer part of the equation.

[0066] In operation, sigma-delta circuit 1003 outputs a 0 or a 1. Sigma-delta circuit 1003 outputs a "1" whenever the output of modulus circuit 1008 is less than the remainder as determined by comparator 1005, and outputs a "0" whenever the output of modulus circuit 1008 is greater than or equal to the remainder as determined by comparator 1005. For example, if the divisor is equal to 31 and the remainder is equal to 7, sigma-delta circuit 1003 outputs a 1 once every four or five cycles.

[0067] In the first cycle, register 1 is set to 0, and third adder 1006 receives (1) the remainder, 7, and (2) the output of register 1 (0 in this example). Third adder 1006 performs the addition 7 + 0 = 7 and outputs the result, "7," to modulus circuit 1008. The modulus of 7 at 31 is 7. The output of modulus circuit 1008 ("7") is sent to register 1 for storage and also sent to comparator 1005. Comparator 1005 compares this 7 with the remainder, 7, and determines that the output of modulus circuit 1008 ("7" in this example) is greater than or equal to the remainder, 7. Therefore, comparator 1005 of sigma-delta circuit 1003 outputs 0.

[0068] In the next cycle, the remainder remains 7, but the output of register 1 becomes 7. The third adder 1006 performs the addition 7 + 7 = 14 and outputs the result to modulus circuit 1008. The modulus of 14 with the divisor 31 is 14. The output of modulus circuit 1008 ("14") is sent to register 1 for storage, and is also sent to comparator 1005. Comparator 1005 compares 14 with the remainder of 7 and determines that 14 is greater than or equal to the remainder of 7. Therefore, comparator 1005 of sigma-delta circuit 1003 outputs 0.

[0069] In the next cycle, the remainder remains 7, but the output of register 1 becomes 14. The third adder 1006 performs the addition 7 + 14 = 21 and outputs the result to modulus circuit 1008. The modulus of 21 with the divisor 31 is 21. The output of modulus circuit 1008 ("21") is sent to register 1 for storage, and is also sent to comparator 1005. Comparator 1005 compares 21 with the remainder of 7 and determines that 21 is greater than or equal to the remainder of 7. Therefore, comparator 1005 of sigma-delta circuit 1003 outputs 0.

[0070] In the next cycle, the remainder remains 7, but the output of register 1 becomes 21. The third adder 1006 performs the addition 7 + 21 = 28 and outputs the result to modulus circuit 1008. The modulus of 28 with the divisor 31 is 28. The output of modulus circuit 1008 ("28") is sent to register 1 for storage, and is also sent to comparator 1005. Comparator 1005 compares 28 with the remainder of 7 and determines that 28 is greater than or equal to the remainder of 7. Therefore, comparator 1005 of sigma-delta circuit 1003 outputs 0.

[0071] In the next cycle, the remainder remains 7, but the output of register 1 becomes 28. The third adder 1006 performs the addition 7 + 28 = 35 and outputs the result to modulus circuit 1008. The modulus of 35 with the divisor 31 is 4. The output of modulus circuit 1008 ("4") is sent to register 1 for storage and also sent to comparator 1005. Comparator 1005 compares 4 with the remainder of 7 and determines that 4 is less than the remainder of 7. Therefore, comparator 1005 of sigma-delta circuit 1003 outputs 1.

[0072] In the next cycle, the remainder remains 7, but the output of register 1 becomes 4. The third adder 1006 performs the addition 7 + 4 = 11. The third adder 1006 outputs this result to modulus circuit 1008. The modulus of 11 with 31 is 11. The output of modulus circuit 1008 ("11") is sent to register 1 for storage and also sent to comparator 1005. Comparator 1005 compares 11 with the remainder of 7 and determines that 11 is greater than or equal to the remainder of 7. Therefore, a 0 is again output by comparator 1005 of sigma-delta circuit 1003. Note that throughout the above processing cycle, the data stream remains the same.

[0073] As shown in the above example, the sigma-delta circuit 1003, when combined with the quotient in the second adder 1004, provides a regular adjustment to the center frequency. Specifically, the output of the sigma-delta circuit 1003 is added to the quotient in the adder 1004. This value then becomes the center frequency value input to 1002. In effect, the output of the sigma-delta circuit 1003 provides periodic or near-periodic increments to the sampling frequency used to capture the data. In this way, the center frequency is adjusted to provide continuous correction for drift in the sampling frequency, thereby supporting a fractional relationship between the reference frequency and the output frequency. Following the above example, using "100" as an example quotient, adding the output of the comparator to the quotient results in the following center frequency output (output frequency):

[0074] [Table 1]

[0075] Similar to the operation of the circuit shown in FIG. 4, the center frequency of FIGS. 4 and 10 is set based on the operating frequency of the transmitter that is time-multiplexing the receiver. When the signal stream detector in burst phase detector 302 generates a data stream detect signal, it causes multiplexer 1001 of controlled oscillator CO2 in clock circuit 903 to select the data stream phase. Thus, controlled oscillator CO2 generates a CO2 phase at its output that is aligned with the phase of the incoming data stream. However, the CO2 phase generated at the output of controlled oscillator CO2 in clock circuit 304 may drift relative to the phase of the incoming data stream. Therefore, sigma-delta circuit 1003 provides a regular correction for the phase of the incoming data stream, so that the drift may be reduced or eliminated.

[0076] As shown in the above embodiments, the clock circuit 304 is configured to operate based on a fractional relationship between the reference clock frequency and the output frequency (e.g., center frequency). In some cases, the output frequency is the same as the data stream frequency. Also, the reference clock frequency and the sample frequency may have an integer relationship (e.g., a ratio of 1). Thus, by configuring the clock circuit 304 to support the fractional relationship between the reference clock frequency and the output frequency, the clock circuit 304 also supports the fractional relationship between the sample frequency and the frequency of the data stream.

[0077] 11 shows a method for data stream sampling using a burst data system. The method includes receiving a data stream as input (item 1101). The method then proceeds to a first sub-method 1111 and a second sub-method 1112. The items in the first sub-method 1111 correspond to the upper branch of the burst data system described with reference to FIGS. 4 and 10. The items in the second sub-method 1112 correspond to the lower branch of the burst data system described with reference to FIGS. 4 and 10. The first sub-method 1111 includes generating a data stream phase and a data stream detect signal using at least a first VCO phase (item 1103), generating a second VCO phase (item 1105), and sending the second VCO phase to a data sample selector (item 1107). A second sub-method 1112 includes at least delaying the data stream provided to the data sample selector (item 1104) before sending the data stream to the data sample selector (item 1108). Finally, the data stream is sampled in the data sample selector using a second VCO phase (item 1109).

[0078] In item 1101, a data stream is received in a burst data system such as those shown in Figures 4 and 10. The data stream is then sent to a first sub-method 1111 and a second sub-method 1112. While various types of data streams may be received, this description is limited to receiving a burst data stream. In some embodiments, the data stream may be a burst data stream that requires a fractional relationship between the output frequency and a reference frequency for accurate and reliable sampling.

[0079] In the first sub-method 1111, a data stream phase and data stream detection signal are generated in item 1103. This may be performed, for example, by using a phase detector PD1, a first voltage controlled oscillator VCO1, a summer configured to receive the outputs of the phase detector PD1 and the first voltage controlled oscillator VCO1, a sample selector, and a detector, as shown in FIG.

[0080] Next, in item 1105, a second VCO phase is generated using a voltage controlled oscillator VCO2, the second VCO phase being generated using a clock circuit that supports a fractional relationship between the reference clock and the output frequency as shown and described with reference to Figures 4 and 10. Details of item 1105 have been described with reference to Figures 4 and 10 and will not be repeated here.

[0081] In item 1107, the second VCO phase is sent to a data sample selector (such as the data sample selector described with reference to FIG. 4).

[0082] At the same time that the first sub-method 1111 is being performed to generate the second VCO phase, the second sub-method 1112 is being performed to delay the data stream between the input and the data sample selector.

[0083] In item 1104, a delay component, such as the delay component described with reference to Figure 4, is used to delay the data stream. In some embodiments, the delay component delays the data stream for the time required for first sub-method 1111 to perform at least items 1103 and 1105. In other embodiments, this time may be greater than or equal to the time required for first sub-method 1111, or may be equal to the time required for first sub-method 1111 plus some predetermined time (e.g., a minimum threshold).

[0084] In item 1108, the data stream is sent to the data sample selector described with reference to FIG.

[0085] In item 1109, a data sample selector receives the second VCO phase and the data stream and accurately and reliably samples the data stream.

[0086] FIG. 12 shows a flowchart illustrating a method for processing a data stream. The method for processing a data stream is described in FIG. 12. The method may be implemented, for example, according to the implementations of FIGS. 3 and 4, or other suitable circuits for processing a data stream. According to one implementation, a burst phase detector, such as burst phase detector 302, is configured to receive a data input signal in block 1202. In block 1204, a clock circuit, such as clock circuit 304, is coupled to the burst phase detector, the clock circuit being configured to receive a delayed data input signal and to receive a phase signal and a detection signal. In block 1206, a programmable clock generator, such as programmable clock generator 308, is configured to receive a plurality of clock signals and a selection signal. In block 1208, a selected clock signal from the plurality of clock signals is generated by the programmable clock generator. In block 1210, the selected clock signal is provided to the burst phase detector and the clock circuit.

[0087] According to some implementations, configuring the burst phase detector may include configuring a controlled oscillator to provide a phase signal at an output; and coupling the phase detector with a first input for receiving the data input signal and a second input coupled to the output of the controlled oscillator, the phase detector configured to provide a phase error at its output.

[0088] Configuring the burst phase detector may further include coupling a sample selector with a first input for receiving the sum of the phase signal and the phase error and a second input coupled to receive the data stream, the sample selector configured to provide the data stream samples at an output thereof; and coupling a data stream detector with the first input for receiving the sum of the VCO phase and the phase error and a second input coupled to an output of the sample selector, the data stream detector configured to generate a data stream phase and a data stream detect signal.

[0089] The method may further include coupling a delay component to the programmable clock generator, the delay component adapted to receive the data input signal and generate a delayed data input signal, and coupling a second delay component to the programmable clock generator, the second delay component adapted to receive the data input signal and generate a delayed data input signal.

[0090] According to some implementations, the delay component may be configured to store the data stream for a period equal to or greater than the processing time for generating the data stream phase and the data stream detection signal. The clock circuit may include a phase detector coupled to receive the delayed data input signal. The clock circuit may include a controlled oscillator coupled to receive an output of the phase detector. The programmable clock generator may include a selection circuit coupled to receive the multiple clock signals, the selection circuit configured to select one clock signal of the multiple clock signals in response to the selection signal. The programmable clock generator may include a delay element coupled to an output of the selection circuit.

[0091] As used herein, the term "output" may refer to an output signal or a physical output of a component (e.g., a port, node, connection, etc.). Similarly, the term "input" may refer to an input signal or a physical input of a component (e.g., a port, node, connection, etc.). Also, a "first output" and a "second output" may refer to separate physical outputs or to a single physical output configured to or capable of outputting first and second output signals. Similarly, a "first input" and a "second input" may refer to separate physical inputs or to a single physical input configured to or capable of receiving first and second input signals.

[0092] The described technology may be expressed in one or more of the following non-limiting examples. Further examples are disclosed below and expressed in the claims.

[0093] A circuit for processing a data stream, comprising: a burst phase detector configured to receive a data input signal; a clock circuit coupled to the burst phase detector, the clock circuit configured to receive the delayed data input signal and to receive the data stream phase signal and the data stream detect signal; a programmable clock generator configured to receive a plurality of clock signals; A circuit in which a selected one of a plurality of clock signals is generated by a programmable clock generator and provided to a burst phase detector and a clock circuit.

[0094] Example 2. The burst phase detector is a controlled oscillator configured to provide a phase signal at an output; 10. The circuit of claim 1, comprising: a phase detector having a first input coupled to receive a data input signal and a second input coupled to an output of the controlled oscillator, the phase detector configured to provide a phase error at an output thereof.

[0095] Example 3. The burst phase detector is a sample selector having a first input coupled to receive the sum of the phase signal and the phase error and a second input coupled to receive the data input signal, the sample selector configured to provide data stream samples at an output thereof; 3. The circuit of example 2, comprising: a signal stream detector having a first input coupled to receive a sum of the phase signal and the phase error and a second input coupled to an output of the sample selector, the signal stream detector configured to generate a data stream phase signal and a data stream detection signal.

[0096] Example 4. The circuit of example 1, further comprising: a delay component coupled to the programmable clock generator and adapted to receive the data input signal and generate a delayed data input signal.

[0097] Example 5. The circuit of example 4, wherein the delay component is configured to store the data input signal for a period based on a processing time for generating the data stream phase signal and the data stream detect signal.

[0098] Example 6. The circuit of example 5, wherein the clock circuit comprises: a phase detector coupled to receive the delayed data input signal; and a controlled oscillator coupled to receive an output of the phase detector.

[0099] Example 7. The circuit of example 6, wherein the clock circuit is configured to operate based on a fractional relationship between the reference frequency and the output frequency.

[0100] Example 8. The circuit of example 7, wherein the clock circuit comprises a sigma-delta circuit, the output of the sigma-delta circuit representing a fractional portion of the output of the controlled oscillator.

[0101] Example 9. The circuit of example 1, wherein the programmable clock generator comprises a selection circuit coupled to receive the plurality of clock signals, the selection circuit configured to select one clock signal of the plurality of clock signals in response to the selection signal.

[0102] Example 10. The circuit of example 9, wherein the programmable clock generator comprises a delay element coupled to the output of the selection circuit.

[0103] Example 11. A method for processing a data stream, the method comprising: configuring a burst phase detector to receive a data input signal; coupling a clock circuit to the burst phase detector, the clock circuit configured to receive the delayed data input signal, the data stream phase signal, and the data stream detect signal; configuring a programmable clock generator to receive a plurality of clock signals; The method, wherein a selected one of the plurality of clock signals is generated by a programmable clock generator and provided to a burst phase detector and a clock circuit.

[0104] Example 12. Configuring a burst phase detector configuring a controlled oscillator to provide a phase signal at an output; 12. The method of example 11, comprising: coupling a phase detector with a first input for receiving the data input signal and a second input to the output of the controlled oscillator, the phase detector configured to provide a phase error at an output thereof.

[0105] Example 13. Configuring a burst phase detector coupling a sample selector to a first input for receiving the sum of the phase signal and the phase error and to a second input coupled to receive the data input signal, the sample selector configured to provide data stream samples at an output thereof; 13. The method of claim 12, comprising: coupling a signal stream detector to a first input for receiving a sum of the phase signal and the phase error and a second input for receiving an output of the sample selector, wherein the signal stream detector is configured to generate a data stream phase signal and a data stream detection signal.

[0106] Example 14. The method of example 11, further comprising coupling a delay component to the programmable clock generator, the delay component adapted to receive the data input signal and generate a delayed data input signal.

[0107] Example 15. The method of example 14, wherein the delay component is configured to store the data input signal for a period based on a processing time for generating the data stream phase signal and the data stream detection signal.

[0108] Example 16. The method of example 15, wherein the clock circuit comprises: a phase detector coupled to receive the delayed data input signal; and a controlled oscillator coupled to receive an output of the phase detector.

[0109] Example 17. The method of example 16, wherein the clock circuit is configured to operate based on a fractional relationship between the reference frequency and the output frequency.

[0110] Example 18. The method of example 17, wherein the clock circuit comprises a sigma-delta circuit, the output of the sigma-delta circuit representing a fractional portion of the output of the controlled oscillator.

[0111] Example 19. The method of example 11, wherein the programmable clock generator comprises a selection circuit coupled to receive the plurality of clock signals, the selection circuit configured to select one clock signal of the plurality of clock signals in response to the selection signal.

[0112] Example 20. The method of example 19, wherein the programmable clock generator comprises a delay element coupled to the output of the selection circuit.

[0113] While particular embodiments have been shown and described, it should be understood that they are not intended to limit the claimed invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the claimed invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The claimed invention is intended to encompass modifications and alternative forms.

Claims

1. 1. A circuit for processing a data stream, comprising: a burst phase detector configured to receive a data input signal, detect a phase and a start of data of the data input signal based on a preamble segment and a data segment of the data input signal, and output a data stream phase signal indicative of the phase of the data input signal and a data stream detect signal indicative of the start of the data input signal; a clock circuit coupled to the burst phase detector, the clock circuit configured to receive a delayed data input signal obtained by delaying the data input signal, and to receive the data stream phase signal and the data stream detect signal from the burst phase detector; a programmable clock generator configured to receive a plurality of clock signals; A circuit wherein a selected one of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clock circuit.

2. The burst phase detector a controlled oscillator configured to provide a phase signal at an output; 2. The circuit of claim 1, comprising: a phase detector having a first input coupled to receive the data input signal and a second input coupled to the output of the controlled oscillator, the phase detector configured to provide a phase error at its output.

3. The burst phase detector a sample selector having a first input coupled to receive the sum of the phase signal and the phase error and a second input coupled to receive the data input signal, the sample selector configured to provide data stream samples at an output thereof; 3. The circuit of claim 2, comprising: a signal stream detector having a first input coupled to receive the sum of the phase signal and the phase error and a second input coupled to the output of the sample selector, the signal stream detector configured to generate the data stream phase signal and the data stream detect signal.

4. 2. The circuit of claim 1, further comprising: a delay component coupled to the programmable clock generator and adapted to receive the data input signal and generate the delayed data input signal.

5. 5. The circuit of claim 4, wherein the delay component is configured to store the data input signal for a period based on a processing time for generating the data stream phase signal and the data stream detect signal.

6. 6. The circuit of claim 5, wherein the clock circuit comprises: a phase detector coupled to receive the delayed data input signal; and a controlled oscillator coupled to receive an output of the phase detector.

7. 2. The circuit of claim 1, wherein the programmable clock generator comprises a selection circuit coupled to receive the plurality of clock signals, the selection circuit configured to select one clock signal of the plurality of clock signals in response to a selection signal.

8. 8. The circuit of claim 7, wherein the programmable clock generator comprises a delay element coupled to an output of the selection circuit.

9. 1. A method for processing a data stream, said method comprising: configuring a burst phase detector to receive a data input signal, detect a phase and a start of the data input signal based on a preamble segment and a data segment of the data input signal, and output a data stream phase signal indicative of the phase of the data input signal and a data stream detect signal indicative of the start of the data input signal; coupling a clock circuit to the burst phase detector, the clock circuit configured to receive a delayed data input signal generated by delaying the data input signal, and to receive a data stream phase signal and a data stream detect signal from the burst phase detector; configuring a programmable clock generator to receive a plurality of clock signals; A method wherein a selected one of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clock circuit.

10. Configuring the burst phase detector includes: configuring a controlled oscillator to provide a phase signal at an output; 10. The method of claim 9, comprising: coupling a phase detector with a first input for receiving the data input signal and a second input to the output of the controlled oscillator, the phase detector configured to provide a phase error at an output thereof.

11. Configuring the burst phase detector includes: coupling a sample selector to a first input for receiving the sum of the phase signal and the phase error and to a second input coupled to receive the data input signal, the sample selector configured to provide data stream samples at an output thereof; 11. The method of claim 10, comprising: coupling a signal stream detector to a first input for receiving the sum of the phase signal and the phase error and to a second input for receiving the output of the sample selector, the signal stream detector configured to generate the data stream phase signal and the data stream detect signal.

12. 10. The method of claim 9, further comprising: coupling a delay component to the programmable clock generator, the delay component adapted to receive the data input signal and generate the delayed data input signal.

13. 13. The method of claim 12, wherein the delay component is configured to store the data input signal for a period based on a processing time for generating the data stream phase signal and the data stream detection signal.

14. 10. The method of claim 9, wherein the programmable clock generator comprises a selection circuit coupled to receive the plurality of clock signals, the selection circuit configured to select one clock signal of the plurality of clock signals in response to a selection signal.

15. 15. The method of claim 14, wherein the programmable clock generator comprises a delay element coupled to an output of the selection circuit.