Memory with flying bitlines for improved burst mode read operation

Abstract

A memory system having flying bitlines for improved burst mode read operations and associated methods are provided. The memory system includes a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously asserting a first wordline signal at a first inner wordline coupled to each of a plurality of inner bitlines and asserting a second wordline signal at a first outer wordline coupled to each of a plurality of outer bitlines, each of the plurality of outer bitlines including a first portion configured to pass over or under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

Description

[Technical Field]

[0001] background [Background technology]

[0002] A processor typically includes at least one or more processing cores coupled to random access memory (e.g., static random access memory (SRAM)) integrated as a single die on an integrated circuit or as multiple dies as part of a stack of integrated circuits. Processors for use in machine learning or other artificial intelligence applications require high-speed access to large chunks of data. As an example, a processor may need to access large amounts of training data and weights that need to be processed to perform machine learning. Other applications of the processor may similarly require high-bandwidth access to large chunks of data.

[0003] There is a constant need for improvements to memory systems to keep up with processor demands in applications that require fast access to large chunks of data. Summary of the Invention

[0004] In one example, the present disclosure relates to a method of operating a memory system including a first memory sub-array and a second memory sub-array, the first memory sub-array includes a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line; and The second memory sub-array includes a third set of memory cells coupled to a second inner word line and a fourth set of memory cells coupled to a second outer word line. In response to a burst mode read request, the method includes: (1) asserting a first word line signal on a first inner word line coupled to each of the first plurality of inner bit lines; (2) asserting a second word line signal on a first outer word line coupled to each of the first plurality of outer bit lines; (3) asserting a third word line signal on a second interior word line coupled to each of the second plurality of interior bit lines; (4) simultaneously asserting a fourth word line signal on a second outer word line coupled to each of the second plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to fly over or under a corresponding inner bit line, and each of the second plurality of outer bit lines including a second portion configured to fly over or under a corresponding inner bit line. The method may further include outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst.

[0005] In another example, the present disclosure relates to a memory system including a memory array, the memory array including a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line, the memory system may include a control unit configured to generate control signals for the following operations: In response to a burst mode read request, the method includes simultaneously (1) asserting a first word line signal on a first inner word line coupled to each of a plurality of inner bit lines and (2) asserting a second word line signal on a first outer word line coupled to each of a plurality of outer bit lines, each of the plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line; and outputting data from each of the first set of memory cells and the second set of memory cells as part of the burst.

[0006] In yet another example, the present disclosure relates to a memory system including a first memory sub-array and a second memory sub-array, the first memory sub-array including a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line, the second memory sub-array including a third set of memory cells coupled to a second inner word line and a fourth set of memory cells coupled to a second outer word line, each of the first set of memory cells and the second set of memory cells being organized into a first plurality of columns, and each of the third set of memory cells and the fourth set of memory cells being organized into a second plurality of columns. The memory system may further include a control unit configured to generate control signals for an operation, the operation including: in a first burst mode, (1) asserting a first wordline signal on a first inner wordline coupled to each of the first plurality of inner bitlines, (2) asserting a second wordline signal on a first outer wordline coupled to each of the first plurality of outer bitlines, (3) asserting a third wordline signal on a second inner wordline coupled to each of the second plurality of inner bitlines, and (4) asserting a third wordline signal on a second outer wordline coupled to each of the second plurality of outer bitlines. simultaneously asserting a fourth word line signal on the outer word lines of the first plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line and each of the second plurality of outer bit lines including a second portion configured to pass over or under a corresponding inner bit line; using shared column circuitry; and outputting data as part of a burst from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells.Alternatively, in the second burst mode, the control unit may be configured to generate control signals for operation including: in response to a second mode read request, simultaneously (1) asserting a first word line signal on a first inner word line coupled to each of the first plurality of inner bit lines and (2) asserting a second word line signal on a first outer word line coupled to each of the first plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line; and outputting data from each of the first set of memory cells and the second set of memory cells.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief explanation of the drawings]

[0008] The present disclosure is illustrated by way of example and not by way of limitation in the accompanying drawings, in which like references indicate like elements and in which elements are illustrated for simplicity and clarity and are not necessarily drawn to scale. [Figure 1] FIG. 1 is a schematic diagram of a memory with flying bitlines for use in burst mode read operations, according to an example. [Figure 2] FIG. 2 illustrates a diagram of a portion of the memory of FIG. 1 according to an example. [Figure 3] FIG. 3 illustrates a cross-sectional view of an example implementation of flying bit lines for use in the memory of FIG. [Figure 4] Figure 4 shows a diagram of a memory system including the memory of Figure 1. [Figure 5] FIG. 5 illustrates waveforms associated with a burst mode read performed using the memory system of FIG. 4 according to one example. [Figure 6] FIG. 6 illustrates a flowchart of a method for performing a burst mode read using the memory system of FIG. 4 according to one example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Examples described in this disclosure relate to memories with flying bitlines for improved memory read operations, particularly burst mode read operations. Traditionally, reading data from memory, even as part of a burst operation, is not energy efficient and may not have a high enough bandwidth to meet requests for data from faster processing cores. This results in less energy-efficient memory tied to the processor having to wait longer to receive data from memory in response to a read request. Particular examples in this disclosure relate to memory systems that improve the energy efficiency of burst mode read operations and support higher bandwidths to meet requests for data from faster processing cores or other processing logic (e.g., FPGA logic).

[0010] FIG. 1 shows a schematic diagram of a memory 100 having flying bitlines for use in burst mode read operations, according to an example. Memory 100 may include memory sub-array 110 and memory sub-array 150. Memory sub-array 110 may include a set of wordlines (WL) (e.g., wordline 120) corresponding to inner rows and another set of wordlines (WL) (e.g., wordline 130) corresponding to outer rows. Memory sub-array 110 may further include a set of inner bitlines 112, 114, 116, and 118 and a set of outer bitlines 122, 124, 126, and 128. Similarly, memory sub-array 150 may include a set of inner wordlines (WL) (e.g., wordline 160) and another set of outer wordlines (WL) (e.g., wordline 170). Memory sub-array 150 may further include a set of inner bitlines 152, 154, 156, and 158 and a set of outer bitlines 162, 164, 166, and 168. In one example, during a burst read operation, each of wordlines 120 and 130 of memory sub-array 110 and each of wordlines 160 and 170 of memory sub-array 150 may be asserted simultaneously to allow access to memory cells connected to both the inner and outer bitlines of each memory sub-array.

[0011] Still referring to Figure 1, Each of the inner bitlines 112, 114, 116, and 118 and outer bitlines 122, 124, 126, and 128 may be coupled to a shared column multiplexer (mux) 132. Each of the outer bitlines may be implemented as part of an integrated circuit in a manner that "fly over" or "fly under" the inner bitlines. In this manner, each of the inner bitlines 112, 114, 116, and 118 and outer bitlines 122, 124, 126, and 128 may be coupled to a shared column multiplexer (mux) 132. The memory sub-array 110 may include additional sets of inner and outer bitlines that may be coupled to respective shared column multiplexers (e.g., column mux 134 and column mux 136). Each of the inner bitlines 152, 154, 156, 158 and outer bitlines 162, 164, 166, 168 may be coupled to a column multiplexer (mux) 172. The memory sub-array 150 may include additional sets of inner and outer bitlines that may be coupled to respective shared column multiplexers (e.g., column mux 174 and column mux 176). Both the column mux 132 and the column mux 172 may be coupled to a shared column circuit 182. Similarly, both the column mux 134 and the column mux 174 may be coupled to a shared column circuit 184. Furthermore, both the column mux 136 and the column mux 176 may be coupled to a shared column circuit 186. As used herein, the term "outer wordlines" refers to a set of outer wordlines. The term "outer bitlines" includes memory rows that are spatially farther from a column circuit (e.g., column circuit 182, 184, or 186), and the term "inner wordlines" includes memory rows that are spatially closer to a column circuit. As used herein, the term "outer bitlines" includes bitlines with memory cells that are accessed when an "outer wordline" is fired, and the term "inner bitlines" includes bitlines with memory cells that are accessed when an "inner wordline" is fired.

[0012] Continuing with reference to FIG. 1, word line signals may be asserted using a row decoder (not shown in FIG. 1) that includes word line drivers. The row decoder may decode address signals and assert the appropriate word lines using corresponding word line drivers. Bit line signals may be asserted using column circuits (e.g., one of column circuits 182, 184, 186). A sense amplifier or other similar circuit may be used to precharge the bit lines before sensing the voltage on the bit lines. Further details of the operation of memory 100 are described in conjunction with memory system 400 of FIG. 4 and waveform 500 shown in FIG. 5.

[0013] Continuing with reference to FIG. 1 , for a burst mode read operation, in one example, two word lines in each of the memory sub-arrays may be fired together, and the read column select signal address may be sequentially incremented. Thus, in one example, word lines 120 and 130 in memory sub-array 110 and word lines 160 and 170 in memory sub-array 150 may be fired together. Once fired, these word lines may be held in this state until both the inner and outer bit lines corresponding to each column of memory sub-arrays 110 and 150 have output data bits. Advantageously, using this configuration, more data bits may be output per burst read operation while consuming less energy per burst mode read cycle. As an example, twice as many bits may be output as part of a burst mode read operation with improved access time. The overall bandwidth (measured in bits / ps) of memory 100 may be approximately 22 percent higher than that of conventional memories. As an example, by decoding addresses for a larger number of data words simultaneously, address decoding time may be saved. At the same time, the energy per bit consumed as part of a burst mode read operation may be approximately 25 percent lower than the energy per bit consumed by conventional memories. Furthermore, effective bitline loading may be reduced because double the number of memory cells (e.g., 256 cells vs. 128 cells) may be associated with each bitline without isolating the inner bitlines from the outer bitlines. The reduced effective bitline loading may further reduce the signal development time on each bitline to approximately 0.6 times the conventional signal development time. While FIG. 1 illustrates memory 100 as including a particular number of components arranged in a particular manner, memory 100 may include additional or fewer components arranged differently.

[0014] FIG. 2 illustrates a diagram of a portion 200 of a memory having flying bitlines for use in burst mode read operations, according to an example. Portion 200 shows further details of a portion of memory sub-array 110 of FIG. 1. As previously described with respect to FIG. 1, each memory sub-array that shares column circuitry may include both inner and outer bitlines. As an example, FIG. 2 illustrates inner bitlines 212 and 214 and outer bitlines 216 and 218. Memory cells (e.g., static random access memory (SRAM) cells) may be coupled to the bitlines. As an example, in FIG. 2, memory cells 222, 224, and 226 are shown coupled to inner bitlines 212 and 214, and memory cells 232, 234, and 236 are shown coupled to outer bitlines 216 and 218. Each row of memory cells may be driven by a corresponding wordline. 2 shows word line (WL1) 242 coupled to memory cells in an outer row, including memory cell 232, and word line (WL2) 244 coupled to memory cells in an inner row, including memory cell 222. Each memory cell may include a cross-coupled inverter and an additional transistor. In one example, each memory cell may be implemented as a six-transistor (6T) memory cell. Other numbers of cells, arranged differently, may also be used. Furthermore, the memory technology is not limited to SRAM and may include other types of memory, including phase change memory and magnetic random access memory.

[0015] Continuing with reference to FIG. 2 , each of the outer bitlines (e.g., outer bitlines 216, 218) may be implemented as part of an integrated circuit in such a way that at least a portion of such outer bitline is in a flying-over or flying-under relationship with respect to a corresponding inner bitline (e.g., inner bitlines 212, 214). In this manner, each of the inner bitlines 212, 214 and the outer bitlines 216, 218 may be coupled to a shared column multiplexer (mux) 270 or another shared column circuit. As shown in FIG. 2 , each outer bitline (including both the BL bitline and the BLB bitline) may include two portions: a first portion (e.g., each of portions 252, 262) that is accessed when the outer wordline (e.g., WL1 242) is fired, and a second portion (e.g., each of portions 256, 266) that is accessed when the inner wordline (e.g., WL2 244) is fired. Each portion of the outer bit line may be coupled via an interconnect. As an example, outer bit line (BL) portion 252 is coupled to outer bit line (BL) portion 256 via interconnect 254. Similarly, as an example, outer bit line (BLB) portion 262 is coupled to outer bit line (BLB) portion 266 via interconnect 264. Interconnects 254, 264 may be implemented as jumpers or other structures capable of electrically connecting two portions of the outer bit line. Furthermore, as shown in FIG. 2, in this example, outer bit line portions 256, 266 are "over" or "under" portions of the corresponding inner bit line.

[0016] Referring further to FIG. 2, in this example, a read column select signal (labeled RDYSEL_B) can be used to select the appropriate column associated with the memory to output the data stored in the memory cell. In this example, the read column select signal (RDYSEL_B signal) is shown as being asserted when it is logic low rather than logic high. A sense amplifier 280 can sense the voltage difference between the positive bit line (BL) and the negative bit line (BLB) by amplifying the voltage difference and then determine whether the stored bit is a logic 1 bit or a logic 0 bit based on the voltage difference. The output bit can be stored in an output data latch 290. Once the read column select signal (RDYSEL_B signal) is used to select a column for reading a data word, the sense amplifier associated with the selected bit line can be enabled via a signal labeled SAEN in FIG. 2. In one example, as described below in connection with Figure 4, control unit 430 of Figure 4 may assert a sense enable (SAEN) signal in response to de-assertion of a corresponding read column select signal (RDYSEL_B signal). As shown in Figure 2, prior to enabling sense amplifier 280 (e.g., by asserting the signal labeled SAEN), sense amplifier 280 may be precharged in response to assertion of a signal labeled SAPCHG_B, which is shown asserted as a logic low signal as opposed to a logic high signal. Additional details of these signals and their relationship to one another are provided further with respect to Figures 4 and 5.

[0017] FIG. 3 illustrates a cross-sectional view 300 of an example implementation of flying bitlines for use with the memory 100 of FIG. 1 . The cross-sectional view 300 shows only a portion of an integrated circuit that may include the memory 100. Furthermore, the cross-sectional view 300 shows only details relevant to a flying bitline implementation for use with the memory 100 of FIG. 1 . The integrated circuit 100 with memory may include a substrate 310. The substrate 310 may correspond to a die associated with the integrated circuit. Using semiconductor processing techniques, various layers may be formed, including metal layers, dielectric layers, and other layers. In this example, a cross-sectional view 320 of one of the inner bitlines (e.g., bitline 212 of FIG. 2 ) that may be formed in the metal layer M0 is shown. The cross-sectional view 320 is shown with a dotted line because the inner bitline may not be visible in the same plane as the cross-section of the outer bitlines. Additionally, a cross-sectional view 330 is shown of a portion of one of the outer bitlines (e.g., portion 252 of the outer bitline, similar to outer bitline 216 of FIG. 2 ) that may be formed at least partially in metal layer M0. Cross-sectional view 340 of a portion of the outer bitline is shown passing over cross-sectional view 320 of the inner bitline. In this example, the flying portion of the outer bitline may be formed in metal layer M2. Additionally, cross-sectional view 350 shows a portion of an interconnect structure (e.g., a jumper) connecting two portions of the outer bitline. Vias or other mechanisms may be used to connect the portion of the outer bitline formed in metal layer M0 with the portion of the outer bitline formed in metal layer M2. While FIG. 3 shows a particular arrangement of layers and the interconnections therebetween, the flying bitline may be formed using a different arrangement of layers with different interconnections. As an example, while FIG. 3 shows the outer bitline “passing over” the inner bitline, the outer bitline may also be formed “passing under” the inner bitline. Furthermore, the bit lines do not need to be directly underneath or above each other, but may be offset from each other.

[0018] FIG. 4 shows a diagram of a memory system 400 including the memory 100 of FIG. 1. The memory system 400 may be included as an SRAM within an integrated circuit having one or more processing cores. Such an integrated circuit may be implemented as a central processing unit (CPU) (single-core or multi-core), a graphics processing unit (GPU), or a field programmable gate array (FPGA). The memory system 400 may include a block RAM (block RAM) as part of an FPGA. The memory system 400 may be implemented as a 3D stacked system (e.g., a high-bandwidth memory (HBM) system) or as a DDR memory (DDR2) or a DDR memory (DDR3) (e.g., a DDR4) or a DDR5 memory (DDR6) (e.g., a DDR5)). The memory system 400 may also be implemented as a standalone memory system. Alternatively, the memory system 400 may be integrated with logic as part of a 3D stacked system (e.g., a high-bandwidth memory (HBM) system). The memory system 400 may include two memory sub-arrays arranged as shown in FIG. 4: a memory sub-array 410 and a memory sub-array 450. The memory system 400 may further include a wordline decoder 412 coupled to the memory sub-array 410 and another wordline decoder 452 coupled to the memory sub-array 450. A column circuit 414 may be coupled to the memory sub-array 410 to interface with bitlines (both inner and outer bitlines) included in the memory sub-array 410. Similarly, column circuitry 454 may be coupled to memory sub-array 450 to interface with bitlines (both inner and outer bitlines) included in memory sub-array 450. I / O circuitry 440 may be coupled to both column circuitry 414 and column circuitry 454. Memory system 400 may further include a control unit 430, which may be coupled to at least wordline decoder 412, wordline decoder 452, column circuitry 414, column circuitry 454, and I / O circuitry 440.

[0019] Continuing with reference to FIG. 4 , the control unit 430 may generate control signals to control the operation of various components of the memory system 400. As an example, the control unit 430 may process any read / write signals, burst mode signals, and addresses. As an example, the control unit 430 may include timing circuits, finite state machines, and other logic to enable generation of appropriate control signals. As an example, the control unit 430 may generate control signals that may generate (directly or indirectly) other signals that result in burst mode operation, as further described with respect to FIG. 5 . Although FIG. 4 depicts the memory system 400 as including a particular number of components arranged in a particular manner, the memory system 400 may include additional or fewer components arranged in a different manner. As an example, the control unit 430 may be configured to enable the memory system 400 to operate in multiple different burst modes. In one burst mode, two word lines per memory sub-array (e.g., memory sub-arrays 410 and 450) may be asserted simultaneously to output data from the memory cells. Alternatively, in another burst mode, only two word lines for one of the memory sub-arrays (e.g., one of memory sub-arrays 410 and 450) may be activated at a time. The other two word lines for the other memory sub-array (e.g., another one of memory sub-arrays 410 and 450) may be activated immediately after outputting data from the first memory sub-array. As part of a third burst mode, one word line per memory sub-array (e.g., memory sub-arrays 410 and 450) may be asserted at a time until all four word lines corresponding to the two memory sub-arrays are asserted sequentially. The data word may still be output as part of a single burst.Additionally, although FIG. 4 shows two memory sub-arrays (eg, memory sub-arrays 410 and 450), memory system 400 may include only one sub-array.

[0020] FIG. 5 illustrates waveforms 500 associated with a burst mode read performed using the memory system 400 of FIG. 4 according to one example. As previously described, the memory system 400 may include memory sub-arrays having both inner and outer bitlines configured to output bits in response to simultaneous assertion of two wordlines per memory sub-array. The memory system 400 may be configured to output a specific number of data words per burst mode cycle. The operation of the memory system 400 described with reference to FIG. 5 assumes that the memory system 400 is configured to output 16 data words in response to a burst mode read operation request. The number of data words output may depend on the number of columns per memory sub-array. The waveforms 500 illustrate internal waveforms corresponding to the operation of the memory system 400, including the memory 100 of FIG. 1. The waveforms 500 illustrate an internal clock signal (CLK) associated with the memory system 400. This clock signal may be used to coordinate the assertion and deassertion timing of various signals associated with memory system 400. Waveform 500 further illustrates a burst mode signal (BURST) that may be processed by control unit 430 associated with memory system 400. Additionally, waveform 500 illustrates providing an address (ADDR) of data (e.g., ADDR1) to be read in burst mode. In this example, the assertion of the BURST signal indicates to control unit 430 that the read operation is a burst mode read operation as opposed to a non-burst mode operation. In response, control unit 430 may activate logic, including finite state machines and timers, to control the internal timing of other signals associated with memory system 400.

[0021] Continuing with FIG. 5, in response to the burst mode signal (BURST) and the address (ADDR1), control unit 430 can determine which two word lines need to be fired for each of the memory sub-arrays (e.g., two word lines for memory sub-array 410 and two word lines for memory sub-array 450). Prior to firing the word lines, control unit 430 can precharge both the inner and outer bit lines by asserting a bit line precharge signal (waveform labeled BLPCHG_B<1,2> ​​in FIG. 5) for both memory sub-array 410 and memory sub-array 450. In this example, the bit line precharge signal is shown as being asserted when the signal is logic low as opposed to logic high. Once precharged, the bit line precharge signals for the two sub-arrays are deasserted as shown in FIG. 5, and the appropriate word line signals are simultaneously asserted. In one example, the address (ADDR1) may include at least two address bits for selecting the appropriate word line. A word line decoder (e.g., word line decoder 412 and word line decoder 452) may fire the appropriate word line. In this example, the control unit 430 may provide a control signal to the word line decoder to control the timing of assertion of the word line signal. As an example, the control unit 430 may assert a control signal that may fire a word line a certain time after deassertion of the bit line precharge signal (BLPCHG_B<1,2>). For ease of illustration, waveform 500 shows the firing of a single word line (WL), but in this example, four word lines—two word lines corresponding to memory sub-array 410 and two word lines corresponding to memory sub-array 450—are fired simultaneously.Advantageously, in a burst mode read operation, multiple words can be output without the need to refire the word line because the word line signal remains asserted for the duration of the burst, ensuring that both the inner and outer bit lines being accessed are held active during the burst read operation.

[0022] Continuing with FIG. 5, column select signals, which enable reading of memory cells coupled to both the inner and outer bitlines corresponding to both memory sub-array 410 and sub-array 450, can be asserted sequentially to read one data word at a time. The read column select signals (labeled RDYSEL_B<15:0>) illustrate exemplary signals generated by control unit 430 to select the appropriate column associated with memory system 400 for outputting data stored in the memory cells. Unlike the other signals, in this example, the read column select signal (RDYSEL_B signal) is shown as being asserted at a logic low, as opposed to a logic high. Once the read column select signal (RDYSEL_B<15:0> signal) is used to select a column for reading a data word, the sense amplifier associated with the selected bitline can be enabled via a signal labeled SAEN in FIG. 5. In one example, the control unit 430 may assert a sense enable (SAEN) signal in response to deasserting a corresponding read column select signal (RDYSEL_B<15:0> signal). As shown in FIG. 5, prior to enabling the sense amplifier, the sense amplifier associated with the column selected for reading may be precharged by asserting a signal labeled SAPCHG_B, which is shown asserted as a logic low signal as opposed to a logic high signal. In this example, a sense amplifier (e.g., the sense amplifier 280 of FIG. 2, which may be included as part of the column circuit 414 and the column circuit 454 of the memory system 400 of FIG. 4) may sense the voltage difference between the positive bit line (BL) and the negative bit line (BLB) by amplifying the voltage difference and then determine whether the stored bit is a logic one bit or a logic zero bit based on the voltage difference.

[0023] Continuing with FIG. 5, after data word D0 is output (shown as being output as part of the waveform labeled DOUT), another data word (e.g., data words D1, D2, ... D15) may be output by memory system 400 every clock cycle (e.g., clock cycles CLK2, CLK3, ... CLK16). While FIG. 5 illustrates waveforms corresponding to a memory system in which the first data word is output a fixed time (e.g., two clock cycles) after receiving an address associated with a burst mode read operation, modifications to the memory system may result in an increase or decrease in the number of clock cycles for the first data word to be output after receiving an address. Furthermore, depending on the size of the memory array, more or fewer data words may be output per burst mode read operation. Furthermore, memory system 400 may operate in a normal mode in which only one or two data words are output per read request (e.g., when the burst mode signal (BURST) is not asserted by the processing logic issuing the read request).

[0024] Figure 6 illustrates a flowchart 600 of an example method for performing a burst mode read using memory system 400 of Figure 4. In one example, the steps described with respect to flowchart 600 may be performed in response (directly or indirectly) to the assertion of a control signal associated with memory system 400 (e.g., a control signal generated by control unit 430 of Figure 4). Step 610 may include simultaneously, in response to a burst mode read request: (1) asserting a first wordline signal at a first inner wordline coupled to each of the first plurality of inner bitlines, (2) asserting a second wordline signal at a first outer wordline coupled to each of the first plurality of outer bitlines, (3) asserting a third wordline signal at a second inner wordline coupled to each of the second plurality of inner bitlines, and (4) asserting a fourth wordline signal at a second outer wordline coupled to each of the second plurality of outer bitlines, where each of the first plurality of outer bitlines includes a first portion configured to pass over or under a corresponding inner bitline and each of the second plurality of outer bitlines includes a second portion configured to pass over or under a corresponding inner bitline. As previously described, the burst mode request may include asserting a signal labeled BURST in FIG. 5. In response, multiple word lines (e.g., two word lines associated with memory sub-array 410 of FIG. 4 and two word lines associated with memory sub-array 450 of FIG. 4) may be asserted based on control signals from control unit 430.

[0025] Step 620 may include outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst. Further details regarding the outputting step are provided with respect to Figures 4 and 5. As an example, Figure 5 shows a DOUT waveform representing multiple data words being output as part of a burst.

[0026] In conclusion, in one example, the present disclosure relates to a method for operating a memory system including a first memory sub-array and a second memory sub-array, the first memory sub-array including a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line, and the second memory sub-array including a third set of memory cells coupled to a second inner word line and a fourth set of memory cells coupled to a second outer word line. The method may include, in response to a burst mode read request, simultaneously: (1) asserting a first wordline signal at a first inner wordline coupled to each of the first plurality of inner bitlines, (2) asserting a second wordline signal at a first outer wordline coupled to each of the first plurality of outer bitlines, (3) asserting a third wordline signal at a second inner wordline coupled to each of the second plurality of inner bitlines, and (4) asserting a fourth wordline signal at a second outer wordline coupled to each of the second plurality of outer bitlines, wherein each of the first plurality of outer bitlines includes a first portion configured to pass over or under a corresponding inner bitline, and each of the second plurality of outer bitlines includes a second portion configured to pass over or under a corresponding inner bitline. The method may further include outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst.

[0027] The first set of memory cells and the second set of memory cells are each organized into a first plurality of columns, and the method may further include selecting one column at a time from the first plurality of columns in response to assertion of a read column select signal to output data as part of a burst. The third set of memory cells and the fourth set of memory cells are each organized into a second plurality of columns, and the method may further include selecting one column at a time from the second plurality of columns in response to assertion of a read column select signal to output data as part of a burst.

[0028] The memory system may be formed as part of an integrated circuit, and each of the first and second plurality of inner bitlines may be formed in a first metal layer associated with the integrated circuit, and each of the first and second portions configured to pass over or under the corresponding inner bitline may be formed in a second metal layer different from the first metal layer. Each of the first plurality of outer bitlines may include a second portion formed in the first metal layer, and the first portion configured to pass over or under the corresponding inner bitline may be coupled to the second portion formed in the first metal layer via an interconnect. Each of the second plurality of outer bitlines may include a second portion formed in the first metal layer, and the second portion configured to pass over or under the corresponding inner bitline may be coupled to the second portion formed in the first metal layer via an interconnect.

[0029] The memory system may include a control unit, and the method may further include the control unit generating a control signal in response to receiving an address associated with the burst mode read request and a burst mode signal. The memory system may further include a first wordline decoder associated with the first memory sub-array and a second wordline decoder associated with the second memory sub-array. The method may further include controlling timing of assertion of wordline signals by both the first wordline decoder and the second wordline decoder such that each of the first inner wordline, the first outer wordline, the second inner wordline, and the second outer wordline is activated during a burst period.

[0030] In another example, the present disclosure relates to a memory system including a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline, the memory system may further include a control unit configured to generate control signals for an operation including: in response to a burst mode read request, simultaneously (1) asserting a first wordline signal at a first inner wordline coupled to each of a plurality of inner bitlines and (2) asserting a second wordline signal at a first outer wordline coupled to each of a plurality of outer bitlines, each of the plurality of outer bitlines including a first portion configured to pass over or under a corresponding inner bitline; and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.

[0031] The first set of memory cells and the second set of memory cells may each be organized into a plurality of columns, and the control unit may be further configured to generate a control signal in response to assertion of a read column select signal to select one column at a time from among the plurality of columns to output data as part of a burst. The memory system may further include a plurality of sense amplifiers coupled to the plurality of columns, such that the plurality of columns have corresponding sense amplifiers.

[0032] The memory system may be formed as part of an integrated circuit, and each of the plurality of inner bitlines may be formed in a first metal layer associated with the integrated circuit, and a first portion configured to pass over or under a corresponding inner bitline may be formed in a second metal layer different from the first metal layer. Each of the plurality of outer bitlines may include a second portion formed in the first metal layer, and the first portion configured to pass over or under the corresponding inner bitline may be coupled to the second portion formed in the first metal layer via an interconnect.

[0033] In yet another example, the present disclosure relates to a memory system including a first memory sub-array and a second memory sub-array, the first memory sub-array including a first set of memory cells coupled to a first inner word line and a second set of memory cells coupled to a first outer word line, the second memory sub-array including a third set of memory cells coupled to a second inner word line and a fourth set of memory cells coupled to a second outer word line, each of the first set of memory cells and the second set of memory cells being organized into a first plurality of columns, and each of the third set of memory cells and the fourth set of memory cells being organized into a second plurality of columns. The memory system further includes a control unit configured to generate control signals for operation, in a first burst mode, in response to a first burst mode read request: (1) asserting a first wordline signal on a first inner wordline coupled to each of the first plurality of inner bitlines, (2) asserting a second wordline signal on a first outer wordline coupled to each of the first plurality of outer bitlines, (3) asserting a third wordline signal on a second inner wordline coupled to each of the second plurality of inner bitlines, and (4) asserting a third wordline signal on a second inner wordline coupled to each of the second plurality of outer bitlines. simultaneously asserting a fourth word line signal on a second outer word line coupled to each of the first plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line, and each of the second plurality of outer bit lines including a second portion configured to pass over or under a corresponding inner bit line; using shared column circuitry; and outputting data as part of a burst from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells. Alternatively, in a second burst mode, the control unit may be configured to generate control signals for operation, the operation including, in response to a second mode read request, simultaneously (1) asserting a first word line signal on a first inner word line coupled to each of a first plurality of inner bit lines and (2) asserting a second word line signal on a first outer word line coupled to each of a first plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line; and outputting data from each of the first set of memory cells and the second set of memory cells.

[0034] The control unit may be further configured to generate a control signal in response to assertion of the read column select signal to select one column at a time from among the first plurality of columns for outputting data as part of a burst. The control unit may be further configured to generate a control signal in response to assertion of the read column select signal to select one column at a time from among the second plurality of columns for outputting data as part of a burst. The memory system may include a plurality of sense amplifiers coupled to the first and second plurality of columns such that each of the first and second plurality of columns has a corresponding shared sense amplifier from the plurality of sense amplifiers.

[0035] The memory system may be formed as part of an integrated circuit, with the first plurality of inner bitlines and the second plurality of inner bitlines each formed in a first metal layer associated with the integrated circuit, and with a first portion configured to pass over or under a corresponding inner bitline and a second portion configured to pass over or under a corresponding inner bitline each formed in a second metal layer different from the first metal layer. Each of the first plurality of outer bitlines may include a second portion formed in the first metal layer, with the first portion configured to pass over or under a corresponding inner bitline coupled to the second portion formed in the first metal layer via an interconnect. Each of the second plurality of outer bitlines may include a second portion formed in the first metal layer, with the second portion configured to pass over or under a corresponding inner bitline coupled to the second portion formed in the first metal layer via an interconnect.

[0036] It should be understood that the methods, modules, and components described herein are merely exemplary. Alternatively, or additionally, the functions described herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems-on-chips (SOCs), complex programmable logic devices (CPLDs), etc. In an abstract but still clear sense, any arrangement of components that achieves the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, any two components combined to achieve a particular function herein can be understood to be "associated" with each other such that the desired functionality is achieved, regardless of architecture or intermediate components. Similarly, any two components so associated can also be construed as being "operably connected" or "coupled" with each other to achieve the desired functionality. Simply because a component, which may be a device, structure, system, or any other implementation of functionality, is described herein as being coupled to another component does not necessarily mean that the components are separate components. For example, a component A described as being coupled to another component B may be a subcomponent of component B, or component B may be a subcomponent of component A.

[0037] Additionally, functionality associated with some examples described in this disclosure may include instructions stored on non-transitory media. As used herein, the term "non-transitory media" refers to any medium that stores data and / or instructions that cause a machine to operate in a specific manner. Exemplary non-transitory media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory such as DRAM, SRAM, cache, or other such media. Non-transitory media is distinct from, but can be used in conjunction with, transmission media. Transmission media are used to transfer data and / or instructions to or from a machine. Exemplary transmission media include coaxial cable, fiber optic cable, copper wire, and wireless media such as radio waves.

[0038] Furthermore, those skilled in the art will recognize that boundaries between the functionality of the operations described above are merely exemplary. The functionality of multiple operations may be combined into a single operation and / or the functionality of a single operation may be distributed among additional multiple operations. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments.

[0039] While the present disclosure provides particular examples, various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings should be interpreted in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems described herein with respect to particular examples are not intended to be construed as critical, necessary, or essential features or elements of any or all claims.

[0040] Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in a claim should not be construed as implying that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to an invention containing only one such element, even if that same claim contains the introductory phrases "one or more" or "at least one" and indefinite article words such as "a." The same is true for the use of definite article words.

[0041] Unless expressly stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between multiple elements that such terms describe, and as such, these terms are not necessarily intended to denote a temporal or other priority of such elements.

Claims

1. 1. A method of operating a memory system including a first memory sub-array and a second memory sub-array, comprising: the first memory sub-array includes a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline; and the second memory sub-array includes a third set of memory cells coupled to a second inner wordline and a fourth set of memory cells coupled to a second outer wordline; The method, in response to a burst mode read request, includes: (1) asserting a first word line signal on the first inner word line coupled to each of a first plurality of inner bit lines; (2) asserting a second word line signal on the first outer word line coupled to each of the first plurality of outer bit lines; (3) asserting a third word line signal on the second inner word line coupled to each of the second plurality of inner bit lines; (4) simultaneously asserting a fourth word line signal on a second outer word line coupled to each of a second plurality of outer bit lines, each of the first plurality of outer bit lines including a first portion configured to pass over or under a corresponding inner bit line, and each of the second plurality of outer bit lines including a second portion configured to pass over or under a corresponding inner bit line; and outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst; A method comprising:

2. 10. The method of claim 1, wherein each of the first set of memory cells and the second set of memory cells is organized into a first plurality of columns, the method further comprising the step of selecting one column at a time from among the first plurality of columns in response to assertion of a read column select signal to output the data as part of a burst.

3. 3. The method of claim 2, wherein the third set of memory cells and the fourth set of memory cells are each organized into a second plurality of columns, the method further comprising the step of selecting one column at a time from among the second plurality of columns in response to assertion of a read column select signal to output the data as part of a burst.

4. 10. The method of claim 1, wherein the memory system is formed as part of an integrated circuit, and wherein each of the first plurality of inner bitlines and the second plurality of inner bitlines is formed in a first metal layer associated with the integrated circuit, and each of a first portion configured to pass over or under a corresponding inner bitline and a second portion configured to pass over or under a corresponding inner bitline is formed in a second metal layer different from the first metal layer.

5. 5. The method of claim 4, wherein each of the first plurality of outer bit lines includes a second portion formed in the first metal layer, the first portion configured to pass over or under the corresponding inner bit line being coupled to the second portion formed in the first metal layer via an interconnect.

6. 6. The method of claim 5, wherein each of the second plurality of outer bit lines includes a second portion formed in the first metal layer, the second portion configured to pass over or under the corresponding inner bit line being coupled to the second portion formed in the first metal layer via an interconnect.

7. 7. The method of claim 6, wherein the memory system includes a control unit, the method further comprising the step of the control unit generating a control signal in response to receiving an address associated with the burst mode read request and a burst mode signal.

8. 8. The method of claim 7, wherein the memory system includes a first wordline decoder associated with the first memory sub-array and a second wordline decoder associated with the second memory sub-array, the method further including controlling timing of assertion of wordline signals by both the first wordline decoder and the second wordline decoder such that each of the first inner wordline, the first outer wordline, the second inner wordline, and the second outer wordline is activated during the burst.

9. 1. A memory system comprising: a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline; and a control unit configured to generate a control signal for operation; and the operations include: In response to a burst mode read request, simultaneously: (1) asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines; and (2) asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, each of the plurality of outer bitlines including a first portion configured to pass over or under a corresponding inner bitline; and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst; 1. A memory system comprising:

10. 10. The memory system of claim 9, wherein each of the first set of memory cells and the second set of memory cells is organized into a plurality of columns, and the control unit is further configured to generate control signals for selecting one column at a time from the plurality of columns in response to assertion of a read column select signal to output the data as part of a burst.

11. 11. The memory system of claim 10, further comprising a plurality of sense amplifiers coupled to the plurality of columns, such that each of the plurality of columns has a corresponding sense amplifier.

12. 12. The memory system of claim 11, wherein the memory system is formed as part of an integrated circuit, and each of the plurality of inner bitlines is formed in a first metal layer associated with the integrated circuit, and a first portion configured to pass over or under a corresponding inner bitline is formed in a second metal layer different from the first metal layer.

13. 13. The memory system of claim 12, wherein each of the plurality of outer bitlines includes a second portion formed in the first metal layer, the first portion configured to pass over or under the corresponding inner bitline being coupled to the second portion formed in the first metal layer via an interconnect.

14. 1. A memory system comprising: a first memory sub-array and a second memory sub-array, the first memory sub-array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline, the second memory sub-array including a third set of memory cells coupled to a second inner wordline and a fourth set of memory cells coupled to a second outer wordline, each of the first set of memory cells and the second set of memory cells being organized into a first plurality of columns, and each of the third set of memory cells and the fourth set of memory cells being organized into a second plurality of columns; and a control unit configured to generate a control signal for operation; and wherein the operations include: In a first burst mode, in response to a first burst mode read request: (1) asserting a first wordline signal on the first inner wordline coupled to each of the first plurality of inner bitlines; (2) asserting a second wordline signal on the first outer wordline coupled to each of the first plurality of outer bitlines; (3) asserting a third wordline signal on the second inner wordline coupled to each of the second plurality of inner bitlines; and (4) asserting a fourth wordline signal on the second outer wordline coupled to each of the second plurality of outer bitlines. wherein each of the first plurality of outer bitlines includes a first portion configured to pass over or under a corresponding inner bitline and each of the second plurality of outer bitlines includes a second portion configured to pass over or under a corresponding inner bitline; using shared column circuitry; and outputting data from each of the first set of memory cells, the second set of memory cells, the third set of memory cells, and the fourth set of memory cells as part of a burst; or in a second burst mode, in response to a second mode read request, simultaneously (1) asserting a first wordline signal on a first inner wordline coupled to each of a first plurality of inner bitlines, and (2) asserting a second wordline signal on a first outer wordline coupled to each of a first plurality of outer bitlines, each of the first plurality of outer bitlines including a first portion configured to pass over or under a corresponding inner bitline; and outputting data from each of the first set of memory cells and the second set of memory cells; 1. A memory system comprising:

15. 15. The memory system of claim 14, wherein the control unit is further configured to generate control signals for selecting one column at a time from among the first plurality of columns in response to assertion of a read column select signal to output the data as part of a burst.

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