Semiconductor device and wireless communication device

Abstract

[Problem] To provide a semiconductor device which is capable of lowering the through potential density without increasing leakage current. [Solution] A semiconductor device which comprises a channel layer contained in a nitride semiconductor multilayer body that is provided on a substrate, and a barrier layer that is contained in a part of the multilayer body positioned above the channel layer, wherein: a part of the multilayer body positioned below the channel layer contains an n-type conversion factor which converts the nitride semiconductor into n-type in the concentration profile that has at least one peak in the stacking direction of the multilayer body; and a part of the multilayer body positioned above the peak in the concentration profile of the n-type conversion factor is provided with a region to be compensated, the region containing 6 × 1018 cm-3 or more of a compensation factor that compensates the n-type conversion factor.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a wireless communication device. [Background technology]

[0002] In recent years, development of semiconductor devices such as high electron mobility transistors (HEMTs) using nitride semiconductors has progressed. HEMTs have high electron mobility, high saturated electron velocity, and high breakdown voltage, and are therefore expected to be used in high-frequency devices and power devices as high-output, high-efficiency transistors.

[0003] In semiconductor devices using nitride semiconductors, it is desirable to reduce defects in the nitride semiconductor crystals in order to improve device characteristics. For example, threading dislocations that occur during the crystal growth of nitride semiconductors cause current collapse, which leads to output fluctuations in semiconductor devices, and therefore reduction of these defects is required.

[0004] For example, Patent Document 1 below discloses a technique for reducing the occurrence of threading dislocations by introducing a mask layer into a laminate of nitride semiconductors. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2018-88528 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the technology disclosed in Patent Document 1, constituent atoms of the mask layer unintentionally convert the surrounding nitride semiconductor into n-type, which can increase leakage current. Therefore, there has been a demand for a technology that can reduce the occurrence of threading dislocations without degrading other device characteristics.

[0007] Therefore, the present disclosure proposes a new and improved semiconductor device that can reduce the density of threading dislocations without increasing the leakage current, and a wireless communication device that includes the semiconductor device. [Means for solving the problem]

[0008] According to the present disclosure, a nitride semiconductor device is provided with a channel layer included in a nitride semiconductor stack provided on a substrate, and a barrier layer included in the stack above the channel layer, wherein the stack below the channel layer contains an n-type conversion factor that converts the nitride semiconductor to n-type, in a concentration profile having at least one peak in the stacking direction of the stack, and the stack above the peak of the concentration profile of the n-type conversion factor contains a compensation factor that compensates for the n-type conversion factor of 6×10 18 cm -3 A semiconductor device is provided that includes the compensated region described above.

[0009] According to the present disclosure, there is also provided a semiconductor device, the semiconductor device including: a channel layer included in a laminate of nitride semiconductors provided on a substrate; and a barrier layer included in the laminate above the channel layer, the laminate below the channel layer containing an n-type conversion factor that converts the nitride semiconductor to n-type, in a concentration profile having at least one peak in a lamination direction of the laminate; and a compensation factor that compensates for the n-type conversion factor, the concentration profile of which is 6×10 18 cm -3 A wireless communication device is provided, which is provided with a compensated region as described above. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic vertical cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a graph showing a schematic concentration profile of an n-type imparting factor and a compensation factor in the stacking direction of a stack. [Figure 3] FIG. 10 is a graph plotting the relationship between the concentration at the peak of the C concentration profile and the sheet resistance Rsh of the channel layer on the mask layer side. [Figure 4] FIG. 10 is a graph plotting the relationship between the distance between the peak of the Si concentration profile and the peak of the C concentration profile and the sheet resistance Rsh of the channel layer on the mask layer side. [Figure 5A] 4 is a schematic vertical cross-sectional view showing one step of the manufacturing method of the semiconductor device according to the embodiment. FIG. [Figure 5B] 4 is a schematic vertical cross-sectional view showing one step of the manufacturing method of the semiconductor device according to the embodiment. FIG. [Figure 5C] 4 is a schematic vertical cross-sectional view showing one step of the manufacturing method of the semiconductor device according to the embodiment. FIG. [Figure 6] 1 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a first specific example. [Figure 7] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a second example. [Figure 8] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a third specific example. [Figure 9] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a fourth specific example. [Figure 10] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a fifth example. [Figure 11] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a sixth example. [Figure 12] FIG. 11 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a seventh example. [Figure 13] FIG. 13 is a vertical cross-sectional view showing the configuration of a semiconductor device according to an eighth specific example. [Figure 14] FIG. 13 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a ninth example. [Figure 15] FIG. 10 is a block diagram showing a configuration of a wireless communication device according to a second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0012] In this specification, the stacking direction of the substrate and each layer is also referred to as the up-down direction. The direction in which the substrate exists is also referred to as the down-down direction, and the direction opposite to the direction in which the substrate exists is also referred to as the up-down direction.

[0013] The explanation will be given in the following order: 1. Example of semiconductor device configuration 2. Manufacturing method of semiconductor device 3. Specific examples of semiconductor devices 4. Example of wireless communication device configuration

[0014] <1. Configuration example of semiconductor device> First, a configuration example of a semiconductor device according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a schematic vertical cross-sectional view showing a configuration example of a semiconductor device 10 according to this embodiment.

[0015] 1, the semiconductor device 10 includes a substrate 100, a stacked body 200, an insulating film 321, a gate electrode 322, a source electrode 310S, and a drain electrode 310D. The semiconductor device 10 is, for example, a so-called high electron mobility transistor (HEMT).

[0016] The substrate 100 is a substrate that supports the stack 200 that constitutes the semiconductor device 10. The substrate 100 may be, for example, a Si substrate. Alternatively, the substrate 100 may be a substrate made of SiC, sapphire, GaN, AlN, diamond, or the like.

[0017] The stacked body 200 is a stacked body including, in order from the substrate 100 side, a buffer layer 210, a mask layer 220, a channel layer 230, and a barrier layer 240. The stacked body 200 is provided by epitaxially growing a nitride semiconductor, which is a III-V group compound semiconductor, on the substrate 100. The stacked body 200 may be configured to include at least one of AlN, InN, GaN, AlGaN, InGaN, AlInGaN, AlScN, SiN, MgN, and TiN.

[0018] The buffer layer 210 is provided on the substrate 100. The buffer layer 210 is provided to gradually change the lattice constant when a nitride semiconductor having a lattice constant significantly different from that of the material constituting the substrate 100 is grown on the substrate 100.

[0019] Specifically, when GaN is grown on a Si substrate 100, the buffer layer 210 may be made of Al(In)(Ga)N. Al(In)(Ga)N refers to a nitride semiconductor in which Al and N are essential elements and In and Ga are optional elements. Specifically, Al(In)(Ga)N is AlInGaN, AlGaN, AlInN, or AlN.

[0020] The buffer layer 210 may also be configured by stacking multiple layers with different composition ratios so that the Al composition ratio decreases toward the upper layer side of the stacked body 200. Alternatively, the buffer layer 210 may be configured by layers with a gradient in composition ratio so that the Al composition ratio gradually decreases toward the upper layer side of the stacked body 200.

[0021] For example, when GaN crystals are grown on the substrate 100, which is a Si substrate, the buffer layer 210 may have a two-layer structure in which an AlN layer and an AlGaN layer are stacked in this order from the Si substrate side. In this case, the thickness of the AlN layer may be, for example, 100 nm to 300 nm, and the thickness of the AlGaN layer may be, for example, 100 nm to 500 nm. The Al composition ratio of the AlGaN layer is, for example, 0.17 to 0.50.

[0022] The mask layer 220 is provided on the buffer layer 210. The mask layer 220 is made of, for example, SiN, and is provided to bend threading dislocations extending in the stacking direction of the stacked body 200 in an in-plane direction perpendicular to the stacking direction. The mask layer 220 can be made of SiO2 or TiN instead of SiN.

[0023] For example, the mask layer 220 may be provided as an island-shaped film that does not completely cover the buffer layer 210. In such a case, the mask layer 220 may not be visible as a layer, unlike the cross-sectional view shown in Figure 1. The thickness of the mask layer 220 may be, for example, 0.2 nm to 2 nm, or even 0.5 nm to 1 nm.

[0024] In such a case, the thickness of the mask layer 220 varies in the in-plane direction of the stacked body 200. Therefore, the channel layer 230 provided on the mask layer 220 grows preferentially in regions where the mask layer 220 is thinner, and grows three-dimensionally on the mask layer 220. As a result, dislocations that occur in the buffer layer 210 and extend in the stacking direction of the stacked body 200 due to the two-dimensional crystal growth of the nitride semiconductor are bent in the in-plane direction of the stacked body 200 by the channel layer 230 growing three-dimensionally. Therefore, the mask layer 220 can reduce the density of threading dislocations that penetrate the stacked body 200 in the stacking direction.

[0025] Furthermore, the mask layer 220 can also block threading dislocations generated in the buffer layer 210, thereby preventing the threading dislocations from reaching the channel layer 230. In such a case, the thicker the mask layer 220 is formed, the higher the coverage of the buffer layer 210 can be, and therefore the greater the effect of blocking threading dislocations can be. However, as will be described later, the thicker the mask layer 220 is, the higher the concentration of Si, which is a factor for converting a nitride semiconductor to n-type. Therefore, taking both factors into consideration, the mask layer 220 is preferably formed as an extremely thin film having a thickness of 0.2 nm to 2 nm, and more preferably 0.5 nm to 1 nm.

[0026] The channel layer 230 is provided on the mask layer 220. The channel layer 230 is a layer including a channel through which electrons supplied from the barrier layer 240 travel. Specifically, on the barrier layer 240 side of the channel layer 230, a two-dimensional electron gas (2DEG) is formed by the electrons supplied from the barrier layer 240.

[0027] The channel layer 230 is made of, for example, GaN. In addition to GaN, the channel layer 230 may be made of a mixed crystal containing (Al)(In)(Ga)N. (Al)(In)(Ga)N represents a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. When the channel layer 230 is made of InGaN, the channel layer 230 can further increase the electron mobility of the channel.

[0028] As described above, the channel layer 230 is provided by growing three-dimensionally on the mask layer 220 and then growing two-dimensionally. For example, the channel layer 230 may be formed by depositing a film of approximately 300 nm on the mask layer 220 in order to bend threading dislocations extending in the stacking direction of the stacked body 200 to an in-plane direction, and then depositing a film of 200 nm to 1700 nm to obtain a channel layer 230 with high crystallinity. In such a case, the channel layer 230 may be provided to have a total film thickness of 500 nm to 2000 nm.

[0029] In the semiconductor device 10 according to this embodiment, the mask layer 220 includes an n-type conversion factor that converts the nitride semiconductor to n-type, and the channel layer 230 includes a compensation factor that compensates for the n-type conversion factor included in the mask layer 220. The n-type conversion factor is a factor that includes at least either an impurity or a defect that converts the nitride semiconductor to n-type. The n-type conversion factor is, for example, Si (silicon), Ge (germanium), or O (oxygen). The compensation factor is a factor that includes at least either an impurity or a defect that cancels the conversion of the nitride semiconductor to n-type due to the n-type conversion factor. The compensation factor is, for example, C (carbon), Mg (magnesium), Fe (iron), or B (boron). The n-type conversion factor and the compensation factor will be described in detail below.

[0030] The barrier layer 240 is made of a nitride semiconductor having a higher conduction band minimum than the channel layer 230, and thereby generates a high concentration of two-dimensional electron gas (2DEG) on the barrier layer 240 side of the channel layer 230. For example, when the channel layer 230 is made of GaN, the barrier layer 240 may be made of Al(In)(Ga)N. Al(In)(Ga)N refers to a nitride semiconductor in which Al and N are essential elements and In and Ga are optional elements. Specifically, Al(In)(Ga)N is AlInGaN, AlGaN, AlInN, or AlN.

[0031] The concentration of the two-dimensional electron gas is determined using, as one of its parameters, the height of the conduction band minimum at the outermost surface of the barrier layer 240 on the channel layer 230 side. For example, the higher the Al composition ratio of the barrier layer 240, the greater the polarization of the barrier layer 240 and the steeper the slope of the conduction band. Furthermore, the thicker the barrier layer 240, the higher the height of the conduction band minimum at the outermost surface of the barrier layer 240. Therefore, the semiconductor device 10 can obtain a desired concentration of two-dimensional electron gas by appropriately controlling the composition and thickness of the barrier layer 240. For example, when the barrier layer 240 is made of AlInN, the Al composition ratio of the barrier layer 240 may be 0.70 to 0.90, and the thickness of the barrier layer 240 may be 3 nm to 20 nm.

[0032] Here, a spacer layer may be provided between the barrier layer 240 and the channel layer 230. The spacer layer may be made of, for example, AlN. The spacer layer can improve the characteristics of the semiconductor device 10 by suppressing fluctuations in composition at the interface between the barrier layer 240 and the channel layer 230. The spacer layer may be made of AlGaN or AlInGaN in addition to AlN. The thickness of the spacer layer may be, for example, greater than 0 nm to 3 nm, preferably 0.5 nm to 1.5 nm.

[0033] Furthermore, an intermediate layer may be further provided between the barrier layer 240 and the spacer layer. The intermediate layer may be made of AlInGaN with a thickness of 0.5 nm to 5.0 nm, for example. The intermediate layer may have a composition that changes stepwise between the barrier layer 240 made of AlInGaN and the spacer layer made of AlN. The intermediate layer may be provided as a layer whose composition gradually changes in the stacking direction of the stacked body 200.

[0034] Furthermore, a protective layer may be provided on the barrier layer 240. The protective layer is made of, for example, GaN and is provided as part of the stacked body 200. The protective layer can prevent the surface of the barrier layer 240 from being oxidized, and therefore can improve the process resistance of the stacked body 200 in the manufacturing process.

[0035] The protective layer may be made of a mixed crystal containing (Al)(In)(Ga)N other than GaN. (Al)(In)(Ga)N refers to a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. Furthermore, the protective layer may be made of a SiN film or the like other than the above. The thickness of the protective layer may be, for example, 0.5 nm to 5 nm, preferably 0.5 nm to 2 nm.

[0036] The gate electrode 322 is a gate terminal of the semiconductor device 10, which is a high electron mobility transistor (HEMT), and is provided, for example, on the stacked body 200 via an insulating film 321. The gate electrode 322 is formed, for example, by sequentially stacking Ni and Au from the stacked body 200 side. The insulating film 321 is formed, for example, of SiN, SiO2, or Al2O3. As described above, the semiconductor device 10 may be configured with an MIS (Metal-Insulator-Semiconductor) gate structure in which the gate electrode 322 is provided on the stacked body 200 via the insulating film 321. However, it goes without saying that the semiconductor device 10 may also be configured with a Schottky gate structure in which the gate electrode 322 is provided directly on the stacked body 200.

[0037] The source electrode 310S and the drain electrode 310D are the source terminal and the drain terminal of the semiconductor device 10, which is a high electron mobility transistor (HEMT), and are provided on both sides of the gate electrode 322 on the stacked body 200. The source electrode 310S and the drain electrode 310D are formed by sequentially stacking Ti, Al, Ni, and Au from the stacked body 200 side, for example.

[0038] A regrowth layer may be provided directly below the source electrode 310S and the drain electrode 310D. The regrowth layer is provided by removing a portion of the barrier layer 240 and the channel layer 230 directly below the regions where the source electrode 310S and the drain electrode 310D are to be provided, and then regrowing n-type GaN crystals in the recesses where the barrier layer 240 and the like have been removed. The regrowth layer is provided as a layer with lower resistance than the barrier layer 240, thereby reducing the resistance between the source electrode 310S and the drain electrode 310D and the channel formed in the channel layer 230.

[0039] Alternatively, Si may be implanted into the barrier layer 240 directly below the source electrode 310S and the drain electrode 310D. The Si-implanted barrier layer 240 can be annealed to further reduce its resistance. As a result, the Si-implanted barrier layer 240 can reduce the resistance between the source electrode 310S and the drain electrode 310D and the channel formed in the channel layer 230, similar to a regrown layer.

[0040] Next, the n-type imparting factors and compensation factors included in the stack 200 of the semiconductor device 10 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a graph diagram schematically showing concentration profiles of the n-type imparting factors and compensation factors in the stacking direction of the stack 200.

[0041] 2, the n-type conversion factor is Si (silicon), and the compensation factor is C (carbon). However, as described above, other n-type conversion factors that convert a nitride semiconductor into an n-type can include Ge (germanium) or O (oxygen) in addition to Si. Other compensation factors for the n-type conversion factor can include Mg (magnesium), Fe (iron), or B (boron) in addition to C.

[0042] 2, the concentration profile of Si (a factor for n-type conversion) in the stacked body 200 of the semiconductor device 10 has a peak near the mask layer 220 made of SiN. For example, the concentration profile of Si in the stacked body 200 has a peak near the mask layer 220, where the Si concentration is 6×10 18 cm -3 or more, and the Si concentration is 1×10 19 cm -3 It may have a peak of more than this.

[0043] Si, a group IV element, is an n-type donor that becomes an n-type donor by substituting Ga, a group III element, in a group III-V nitride semiconductor, and therefore makes it easier for current to flow in the channel layer 230 near the mask layer 220, which has a high Si concentration. As a result, in the semiconductor device 10 provided with the mask layer 220, electrons may be conducted in unintended regions, generating leakage current or parallel channels, which may result in a deterioration in on-off characteristics and an increase in power consumption.

[0044] In the semiconductor device 10, the compensation factor C is added to the upper layer side of the laminate 200 above the mask layer 220 where the Si concentration profile has a peak. 18 cm -3 A compensated region CA containing at least one of these elements is provided. In a III-V nitride semiconductor, C, a group IV element, substitutes for N (nitrogen), a group V element, and can function as a compensation factor that captures carriers supplied by Si, which is an n-type conversion factor. Therefore, the semiconductor device 10 can insulate the channel layer 230 near the mask layer 220, which has a high Si concentration, by controlling the concentration profile of C in the stacked body 200 and compensating for the n-type conversion caused by Si with C.

[0045] C (carbon) 6 x 10 18 cm -3 The thickness of the compensated region CA containing C at the above concentration is preferably about 100 nm, and a thicker thickness is preferable to obtain higher insulating properties. Furthermore, the compensated region CA can obtain higher insulating properties by containing C at a higher concentration. For example, the compensated region CA can further contain C at a concentration of 2×10 19 cm -3 It is preferable that the concentration is more than or equal to 100 ppm.

[0046] The concentration profile of C, which is a compensation factor, may be controlled so that the concentration of C is equal to or greater than the concentration of Si, which is a factor for n-type conversion, at a position where the concentration of Si, which is a factor for n-type conversion, reaches a peak. For example, the concentration profile of C, which is a compensation factor, may be controlled so that the concentration of Si, which is a factor for n-type conversion, reaches a peak where the concentration of C is equal to or greater than the concentration of Si, which is a factor for n-type conversion, at a position where the concentration of Si is equal to or greater than 6×10 18 cm -3 In the region where the concentration of C is 6×10 18cm -3 Alternatively, the concentration profile of C, which is a compensation factor, may be controlled so that the concentration of C is less than the concentration of Si, which is a factor for imparting n-type conductivity, at a position where the concentration of Si reaches a peak.

[0047] However, if the C concentration is excessively higher than the Si concentration, the crystallinity of the nitride semiconductor may be reduced. Also, if the C concentration is excessively lower than the Si concentration, the electrical characteristics of the semiconductor device 10 may be reduced. Therefore, it is desirable to appropriately set the C concentration profile at the position where the Si concentration peaks, taking into consideration the device characteristics required of the semiconductor device 10.

[0048] Next, the effects of the semiconductor device 10 according to this embodiment will be described.

[0049] First, the effect of the mask layer 220 will be described. In the semiconductor device 10 according to this embodiment, by introducing the mask layer 220 into the stacked body 200, the density of threading dislocations can be reduced to 4.0×10 9 cm -2 About 2.5 x 10 9 cm -2 That is, in the semiconductor device 10, the mask layer 220 can reduce the threading dislocation density by 35% or more. As a result, in the semiconductor device 10, the threading dislocation density on the surface of the stacked body 200 (the surface opposite to the surface on which the substrate 100 is provided) can be reduced to about 3×10 9 cm -2 Since the current can be reduced to or below the threshold, the occurrence of current collapse can be suppressed.

[0050] 3 and 4, the effect of the compensation factor in the stack 200 will be described. In the semiconductor device 10 according to this embodiment, by including a compensation factor in the stack 200 with a predetermined concentration profile, it is possible to further increase the sheet resistance Rsh of the channel layer 230 on the mask layer 220 side.

[0051] 3 is a graph plotting the relationship between the concentration at the peak of the C concentration profile and the sheet resistance Rsh of the channel layer 230 on the mask layer 220 side. In FIG. 3, the concentration at the peak of the Si concentration profile is 1×10 19 cm -3 The peak of the C concentration profile refers to a peak included in the compensated region CA provided in the layer stack 200 above the mask layer 220 that includes the peak of the Si concentration profile.

[0052] As shown in Figure 3, the C (carbon) concentration at the peak is 6 × 10 18 cm -3 When the C (carbon) content in the compensated region CA is 6×10 or more (the group plotted with circles in FIG. 3), the sheet resistance Rsh of the channel layer 230 is 400 Ω / sq or more, which is sufficient to suppress the leakage current. 18 cm -3 When the concentration is less than 400 Ω / sq (the group plotted with triangles in FIG. 3), the sheet resistance Rsh of the channel layer 230 does not reach 400 Ω / sq, which is sufficient to suppress leakage current. Therefore, in the graph shown in FIG. 3, it is considered that the higher the concentration of C, which is the compensation factor, the higher the insulating properties obtained, and the higher the sheet resistance Rsh of the channel layer 230 on the mask layer 220 side.

[0053] In particular, in the graph shown in Figure 3, the peak value of the C concentration is 6 × 10 18 cm -3 The sheet resistance Rsh of the channel layer 230 on the mask layer 220 side begins to increase rapidly from around 0.5 μm. Therefore, in order to sufficiently suppress the leakage current, the compensated region CA should have a compensation factor C of 6×10 18 cm -3 It is considered important to include the above.

[0054] FIG. 4 is a graph plotting the relationship between the distance between the peak of the Si concentration profile and the peak of the C concentration profile in the stacking direction of the stacked body 200 and the sheet resistance Rsh of the channel layer 230 on the mask layer 220 side.

[0055] The peak of the Si concentration profile represents a peak contained in the mask layer 220, and the peak of the C concentration profile represents a peak contained in the compensated region CA provided on the upper layer side of the stacked body 200. Therefore, the distance between the two peaks represents, for example, the distance pp between the highest point of the peak of the Si concentration profile and the highest point of the peak of the C concentration profile in FIG.

[0056] In addition, the group plotted with a circle in Figure 3 (the concentration of C at the peak is 6 × 10 18 cm -3 The group plotted with triangles in Figure 3 (the group with a C concentration of 6 × 10 or more at the peak) is also plotted with circles in Figure 4. 18 cm -3 The group of people with a mean score of less than 100 (the group of people with a mean score of less than 100) is also plotted with triangles in Figure 4.

[0057] As shown in FIG. 4, the closer the peak of the Si concentration profile and the peak of the C concentration profile are, the more C can compensate for the effect of Si, which is thought to result in a higher sheet resistance Rsh on the mask layer 220 side of the channel layer 230. However, when the distance between the two peaks is at least 150 nm or less, no correlation is observed between the distance between the two peaks and the sheet resistance Rsh. In other words, when the distance between the two peaks is 150 nm or less, the two peaks are thought to be sufficiently close to each other. Therefore, the sheet resistance of the channel layer 230 on the mask layer 220 side is thought to increase depending on the concentration at the peak of the C concentration profile, as shown in FIG.

[0058] <2. Manufacturing Method of Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device 10 according to this embodiment will be described with reference to Figures 5A to 5C. Figures 5A to 5C are schematic vertical cross-sectional views showing each step of the method for manufacturing the semiconductor device 10 according to this embodiment. Note that the manufacturing conditions and materials exemplified below are merely examples and do not limit the semiconductor device 10 according to this embodiment.

[0059] As shown in FIG. 5A, first, a stacked body 200 is formed on a substrate 100, which is a Si substrate, using a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or the like.

[0060] Specifically, first, an insulating Si substrate having a (111) plane as its main surface is prepared as the substrate 100. Next, the substrate 100 is placed in an MOCVD apparatus or MBE apparatus and thermally cleaned at 1000°C for about 10 minutes. Subsequently, AlN is layered on the substrate 100 to a thickness of 100 nm to 300 nm at 700°C to 1100°C, and then AlGaN is layered to a thickness of 100 nm to 500 nm at 900°C to 1100°C, thereby forming the buffer layer 210.

[0061] Next, a mask layer 220 is formed by stacking SiN to a thickness of 0.2 nm to 2 nm on the buffer layer 210 at 900° C. to 1000° C. When the mask layer 220 is made of SiN, the n-type imparting factor is Si.

[0062] Subsequently, GaN is deposited on the mask layer 220 at 900° C. to 1100° C. to a thickness of 500 nm to 2000 nm, thereby forming the channel layer 230.

[0063] In the semiconductor device 10 according to this embodiment, for example, the concentration profile of the compensation factor can be controlled by controlling the crystal growth conditions of the nitride semiconductor during the formation of the channel layer 230. Specifically, when the compensation factor is C (carbon), the C contained in the source gas of the channel layer 230 can be introduced into the channel layer 230 with a desired concentration profile by controlling the supply ratio, pressure, temperature, etc. of the source gases to the MOCVD apparatus or MBE apparatus. For example, when the channel layer 230 is made of GaN, the concentration profile of C contained in the channel layer 230 can be controlled by controlling the supply ratio, pressure, temperature, etc. of the source gases Ga(CH3)3 (trimethylgallium: TMGa) and NH3.

[0064] Thereafter, AlInN is deposited to a thickness of 3 nm to 20 nm at 700°C to 900°C on the channel layer 230 to form the barrier layer 240. A spacer layer may be further formed between the channel layer 230 and the barrier layer 240, by depositing AlN to a thickness of 0.5 nm to 5 nm at 900°C to 1100°C. Furthermore, a protective layer may be further formed on the barrier layer 240, by depositing GaN to a thickness of 0.5 nm to 5 nm at 700°C to 900°C.

[0065] 5B, a film of SiN, SiO, AlO, or the like is formed on the stacked body 200 by using a CVD method or the like to form an insulating film 321. Thereafter, using a resist mask with openings in the regions where the source electrode 310S and the drain electrode 310D are to be formed, the insulating film 321 corresponding to the openings is removed by wet etching.

[0066] 5C, the source electrode 310S and the drain electrode 310D are formed by sequentially stacking Ti, Al, Ni, and Au on the stacked body 200 in the region where the insulating film 321 has been removed. In addition, the gate electrode 322 is formed by sequentially stacking Ni and Au on the insulating film 321 between the source electrode 310S and the drain electrode 310D.

[0067] According to the above manufacturing method, the semiconductor device 10 according to this embodiment can be manufactured.

[0068] When a regrowth layer is provided directly below the source electrode 310S and the drain electrode 310D, the insulating film 321 is removed from the region where the source electrode 310S and the drain electrode 310D are to be formed, and then the barrier layer 240 and a portion of the channel layer 230 are removed by dry etching. Then, the regrowth layer can be formed by regrowing n-type GaN in the region removed by dry etching using MOCVD or sputtering. The n-type dopant for the regrowth layer can be, for example, Si or Ge.

[0069] It is also possible to form the mask layer 220 containing the n-type imparting factor and the channel layer 230 containing the compensation factor by a method other than the above.

[0070] For example, the substrate 100 on which layers up to the buffer layer 210 have been deposited may be removed from the MOCVD or MBE apparatus, and a mask layer 220 containing an n-type imparting factor made of SiN, SiO, TiN, or the like may be formed separately using a CVD method or the like. The substrate 100 may then be returned to the MOCVD or MBE apparatus, and a channel layer 230 may be deposited on the mask layer 220. The substrate 100 may then be removed from the MOCVD or MBE apparatus again, and a compensation factor such as B may be implanted into the channel layer 230 to form the channel layer 230 containing the compensation factor. Even with this method, the semiconductor device 10 can achieve both reduced threading dislocations and insulation near the mask layer 220.

[0071] <3. Specific examples of semiconductor devices> Next, first to ninth specific examples of the semiconductor device 10 according to this embodiment will be described with reference to Figures 6 to 14. The semiconductor devices 10A to 10I according to the first to ninth specific examples differ from one another in the layer structure and materials constituting the stacked body 200. Therefore, in the following, descriptions of the substrate 100, the source electrode 310S, the drain electrode 310D, the insulating film 321, and the gate electrode 322 will be omitted.

[0072] (First specific example) Fig. 6 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10A according to a first specific example. As shown in Fig. 6, in the semiconductor device 10A, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, a channel layer 230, a spacer layer 241, and a barrier layer 240.

[0073] The first buffer layer 211 is made of AlN, and the second buffer layer 212 is made of AlGaN. Like the buffer layer 210, the first buffer layer 211 and the second buffer layer 212 have a lattice constant that changes stepwise, allowing GaN, which has a lattice constant different from that of Si that constitutes the substrate 100, to grow with higher crystallinity.

[0074] The mask layer 220 is made of SiN containing Si, which is an n-type imparting factor. The mask layer 220 may be made of an extremely thin film of 0.2 nm to 2 nm, preferably 0.5 nm to 1 nm, or may be made of a thick film exceeding several nm.

[0075] The channel layer 230 is made of GaN. The channel layer 230 has a compensation factor C of 6×10 18 cm -3 A compensated area CA containing the above concentration is provided.

[0076] The spacer layer 241 is made of Al(In)(Ga)N. The spacer layer 241 can improve the characteristics of the semiconductor device 10 by suppressing fluctuations in composition at the interface between the barrier layer 240 and the channel layer 230. Al(In)(Ga)N represents a nitride semiconductor in which Al and N are essential elements and In and Ga are optional elements. Specifically, Al(In)(Ga)N is AlInGaN, AlGaN, AlInN, or AlN.

[0077] The barrier layer 240 is made of Al(In)(Ga)N. A two-dimensional electron gas (2DEG) is generated on the barrier layer 240 side of the channel layer 230 due to the junction between the barrier layer 240 and the channel layer 230. Al(In)(Ga)N represents a nitride semiconductor in which Al and N are essential elements and In and Ga are optional elements. Specifically, Al(In)(Ga)N is AlInGaN, AlGaN, AlInN, or AlN.

[0078] According to the semiconductor device 10A according to the first specific example, which includes the stacked body 200, it is possible to reduce the density of threading dislocations in the stacked body 200 without increasing the leakage current.

[0079] (Second specific example) Fig. 7 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10B according to a second specific example. As shown in Fig. 7, in the semiconductor device 10B, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a mask layer 220, a second buffer layer 212, a channel layer 230, a spacer layer 241, and a barrier layer 240.

[0080] The semiconductor device 10B according to the second specific example differs from the semiconductor device 10A according to the first specific example in that a mask layer 220 is provided between the first buffer layer 211 and the second buffer layer 212. In this case, the second buffer layer 212, the channel layer 230, or both of them provided on the upper layer side of the mask layer 220 are provided with a compensation factor C of 6×10 18 cm -3 A compensated area CA containing the above concentration is provided.

[0081] The mask layer 220 does not have to be provided directly below the channel layer 230, but may be provided in the stacked body 200 below the channel layer 230. Therefore, according to the semiconductor device 10B of the second specific example, similar to the semiconductor device 10A of the first specific example, it is possible to reduce the density of threading dislocations in the stacked body 200 without increasing the leakage current.

[0082] (Third specific example) Fig. 8 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10C according to a third specific example. As shown in Fig. 8, in the semiconductor device 10C, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a first channel layer 231, a mask layer 220, a second channel layer 232, a spacer layer 241, and a barrier layer 240. The first channel layer 231 and the second channel layer 232 are made of GaN.

[0083] The semiconductor device 10C according to the third specific example differs from the semiconductor device 10A according to the first specific example in that a mask layer 220 is provided between the first channel layer 231 and the second channel layer 232. In this case, the second channel layer 232 provided on the upper layer side of the mask layer 220 is provided with a compensation factor C of 6×10 18 cm -3 A compensated region CA containing the above concentration is provided. Furthermore, on the barrier layer 240 side of the second channel layer 232, a channel through which electrons supplied from the barrier layer 240 travel is formed.

[0084] The mask layer 220 is provided on the first channel layer 231 made of GaN, thereby reducing the density of threading dislocations in the second channel layer 232 and improving the crystallinity of the second channel layer 232. Therefore, according to the semiconductor device 10C according to the third specific example, similar to the semiconductor device 10A according to the first specific example, it is possible to reduce the density of threading dislocations in the stacked body 200 without increasing the leakage current.

[0085] (Fourth Specific Example) Fig. 9 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10D according to a fourth specific example. As shown in Fig. 9, in the semiconductor device 10D, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, an inter-mask layer 251, an upper mask layer 252, a channel layer 230, a spacer layer 241, and a barrier layer 240.

[0086] The inter-mask layer 251 is made of (Al)(In)(Ga)N and is provided on the mask layer 220. (Al)(In)(Ga)N represents a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. The upper mask layer 252 is made of SiN containing Si, which is an n-type imparting factor, and is provided on the inter-mask layer 251.

[0087] The semiconductor device 10D according to the fourth specific example differs from the semiconductor device 10A according to the first specific example in that a plurality of layers (mask layer 220 and upper mask layer 252) made of SiN are provided. The semiconductor device 10D according to the fourth specific example may be provided with three or more layers made of SiN by repeatedly stacking two layers, that is, an inter-mask layer 251 made of (Al)(In)(Ga)N and an upper mask layer 252 made of SiN, multiple times as a repeating unit. In such a case, the channel layer 230 provided above the uppermost upper mask layer 252 of the layers made of SiN may be provided with a compensation factor C of 6×10 18 cm -3 A compensated area CA containing the above concentration is provided.

[0088] The semiconductor device 10D according to the fourth specific example is provided with a plurality of layers made of SiN (the mask layer 220 and the upper mask layer 252), thereby making it possible to further reduce the occurrence of threading dislocations in the stacked body 200. Therefore, according to the semiconductor device 10D according to the fourth specific example, it is possible to further reduce the density of threading dislocations in the stacked body 200 without increasing the leakage current.

[0089] (Fifth Specific Example) Fig. 10 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10E according to a fifth example. As shown in Fig. 10, in the semiconductor device 10E, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a buffer layer 210, a mask layer 220, an inter-mask layer 251, an upper mask layer 252, a channel layer 230, a spacer layer 241, and a barrier layer 240.

[0090] The buffer layer 210 is made of AlN, and the mask layer 220 is made of SiN. The inter-mask layer 251 is made of (Al)(In)(Ga)N and is provided on the mask layer 220. (Al)(In)(Ga)N represents a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. The upper mask layer 252 is made of SiN containing Si, which is an n-type imparting factor, and is provided on the inter-mask layer 251.

[0091] The semiconductor device 10E according to the fifth specific example differs from the semiconductor device 10D according to the fourth specific example in that a buffer layer 210 is provided instead of the first buffer layer 211 and the second buffer layer 212.

[0092] Like the semiconductor device 10D according to the fourth specific example, the semiconductor device 10E according to the fifth specific example is provided with a plurality of layers made of SiN (the mask layer 220 and the upper mask layer 252), and therefore can further reduce the occurrence of threading dislocations in the stacked body 200. Therefore, according to the semiconductor device 10E according to the fifth specific example, it is possible to further reduce the density of threading dislocations in the stacked body 200 without increasing the leakage current.

[0093] (Sixth Specific Example) Fig. 11 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10F according to a sixth example. As shown in Fig. 11, in the semiconductor device 10F, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, a channel layer 230, a spacer layer 241, and a barrier layer 240.

[0094] The semiconductor device 10F according to the sixth specific example differs from the semiconductor device 10A according to the first specific example in that the channel layer 230 is made of (Al)(In)(Ga)N. (Al)(In)(Ga)N represents a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. The channel layer 230 provided on the upper side of the mask layer 220 contains a compensation factor C of 6×10 18 cm -3 A compensated area CA containing the above concentration is provided.

[0095] The channel layer 230 may be made of any nitride semiconductor as long as it can generate two-dimensional electron gas (2DEG) through a junction with the barrier layer 240. Therefore, according to the semiconductor device 10F according to the sixth specific example, it is possible to reduce the density of threading dislocations in the stack 200 without increasing the leakage current, similar to the semiconductor device 10A according to the first specific example.

[0096] (Seventh Specific Example) Fig. 12 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10G according to a seventh example. As shown in Fig. 12, in the semiconductor device 10G, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, a first channel layer 231, a second channel layer 232, a spacer layer 241, and a barrier layer 240.

[0097] The semiconductor device 10G according to the seventh specific example differs from the semiconductor device 10A according to the first specific example in that a first channel layer 231 and a second channel layer 232 are provided instead of the channel layer 230. The first channel layer 231 is made of GaN, and the second channel layer 232 is made of (Al)(In)(Ga)N. (Al)(In)(Ga)N represents a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN. The first channel layer 231, the second channel layer 232, or both, provided on the upper layer side of the mask layer 220 are provided with a compensation factor C of 6×10 18 cm -3 A compensated area CA containing the above concentration is provided.

[0098] The channel layer 230 may be made of any nitride semiconductor and layer structure as long as it can generate two-dimensional electron gas (2DEG) through a junction with the barrier layer 240. Therefore, according to the semiconductor device 10G according to the seventh specific example, similar to the semiconductor device 10A according to the first specific example, it is possible to reduce the density of threading dislocations in the stack 200 without increasing the leakage current.

[0099] (Eighth Specific Example) Fig. 13 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10H according to an eighth specific example. As shown in Fig. 13, in the semiconductor device 10H, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, a channel layer 230, a spacer layer 241, an intermediate layer 242, and a barrier layer 240.

[0100] The semiconductor device 10H according to the eighth specific example differs from the semiconductor device 10A according to the first specific example in that an intermediate layer 242 is further provided between the spacer layer 241 and the barrier layer 240. The intermediate layer 242 is made of (Al)(In)(Ga)N. (Al)(In)(Ga)N refers to a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN.

[0101] The intermediate layer 242 can further improve the crystallinity of the barrier layer 240 by gradually changing the composition of the nitride semiconductor between the barrier layer 240 and the spacer layer 241. As a result, the semiconductor device 10H according to the eighth specific example can further improve the device characteristics by improving the crystallinity of the barrier layer 240.

[0102] (Ninth Specific Example) Fig. 14 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 10I according to a ninth specific example. As shown in Fig. 14, in the semiconductor device 10I, a stacked body 200 is formed by stacking, in order from the substrate 100 side, which is a Si substrate, a first buffer layer 211, a second buffer layer 212, a mask layer 220, a channel layer 230, a spacer layer 241, a barrier layer 240, and a protective layer 243.

[0103] The semiconductor device 10I according to the ninth specific example differs from the semiconductor device 10A according to the first specific example in that a protective layer 243 is further provided on the barrier layer 240. The protective layer 243 is made of (Al)(In)(Ga)N. (Al)(In)(Ga)N refers to a nitride semiconductor in which N is an essential element and Al, In, and Ga are optional elements. Specifically, (Al)(In)(Ga)N is AlInGaN, AlGaN, AlInN, InGaN, AlN, InN, or GaN.

[0104] The protective layer 243 can prevent the surface of the barrier layer 240 from being oxidized, thereby improving the process resistance of the stacked body 200 in the manufacturing process. As a result, the semiconductor device 10I according to the ninth specific example can prevent the device characteristics from being deteriorated in the manufacturing process.

[0105] <4. Configuration example of wireless communication device> Next, a wireless communication device according to a second embodiment of the present disclosure will be described with reference to Fig. 15. Fig. 15 is a block diagram showing the configuration of a wireless communication device 1 according to this embodiment.

[0106] 15, the wireless communication device 1 includes an antenna ANT, a high-frequency switch 2, a high-power amplifier (HPA) 3, a radio frequency integrated circuit (RF IC) 4, a baseband unit 5, an audio output unit MIC, a data output unit DT, and an interface unit I / F. The wireless communication device 1 includes a semiconductor device 10 according to the first embodiment of the present disclosure as a semiconductor device included in the high-frequency switch 2, the high-power amplifier 3, the radio frequency integrated circuit 4, or the baseband unit 5.

[0107] The wireless communication device 1 is, for example, a mobile phone system that realizes multiple functions such as voice communication, data communication, LAN (Local Area Network) connection, etc. The wireless communication device 1 may be a mobile phone system compatible with the fifth generation mobile communication system (so-called 5G).

[0108] In the wireless communication device 1, during transmission, a transmission signal output from the baseband unit 5 is output to the antenna ANT via the high-frequency integrated circuit 4, the high-power amplifier 3, and the high-frequency switch 2. In addition, during reception in the wireless communication device 1, a reception signal received by the antenna ANT is input to the baseband unit 5 via the high-frequency switch 2 and the high-frequency integrated circuit 4. The reception signal processed by the baseband unit 5 is output from the audio output unit MIC, the data output unit DT, the interface unit I / F, or the like.

[0109] The wireless communication device 1 includes the semiconductor device 10 according to the first embodiment of the present disclosure in a circuit that handles a transmission signal or a reception signal, thereby enabling more efficient processing of higher-power signals.

[0110] Although the preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0111] For example, in the above embodiment, the semiconductor device 10 has been described as a high electron mobility transistor (HEMT), but the technology according to the present disclosure is not limited to the above example. The technology according to the present disclosure can also be similarly applied to various semiconductor devices that grow crystals of nitride semiconductors, such as light-emitting diodes, laser diodes, photodiodes, heterojunction bipolar transistors, field-effect transistors, and Schottky barrier diodes. Therefore, it is understood that the above various semiconductor devices are naturally included in the category of the semiconductor device according to the present embodiment.

[0112] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0113] The following configurations also fall within the technical scope of the present disclosure. (1) a channel layer included in a laminate of nitride semiconductors provided on a substrate; a barrier layer included in the stack above the channel layer; Equipped with the stacked body below the channel layer contains an n-type conversion factor that converts the nitride semiconductor to n-type, with a concentration profile having at least one peak in the stacking direction of the stacked body; The layered body above the peak of the concentration profile of the n-type conversion factor is provided with a compensation factor of 6×10 18 cm -3 A semiconductor device provided with the compensated region described above. (2) The semiconductor device according to (1) above, wherein the n-type impurity-imparting factor includes at least one of impurities and defects contained in the stack. (3) The semiconductor device according to (1) or (2) above, wherein the compensation factor includes at least one of an impurity and a defect contained in the stack. (4) The semiconductor device according to any one of (1) to (3) above, wherein the sheet resistance of the compensated region is 400 Ω / sq or more. (5) The threading dislocation density on the surface of the laminate opposite to the surface on which the substrate is provided is 3×10 9 cm -2 The semiconductor device according to any one of (1) to (4) above, which is: (6) The semiconductor device according to any one of (1) to (5) above, wherein the substrate includes at least one of Si, SiC, sapphire, GaN, AlN, and diamond. (7) The semiconductor device according to any one of (1) to (6) above, wherein the nitride semiconductor includes at least one of AlN, InN, GaN, AlGaN, InGaN, AlInGaN, AlScN, SiN, MgN, and TiN. (8) The semiconductor device according to any one of (1) to (7), wherein the compensated region has a peak in the concentration profile of the compensation factor in a region within 150 nm above the peak in the concentration profile of the n-type conversion factor. (9) The semiconductor device according to any one of (1) to (8) above, wherein the n-type imparting factor includes at least one of Si, Ge, and O. (10) The semiconductor device according to any one of (1) to (9) above, wherein the compensation factor includes at least one of C, Mg, Fe, and B. (11) The concentration profile of the n-type conversion factor in the stacking direction of the stacked body is such that the concentration of the n-type conversion factor is 6×10 18 cm -3 The semiconductor device according to any one of (1) to (10) above, wherein the semiconductor device includes the peaks equal to or greater than the peaks. (12) The semiconductor device according to (11) above, wherein the concentration of the compensation factor is equal to or higher than the concentration of the n-type factor at the position where the peak of the n-type factor exists. (13) The semiconductor device according to (11) above, wherein the concentration of the compensation factor is less than the concentration of the n-type factor at the position where the peak of the n-type factor exists. (14) The concentration profile of the n-type conversion factor in the stacking direction of the stacked body is such that the concentration of the n-type conversion factor is 1×10 19 cm -3 The semiconductor device according to any one of (11) to (13) above, wherein the peak is equal to or greater than the peak. (15) In the stacking direction of the stacked body, the concentration of the n-type conversion factor is 6×10 18 cm -3 In the above region, the concentration of the compensation factor is 6×10 18 cm -3 The semiconductor device according to any one of (1) to (12) above. (16) a gate electrode provided on a surface of the stack opposite to the surface on which the substrate is provided; a source electrode and a drain electrode provided on the opposite surface to sandwich the gate electrode; The semiconductor device according to any one of (1) to (15) above, further comprising: (17) A semiconductor device is provided, The semiconductor device includes: a channel layer included in a laminate of nitride semiconductors provided on a substrate; a barrier layer included in the stack above the channel layer; Including, the stacked body below the channel layer contains an n-type conversion factor that converts the nitride semiconductor to n-type, with a concentration profile having at least one peak in the stacking direction of the stacked body; The layered body above the peak of the concentration profile of the n-type conversion factor is provided with a compensation factor of 6×10 18 cm -3 A wireless communication device provided with the compensated area described above. [Explanation of symbols]

[0114] 10 Semiconductor devices 100 boards 200 laminate 210 Buffer Layer 211 First buffer layer 212 Second buffer layer 220 Mask Layer 230 Channel Layer 231 First Channel Layer 232 Second Channel Layer 240 Barrier Layer 241 Spacer layer 242 Middle Class 243 Protective layer 251 Inter-mask layer 252 upper mask layer 310D drain electrode 310S Source Electrode 321 Insulating Film 322 gate electrode

Claims

1. a channel layer included in a laminate of nitride semiconductors provided on a substrate; a barrier layer included in the stack above the channel layer; Equipped with the stacked body below the channel layer contains an n-type conversion factor that converts the nitride semiconductor to n-type, with a concentration profile having at least one peak in a stacking direction of the stacked body; The layered body above the peak of the concentration profile of the n-type conversion factor is provided with a compensation factor of 6×10 １８ cm －３ A semiconductor device provided with the compensated region described above.

2. 2. The semiconductor device according to claim 1, wherein the factor for providing n-type conductivity includes at least one of impurities and defects contained in the stacked layer.

3. 2. The semiconductor device according to claim 1, wherein the compensation factor includes at least one of an impurity and a defect contained in the stack.

4. 2. The semiconductor device according to claim 1, wherein the sheet resistance of said compensated region is 400 Ω / sq or more.

5. The threading dislocation density present on the surface of the laminate opposite to the surface on which the substrate is provided is 3×10 ９ cm －２ 2. The semiconductor device according to claim 1, wherein:

6. The semiconductor device according to claim 1 , wherein the substrate includes at least one of Si, SiC, sapphire, GaN, AlN, and diamond.

7. 2. The semiconductor device according to claim 1, wherein the nitride semiconductor includes at least one of AlN, InN, GaN, AlGaN, InGaN, AlInGaN, AlScN, SiN, MgN, and TiN.

8. 2. The semiconductor device according to claim 1, wherein the compensated region has a peak in the concentration profile of the compensation factor within 150 nm above the peak in the concentration profile of the n-type conversion factor.

9. The semiconductor device according to claim 1 , wherein the n-type imparting factor includes at least one of Si, Ge, and O.

10. The semiconductor device according to claim 1 , wherein the compensation factor includes at least one of C, Mg, Fe, and B.

11. The concentration profile of the n-type conversion factor in the stacking direction of the stacked body is such that the concentration of the n-type conversion factor is 6×10 １８ cm －３ The semiconductor device according to claim 1 , wherein the peak is equal to or greater than the peak.

12. 12. The semiconductor device according to claim 11, wherein the concentration of the compensation factor is equal to or greater than the concentration of the n-type factor at the position where the peak of the n-type factor exists.

13. 12. The semiconductor device according to claim 11, wherein the concentration of the compensation factor is less than the concentration of the n-type factor at the position where the peak of the n-type factor exists.

14. The concentration profile of the n-type conversion factor in the stacking direction of the stacked body is such that the concentration of the n-type conversion factor is 1×10 １９ cm －３ The semiconductor device according to claim 11 , wherein the peak is equal to or greater than the peak.

15. In the stacking direction of the stacked body, the concentration of the n-type conversion factor is 6×10 １８ cm －３ In the above region, the concentration of the compensation factor is 6×10 １８ cm －３ 2. The semiconductor device according to claim 1, wherein:

16. a gate electrode provided on a surface of the stack opposite to the surface on which the substrate is provided; a source electrode and a drain electrode provided on the opposite surface to sandwich the gate electrode; The semiconductor device according to claim 1 , further comprising:

17. A semiconductor device is provided, The semiconductor device includes: a channel layer included in a laminate of nitride semiconductors provided on a substrate; a barrier layer included in the stack above the channel layer; Including, the stacked body below the channel layer contains an n-type conversion factor that converts the nitride semiconductor to n-type, with a concentration profile having at least one peak in a stacking direction of the stacked body; The layered body above the peak of the concentration profile of the n-type conversion factor is provided with a compensation factor of 6×10 １８ cm －３ A wireless communication device provided with the compensated area described above.

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