Indication device

Abstract

To provide a semiconductor device with a high aperture ratio.SOLUTION: A semiconductor device includes a transistor and a capacitor having a pair of electrodes, and a channel formation region of the transistor and one electrode of the capacitor are formed of an oxide semiconductor layer on the same insulating surface, and the other electrode of the capacitor is a light-transmitting conductive film. One electrode of the capacitor is electrically connected to a wiring formed on the same insulating surface as the insulating surface on which a source electrode or a drain electrode of the transistor is formed, and the other electrode of the capacitor is electrically connected to one of the source electrode or the drain electrode of the transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a In particular, the present invention relates to a semiconductor device having an oxide semiconductor, The present invention relates to a display device or a light-emitting device, and a manufacturing method thereof. [Background technology]

[0002] In recent years, flat panel displays such as liquid crystal displays (LCDs) have become widely used. In a display device such as a flat panel display, pixels are arranged in the row and column directions. In the pixel, a transistor which is a switching element and an electric a liquid crystal element connected in series to the liquid crystal element, and a capacitance element connected in parallel to the liquid crystal element. do.

[0003] The semiconductor material constituting the semiconductor film of the transistor is amorphous (non-crystalline) silicon. Silicon semiconductors such as silicon or polysilicon are widely used.

[0004] Metal oxides that exhibit semiconductor properties (hereinafter referred to as oxide semiconductors) are used as semiconductors for transistors. It is a semiconductor material that can be used for conductor films. For example, zinc oxide or In-Ga-Zn oxide Techniques for fabricating transistors using semiconductors have been disclosed (Patent Document 1 and Patent Document 2). See reference 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0006] The capacitance element has a pair of electrodes and a dielectric film between the pair of electrodes. One electrode is a gate electrode, a source electrode, a drain electrode, or the like that constitutes a transistor. Since it is made of the same material as the many.

[0007] In addition, the larger the capacitance value of the capacitance element, the more the liquid crystal of the liquid crystal element will change when an electric field is applied. The period during which the molecular orientation can be kept constant can be extended. In a display device capable of rewriting image data, the ability to extend the period is advantageous. This reduces the number of times, which is expected to reduce power consumption.

[0008] In order to increase the charge capacity of the capacitance element, the area occupied by the capacitance element in the pixel must be increased. Specifically, there is a means to increase the area where the pair of electrodes overlap. However, in the above display device, in order to increase the area where the pair of electrodes overlap, Increasing the area of ​​the conductive film having this property reduces the aperture ratio of the pixel, resulting in a deterioration in the display quality of the image. do.

[0009] In view of the above, one embodiment of the present invention provides a semiconductor device or the like having a high aperture ratio. Alternatively, the present invention has a capacitor element capable of increasing the charge capacity. One of the objects is to provide a semiconductor device or the like. One object is to provide a semiconductor device or the like that can reduce the number of masks. Another object is to provide a semiconductor device or the like with low off-state current. One of the objects is to provide a semiconductor device or the like that consumes less power. One of the objects is to provide a semiconductor device using a conductor layer. One of the objectives is to provide a semiconductor device that is easy on the eyes. One of the objects is to provide a novel semiconductor device, etc. Another object is to provide a method for manufacturing a novel semiconductor device or the like. It shall be one.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device in which an oxide semiconductor layer serves as one electrode and a light-transmitting conductive film serves as the other electrode. The present invention relates to a semiconductor device including a light-transmitting capacitor element.

[0012] One embodiment of the present invention is a semiconductor device having a transistor, wherein a first insulating film is formed over the first insulating film. a first oxide semiconductor layer and a second oxide semiconductor layer, and a source electrode layer and a drain electrode layer electrically connected to the second oxide semiconductor layer; The first insulating film, the first oxide semiconductor layer, the second oxide semiconductor layer, the source a second insulating film formed on the source electrode layer, the drain electrode layer, and the wiring; a gate electrode layer overlapping the first oxide semiconductor layer with an insulating film interposed therebetween; a second insulating film; and a gate electrode a third insulating film formed on the layer; a fourth insulating film formed on the third insulating film; and a second insulating film. a light-transmitting conductive film formed on a fourth insulating film over the oxide semiconductor layer, a first electrode formed on the second oxide semiconductor layer; The semiconductor device is characterized by having a capacitor element at least part of which serves as a second electrode.

[0013] The first oxide semiconductor layer and the second oxide semiconductor layer are preferably formed of the same material. I wish.

[0014] The first oxide semiconductor layer and the second oxide semiconductor layer have an energy gap of 2. It is preferably 0 eV or more.

[0015] The second oxide semiconductor layer is doped with hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, or indium. One or more dopants selected from the group consisting of tungsten, tin, antimony and rare gas elements are added. It may also be used.

[0016] The dielectric may be formed of a second insulating film, a third insulating film, and a fourth insulating film.

[0017] The dielectric may also be formed of a third insulating film and a fourth insulating film.

[0018] The dielectric may also be formed of a fourth insulating film.

[0019] The third insulating film may be made of silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. A single layer structure of an oxide insulating material selected from aluminum, gallium oxide, or Ga-Zn-based metal oxides. It is preferable to form it in a laminated structure.

[0020] The fourth insulating film may be made of silicon oxynitride, silicon nitride, aluminum nitride, or nitride oxide. It is preferable to form the insulating film with a single layer structure or a laminated structure of a nitride insulating material selected from aluminum. It's nice.

[0021] In addition, a nitride insulating film containing hydrogen is formed between the first insulating film and the second oxide semiconductor layer. It's fine.

[0022] The source electrode layer, the drain electrode layer, and the wiring are formed on the same insulating surface. It can be said that:

[0023] The source electrode layer, the drain electrode layer, and the wiring may be formed of the same material. This can be done.

[0024] The transparent conductive film is electrically connected to either the source electrode or the drain electrode. It can be concluded that

[0025] Another embodiment of the present invention is a method for forming a first oxide semiconductor layer and a second oxide semiconductor layer over a first insulating film. a source electrode layer and a drain electrode layer electrically connected to the first oxide semiconductor layer; The first oxide semiconductor layer is formed on the first insulating film and the second insulating film is formed on the second insulating film. Insulating film, first oxide semiconductor layer, second oxide semiconductor layer, source electrode layer, drain electrode layer and forming a second insulating film over the wiring, and forming a first oxide semiconductor layer on the second insulating film so as to overlap the first oxide semiconductor layer. a gate electrode layer is formed on the second insulating film and the gate electrode layer; and a third insulating film is formed on the second insulating film and the gate electrode layer. a fourth insulating film is formed on the third insulating film; and a second insulating film, a third insulating film, and a fourth insulating film are formed on the third insulating film. An opening leading to the source electrode layer or the drain electrode layer is formed in the insulating film, and a second insulating film is formed on the fourth insulating film. forming a light-transmitting conductive film electrically connected to the source electrode layer or the drain electrode layer in the opening; a transistor, at least a part of the second oxide semiconductor layer as a first electrode, a second electrode and forming a capacitor element having at least a part of a transparent conductive film and a dielectric layer as the light-transmitting layer. The present invention provides a method for manufacturing a semiconductor device.

[0026] The first oxide semiconductor layer and the second oxide semiconductor layer are preferably formed of the same material. .

[0027] The first oxide semiconductor layer and the second oxide semiconductor layer have an energy gap of 2. It is preferable to form it from a material having a voltage of 0 eV or more.

[0028] In addition, the second oxide semiconductor layer may contain hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, or arsenic. , indium, tin, antimony, and one or more dopants selected from the group consisting of rare gas elements It may be added.

[0029] The dielectric may be formed of a second insulating film, a third insulating film, and a fourth insulating film.

[0030] Also, the second insulating film on the second oxide semiconductor layer is etched, and the dielectric is formed by etching the third insulating film and the The second insulating film may be formed of a third insulating film and a fourth insulating film.

[0031] The second insulating film and the third insulating film on the second oxide semiconductor layer are etched to form a dielectric film. The body may be formed of a fourth insulating film.

[0032] The third insulating film may be made of silicon oxide, silicon oxynitride, aluminum oxide, or hafnium oxide. A single layer structure of an oxide insulating material selected from aluminum, gallium oxide, or Ga-Zn-based metal oxides. It is preferable to form it in a laminated structure.

[0033] The fourth insulating film may be made of silicon nitride oxide, silicon nitride, aluminum nitride, or nitride oxide. It is preferable to form the insulating film with a single layer structure or a laminated structure of a nitride insulating material selected from aluminum. It's nice.

[0034] Furthermore, a nitride insulating film containing hydrogen may be formed between the first insulating film and the second oxide semiconductor layer. good.

[0035] In addition, it is preferable that the source electrode layer, the drain electrode layer, and the wiring are formed using the same material. .

[0036] The source electrode layer, the drain electrode layer, and the wiring are formed on the same insulating surface. It is preferable that [Effects of the Invention]

[0037] According to one embodiment of the present invention, a semiconductor device or the like with a high aperture ratio can be provided. It is possible to provide a semiconductor device having a capacitive element capable of increasing the load capacity. Alternatively, a semiconductor device that can reduce the number of masks used in the photolithography process may be used. Alternatively, a semiconductor device with low off-state current or the like can be provided. Alternatively, a semiconductor device or the like with reduced power consumption can be provided. It is possible to provide a semiconductor device using a transparent semiconductor layer. It is possible to provide a semiconductor device that is easy on the eyes. Alternatively, a method for manufacturing a semiconductor device can be provided. [Brief explanation of the drawings]

[0038] [Figure 1] 1A and 1B are top views illustrating a semiconductor device. [Figure 2] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 3] 1A to 1C illustrate a semiconductor device. [Figure 4] FIG. 1 is a circuit diagram illustrating a pixel of a semiconductor device. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Figure 7] 1 is a cross-sectional view illustrating a capacitor of a semiconductor device. [Figure 8] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 9] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 10] 10A and 10B show electron microbeam diffraction patterns of oxide semiconductor films. [Figure 11] 10A and 10B show CPM measurement results of an oxide semiconductor film. [Figure 12] FIG. 1 shows the results of CPM measurement of a CAAC-OS film. [Figure 13] Cross-sectional TEM image and micro-electron diffraction pattern of an oxide semiconductor film. [Figure 14] Planar TEM image and selected area electron diffraction pattern of an oxide semiconductor film. [Figure 15] Schematic diagram of electron beam diffraction intensity distribution. [Figure 16] Ultrafine electron diffraction pattern of a quartz glass substrate. [Figure 17] Ultra-fine electron diffraction pattern of an oxide semiconductor film. [Figure 18]Cross-sectional TEM image of an oxide semiconductor film. [Figure 19] X-ray diffraction analysis results of oxide semiconductor film. [Figure 20] Cross-sectional TEM image of CAAC-OS film. [Figure 21] Electron diffraction pattern of the CAAC-OS film. [Figure 22] Cross-sectional TEM image of CAAC-OS film. [Figure 23] Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Figure 24] Electron diffraction pattern of the CAAC-OS film. [Figure 25] Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Figure 26] Electron diffraction pattern of the CAAC-OS film. [Figure 27] Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Figure 28] Electron diffraction pattern of the CAAC-OS film. [Figure 29] 1A and 1B are top views illustrating a semiconductor device. [Figure 30] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 31] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device. [Figure 32] FIG. 1 is a block diagram illustrating a configuration of an information processing device having a display function. [Figure 33] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration of a display unit of an information processing device. [Figure 34] 1A and 1B are a block diagram illustrating a configuration of an information processing apparatus and a schematic diagram illustrating image data. [Figure 35] FIG. 10 is a diagram illustrating the effect of the information processing device. [Figure 36] FIG. 1 is a block diagram illustrating an information processing apparatus. [Figure 37] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 38] 1A to 1C illustrate electronic devices using semiconductor devices. [Figure 39]1A to 1C illustrate electronic devices using semiconductor devices. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0040] In the configuration of the present invention described below, the same parts or parts having similar functions are designated as identical. The same reference numerals are used in common among different drawings, and repeated explanations thereof will be omitted. When referring to a part that has a function, the hatch pattern is the same and no particular symbol is attached. be.

[0041] In each figure described herein, the size of each structure, film thickness, or area is shown for clarity. The figures may be exaggerated for illustrative purposes only and are not necessarily limited to that scale.

[0042] In this specification and elsewhere, ordinal numbers such as 1st, 2nd, etc. are used for convenience, It does not indicate the order of processes or stacking layers. It does not indicate a specific name for the matter.

[0043] Voltage refers to the potential difference between two points, and potential refers to the electrostatic field at a certain point. It refers to the electrostatic energy (electrical potential energy) of a unit charge in a particle. Generally, the potential difference between the potential at a certain point and a reference potential (for example, ground potential) is This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, the term "potential" may be read as "voltage" or Voltage may be read as potential.

[0044] In this specification, when etching is performed after photolithography, The resist mask formed by the photolithography process is removed.

[0045] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a semiconductor device according to one embodiment of the present invention will be described using a liquid crystal display device as an example. Note that the semiconductor device which is one embodiment of the present invention can also be applied to other display devices. Cut.

[0046] 3 illustrates a semiconductor device according to one embodiment of the present invention. The element 100, the first driving circuit 104, and the second driving circuit 106 are arranged in parallel or substantially parallel to each other. m scanning lines 10 arranged in parallel and having potentials controlled by a first driving circuit 104 7 are arranged parallel or approximately parallel to each other, and the potential is controlled by a second driving circuit 106. The pixel section 100 has n signal lines 109 that are controlled by the signal lines 109. The semiconductor device has a plurality of pixels 101. The capacitance lines 115 are arranged parallel or approximately parallel to the scanning lines 107. Alternatively, they are arranged parallel or approximately parallel to each other along the signal line 109 .

[0047] Each scanning line 107 corresponds to any one of the pixels 101 arranged in m rows and n columns in the pixel section 100. Each signal line 109 is electrically connected to n pixels 101 arranged in a row. , m pixels 101 arranged in any one of the columns of the pixels 101 arranged in m rows and n columns. Both m and n are integers equal to or greater than 1. Each capacitance line 115 is electrically connected to , n pixels 101 arranged in any one of the rows of the pixels 101 arranged in m rows and n columns. The capacitance lines 115 are electrically connected to the signal lines 109. When the pixels 101 are arranged in approximately parallel rows and columns, one of the pixels 101 arranged in m rows and n columns It is electrically connected to m pixels 101 arranged in a column.

[0048] The first driving circuit 104 switches the transistor connected to the scanning line 107. For example, the circuit can have a function of supplying signals to the display device, such as a function as a scanning line driver circuit. The second driver circuit 106 supplies a video signal to a transistor connected to a signal line 109. For example, it can have a function as a signal line driver circuit. However, the first drive circuit 104 and the second drive circuit 106 may supply different signals. is also possible.

[0049] In addition, in this embodiment, a liquid crystal display device will be described as an example, and for convenience, the first driving circuit The wiring connected to the line 104 is called the scanning line 107 and the capacitance line 115, and the second driving circuit 106 The wiring connected to the signal line 109 is called the signal line 109, but the name does not limit the function. do not have.

[0050] FIG. 1 is a top view illustrating an example of the configuration of a pixel 101 included in the semiconductor device. In FIG. 1, one of a pair of electrodes of the liquid crystal layer and the liquid crystal element is omitted. .

[0051] In the pixel 101 shown in FIG. 1, the scanning line 107 extends in a direction substantially perpendicular to the signal line 109 (the direction The signal lines 109 extend in a direction (column direction) substantially perpendicular to the scanning lines 107. The capacitance line 115 is provided so as to extend in a direction parallel to the signal line 109. The scanning lines 107 are electrically connected to the first driving circuit 104 (see FIG. 3). The signal line 109 is electrically connected to the second driving circuit 106 (see FIG. 3). are.

[0052] The transistor 103 is provided near the area where the scanning line 107 and the signal line 109 intersect. The transistor 103 includes at least a semiconductor film 111 having a channel formation region. , a gate electrode, a gate insulating film (not shown in FIG. 1), a source electrode, and a drain electrode. Note that the region of the scan line 107 that overlaps with the semiconductor film 111 is the region of the transistor 103. The signal line 109 functions as a gate electrode of the semiconductor film 111. The conductive film 11 functions as one of a source electrode and a drain electrode of the transistor 103. 3, the region overlapping with the semiconductor film 111 is the source electrode or drain electrode of the transistor 103. Therefore, the gate electrode, source electrode, and drain electrode These may be referred to as a scanning line 107, a signal line 109, and a conductive film 113, respectively. In the top view, the end of the scanning line 107 is positioned outside the end of the semiconductor film 111. Therefore, the scanning lines 107 function as a light-shielding film that blocks external light. The semiconductor film 111 included in the transistor is not irradiated with light, and the electrical characteristics of the transistor are not changed. This can suppress movement.

[0053] In one embodiment of the present invention, an oxide semiconductor is preferably used for the semiconductor film 111. Transistors using semiconductors can be fabricated under appropriate conditions to have extremely low off-state current. Therefore, the power consumption of the semiconductor device can be reduced.

[0054] In one embodiment of the present invention, the transistor including an oxide semiconductor is an n-channel transistor. In addition, oxygen vacancies in oxide semiconductors can generate carriers, This may degrade the electrical characteristics and reliability of the transistor. The threshold voltage shifts in the negative direction, and the drain current flows when the gate voltage is 0V. In this way, drain current may flow when the gate voltage is 0V. This is called a normally-on characteristic. When the gate voltage is 0V, the drain current flows. A transistor that can be considered as having no gate voltage is called a normally-off transistor.

[0055] Therefore, when an oxide semiconductor is used for the semiconductor film 111, It is preferable that defects (typically oxygen vacancies) contained in the membrane are reduced as much as possible. For example, the g value of 1000 times higher than that of the ... The spin density of 0.93 (corresponding to the defect density in the oxide semiconductor film) was detected by the measuring instrument. It is preferable that the number of defects contained in the oxide semiconductor film is reduced to the lower limit or less. By reducing the current, the transistor 103 is prevented from becoming a normally-on transistor. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0056] The negative shift in the threshold voltage of a transistor is not only due to oxygen vacancies, but also to oxide semiconductors. It can also be caused by hydrogen (including hydrogen compounds such as water) contained in the conductor. Some of the hydrogen contained in the oxide semiconductor contributes to the formation of donor levels, and electrons, which are carriers, Therefore, a transistor using an oxide semiconductor containing hydrogen tends to be normally-on.

[0057] Therefore, when an oxide semiconductor is used for the semiconductor film 111, the oxide semiconductor It is preferable that the film has as little hydrogen as possible. Secondary Ion Mass Spectrometry (SIMS) The hydrogen concentration obtained is 5×10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 Further details are as follows: Preferably 1 x 10 16 atoms / cm 3 The semiconductor film 11 has the following regions: Form 1.

[0058] In addition, the concentration of alkali metals or alkaline earth metals obtained by secondary ion mass spectrometry 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Below It is preferable to form the semiconductor film 111 so as to have a region under the alkali metal. When alkaline earth metals and oxide semiconductors are bonded, they can generate carriers. This may increase the off-state current of the transistor 103.

[0059] In addition, when nitrogen is contained in the oxide semiconductor film that is the semiconductor film 111, the electrons that are carriers This increases the carrier density and makes it easier to become n-type. Transistors using oxide semiconductors tend to be normally-on. In the nitride semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, nitrogen The concentration is 5 x 10 18 atoms / cm 3 The semiconductor film 111 has the following regions: It is preferable to form

[0060] In this way, impurities (hydrogen, nitrogen, alkali metals or alkaline earth metals, etc.) can be removed. The semiconductor film 111 is formed by reducing the amount of ions contained in the oxide semiconductor film as much as possible and purifying it to a high degree. This can prevent the transistor 103 from becoming normally on, and the off-current of the transistor 103 can be reduced. Therefore, a semiconductor device having good electrical characteristics can be manufactured. In addition, a semiconductor device with improved reliability can be manufactured.

[0061] Note that the off-state current of a transistor using a highly purified oxide semiconductor film is low. This can be proved by various experiments. For example, when the channel width is 1×10 6 The channel length L in μm Even with a 10 μm element, the voltage between the source and drain electrodes (drain voltage) is 1 V. In the range of 10V to 10V, the off-state current is below the measurement limit of the semiconductor parameter analyzer. That is, 1 x 10 -13 In this case, the transistor The off-state current, which corresponds to the value obtained by dividing the value by the channel width, was found to be 100 zA / μm or less. In addition, by connecting the capacitance element and the transistor, the current flowing into or out of the capacitance element can be reduced. The off-state current was measured using a circuit that controls the outflow of charge using the transistor. In the measurement, a highly purified oxide semiconductor film was used for a channel formation region of the transistor. The off-state current of the transistor is measured from the change in the amount of charge per unit time of the capacitor. As a result, when the voltage between the source and drain electrodes of the transistor was 3 V, several tens of It was found that an extremely low off-state current of yA / μm was obtained. A transistor using a modified oxide semiconductor film has an extremely small off-state current. can.

[0062] In FIG. 1, the conductive film 113 is formed of a conductive film that transmits light through the opening 117. It is electrically connected to a pixel electrode 121 which is one of the electrodes of the liquid crystal element.

[0063] The capacitor 105 has a semiconductor film 119 formed of a light-transmitting oxide semiconductor. The pixel electrode 121 having light transmitting property is the other electrode, and the transistor 103 The dielectric film is a light-transmitting insulating film (not shown in FIG. 1). The capacitor 105 has a light-transmitting property. 119 is electrically connected to the capacitance line 115 .

[0064] In this manner, since the capacitor 105 has a light-transmitting property, the capacitor 105 transmits light even in the overlapping region with the liquid crystal element. Therefore, the capacitance element 105 can be made large (large surface area) in the pixel 101. Even if the film is formed in a multi-layer structure, the aperture ratio can be increased to, for example, 55% or more, or even 60% or more. Furthermore, a semiconductor device with an increased charge capacity in the capacitor element can be obtained.

[0065] For example, in a high-resolution liquid crystal display device, the area of ​​the entire pixel is reduced, but the capacitance element The necessary charge capacity must be secured in the element, and there is a limit to how much the area can be reduced. Therefore, in a liquid crystal display device with high resolution, the aperture ratio becomes small. Since the capacitor 105 shown in the embodiment has a light-transmitting property, the capacitor can be provided in the pixel. This allows each pixel to have a sufficient charge capacity while increasing the aperture ratio. , high-resolution LCD display devices with pixel densities of 200 ppi or more, and even 300 ppi or more. In addition, one embodiment of the present invention is suitable for use in a device that can increase the aperture ratio. This allows for efficient use of light from light sources such as backlights, reducing the power consumption of the display device. can be reduced.

[0066] Next, the dashed lines A1-A2, B1-B2, and C1-C2 shown in FIG. 4 is a cross-sectional view of a transistor used in the first driver circuit 104 shown in FIG. 2. Note that a top view of the first driver circuit 104 is omitted, and in FIG. , a cross-sectional view of the first driving circuit 104 is shown as D1-D2. The transistor used in the second driver circuit 106 can also be used in the second driver circuit 106.

[0067] First, the dashed lines A1 and A2 of the pixel 101, the dashed lines B1 and B2, and the dashed lines The cross-sectional structure between C1 and C2 will be described.

[0068] A base insulating film 110 is provided on a substrate 102, and a semiconductor film 111 and a semiconductor layer 112 are formed on the base insulating film. A conductive film 119 is provided on the semiconductor film 111. The source electrode of the transistor 103 is formed on the semiconductor film 111. a signal line 109 including either a source or drain electrode of the transistor 103; A conductive film 113 including the other of the electrode and the drain electrode is provided on the semiconductor film 119. A measurement line 115 is provided. A semiconductor film 111, a semiconductor film 119, a signal line 109, a conductive film A gate insulating film 127 is provided on the capacitor line 115. The scanning line 107 is provided on the region overlapping with the semiconductor film 111. 7, the signal line 109, the semiconductor film 111, the conductive film 113, and the semiconductor film 119. The insulating film 129 and the insulating film 131 function as a protective insulating film for the transistor 103, and the insulating film The insulating film 129, the insulating film 131, and the insulating film 132 are provided with conductive layers. An opening 117 (see FIG. 1) reaching the film 113 is provided, and a pixel is formed to cover the opening. An electrode 121 (see FIG. 1) is provided.

[0069] In the capacitor 105 shown in this embodiment, one of a pair of electrodes is formed over a base insulating film 110. The semiconductor film 119 is formed in the same manner as the semiconductor film 111. The other electrode is a pixel electrode 121, and the dielectric film provided between the pair of electrodes is an insulating film 12 9, insulating film 131, and insulating film 132.

[0070] Note that a dopant may be added to the semiconductor film 119. In the case of semiconductors, for example, hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, Adding one or more dopants selected from indium, tin, antimony and rare gas elements By adding an N-type impurity, the oxide semiconductor layer can be made n-type, and the conductivity can be increased. The semiconductor film 119 can also be called a conductive film, and can be used as one electrode of a capacitor. This can be done.

[0071] The semiconductor film 119 acting as a conductive film has a higher hydrogen concentration than the semiconductor film 111. It is preferable that the semiconductor film 119 is subjected to secondary ion mass spectrometry (SIMS). The hydrogen concentration obtained by ion mass spectrometry (IMS) is x10 19 atoms / cm 3 or more, preferably 1 × 10 20 atoms / cm 3 That's all, More preferably, 5 × 10 20 atoms / cm 3 In the semiconductor film 111, The hydrogen concentration obtained by secondary ion mass spectrometry is 5×10 19 atoms / cm 3 below , preferably 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 ato ms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 The following are more preferred: 1×10 16 atoms / cm 3 The following is the result.

[0072] In addition, the semiconductor film 119 acting as a conductive film has a lower resistivity than the semiconductor film 111. The resistivity of the semiconductor film 119 is 1×10 ―8 1×10 times more ―1 more than twice It is preferable that the concentration is less than 1×10 ―3 Ωcm or more 1×10 4 Less than Ωcm, More preferably, the resistivity is 1×10 ―3 Ωcm or more 1×10 ―1 It is better if it is less than Ωcm .

[0073] The semiconductor film 119 is made of a material different from that of the semiconductor film 111 or the semiconductor film 231. That is, the semiconductor film 119 can be formed by using the semiconductor film 111 or the semiconductor film 112. It is also possible to form the conductive film 231 using a different process.

[0074] A semiconductor film is formed in the same manner as the semiconductor film 119, and a resistor element is constructed using the semiconductor film. It is also possible to configure a protection circuit using the resistor element. By providing a protection circuit, damage caused by static electricity etc. can be reduced. .

[0075] Next, the structure of the transistor provided in the first driver circuit 104 will be described.

[0076] A conductive film 241 is provided on a substrate 102, and a base insulating film is provided on the substrate and the conductive film. In a region on the base insulating film 110 that overlaps with the conductive film 241, a semiconductor A semiconductor film 231 is provided on the semiconductor film 231. The source electrode of the transistor 223 is provided on the semiconductor film 231. or a wiring 229 including one of the drain electrodes and a source electrode or The semiconductor film 231 and the wiring 22 are connected to each other. 9. The gate insulating film 127 is provided on the wiring 233. A gate electrode 227 is provided on the region overlapping the gate insulating film 127. On the top, on the gate electrode 227, an insulating film 1 is formed, which functions as a protective insulating film for the transistor 223. 29, an insulating film 131, and an insulating film 132 are provided. The transistor provided in 4 may not include the conductive film 241.

[0077] In the transistor 223, a conductive film overlapping the gate electrode 227 with the semiconductor film 231 interposed therebetween By providing the film 241, the rise of the gate voltage of the on-current is In addition, the semiconductor film 231 facing the conductive film 241 can be prevented from being uneven. In this case, it is possible to control the current flowing between the wiring 229 and the wiring 233. This can reduce variations in electrical characteristics between transistors. By providing 41, the influence of the change in the surrounding electric field on the semiconductor film 231 is reduced, and the transistor Furthermore, the potential of the conductive film 241 can be controlled by the driver circuit. (Vss, for example, the potential of the wiring 229 when the potential of the wiring 229 is used as the reference) By making the potential equal to or equal to that, the fluctuation of the threshold voltage of the transistor is reduced. This makes it possible to improve the reliability of the transistor.

[0078] The insulating films provided on the gate insulating film 127, the scanning line 107, and the gate electrode 227 are: The structure is not limited to the three layers described above, and may be one layer, two layers, or four or more layers.

[0079] Next, the components of the above structure will be described in detail.

[0080] There is no particular restriction on the material of the substrate 102, but at least in the manufacturing process of the semiconductor device, For example, glass substrates, ceramic substrates, etc. There are various substrates, such as ceramic substrates and plastic substrates, and glass substrates are made of barium borosilicate Glass, alkali-free glass such as aluminoborosilicate glass or aluminosilicate glass It is also possible to use a substrate that does not have light-transmitting properties, such as a stainless steel alloy. In this case, it is preferable to provide an insulating film on the surface of the substrate. Examples include quartz substrates, sapphire substrates, single crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor substrates. Substrates, SOI (Silicon On Insulator) substrates, etc. can also be used. Cut.

[0081] The base insulating film 110 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn based metals The insulating material may be an oxide or other insulating material, and may be formed in a single layer structure or a multilayer structure. The thickness of one region of the vein film 110 is 30 nm or more and 500 nm or less, preferably 150 nm or more. 400nm or less.

[0082] The semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 are formed using oxide semiconductor films. The oxide semiconductor film preferably has an amorphous structure, a single crystal structure, or a polycrystalline structure. The thickness of one region of the semiconductor film 111 can be 1 nm or more and 100 nm or less. Preferably, the thickness is 1 nm or more and 50 nm or less, more preferably, 1 nm or more and 30 nm or less, and most preferably, Or, it should be 3 nm or more and 20 nm or less.

[0083] A light-shielding film is formed under the base insulating film 110 so as to hide the channel region of the semiconductor film 111. The light-shielding film may be formed at the same time as the conductive film 241, for example. good.

[0084] Semiconductors applicable to the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 include: The energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. and less than 3.9 eV, preferably less than 3.7 eV, more preferably less than 3.5 eV In this way, oxide semiconductors with wide energy gaps can be used. By using the oxide, the off-state current of the transistor 103 can be reduced. A semiconductor has high transmittance to visible light, and when used for one electrode of the capacitor 105, Capacitor elements having optical properties can be formed, and the aperture ratio of pixels in liquid crystal display devices and the like can be improved. It is possible.

[0085] By making the oxide semiconductor film n-type, the optical band gap of the oxide semiconductor film is increased to 2 It can be 0.4 eV or more and 3.1 eV or less, or 2.6 eV or more and 3.0 eV or less. . In addition, for example, an oxide semiconductor film used as the semiconductor film 119 may be formed by using an oxide semiconductor film having an atomic ratio of In:Ga:Z. In the case of an In-Ga-Zn metal oxide with n=1:1:1, the optical band gap is The optical conductivity of the indium tin oxide used in the pixel electrode 121 is 3.15 eV. The band gap is 3.7 eV to 3.9 eV. The light with the highest energy wavelengths in the visible light spectrum and ultraviolet light are filtered through the semiconductor film 1. 19 can be absorbed by light containing high energy wavelengths and ultraviolet light. There are concerns about eye damage, and the pixel 101 is made of a semiconductor device using a light-transmitting capacitor element 105. The device can be said to be easy on the eyes. The capacitor 105 does not have to overlap with the pixel 101. This allows it to absorb visible light with high energy wavelengths as well as ultraviolet light. can.

[0086] Oxide semiconductors applicable to the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 include: It is preferable that at least indium (In) or zinc (Zn) is contained. It is preferable that the oxide semiconductor include both n and Zn. To reduce the variation in electrical characteristics, one or more stabilizers are used together with them. It is preferable to do so.

[0087] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. do.

[0088] Examples of oxide semiconductors that can be used for the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 include: For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and two types of gold. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, which are oxides containing metals, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxide (also written as IGZO), an oxide containing three types of metals In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, A l-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In -Zr-Zn oxide, In-Ti-Zn oxide, In-Sc-Zn oxide, In- Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr -Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu- Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Z n-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn In-Yb-Zn oxide, In-Lu-Zn ​​oxide, and four metal oxides Oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, and In -Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Z n-based oxides and In-Hf-Al-Zn-based oxides can be used.

[0089] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements may also be included.

[0090] In addition, as an oxide semiconductor, InMO3(ZnO) m Using materials expressed as (m>0) M may be one or more metal elements selected from Ga, Fe, Mn, and Co. The number of metal elements or the above stabilizer elements is shown.

[0091] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 Use In-Ga-Zn metal oxide with an atomic ratio of (=1 / 2:1 / 6:1 / 3) Alternatively, In:Sn:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), I n:Sn:Zn=2:1:3 (=1 / 3:1 / 6:1 / 2) or In:Sn:Zn= In-Sn-Zn metal oxide with an atomic ratio of 2:1:5 (=1 / 4:1 / 8:5 / 8) It is recommended to use the atomic ratio of the metal oxide. Includes a 20% variation in eggplant.

[0092] However, the semiconductor properties and electrical properties required (field effect mobility, etc.) are not limited to these. The appropriate atomic ratio can be used depending on the semiconductor material (threshold voltage, etc.). To obtain the desired characteristics, the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, It is preferable to make the interatomic distance, density, etc. appropriate. For example, In-Sn-Zn based oxide High field-effect mobility can be obtained relatively easily in In-Ga-Zn Even in the case of oxides containing silicon, the field-effect mobility can be increased by reducing the defect density in the bulk. can.

[0093] The signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 have a resistance loss. To reduce loss, it is preferable to form it with a metal film with low resistance. For example, molybdenum ( Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al) , copper (Cu), chromium (Cr), neodymium (Nd), scandium (Sc) and other metal materials The material is formed in a single layer or laminated structure using a material or an alloy material whose main component is the material. can be done.

[0094] Examples of the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 are The following are examples of the structure: a single layer structure using aluminum containing silicon; a structure in which titanium is laminated on aluminum; Two-layer structure with titanium layered on titanium nitride, two-layer structure with tungsten layered on titanium nitride Two-layer structure with tungsten on tantalum nitride, two-layer structure with tungsten on tantalum nitride, copper-magnesium Two-layer structure with copper laminated on titanium-aluminum alloy, copper laminated on titanium nitride, and There are three-layer structures, such as a tungsten layer on top of the silicon layer.

[0095] For example, the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 It is preferable to use aluminum or copper, which are low resistance materials. This reduces signal delay and improves display quality. It has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. To prevent aluminum migration, aluminum is mixed with molybdenum and titanium. It is preferable to laminate a metal material having a higher melting point than aluminum, such as tungsten. In addition, when copper is used, it is necessary to use a copper-based solder paste to prevent defects caused by migration and the diffusion of copper elements. By laminating metal materials with higher melting points than copper, such as molybdenum, titanium, and tungsten, It is preferable that:

[0096] In addition, the materials of the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 As the material, a light-transmitting conductive material applicable to the pixel electrode 121 can be used. Note that when the semiconductor device according to one embodiment of the present invention is used as a reflective display device, the pixel electrode 121 Alternatively, a conductive material that does not transmit light can be used for the substrate 102 .

[0097] The gate insulating film 127 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn based gold The insulating layer 10 can be formed using an insulating material such as a metal oxide and has a single layer structure or a multilayer structure. In order to improve the interface characteristics with the oxide semiconductor film, which is the semiconductor film 111, the gate insulating film 1 In the case of the semiconductor film 111, at least the region in contact with the semiconductor film 111 is formed of an insulating film containing oxygen. It is preferable that:

[0098] In addition, the gate insulating film 127 is made of an insulating film having a barrier property against oxygen, hydrogen, water, etc. By this, oxygen can be diffused from the oxide semiconductor film, which is the semiconductor film 111, to the outside and from the outside. Therefore, it is possible to prevent hydrogen, water, and the like from entering the oxide semiconductor film. Examples of insulating films having a barrier property against the above include aluminum oxide, aluminum oxynitride, Gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide Examples include hafnium, hafnium oxynitride, and silicon nitride.

[0099] The gate insulating film 127 is made of hafnium silicate (HfSiO x ), nitrogen-containing Hafnium silicate (HfSi x O y N z ), hafnium aluminate with nitrogen (HfAlx O y N z ), hafnium oxide, yttrium oxide, and other high-k materials By using this, the gate leakage of the transistor 103 can be reduced.

[0100] The gate insulating film 127 preferably has the following laminated structure from the gate electrode side. As the first silicon nitride film, a silicon nitride film having a small amount of defects is provided, and the first silicon nitride film A silicon nitride film having a small amount of hydrogen desorption and ammonia desorption is formed on the silicon nitride film as a second silicon nitride film. A silicon film is provided on the second silicon nitride film and used as the gate insulating film 127. It is preferable to provide either an insulating film containing oxygen that can be decomposed into a film containing oxygen or an insulating film containing oxygen that can be decomposed into a film containing oxygen.

[0101] The second silicon nitride film is a film in which the amount of desorption of hydrogen molecules is 5× 10 21 molecule / cm 3 Less than 3 x 10 21 molecule / cm 3 The following is more preferably is 1 x 10 21 molecule / cm 3 The number of ammonia molecules released is 1 × 10 22 molecule / cm 3 Less than 5 x 10 21 molecule / cm 3 or less, more preferably 1 × 10 21 molecule / cm 3 It is preferable to use a silicon nitride film having the following properties: By using the silicon nitride film and the second silicon nitride film as a part of the gate insulating film 127, The gate insulating film 127 has a small amount of defects and a small amount of hydrogen and ammonia desorbed. Therefore, the hydrogen and the ions contained in the gate insulating film 127 can be removed. In addition, the amount of nitrogen diffused into the semiconductor film 111 can be reduced.

[0102] In a transistor using an oxide semiconductor, the interface between the oxide semiconductor film and the gate insulating film Alternatively, if a trap state (also called an interface state) exists in the gate insulating film, the threshold of the transistor This makes it easier for the threshold voltage to fluctuate, typically in the negative direction. In addition, the trap level changes the drain current by one order of magnitude when the transistor is turned on. This also causes an increase in the subthreshold coefficient (S value), which indicates the gate voltage required for In addition, the above-mentioned changes in electrical characteristics are not uniform, and the electrical characteristics vary for each transistor. For this reason, it is recommended to use a silicon nitride film with a small number of defects as the gate insulating film. Furthermore, by providing an insulating film containing oxygen in a region in contact with the semiconductor film 111, the threshold voltage This reduces the negative pressure shift and suppresses the increase in the S value.

[0103] The thickness of one region of the gate insulating film 127 is 5 nm or more and 400 nm or less, and more preferably 10 The thickness is set to 300 nm or more, and more preferably 250 nm or more.

[0104] The scanning line 107, the gate electrode 227, and the conductive film 241 are connected to the signal line 109, the conductive film 113, A single layer structure or a layer structure using materials applicable to the capacitance line 115, the wiring 229, and the wiring 233. It can be formed in a laminated structure.

[0105] Furthermore, the scanning line 107, the gate electrode 227, and the conductive film 241 are partially made of nitrogen. Metal oxides containing nitrogen, specifically, In-Ga-Zn oxides containing nitrogen and I n-Sn oxides, In-Ga oxides containing nitrogen, and In-Zn oxides containing nitrogen Nitrogen-containing Sn-based oxides, nitrogen-containing In-based oxides, and metal nitride films (InN, Sn These materials have a work function of 5 eV (electron volts) or more. When an oxide semiconductor is used for the semiconductor film 111 of the transistor 103, By using a metal oxide containing nitrogen as the gate electrode of the transistor 103, The threshold voltage of the transistor 103 can be changed in the positive direction. For example, a nitrogen-containing In-Ga-Zn oxide can be used to realize a transistor with off-state characteristics. When an oxide is used, the nitrogen concentration is at least higher than that of the oxide semiconductor film of the semiconductor film 111. In practice, an In-Ga-Zn oxide having a nitrogen concentration of 7 atomic % or more can be used.

[0106] The insulating film 129 and the insulating film 131 are made of, for example, silicon oxide, silicon oxynitride, or aluminum oxide. oxide, such as aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn-based metal oxides The edging material can be formed in a single layer or laminated structure.

[0107] The thickness of one region of the insulating film 129 is 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 The thickness of one region of the insulating film 131 is set to 10 nm or less, and more preferably 10 nm or more and 30 nm or less. The thickness of the region is 30 nm or more and 500 nm or less, preferably 150 nm or more and 400 nm or less. do.

[0108] One or both of the insulating film 129 and the insulating film 131 are formed of oxygen that satisfies the stoichiometric composition. It is preferable that the oxide insulating film contains as much oxygen as possible. This prevents oxygen from being desorbed from the semiconductor film and also removes oxygen from the oxygen-excess region by absorbing it into the gate. The oxygen can be diffused into the oxide semiconductor film through the insulating film 127 to fill oxygen vacancies. For example, at 100℃, measured by thermal desorption spectroscopy (hereinafter referred to as TDS analysis), of oxygen molecules in a heat treatment at a temperature of 100°C to 700°C, preferably 100°C to 500°C. The amount of emission is 1.0×10 18 molecule / cm 3 By using the oxide insulating film, The insulating film 129 and the insulating film 128 can compensate for oxygen vacancies contained in the semiconductor film. In one or both of the films 131, there is a region containing oxygen in excess of the stoichiometric composition (oxygen The semiconductor film 11 may be an oxide insulating film in which the excess region is partially present. The presence of an oxygen-excess region in the region overlapping with 1 facilitates oxygen desorption from the oxide semiconductor film. The oxygen in the oxygen-excess region is diffused into the oxide semiconductor film, and the oxygen It is possible to compensate for the loss.

[0109] When the insulating film 131 is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition, In this case, the insulating film 129 is preferably an oxide insulating film that transmits oxygen. In 29, all oxygen that enters the insulating film 129 from the outside passes through the insulating film 129 and diffuses. Some oxygen remains in the insulating film 129 without being oxidized. Therefore, some oxygen diffuses from the insulating film 129 to the outside. An insulating oxide film with a large number of insulating films is preferable.

[0110] In addition, one or both of the insulating film 129 and the insulating film 131 has a barrier property against nitrogen. For example, a dense oxide insulating film can provide a barrier to nitrogen. Specifically, the fluoride can be dissolved in 0.5% by weight of hydrofluoric acid at 25°C. It is preferable that the oxide insulating film has an etching rate of 10 nm / min or less when used. .

[0111] One or both of the insulating film 129 and the insulating film 131 may be formed of silicon oxynitride or nitride. When using an oxide insulating film containing nitrogen, such as silicon dioxide, the nitrogen concentration obtained by SIMS is above the SIMS detection limit of 3 x 10 20 atoms / cm 3 Less than 1 x 10 1 8 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following areas are to be considered: In this way, the semiconductor included in the transistor 103 This reduces the amount of nitrogen transferred to the membrane 111. The number of defects in the nitrogen-containing oxide insulating film itself can be reduced.

[0112] The insulating film 132 may be made of, for example, silicon oxynitride, silicon nitride, aluminum nitride, or nitride. It is formed in a single layer or multilayer structure using nitride insulating materials such as aluminum oxide. can be done.

[0113] As the insulating film 132, a nitride insulating film with a low hydrogen content may be provided. For example, the surface temperature of the film is 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower. The amount of hydrogen molecules released measured by TDS analysis performed at a temperature below 500°C .0×10 21 molecule / cm3 less than 3.0 x 10 21 molecule / cm 3 less than and more preferably 1.0 × 10 21 molecule / cm 3 A nitride insulating film having a thickness of less than It is possible.

[0114] One region of the insulating film 132 has the function of suppressing the intrusion of impurities such as hydrogen and water from the outside. For example, it is preferable that the thickness is 50 nm or more and 200 nm or less, and preferably 50 The insulating film has a thickness of 50 nm or more and 150 nm or less, and more preferably 50 nm or more and 100 nm or less. By providing the insulating film 132, impurities such as carbon are blocked by the insulating film 132, and the transistor The impurities in the semiconductor film 111 and the semiconductor film 231 of the transistor 103 and the transistor 223 Since external migration is reduced, the variation in the electrical characteristics of the transistor can be reduced. It is possible.

[0115] The insulating film provided on the gate insulating film 127, the scanning line 107, and the gate electrode 227 is 1. In the case where the insulating film is a two-layer film, it is preferable to provide an insulating film 131. It is preferable that the insulating film 131 and the insulating film 132 be provided in this order from the semiconductor film side.

[0116] In addition, the gate insulating film 127, the scanning line 107, the gate electrode 227, the pixel electrode 121, the conductive film 122, The insulating film formed between the film 241 and wiring or the like that can be formed at the same time as the film 241 and the wiring or the like. The oxide insulating film formed by the CVD method (chemical vapor deposition method) using organic silane gas is Typically, a silicon oxide film may be included.

[0117] The silicon oxide film can be formed to a thickness of 300 nm or more and 600 nm or less. The gases used were ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TEOS: chemical formula Si(OC2H5)4), and Lanthanum (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TM CTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), trisdimethylamine Silicon-containing compounds such as silane (SiH(N(CH3)2)3) can be used. do.

[0118] The silicon oxide film is formed by a CVD method using organic silane gas, thereby forming a silicon dioxide film on the substrate 10. As a result, it is possible to improve the flatness of the surface of the element portion formed on the organic resin. Even without providing a planarizing film, it is possible to reduce the alignment disorder of the liquid crystal and reduce light leakage. Of course, instead of the silicon oxide film, Alternatively, a laminate including the silicon oxide film and the organic resin may be used. .

[0119] The pixel electrode 121 is made of indium tin oxide, indium oxide containing tungsten oxide, or oxide. Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium, indium zinc oxide, indium with silicon oxide The insulating film 11 can be formed of a light-transmitting conductive material such as aluminum tin oxide.

[0120] Next, each component included in the pixel 101 according to this embodiment will be described.

[0121] 4A is an example of a circuit diagram of the pixel 101. The pixel 101 includes a transistor The gate of the transistor 103 is connected to the gate electrode 104. ... The electrode is electrically connected to the scanning line 107, and one of the source electrode and the drain electrode is connected to the signal line 109, and the other of the source electrode and the drain electrode is electrically connected to one of the capacitor elements 105. The electrode is electrically connected to one electrode (pixel electrode) of the liquid crystal element 108. The other electrode of the capacitor element 105 is electrically connected to a capacitor line 115, and the other electrode of the liquid crystal element 108 is electrically connected to a capacitor line 115. This electrode (counter electrode) is electrically connected to a wiring that supplies a counter potential to the counter electrode.

[0122] The liquid crystal element 108 is formed on a substrate opposite to the substrate on which the transistor 103 and the pixel electrode are formed. The optical modulation effect of the liquid crystal sandwiched between the substrate (e.g., the substrate on which the counter electrode is formed) It is an element that controls the transmission or non-transmission of light. The electric field (including the vertical electric field and the oblique electric field) controls the image. When the base electrode and the counter electrode (also called the common electrode) are formed on one of the substrates, Such an electric field is a lateral electric field.

[0123] FIG. 4B is an example of a detailed circuit diagram of the pixel 101. As shown, the transistor 103 has a scan line 107 which includes a gate electrode and a source electrode or The signal line 109 includes one of the drain electrodes, and the other of the source electrode and drain electrode. The conductive film 113 includes a conductive film 114.

[0124] In the capacitor element 105, the semiconductor film 119 connected to the capacitor line 115 serves as one electrode. In addition, the pixel connected to the conductive film 113 including the other of the source electrode and the drain electrode functions as a pixel. The pixel electrode 121 functions as the other electrode. The insulating films 129, 131, and 132 provided between the insulating films 129, 131, and 132 function as dielectric films. do.

[0125] The liquid crystal element 108 includes a pixel electrode 121, a counter electrode 154, and a It is composed of a liquid crystal layer provided between electrodes 154 .

[0126] In the capacitor 105, the semiconductor film 119 may have a high resistance similar to the semiconductor film 111. , which functions as an electrode of the capacitor element 105. This is because the pixel electrode 121 is The film 129, the insulating film 131, and the insulating film 132 are used as gate insulating films, and the capacitance line 115 is used as a source electrode. The capacitor element 105 can function as a transistor or drain electrode. This is because the semiconductor film 119 can be made to operate in the same manner as a transistor and brought into a conductive state. Therefore, the semiconductor film 119 can function as one electrode of the capacitor 105. do.

[0127] Next, a manufacturing method of the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIGS. 5 and 6. do.

[0128] First, a conductive film 241 is formed on the substrate 102, and a base insulating film 110 is formed on the conductive film 241 so as to cover the conductive film. Form.

[0129] The conductive film 241 is formed by forming a conductive film using the above-mentioned material and forming a mask on the conductive film. The conductive film can be formed by processing using the mask. Various film formation methods such as a sputtering method and a spin coating method can be used. The thickness of the conductive film is not particularly limited and is determined in consideration of the formation time, the desired resistivity, etc. The mask can be, for example, a resist formed by a photolithography process. The conductive film can be processed by dry etching and wet etching. This can be done by one or both of the etching steps.

[0130] The base insulating film 110 can be formed using the above-described materials. Use of various film formation methods such as vapor deposition, CVD, sputtering, and spin coating can be done.

[0131] Next, the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 are formed (see FIG. 1). The semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 are made of the above-described oxide semiconductor. an oxide semiconductor film is formed using a mask; a mask is formed over the oxide semiconductor film; and The oxide semiconductor film can be formed by processing it using a sputtering method, a coating method, or the like. It can be formed by using a method such as a pulsed laser deposition method or a laser ablation method. By using a printing method, the semiconductor film 111 and the semiconductor film 119 are formed on the substrate. The oxide semiconductor film can be formed directly on the insulating film 110. When forming the plasma, the power supply to generate the plasma can be an RF power supply, an AC power supply or A DC power supply or the like can be used as appropriate. The sputtering gas is a rare gas (typically Typically, argon, oxygen, a rare gas, and a mixed gas of oxygen are used. In the case of a mixed gas of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to rare gas. The target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. The mask may be a resist mask formed by a photolithography process, for example. The oxide semiconductor film can be processed by dry etching and wet etching. This can be done by one or both of the etching steps. Etching conditions (etching gas, etching solution, etching time, temperature) are adjusted to suit the material. etc.) as appropriate.

[0132] The oxide semiconductor film may be formed by a CVD method. VD(Metal Organic Chemical Vapor Depositi) Thermal CV such as the on method and ALD (Atomic Layer Deposition) method Method D may also be used.

[0133] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0134] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber, and the pressure inside the chamber is increased to atmospheric pressure. The film is formed by reacting the material near or on the substrate under reduced pressure and depositing it on the substrate. It is also possible.

[0135] In the ALD method, the chamber is kept at atmospheric pressure or reduced pressure, and the source gases for the reaction are sequentially introduced. Next, the gas is introduced into the chamber, and the film may be formed by repeating this gas introduction sequence. For example, by switching between two or more types of switching valves (also called high-speed valves), The source gases are supplied to the chamber in order, and the first source gas is supplied to the chamber in order to prevent the mixture of the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the fuel gas. In case of simultaneously introducing an inert gas, the inert gas is The second source gas may be introduced as a carrier gas, and an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first raw material gas is discharged by vacuum evacuation. The first source gas may be adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction order until a desired thickness is achieved. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film is determined by the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin transistors.

[0136] For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethyl The chemical formula of trimethylindium is I The chemical formula for trimethylgallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn(CH3)2. Not limited to, triethylgallium (chemical formula Ga(C2H5 )3) can also be used, and diethyl zinc (chemical formula Zn(C2H5 )2) can also be used.

[0137] When forming an In-Ga-Zn-O film by the ALD method, In(CH3)3 gas and O3 gas are used. The InO2 layer is formed by repeatedly introducing gases, and then Ga(CH3)3 gas and O3 gas are introduced. The GaO layer was formed by simultaneously introducing Zn(CH3)2 and O3 gases. The order of these layers is not limited to this example. These gases are mixed to form In-Ga-O layers, In-Zn-O layers, Ga-In-O layers, and Zn-In layers. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain In(CH3)3. Alternatively, Ga(CH3)3 gas may be replaced with Ga(C2H5) Alternatively, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Alternatively, Zn(CH3)2 gas may be used.

[0138] After the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 are formed, heat treatment is performed. Dehydrogenation of the oxide semiconductor films, which are the semiconductor film 111, the semiconductor film 119, and the semiconductor film 231 The temperature of the heat treatment is typically 150°C or higher. Lower than the strain point of the upper substrate, preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher The temperature is set to 450° C. or lower. This may be performed on the oxide semiconductor film before it is processed into the conductor film 231.

[0139] In this heat treatment, the heat treatment device is not limited to an electric furnace, and may be a medium such as a heated gas. The apparatus may be an apparatus that heats the object to be treated by thermal conduction or thermal radiation from the object. For example, GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (La RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with a halogen lamp. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure natri The treated object is irradiated with light (electromagnetic waves) emitted from lamps such as mercury lamps and high-pressure mercury lamps. The GRTA device is a device that uses high-temperature gas to perform heat treatment. do.

[0140] The heat treatment is carried out in a gas atmosphere containing nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less of air), or rare gases (argon, helium, etc. The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be added to hydrogen, It is preferable that the material does not contain water, etc. After heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. The treatment time is preferably 3 minutes to 24 hours.

[0141] Here, a dopant may be added to the semiconductor film 119. The method of adding is to provide a mask on the region other than the semiconductor film 119, and then, using the mask, Hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, antimony One or more dopants selected from fluorine and rare gas elements are implanted by ion implantation or ion doping. Instead of the ion implantation method or the ion doping method, the By exposing the semiconductor film 119 to plasma containing the dopant, the dopant is added. After the dopant is added, heat treatment may be performed. The details of the heat treatment for dehydrogenating or dehydrating the semiconductor film 111 and the semiconductor film 119 are shown in Table 1. This can be done appropriately in light of the above.

[0142] Next, the signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 are formed. The signal line 109, the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233 are A conductive film is formed using the above-mentioned material, a mask is formed on the conductive film, and the mask is The mask and the processing are the same as those for the conductive film 241. This can be done in the same way.

[0143] Next, the base insulating film 110, the semiconductor film 111, the semiconductor film 119, the semiconductor film 231, and the signal line 1 09, a gate electrode is formed to cover the conductive film 113, the capacitance line 115, the wiring 229, and the wiring 233. An insulating film 127 is formed.

[0144] The gate insulating film 127 is formed by using the above-mentioned material by a CVD method, a sputtering method, or the like. The gate insulating film 127 can be formed by using various film formation methods. When applying MOCVD (Metal Organic Chemical Vapor Deposition), The film can be formed by using a photo-deposition method.

[0145] Next, the scanning line 107 is formed in the region on the gate insulating film 127 that overlaps with the semiconductor film 111. A gate electrode 227 is formed in a region overlapping with the semiconductor film 231 (see FIG. 5B).

[0146] The scanning line 107 and the gate electrode 227 are formed by forming a conductive film using the above-mentioned material. The mask is formed on the conductive film, and the conductive film is processed using the mask. The mask and processing can be performed in the same manner as for the conductive film 241.

[0147] Next, an insulating film 129 is formed on the gate insulating film 127, the scanning line 107, and the gate electrode 227. An insulating film 131 and an insulating film 132 are formed (see FIG. 6A). Preferably, the insulating film 131 and the insulating film 132 are formed successively. By this, impurities are formed at the interfaces of the insulating film 129, the insulating film 131, and the insulating film 132. This can prevent the inclusion of

[0148] The insulating films 129, 131, and 132 are formed by the CVD method using the above-mentioned materials. Alternatively, it can be formed by various film formation methods such as sputtering.

[0149] The insulating film 129 can be formed using, for example, the above-described oxide insulating film. In this case, a silicon oxide film or a silicon oxynitride film is formed as the oxide insulating film. The formation conditions are as follows: The substrate is heated to a temperature of 180°C or higher and 400°C or lower, more preferably 200°C or higher and 370°C or lower. The temperature is maintained at 100° C., and a deposition gas containing silicon and an oxidizing gas as source gases are introduced into the processing chamber. The pressure in the treatment chamber is set to 20 Pa or more and 250 Pa or less, more preferably 40 Pa or more and 20 0 Pa or less, and high frequency power is supplied to an electrode provided in the processing chamber.

[0150] Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and silicon fluoride. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide. be.

[0151] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content contained in the insulating film 129 and also to The oxygen diffused from the insulating film 131 can be reduced by Since the insulating film 129 may capture the dangling bonds, When the dangling bonds contained in 129 are reduced, the oxygen contained in the insulating film 131 are efficiently diffused into the semiconductor film 111 and the semiconductor film 231 through the gate insulating film 127. The oxygen vacancies in the oxide semiconductor films, which are the semiconductor film 111 and the semiconductor film 231, are filled. As a result, the amount of hydrogen mixed into the oxide semiconductor film can be reduced. In both cases, oxygen vacancies in the oxide semiconductor film can be reduced.

[0152] The insulating film 131 is an oxide insulating film containing the above-mentioned oxygen excess region or an oxygen insulating film having a stoichiometric composition. When an oxide insulating film containing more oxygen than Note that the oxide insulating film here is a silicon oxide film or a silicon oxynitride film. The formation conditions are as follows: The substrate placed in the evacuated processing chamber is heated to 180°C or higher and 260°C or lower, more preferably 1 The temperature is maintained at 80°C or higher and 230°C or lower, and the raw material gas is introduced into the processing chamber to increase the pressure in the processing chamber. 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less, 0.17W / cm to the electrode installed in the processing chamber 2 More than 0.5W / cm 2 Below are some more preferred Or 0.25W / cm 2More than 0.35W / cm 2 The following conditions for supplying high frequency power are met: can be cited as an example.

[0153] The source gas for the insulating film 131 can be a source gas that can be used for the insulating film 129 .

[0154] The conditions for forming the insulating film 131 are: high frequency power of the above power density in a reaction chamber of the above pressure; By supplying the source gas, the decomposition efficiency in the plasma increases, oxygen radicals increase, As the oxidation of the source gas progresses, the oxygen content in the insulating film 131 becomes higher than the stoichiometric composition. However, if the substrate temperature is set to the temperature of the above-mentioned formation conditions, the bond between silicon and oxygen Because the resultant force is weak, some of the oxygen is released by heating. As a result, the stoichiometric composition is satisfied. The oxide insulating film contains more oxygen than the silicon dioxide, and some of the oxygen is released by heating. This can be done.

[0155] In addition, by increasing the thickness of the insulating film 131, the amount of oxygen released by heating can be increased. Therefore, the insulating film 131 is preferably thicker than the insulating film 129. By providing the film 129, it is possible to improve the coverage even when the insulating film 131 is provided thickly. Cut.

[0156] When the insulating film 132 is formed using a nitride insulating film with a low hydrogen content, the insulating film is formed under the following conditions. In this case, a silicon nitride film is formed as the nitride insulating film. An example of the formation conditions is a process chamber evacuated to a vacuum in a plasma CVD apparatus. The substrate placed in the oven is heated to a temperature of 80°C to 400°C, more preferably 200°C to 370°C. The pressure in the processing chamber is maintained at 100 Pa or more and 25 Pa or less by introducing the raw material gas into the processing chamber. The pressure is set to 0 Pa or less, preferably 100 Pa or more and 200 Pa or less, and The condition is that high frequency power is supplied to the electrode.

[0157] The source gas for the insulating film 132 is a deposition gas containing silicon, nitrogen, and ammonia. It is preferable to use the following gases. Typical examples of deposition gases containing silicon include silane, disilane, and the like. The nitrogen flow rate is different from the ammonia flow rate. The ratio is preferably 5 to 50 times, more preferably 10 to 50 times. By using ammonia as a source gas, the separation of silicon-containing deposition gas and nitrogen This is because ammonia is heated by plasma energy and thermal energy. The energy generated by the dissociation is used to bond and decompose the deposition gas molecules containing silicon. This contributes to the decomposition of the bonds of the nitrogen molecules. The silicon nitride film is low in impurities and can prevent the intrusion of impurities such as hydrogen and water from the outside. It can be formed.

[0158] After forming at least the insulating film 131, a heat treatment is performed to form the insulating film 129 or the insulating film 13 The excess oxygen contained in the semiconductor film 111 and the semiconductor film 23 is removed through the gate insulating film 127. 1, and oxygen vacancies in the oxide semiconductor film, which is the semiconductor film 111 and the semiconductor film 231, are eliminated. It is preferable to fill the gap between the semiconductor film 111 and the semiconductor film 231. The dehydrogenation or dehydration can be appropriately carried out by referring to the details of the heat treatment for dehydrogenation or dehydration described above.

[0159] Next, the insulating films 129, 131, and 132 are formed in regions overlapping with the conductive film 113. An opening 117 (see FIG. 1) reaching the conductive film 113 is formed in the insulating film 114 .

[0160] Next, the pixel electrode 121 is formed, thereby completing the semiconductor device shown in FIGS. The pixel electrode 121 is made of the above-mentioned material and is formed through the opening 117 (see FIG. 6(B)). a conductive film in contact with the conductive film 113 is formed, a mask is formed over the conductive film, and the mask is The mask and the processing can be performed by using the conductive film 24. This can be done in the same way as in 1.

[0161] Note that in the semiconductor device according to one embodiment of the present invention, the structure of the capacitor may be changed as appropriate. For example, as shown in the cross-sectional view of the capacitor 105 in FIG. The gate insulating film 127 may be removed from the dielectric portion. The thickness of the body portion can be reduced, and the charge capacity of the capacitance element 105 can be improved. In order to partially remove the gate insulating film 127, a mask is placed on the gate insulating film. The mask and the corresponding mask are used for processing. This processing can be performed in the same manner as the conductive film 241. When forming the gate electrode 227, a part of the gate insulating film 127 may be removed. In this case, the number of photolithography steps can be reduced. Alternatively, either the insulating film 29 or the insulating film 131 may be removed.

[0162] As shown in the cross-sectional view of the capacitance element 105 in FIG. 7B, the dielectric portion of the capacitance element 105 The gate insulating film 127, the insulating film 129, and the insulating film 131 may be removed from this. By doing so, the film thickness of the dielectric portion becomes thinner, and the charge capacity of the capacitance element 105 is increased. It can be raised.

[0163] In addition, in the capacitor element 105 shown in FIG. 7B, the semiconductor film 119 and the insulating film 132 are in contact with each other. As described above, the insulating film 132 is preferably a nitride insulating film. The film contains a large amount of nitrogen and hydrogen, and by diffusing these into the semiconductor film 119, When an oxide semiconductor is used as the semiconductor film 119, the oxide semiconductor can be Some of the nitrogen and hydrogen atoms that are oxidized contribute to the formation of donor levels that generate carriers. Therefore, the conductivity of the semiconductor film 119 can be improved. This allows the step of doping the semiconductor film 119 with impurities to be omitted.

[0164] 8, the semiconductor film 119, which is one electrode of the capacitor element 105, and the base insulating film 118 are A nitride insulating film 118 may be provided between the film 110 and the insulating film 118. In this configuration, As in FIG. 7B, nitrogen and hydrogen are diffused from the nitride insulating film 118 into the semiconductor film 119. This can improve the conductivity of the semiconductor film 119. To form 18, a film that can be used as the insulating film 132 is formed, and a mask is formed on the film. The mask and the processing can be performed by forming the mask. The processing can be performed in the same manner as the conductive film 241. The capacitive element configurations shown in (A) and (B) may be combined.

[0165] In addition, in the semiconductor device according to one embodiment of the present invention, The shape of the transistor is not limited to that shown in FIGS. 1 and 2 and may be changed as appropriate. For example, in a transistor, the source electrode or the drain electrode included in the signal line 109 One of the electrodes is U-shaped (C-shaped, U-shaped, or horseshoe-shaped), and the other is the source electrode or drain electrode. The transistor may have a shape that surrounds the conductive film including the other of the inner electrodes. By doing so, it is possible to ensure a sufficient channel width even if the transistor area is small. This increases the amount of drain current (also called on-current) that flows when the transistor is turned on. It becomes possible to do this.

[0166] In the pixel 101 shown above, the transistor has one gate electrode. The transistor shown in FIG. 1 has two gate electrodes facing each other via a semiconductor film 111. A transistor having two gate electrodes can be used. For example, the first driving circuit having the gate electrode 227 and the conductive film 241 shown in FIG. The transistors used in the operating circuit 104 can be referred to.

[0167] The transistor having the two gate electrodes is the transistor 1 described in this embodiment. The conductive film is provided under the base insulating film 110 of the semiconductor film 111. The conductive film is formed at a position overlapping with the channel formation region of the semiconductor film 111. By providing the signal line 109, the potential of the conductive film is set to the minimum potential of the video signal input to the signal line 109. As a result, the surface of the semiconductor film 111 facing the conductive film is It is possible to control the current flowing between the source electrode and the drain electrode of the transistor. Furthermore, by providing a conductive film, it is possible to reduce the variation in the electrical characteristics of the surrounding This reduces the influence of changes in the field on the semiconductor film 111, thereby improving the reliability of the transistor. This can be done.

[0168] The conductive film includes the conductive film 241, the scanning line 107, the signal line 109, the pixel electrode 121, etc. It can be formed using the same materials and methods as those described above.

[0169] As described above, one electrode of the capacitor element can be formed by the same forming process as the semiconductor film included in the transistor. By using a semiconductor film formed in this process, the aperture ratio can be increased while the charge capacity can be increased. As a result, a semiconductor device having an element can be manufactured. You can get a position.

[0170] In addition, one electrode of the capacitor element is formed by the same formation process as the semiconductor film included in the transistor. By using the semiconductor film formed, the number of masks required for the photolithography process can be increased. A semiconductor device having a capacitor element with a high aperture ratio and a large charge capacity is manufactured without using a It is possible.

[0171] In addition, oxygen vacancies are reduced in an oxide semiconductor film, which is a semiconductor film included in a transistor, and water is Since impurities such as silicon are reduced, the semiconductor device according to one embodiment of the present invention has good This results in a semiconductor device with good electrical properties.

[0172] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0173] (Embodiment 2) In this embodiment mode, the transistors and the semiconductor device included in the semiconductor device described in the above embodiment modes are and a capacitor element. We will explain about this.

[0174] The oxide semiconductor may have a non-single crystal structure. The non-single crystal structure may be, for example, a CAAC (C Axi Aligned Crystal), polycrystalline, microcrystalline, and amorphous parts.

[0175] The oxide semiconductor may contain CAAC. AAC-OS(C Axis Aligned Crystalline Oxide It is called a semiconductor.

[0176] CAAC-OS is a transmission electron microscope (TEM). In some cases, crystals can be seen in the image observed using a chromon microscope. The crystals contained in CAAC-OS are shown in TEM images as being 100 nm on a side. In addition, CAAC-OS is often small enough to fit inside a rectangular box. In some cases, the boundaries between the crystalline regions cannot be clearly identified. In the TEM observation image, the grain boundary cannot be clearly identified. Since CAAC-OS does not have clear grain boundaries, impurities may segregate. In addition, the CAAC-OS does not have clear grain boundaries, so the density of defect states is high. In addition, the CAAC-OS does not have clear grain boundaries, so the electron mobility is not reduced. is small.

[0177] CAAC-OS has a plurality of crystalline parts, and the c-axes of the crystalline parts are aligned along the normal to the surface on which they are formed. They may be aligned parallel to a line vector or a surface normal vector. CAAC-OS uses an X-ray diffraction (XRD) device. When the out-of-plane analysis was performed, a peak appeared at 2θ around 31°. The peak at 2θ around 31° may be (00 9) plane. CAAC-OS also shows a peak at 2θ of around 36°. The peak at 2θ around 36° may appear if it is a ZnGa2O4 crystal. The CAAC-OS preferably has a 2θ angle of approximately 31°. A peak appears near the center, but no peak appears near 2θ of 36°.

[0178] In addition, the a-axis and b-axis of different crystal regions of CAAC-OS are aligned. If the CAAC-OS has InGaZnO4 crystals, an XRD instrument When an analysis is performed using the in-plane method in which X-rays are incident from a direction perpendicular to the c-axis, A peak at 2θ around 56° may appear. The peak at 2θ around 56° is due to InG The (110) plane of a ZnO4 crystal is shown. Here, 2θ is fixed at around 56°, and the normal to the surface is When the sample is rotated around the line vector (φ axis) and analyzed (φ scan), the a-axis and In the case of single-crystal oxide semiconductors in which the orientation of the b-axis is aligned, six symmetric peaks appear. In the case of CAAC-OS, no clear peak appears.

[0179] Thus, the CAAC-OS has a c-axis orientation, and the a-axis and / or b-axis are macroscopically aligned. There may not be any.

[0180] In addition, CAAC-OS may show bright spots in the electron diffraction pattern. In particular, the beam diameter obtained by using an electron beam of 10 nm or less, or 5 nm or less, The electron diffraction pattern obtained is called an electron micro diffraction pattern.

[0181] FIG. 10(A) shows an example of an electron microbeam diffraction pattern of a sample having a CAAC-OS. Here, the sample was cut in a direction perpendicular to the CAAC-OS surface to form a film with a thickness of about 40 nm. In this case, an electron beam with a beam diameter of 1 nm was used to slice the sample. The electron beam is incident from a direction perpendicular to the cross section. The pattern shows that spots are observed.

[0182] The crystalline part of the CAAC-OS has a c-axis that is perpendicular to the normal vector of the CAAC-OS surface. or the normal vector of the surface, and viewed from the direction perpendicular to the ab plane. The metal atoms are arranged in a triangular or hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers. In addition, the crystals are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The orientation of the a-axis and the b-axis may be different. In this case, the range of 80° to 100°, preferably 85° to 95°, is also included. In addition, when simply describing it as parallel, it means -10° or more and 10° or less, preferably -5° or less. This also includes a range of up to 5°.

[0183] The c-axis of the crystalline part of the CAAC-OS is the normal vector of the surface on which the CAAC-OS is formed. The shape of the CAAC-OS (the object) is aligned parallel to the normal vector of the surface. Depending on the cross-sectional shape of the forming surface or the cross-sectional shape of the surface, they may face in different directions. In addition, the crystalline part is formed when the film is formed or when a crystallization process such as heat treatment is performed after the film is formed. Therefore, the c-axis of the crystal part is the same as the shape of the CAAC-OS when it is formed. The vectors are aligned to be parallel to the normal vector of the resulting surface or the normal vector of the surface.

[0184] In some cases, the CAAC-OS can be formed by reducing the impurity concentration. Impurities are hydrogen, carbon, silicon, transition metal elements, and other elements that are not the main components of oxide semiconductors. In particular, elements such as silicon have a higher affinity with oxygen than the metal elements that make up oxide semiconductors. Therefore, when the element removes oxygen from the oxide semiconductor, It can disrupt the atomic arrangement of the conductor and reduce its crystallinity. Metals, argon, and carbon dioxide have large atomic radii (or molecular radii), so they are oxide semiconductors. This can disrupt the atomic arrangement of the conductor and reduce the crystallinity of the oxide semiconductor. AAC-OS is an oxide semiconductor with a low impurity concentration. Impurities may act as a carrier generation source.

[0185] In the CAAC-OS, the distribution of the crystal parts does not have to be uniform. In the process of forming an OS, when crystals are grown from the surface side of the oxide semiconductor, The proportion of crystalline parts may be higher near the surface than near the surface. When impurities are mixed into the OS, the crystallinity of the crystalline part in the region where the impurities are mixed decreases. Sometimes I do.

[0186] CAAC-OS can be formed by reducing the density of defect states. In semiconductors, oxygen vacancies are defect levels. Oxygen vacancies can become trap levels, The hydrogen trapping can act as a carrier generation source. To achieve this, it is important to prevent oxygen vacancies from occurring in the oxide semiconductor. The AAC-OS is an oxide semiconductor with a low density of defect states. The oxide semiconductor has few oxygen vacancies.

[0187] High purity intrinsic or actual silicon has a low impurity concentration and a low defect level density (low oxygen vacancy). A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is Since there are fewer carrier generation sources, it may be possible to lower the carrier density. Therefore, the threshold voltage of a transistor using the oxide semiconductor for a channel formation region is In some cases, the electrical characteristics are negative (also called normally-on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states. Therefore, the trap state density may be reduced. The transistor used in the formation region has little fluctuation in electrical characteristics and is highly reliable. Note that charges trapped in the trap states of the oxide semiconductor do not disappear until It takes a long time for the charge to dissipate, and it may behave as if it were a fixed charge. A transistor using an oxide semiconductor with a high density of drop states in the channel formation region has may become unstable.

[0188] In addition, a transistor using a CAAC-OS that is highly pure intrinsic or substantially highly pure intrinsic The electrical characteristics of this material change little when exposed to visible or ultraviolet light.

[0189] The CAAC-OS can be formed by, for example, a sputtering method using a DC power supply. can.

[0190] The oxide semiconductor may have a polycrystalline structure. The polycrystalline oxide semiconductor includes a plurality of crystal grains.

[0191] In polycrystalline oxide semiconductors, crystal grains can sometimes be confirmed in TEM images. The crystal grains contained in the polycrystalline oxide semiconductor are 2 nm or larger and 300 nm or smaller in size in the TEM observation image. The particle size is 3 nm or less, 3 nm to 100 nm or 5 nm to 50 nm. In addition, in the TEM observation image of polycrystalline oxide semiconductors, the boundaries between the crystal grains are clearly visible. In addition, polycrystalline oxide semiconductors can be observed, for example, by TEM observation. Grain boundaries may be visible.

[0192] The polycrystalline oxide semiconductor has a plurality of crystal grains, and the crystal grains have different orientations. In addition, polycrystalline oxide semiconductors can be analyzed by out-of-plane diffraction (XRD) When the ane method was used, a peak at 2θ of approximately 31°, which indicates orientation, or multiple types of orientation were observed. In addition, a peak indicating the direction of the crystallographic polarization may appear in the electron diffraction pattern of a polycrystalline oxide semiconductor. Spots may be observed.

[0193] A polycrystalline oxide semiconductor has high crystallinity and therefore high electron mobility in some cases. Therefore, a transistor using a polycrystalline oxide semiconductor for a channel formation region has a high electric field. However, in polycrystalline oxide semiconductors, impurities may segregate at the grain boundaries. In addition, the grain boundaries of polycrystalline oxide semiconductors become defect states. Since polycrystalline oxide semiconductors can become carrier sources and trap states, The transistor used in the channel formation region is a transistor using CAAC-OS. Compared to conventional transistors, the electrical characteristics may fluctuate more, resulting in a less reliable transistor.

[0194] The polycrystalline oxide semiconductor can be formed by heat treatment at high temperature or laser light treatment. can.

[0195] The oxide semiconductor may have microcrystals. This is called an oxide semiconductor.

[0196] In the microcrystalline oxide semiconductor, crystals cannot be clearly seen in the TEM observation image. The crystal parts contained in the microcrystalline oxide semiconductor may have a size of 1 nm to 100 nm. In particular, the size of the particles is between 1 nm and 10 nm. The microcrystals are called nanocrystals (nc). Oxides with nanocrystals The semiconductor is called nc-OS (nanocrystalline oxide semiconductor). In addition, nc-OS is characterized by a crystalline part and a crystalline part in a TEM image. In addition, the boundary between nc-OS and the crystalline phase may not be clearly visible in TEM images. Since nc-OS does not have clear grain boundaries, impurities rarely segregate. Since there are no clear grain boundaries, the defect level density is less likely to be high. Since there are no clear grain boundaries, the decrease in electron mobility is small.

[0197] nc-OS is an atomic arrangement in a microscopic area (for example, an area of ​​1 nm to 10 nm). In addition, nc-OS has a periodic structure where the crystal regions are not regularly spaced. Therefore, there are cases where the atomic arrangement does not show periodicity or long-range order macroscopically. Therefore, depending on the analysis method, nc-OS may be distinguished from an amorphous oxide semiconductor. In the case of nc-OS, for example, it is difficult to distinguish between the crystal and the crystalline part by using an XRD device. When an out-of-plane analysis is performed using X-rays with a small beam diameter, a peak indicating orientation appears. In addition, the nc-OS may not be detected if the beam diameter is larger than the crystal part (for example, In the electron diffraction pattern using an electron beam of 20 nm or more, or 50 nm or more, Halo patterns may be observed. In addition, the nc-OS has the same or higher structure than the crystalline part. Ultra-small electron beams with a smaller beam diameter (for example, 10 nm or less, or 5 nm or less) In the electron diffraction pattern, spots may be observed. In electron diffraction patterns, circular bright areas may be observed. In the ultrafine electron diffraction pattern of nc-OS, multiple spots are observed within the same region. There is.

[0198] FIG. 10(B) shows an example of an electron microbeam diffraction pattern of a sample having nc-OS. The sample was cut in a direction perpendicular to the nc-OS surface to a thickness of about 40 nm. In this case, an electron beam with a beam diameter of 1 nm was applied perpendicular to the cut surface of the sample. The electron diffraction pattern of nc-OS is shown in Figure 10(B). A circular area of ​​high brightness is observed, and multiple spots are observed within that area. It can be seen that...

[0199] nc-OS may have periodic atomic arrangement in a microscopic region, and therefore it is an amorphous oxide. However, the nc-OS has a lower defect level density than the crystalline semiconductor. Since there is no regularity between the layers, the density of defect states is higher than that of CAAC-OS.

[0200] Therefore, the carrier density of the nc-OS may be higher than that of the CAAC-OS. Oxide semiconductors with high carrier density can have high electron mobility. Transistors using nc-OS for the channel formation region have high field-effect mobility. However, the nc-OS has a higher density of defect states than the CAAC-OS. Therefore, the trap density may be high. The transistor used in the channel formation region is a transistor using CAAC-OS. Compared to conventional transistors, the electrical characteristics may fluctuate more, resulting in a transistor with low reliability. However, nc-OS can be formed even if it contains a relatively large amount of impurities, so C It is easier to form than AAC-OS, and may be suitable for some applications. In addition, nc-OS can be formed by a film formation method such as sputtering using an AC power supply. The sputtering method using an AC power supply can form a film with high uniformity on a large substrate. Therefore, a semiconductor device having a transistor using nc-OS in the channel formation region can be The device can be manufactured with high productivity.

[0201] The oxide semiconductor may have an amorphous portion. Amorphous oxide semiconductors have disordered atomic arrangement and have crystalline parts. Alternatively, amorphous oxide semiconductors have an amorphous state like quartz and do not have a regular atomic arrangement. No regularity is observed.

[0202] In amorphous oxide semiconductors, crystals may not be visible in TEM images. be.

[0203] Amorphous oxide semiconductors are analyzed by the out-of-plane method using an XRD device. In addition, the peak indicating the orientation may not be detected. A halo pattern may be observed in the X-ray diffraction pattern. In the electron microbeam diffraction pattern, no spots were observed, and a halo pattern was observed. This may be the case.

[0204] Amorphous oxide semiconductors are formed by incorporating impurities such as hydrogen at high concentrations. Therefore, amorphous oxide semiconductors are oxides containing high concentrations of impurities. It is a compound semiconductor.

[0205] When an oxide semiconductor contains a high concentration of impurities, defect levels such as oxygen vacancies are formed in the oxide semiconductor. Therefore, an amorphous oxide semiconductor with a high impurity concentration may form defect states. In addition, amorphous oxide semiconductors have low crystallinity, so they are difficult to fabricate with CAAC-OS or nc-O. The defect level density is higher than that of S.

[0206] Therefore, the amorphous oxide semiconductor has a higher carrier density than the nc-OS. Therefore, a transistor using an amorphous oxide semiconductor for a channel formation region Therefore, the electrical characteristics of the normally-on transistor may be different from those of the normally-on transistor. It may be suitable for use in transistors that require high performance. The body may have a high density of defect states and therefore a high density of trap states. Transistors using amorphous oxide semiconductors for the channel formation region include CAAC-OS and nc Compared with transistors using an OS in the channel formation region, the fluctuation in electrical characteristics is large and the signal However, amorphous oxide semiconductors are relatively impure. It can be formed using a film formation method that contains a lot of substances, making it easy to form. For example, spin coating, Lubrication method, immersion method, spray method, screen printing method, contact printing method, inkjet printing method Amorphous oxide semiconductors are deposited by film formation methods such as jet printing, roll coating, and mist CVD. Therefore, a transistor using an amorphous oxide semiconductor for a channel formation region may be formed. A semiconductor device having a transistor can be manufactured with high productivity.

[0207] Note that the oxide semiconductor may be a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or a non-crystalline oxide semiconductor. The mixed film may be a film containing two or more kinds of amorphous oxide semiconductors. Oxide semiconductor region, microcrystalline oxide semiconductor region, polycrystalline oxide semiconductor region, CAAC In addition, the mixed film may have two or more regions, for example, , an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, The CAAC-OS region may have a laminated structure of two or more of these regions.

[0208] The oxide semiconductor may have, for example, a single crystal. The oxide semiconductor is called a single-crystal oxide semiconductor.

[0209] A single-crystal oxide semiconductor has, for example, a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. The transistor used in the channel formation region rarely has normally-on electrical characteristics. In addition, since a single-crystal oxide semiconductor has a low density of defect states, the density of trap states is low. Therefore, when a single-crystal oxide semiconductor is used for a channel formation region, The transistor may have small variations in electrical characteristics, making it a highly reliable transistor. .

[0210] Oxide semiconductors can have a high density if they have few defects. High crystallinity can increase density. The density increases when the concentration of impurities is low. The density of CAAC-OS is higher than that of microcrystalline oxide semiconductors. In addition, a polycrystalline oxide semiconductor may have a higher density than a microcrystalline oxide semiconductor. In addition, a microcrystalline oxide semiconductor may have a higher density than an amorphous oxide semiconductor.

[0211] In addition, the following conditions are preferably applied to form a CAAC-OS film.

[0212] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0213] In addition, by increasing the heating temperature of the surface to be film-formed (for example, the substrate heating temperature), After reaching the target, migration of sputtered particles occurs. The temperature is set to 100°C or higher and 740°C or lower, preferably 150°C or higher and 500°C or lower.

[0214] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0215] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0216] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000℃ and 1500℃, polycrystalline In-Ga -Zn-based metal oxide target. Note that the pressure treatment is not performed without cooling (or cooling naturally). The heating may be carried out while heating or while heating. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powders are mixed in ratios of 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3: The type of powder and the molar ratio of the powder to be mixed depend on the type of powder to be produced. The thickness may be changed as appropriate depending on the target to be used for pulverization.

[0217] Here, an oxide semiconductor (referred to as OS) and silicon (referred to as Si) in a crystalline state are used. ) are compared in Table 1.

[0218] [Table 1]

[0219] The crystalline state of oxide semiconductors includes, for example, amorphous oxide semiconductors (aO S, a-OS:H), microcrystalline oxide semiconductors (nc-OS, μc-OS), polycrystalline oxide semiconductors Conductor (polycrystalline OS), continuous crystalline oxide semiconductor (CAAC-OS), single crystal oxide semiconductor ( There are various types of silicon crystals, such as monocrystalline silicon (OS) and silicon dioxide (SiO2). Amorphous silicon (a-Si and a-Si:H), microcrystalline silicon (nc-Si, μc-Si ), polycrystalline silicon (polycrystalline Si), continuous crystalline silicon (CG Grain silicon), and single crystal silicon (single crystal Si).

[0220] For oxide semiconductors in each crystalline state, electron beams were focused to a beam diameter of 10 nm or less. When electron beam diffraction (ultrafine electron beam diffraction) is performed using In amorphous oxide semiconductors, a halo pattern (halo In the case of a microcrystalline oxide semiconductor, spots are observed. In the polycrystalline oxide semiconductor, spots and / or ring patterns are observed. In the case of a continuous crystal oxide semiconductor, spots are observed. In the case of a single crystal oxide semiconductor, , a spot is observed.

[0221] In addition, from the ultrafine electron diffraction pattern, the crystal part of the microcrystalline oxide semiconductor is nanometer (n The diameter of the polycrystalline oxide semiconductor is in the range of 1000 to 1500 μm. It can be seen that there are grain boundaries between the crystalline parts, and the boundaries are discontinuous. It can be seen that the conductor has no observable boundaries between the crystalline regions, and is continuously connected.

[0222] The density of an oxide semiconductor in each crystalline state will be described. The density of an amorphous oxide semiconductor is The density of a microcrystalline oxide semiconductor is low. The density of a continuous crystalline oxide semiconductor is medium. That is, the density of the continuous crystal oxide semiconductor is higher than that of the microcrystalline oxide semiconductor. The density of the semiconductor is higher than that of an amorphous oxide semiconductor.

[0223] The characteristics of the density of states (DOS) present in oxide semiconductors in each crystalline state are explained. The DOS of a crystalline oxide semiconductor is high. The DOS of a microcrystalline oxide semiconductor is slightly low. Semiconductors have a low DOS. Single-crystal oxide semiconductors have an extremely low DOS. The DOS of continuous crystalline oxide semiconductors is lower than that of microcrystalline oxide semiconductors. DOS is lower than that of amorphous oxide semiconductors, and microcrystalline oxide semiconductors have a lower DOS than amorphous oxide semiconductors. .

[0224] The oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. 9(A), the semiconductor film is a first oxide semiconductor film 188a and a second oxide semiconductor film 188b. The first oxide semiconductor film 188a and the second oxide semiconductor film 188b can be stacked. The second oxide semiconductor film 188b may be formed using a metal oxide having a different atomic ratio. , an oxide containing two kinds of metals in one oxide semiconductor film, an oxide containing three kinds of metals, an oxide containing four kinds of metals One of the oxides containing a metal is used, and the other oxide semiconductor film is oxides containing two different metals, oxides containing three different metals, and acids containing four different metals. Compounds may also be used.

[0225] In addition, the first oxide semiconductor film 188a and the second oxide semiconductor film 188b are made of the same elements. For example, the atomic ratio of one oxide semiconductor film may be set to The atomic ratio of the other oxide semiconductor film was In:Ga:Zn=3:1:2. The atomic ratio of one of the oxide semiconductor films may be In:Ga:Z The atomic ratio of the other oxide semiconductor film is In:Ga:Zn=1:3:2 In addition, the atomic ratio of one of the oxide semiconductor films may be In:Ga:Zn=1:1:1. The atomic ratio of the other oxide semiconductor film may be In:Ga:Zn=1:3:2. The atomic ratio of one oxide semiconductor film is In:Ga:Zn=1:1:1, and the atomic ratio of the other oxide semiconductor film is In:Ga:Zn=1:1:1. The atomic ratio of the oxide semiconductor film may be In:Ga:Zn=1:6:4. The atomic ratio of the oxide semiconductor film is In:Ga:Zn=1:1:1, and the other oxide semiconductor film is The atomic ratio of In:Ga:Zn may be 1:9:6. The atomic ratio includes a margin of error of plus or minus 20% of the atomic ratio.

[0226] At this time, among one oxide semiconductor film and the other oxide semiconductor film, the atomic number ratio of In and Ga of the oxide semiconductor film on the side closer to the gate electrode ( channel side) is set to In≧Ga, and the atomic number ratio of In and Ga of the oxide semiconductor film on the side farther from the gate electrode (back channel side) is set to In<Ga . By doing so, a transistor with a high field-effect mobility can be fabricated. On the other hand, by setting the atomic number ratio of In and Ga of the oxide semiconductor film on the channel side to In<Ga and the atomic number ratio of In and Ga of the oxide semiconductor film on the back channel side to In≧Ga, the change over time of the transistor and the amount of change in the threshold voltage due to the reliability test can be reduced. Also, the semiconductor film of the transistor may have a three-layer structure composed of a first oxide semiconductor film to a third oxide semiconductor film. At this time, the constituent elements of the first oxide semiconductor film to the third oxide semiconductor film may be the same, and the atomic number ratios thereof may be different. The configuration of the transistor having a three-layer structure of the semiconductor film will be described using FIG. 9(B).

[0227] The transistor shown in FIG. 9(B) has a first oxide semiconductor film 199a, a second oxide semiconductor film 199b, and a third oxide semiconductor film 199c laminated in this order from the gate insulating film 127 side. The materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c

[0228] are materials that can be expressed as InM Zn O 1x (x≧1, y>1, z>0, M1=Ga, Hf, etc.). However, when Ga is included in the materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c, if the proportion of Ga included is large, specifically y z InM Zn y O z (x≧1, y>1, z>0, M1=Ga, Hf, etc.). However, when Ga is included in the materials constituting the first oxide semiconductor film 199a and the third oxide semiconductor film 199c, if the proportion of Ga included is large, specifically InM 1X ZnY O Z If X exceeds 10, powder will be generated during film formation. This is inappropriate as it may cause

[0229] The material forming the second oxide semiconductor film 199b is InM 2x Zn y O z (x≧1 , y≧x, z>0, M2=Ga, Sn, etc.)

[0230] The conduction band minimum of the first oxide semiconductor film 199a and the conduction band minimum of the third oxide semiconductor film 199c The conduction band minimum of the second oxide semiconductor film 199b is the deepest from the vacuum level compared to the band minimum. The materials of the first, second, and third oxide semiconductor films are selected so as to form a well structure. Select as appropriate.

[0231] In an oxide semiconductor film, silicon and carbon, which are elements of Group 14, have donor levels Therefore, when silicon or carbon is contained in the oxide semiconductor film, The oxide semiconductor film becomes n-type. Therefore, the respective concentrations of silicon and carbon is 3 x 10 18 / cm 3 Less than or equal to 3 x 10 17 / cm 3 It has an area where In particular, it is preferable to form the second oxide semiconductor film 199b. The first oxide semiconductor film 199a and the third oxide semiconductor film 199b are formed in such a manner that a large amount of Group 14 elements are not mixed in. The second oxide semiconductor film 199b, which serves as a carrier path, is sandwiched between the oxide semiconductor films 199c. That is, the first oxide semiconductor film 199a and the third oxide semiconductor film 199b are preferably surrounded by the insulating film 199c. The oxide semiconductor film 199c is a second oxide semiconductor film containing a Group 14 element such as silicon or carbon. It can also be called a barrier film that prevents contamination of 199b.

[0232] For example, the first oxide semiconductor film 199a and the third oxide semiconductor film 199c are formed in an atomic ratio of 199a / 199c. In:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 The second oxide semiconductor film 199b is formed of a conductive film, and the atomic ratio of the second oxide semiconductor film 199b is In:Ga:Zn=1:1. The oxide semiconductor film can be formed using an oxide semiconductor film having a ratio of 1:1 or 3:1:2.

[0233] Alternatively, the first oxide semiconductor film 199a may be formed of a material having an atomic ratio of In:Ga:Zn=1:3:2. The second oxide semiconductor film 199b is formed of an oxide semiconductor film having an atomic ratio of In:Ga:Z. The oxide semiconductor film is formed of an oxide semiconductor film having n=1:1:1 or In:Ga:Zn=3:1:2. The oxide semiconductor film 199c of No. 3 is formed by etching the oxide semiconductor film 199c with an atomic ratio of In:Ga:Zn=1:6:4 or 1:9 The insulating film 10 may be formed of an oxide semiconductor film as described in Item 6.

[0234] The first to third oxide semiconductor films 199a to 199c contain the same constituent elements. Therefore, the second oxide semiconductor film 199b has a low conductivity at the interface with the first oxide semiconductor film 199a. In detail, the defect level (trap level) is The defect level at the interface between the gate insulating film 127 and the first oxide semiconductor film 199a is smaller than that at the interface between the gate insulating film 127 and the first oxide semiconductor film 199a. Therefore, by stacking oxide semiconductor films as described above, The amount of variation in threshold voltage due to aging and reliability testing can be reduced.

[0235] In addition, the conduction band minimum of the first oxide semiconductor film 199a and the third oxide semiconductor film 199c The conduction band minimum of the second oxide semiconductor film 199b is the deepest from the vacuum level compared to the conduction band minimum of the first oxide semiconductor film 199b. The first, second, and third oxide semiconductor films are formed to form a well structure such that By selecting the appropriate materials, it is possible to increase the field-effect mobility of transistors. Both aim to reduce the amount of variation in threshold voltage due to aging and reliability testing of transistors. can be done.

[0236] In addition, the first to third oxide semiconductor films 199a to 199c have different crystallinity. That is, a single-crystal oxide semiconductor, a polycrystalline oxide semiconductor, or the like may be used. oxide semiconductor, microcrystalline (nanocrystalline) oxide semiconductor, amorphous oxide semiconductor, and CAAC-OS film The first to third oxide semiconductor films 199a to 199c may be formed of any of the oxide semiconductor films 199a to 199c. When an amorphous oxide semiconductor is applied to one of the oxide semiconductor films 199c, the oxide semiconductor This reduces the internal and external stress of the film, reducing the variation in transistor characteristics. It is possible to reduce the amount of fluctuation in threshold voltage due to aging of transistors and reliability testing. do.

[0237] At least the second oxide semiconductor film 199b which can be a channel formation region is formed of CAAC Preferably, the film is an -OS film.

[0238] In addition, conductive materials that easily bond with oxygen (for example, When the oxide semiconductor film is brought into contact with a metal, oxygen in the oxide semiconductor film is easily bonded to the metal. The phenomenon of diffusion occurs toward the conductive material. The higher the temperature, the more pronounced this phenomenon becomes. The manufacturing process of the transistor involves several heating steps, and the above phenomenon can cause the oxide semiconductor Oxygen vacancies occur in the area of ​​the conductor layer near the contact with the source electrode or the drain electrode, The region is made n-type. Therefore, the n-type region becomes the source or drain of the transistor. It can act as an in

[0239] The n-type region is shown in FIGS. 9(A) and 9(B). The boundary 135 is the boundary between the intrinsic semiconductor region and the n-type semiconductor region, and is the boundary between the oxide semiconductor and the n-type semiconductor region. The area in contact with the source or drain electrode becomes the n-type area. 135 is a schematic illustration and may not be clear in reality. The position of 5 may also differ from the position shown.

[0240] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0241] (Embodiment 3) In this embodiment, electrons of a nanocrystalline oxide semiconductor film that can be used in one embodiment of the present invention will be described. The X-ray diffraction pattern and localized levels will be explained.

[0242] The nanocrystalline oxide semiconductor film was analyzed by electron diffraction (ultrafine electron diffraction) with a beam diameter of 10 nm or less. In the electron diffraction pattern using the diffractometer, a halo pattern indicating an amorphous state was observed, and a specific Unlike regular spots that show a crystalline state oriented in the plane, spots that have no directionality This is an oxide semiconductor film in which pots are observed.

[0243] Figure 13(A) shows a cross-sectional TEM (Transmission Electrical Transmission Electron Microscopy) image of the nanocrystalline oxide semiconductor film. The electron microscope (TEM) image is shown in Fig. 13 ( B) shows the electron diffraction pattern measured by using the electron microdiffraction at point 1 in Figure 13(A). The turn is shown in FIG. 13(C) as measured by microelectron diffraction at point 2 in FIG. 13(A). The electron diffraction pattern measured at point 3 in Figure 13(A) is shown in Figure 13(D). The electron diffraction patterns measured using sagittal beam diffraction are shown.

[0244] In FIG. 13, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film of 50 nm on a glass substrate. The deposition conditions for the conductor film were as follows: oxide target with In:Ga:Zn=1:1:1 (atomic ratio) Using a gas turbine, the temperature was measured under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, and DC power 0 The power was set to 0.5 kW and the substrate temperature was room temperature. The specimen is then sliced ​​to a width of 100 mm or less (for example, 40 nm ± 10 nm), and cross-sectional TEM images and ultrafine electron beam Electron diffraction patterns were obtained by diffraction.

[0245] Figure 13(A) shows the results of a transmission electron microscope (Hitachi High-Technologies Corporation "H-9000NAR" ) at an accelerating voltage of 300 kV and a magnification of 2 million times. 13(B) to 13(D) are cross-sectional TEM images of the film. Hitachi High-Technologies Corporation "HF-2000" was used, and the accelerating voltage was set to 200 kV. The electron diffraction pattern was obtained by ultrafine electron diffraction with a diameter of approximately 1 nmφ. The measurement range of the electron microbeam diffraction with a beam diameter of approximately 1 nm is 5 nm or more. nmφ or less.

[0246] As shown in FIG. 13(B), the nanocrystalline oxide semiconductor film was analyzed by electron beam diffraction using ultrafine electron beam diffraction. In the diffraction pattern, multiple spots (bright points) arranged circumferentially are observed. Then, in the nanocrystalline oxide semiconductor film, multiple spots distributed in a circumferential (concentric) pattern were observed. Alternatively, multiple spots distributed circumferentially form multiple concentric circles. It can also be said that...

[0247] In addition, the vicinity of the interface with the quartz glass substrate is shown in FIG. 13(D), and the nanocrystalline oxide semiconductor film is shown in FIG. In the center of the film thickness direction in FIG. 13(C), similar to FIG. 13(B), multiple circumferentially distributed In Figure 13(C), a circular spot is observed from the main spot. The distance to the surface was 3.88 / nm to 4.93 / nm. When converted to interplanar spacing, it was 0. 203nm to 0.257nm.

[0248] From the ultrafine electron diffraction pattern in Figure 13, it is clear that the nanocrystalline oxide semiconductor film has irregular plane orientation. It can be seen that the film contains a mixture of multiple crystal portions of different sizes.

[0249] Next, Fig. 14(A) shows a planar TEM image of the nanocrystalline oxide semiconductor film. B) shows the electron diffraction pattern of the circled area in Fig. 14(A) measured by selected area electron diffraction. The sagittal diffraction pattern is shown.

[0250] In FIG. 14, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film with a thickness of 30 nm on a glass substrate. The deposition conditions for the thin film were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, the experiment was carried out in an oxygen atmosphere (flow rate 45sccm), with a pressure of 0.4Pa and a direct current (DC) power supply of 0. The power was 5 kW and the substrate temperature was room temperature. Then, the sample was thinned and the flatness of the nanocrystalline oxide semiconductor film was measured. Area TEM images and electron diffraction patterns were obtained by electron beam diffraction.

[0251] Figure 14(A) shows the results of a transmission electron microscope (Hitachi High-Technologies Corporation "H-9000NAR" ) at an accelerating voltage of 300 kV and a magnification of 500,000 times. In addition, Fig. 14(B) shows the electron beam with a selected field of view of 300 nmφ. This is the electron beam diffraction pattern obtained by diffraction. Taking into account the spread of the electron beam, The measurement range is 300 nmφ or more.

[0252] As shown in FIG. 14(B), the nanocrystalline oxide semiconductor film has a measurement range larger than that of the ultrafine electron diffraction. In the electron diffraction pattern using wide selected area electron diffraction, The multiple spots observed are not seen, and a halo pattern is observed.

[0253] Next, FIG. 15 shows an outline of the distribution of diffraction intensity in the electron beam diffraction patterns of FIGS. 13 and 14. FIG. 15(A) shows the electron microbeam diffraction patterns shown in FIGS. 13(B) to 13(D). 15(B) is a conceptual diagram of the distribution of diffraction intensity in the beam. 15(a) and 15(b) are schematic diagrams of the distribution of diffraction intensity in a selected area electron diffraction pattern. C) is the concept of the distribution of diffraction intensities in the electron diffraction pattern of a single crystal structure or polycrystalline structure Figure.

[0254] In Figure 15, the vertical axis is the electron beam diffraction intensity (arbitrary unit) that shows the distribution of spots, etc., and the horizontal axis is Indicates the distance from the main spot.

[0255] In the single crystal structure or polycrystalline structure shown in FIG. 15(C), the interplanar orientation of the crystal part is The spots are seen at a specific distance from the main spot depending on the spacing (d value).

[0256] On the other hand, as shown in Figure 13, the electron diffraction pattern of the nanocrystalline oxide semiconductor film is The spots have a relatively large width. In addition, the electron microdiffraction pattern shows clear spots between the concentric regions. It can be seen that there are areas with high brightness that are not bright.

[0257] In addition, as shown in FIG. 15(B), the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film was The electron beam diffraction intensity distribution in the graph shows a continuous intensity distribution. A) can be approximated by the results of observing the electron beam diffraction intensity distribution over a wide area. It is considered that the multiple spots shown in A) overlap and connect to obtain a continuous intensity distribution. can.

[0258] As shown in FIGS. 15A to 15C, the nanocrystalline oxide semiconductor film has irregular plane orientation. The film is a mixture of crystal parts of different sizes, and the crystal parts are controlled by the The particles must be so fine that no spots are observed in the limited-field electron diffraction pattern. is suggested.

[0259] In Figure 13, where multiple spots were observed, the nanocrystalline oxide semiconductor film was 50 nm or less. The electron beam diameter is focused to 1 nm, so the measurement range is The range is 5 nm to 10 nm. is at least 50 nm or less, for example, 10 nm or less, or 5 nm or less. It is speculated that:

[0260] Here, FIG. 16 shows the electron microbeam diffraction pattern on the quartz glass substrate. The set conditions were the same as those in FIGS. 13(B) to 13(D).

[0261] As shown in FIG. 16, the quartz glass substrate having an amorphous structure does not have a specific spot. A halo pattern with continuously changing brightness is observed from the main spot. In a film with an amorphous structure, even if electron beam diffraction is performed on a very small area, nanocrystals are not observed. A plurality of spots distributed in a circumferential shape, which are observed in a crystalline oxide semiconductor film, are not observed. Therefore, the multiple spots distributed circumferentially as observed in FIGS. 13(B) to 13(D) It is confirmed that this is unique to nanocrystalline oxide semiconductor films.

[0262] Also, in FIG. 17, the electron beam diameter is converged to about 1 nmφ at point 2 shown in FIG. 13(A). The electron diffraction pattern was measured after irradiation with the beam for 1 minute.

[0263] The electron beam diffraction pattern shown in FIG. 17 is similar to the electron beam diffraction pattern shown in FIG. 13(C). Multiple spots distributed circumferentially were observed, and no significant differences were found between the two measurement results. This means that the crystalline part confirmed in the electron diffraction pattern of Figure 13(C) is a nanocrystalline part. This means that the oxide semiconductor film is present from the time of film formation, and it is not irradiated with a focused electron beam. This means that the crystal part is not formed by the above.

[0264] Next, Fig. 18 shows a partially enlarged view of the cross-sectional TEM image shown in Fig. 13(A). , the vicinity of point 1 (surface of nanocrystalline oxide semiconductor film) in Figure 13(A) was photographed at a magnification of 8 million times. 18(B) shows the cross-sectional TEM image observed near point 2 in FIG. 13(A) ( Cross-sectional TEM image of the central part of the nanocrystalline oxide semiconductor film in the thickness direction, observed at 8 million times magnification. is.

[0265] The cross-sectional TEM image shown in Figure 18 does not clearly show the crystal structure of the nanocrystalline oxide semiconductor film. Cannot be confirmed.

[0266] The nanocrystals of this embodiment were also formed on the quartz glass substrate used for the observations of FIGS. 13 and 14. The sample on which the oxide semiconductor film was formed was analyzed by X-ray diffraction (XRD). Figure 19 shows the XRD spectrum obtained using the out-of-plane method. The results of measuring the

[0267] In FIG. 19, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg. The XRD spectrum was measured using an X-ray diffractometer manufactured by Bruker AXS. -8 ADVANCE was used.

[0268] As shown in FIG. 19, a peak due to quartz is observed in the vicinity of 2θ=20 to 23°. No peaks due to the crystalline portions contained in the nanocrystalline oxide semiconductor film can be confirmed.

[0269] From the results of Figures 18 and 19, it can be seen that the crystalline parts contained in the nanocrystalline oxide semiconductor film are extremely fine. This suggests that it is a crystalline part.

[0270] As described above, the nanocrystalline oxide semiconductor film of this embodiment can be measured using X-ray diffraction with a wide measurement range. X-ray diffraction (XRD) analysis showed a peak indicating orientation. The electron diffraction pattern obtained by selected area electron diffraction with a wide measurement range is Therefore, a halo pattern is observed in the nanocrystalline oxide semiconductor of this embodiment. Macroscopically, the film is equivalent to a film with disordered atomic arrangement. By using ultrafine electron beam diffraction with a sufficiently small sagittal beam diameter (for example, 10 nm or less), By measuring the nanocrystalline oxide semiconductor film, the electron diffraction pattern obtained shows spots. Therefore, the nanocrystalline oxide semiconductor film of this embodiment has a high luminance. , extremely small crystal parts with irregular crystal orientation (for example, grain size of 10 nm or less, or 5 nm or less, It can be assumed that the film is formed by the aggregation of extremely fine crystals (crystals of 3 nm or less). The nanocrystalline region containing do.

[0271] Here, the localized levels of the nanocrystalline oxide semiconductor film will be explained. The semiconductor film was measured by CPM (Constant Photocurrent Method). The results of the evaluation will be explained below.

[0272] First, the structure of the measurement sample will be described.

[0273] The measurement sample was an oxide semiconductor film provided on a glass substrate and a thin film in contact with the oxide semiconductor film. The semiconductor device includes a pair of electrodes and an insulating film that covers the oxide semiconductor film and the pair of electrodes.

[0274] Next, a method for forming the oxide semiconductor film included in the measurement sample will be described.

[0275] The target was In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]). The deposition gases used were argon gas at 30 sccm and oxygen gas at 15 sccm. The pressure was set to 0.4 Pa, the substrate temperature was set to room temperature, and a DC power of 0.5 kW was applied. The first oxide semiconductor film was formed by a sputtering method. The body film is a nanocrystalline oxide semiconductor film.

[0276] The first oxide semiconductor film was heated in a nitrogen atmosphere at 450° C. for 1 hour and then heated at 450° C. The first oxide semiconductor film is heated in an oxygen atmosphere for one hour to release hydrogen from the first oxide semiconductor film. and a treatment for supplying oxygen to the first oxide semiconductor film. The second oxide semiconductor film was a nanocrystalline oxide semiconductor film.

[0277] Next, a measurement sample having a first oxide semiconductor film and a measurement sample having a second oxide semiconductor film were Specifically, a pair of electrodes provided in contact with the oxide semiconductor film were subjected to CPM measurement. With a voltage applied between the electrodes, the light is irradiated onto the measurement sample surface between the terminals so that the photocurrent value is constant. The amount of light applied was adjusted, and the absorption coefficient was derived from the amount of irradiated light in the desired wavelength range.

[0278] The absorption coefficient due to the band tail was subtracted from the absorption coefficient obtained by CPM measurement of each measurement sample. The absorption coefficient, i.e., the absorption coefficient due to defects, is shown in Figure 11. In Figure 11, the horizontal axis is the absorption coefficient The vertical axis of FIG. 11 represents the number of times the oxide semiconductor film is heated, and the vertical axis represents the light energy. The lower end of the conduction band is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. Each curve indicates the relationship between the absorption coefficient and the light energy, and corresponds to a defect level.

[0279] FIG. 11A shows the measurement results of the measurement sample including the first oxide semiconductor film. The absorption coefficient is 5.28 x 10 -1 cm -1 FIG. 11(B) shows the second oxide The measurement results for a sample with a semiconductor film show that the absorption coefficient due to the defect level is 1.75 × 1 0 -2 cm -1 It was.

[0280] Therefore, defects in the oxide semiconductor film can be reduced by the heat treatment.

[0281] The first oxide semiconductor film and the second oxide semiconductor film were measured by X-ray reflectometry (XRR). The film density was measured using X-ray Reflectometry. The film density of the oxide semiconductor film is 5.9 g / cm 3 and the film density of the second oxide semiconductor film is 6.1g / cm 3 It was.

[0282] Therefore, the film density of the oxide semiconductor film can be increased by the heat treatment.

[0283] That is, it has been found that the higher the film density of an oxide semiconductor film, the fewer defects there are in the film. Light.

[0284] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0285] (Fourth embodiment) In this embodiment, a CAAC-OS film that can be used in one embodiment of the present invention will be described. The sagittal diffraction pattern and localized levels will be explained.

[0286] The CAAC-OS film used in this embodiment is an In—Ga—Zn oxide (In:Ga:Zn = 1:1:1 [atomic ratio]) and a spatula using a deposition gas containing oxygen. The CAAC-OS film is an In-Ga-Zn oxide film formed by the quartz crystal deposition method. For detailed explanation of the manufacturing method etc., please refer to the first and second embodiments.

[0287] Figure 20 shows a cross-sectional TEM (Transmission Electron Microscopy) image of the CAAC-OS film. The image of the point in Figure 20 is shown in Figure 21. Electron diffraction patterns measured at points 1 to 4 using electron diffraction are shown.

[0288] The cross-sectional TEM image shown in Figure 20 was taken using a transmission electron microscope (Hitachi High-Technologies Corporation's "H-9 The image was taken using a 300kV accelerating voltage and 2 million times magnification. The electron beam diffraction pattern shown in Figure 21 was obtained using a transmission electron microscope (Hitachi High-Technologies The acceleration voltage was 200 kV and the beam diameter was approximately 1 nmφ or The electron diffraction pattern was obtained with a beam diameter of approximately 50 nm. Electron beam diffraction is sometimes called ultrafine electron beam diffraction. In this case, the measurement range by electron beam diffraction is 5 nmφ or more and 10 nmφ or less.

[0289] Point 1 (surface side of the film), Point 2 (center of the film), Point 3 (underlying side of the film) shown in Figure 20 The electron diffraction patterns in the samples correspond to Figures 21(A), (B), and (C), respectively. The electron beam diameter was approximately 1 nmφ. The electron beam diffraction pattern for the entire film is shown in Figure 21(D). This is an electron beam diffraction pattern with a diameter of 0 nm.

[0290] The electron diffraction patterns at point 1 (surface side of the film) and point 2 (center of the film) are The formation of a pattern by the bright spots can be seen, but at point 3 (underlying film side), the pattern is slightly This is because the crystalline state of the CAAC-OS film varies in the thickness direction. At point 4 (whole film), the pattern due to spots (bright points) Since the formation of turns can be confirmed, the membrane as a whole is a CAAC-OS membrane, or It can be said that the film contains a CAAC-OS film.

[0291] Fig. 22 is an enlarged photograph of the vicinity of point 1 (film surface side) in Fig. 20. Interlayer insulating film A clear lattice image showing the orientation of the CAAC-OS film was confirmed up to the interface with the silicon oxynitride film. It is possible.

[0292] 23(A) and (B) show the CAAC-OS film, which is different from the CAAC-OS film used in the cross-sectional TEM observation of FIG. The cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film are shown. There are various forms, and as shown in Figure 23(B), peak A indicates a crystalline component near 2θ = 31°. appears. However, this peak may not appear clearly.

[0293] In the region shown by the concentric circles on the CAAC-OS film in FIG. 23(A), the beam diameter of the electron beam is set to 1n The results of electron beam diffraction were shown in Figure 24( (A), (B), (C), and (D). When the electron beam diameter is 1 nm, the results are shown in Figure 21. As in (A) and (B), the formation of a pattern with clear spots (bright points) can be confirmed. Yes. If the electron beam diameter is increased, the spot (bright point) becomes slightly unclear, The diffraction pattern confirmed that the film as a whole was a CAAC-OS film, or C It can be said that the film contains an AAC-OS film.

[0294] 25(A) and (B) show the CAAC-OS film used for the cross-sectional TEM observation in FIG. 23(A) after 4 min. The cross-sectional TEM photograph and X-ray diffraction spectrum are shown after annealing at 50°C.

[0295] In the region shown by the concentric circles on the CAAC-OS film in FIG. 25(A), the beam diameter of the electron beam is set to 1n The results of electron beam diffraction were shown in Figure 26( As shown in Figure 24, the electron beam diameter However, at 1 nm diameter, it is possible to confirm the formation of a pattern with clear spots (bright points). In addition, as the electron beam diameter increases, the spot (bright spot) becomes slightly unclear. However, the diffraction pattern can be confirmed, and the film as a whole is a CAAC-OS film. It can be said that the film is a film containing a CAAC-OS film.

[0296] 27(A) and 27(B) show the CAAC-OS film used in the cross-sectional TEM photograph of FIG. 20 and the The cross section of the CAAC-OS film is different from that used for the cross-sectional TEM observation of 23(A). The CAAC-OS films have various morphologies, as shown in Figure 2. As shown in 7(B), peak A, which indicates a crystalline component, appears near 2θ=31°. Peak B, which is derived from the spinel crystal structure, may also appear.

[0297] In the region shown by the concentric circles on the CAAC-OS film in FIG. 27(A), the beam diameter of the electron beam is set to 1n The results of electron beam diffraction were shown in Figure 28( (A), (B), (C), and (D). When the electron beam diameter is 1 nm, a clear The formation of patterns by spots (bright points) can be confirmed. As the diameter increases, the spot (bright spot) becomes slightly unclear, but the diffraction pattern can still be confirmed. In addition, a clearer spot (bright spot) can be seen with a beam diameter of 90 nm. Therefore, the entire film is a CAAC-OS film, or a CAAC- It can be said that the film contains an OS film.

[0298] Here, we will explain the localized states of the CAAC-OS film. Evaluated by CPM (Constant Photocurrent Method) measurement The results will be explained.

[0299] First, the structure of the sample measured by CPM will be explained.

[0300] The measurement sample was an oxide semiconductor film provided on a glass substrate and a thin film in contact with the oxide semiconductor film. The semiconductor device includes a pair of electrodes and an insulating film that covers the oxide semiconductor film and the pair of electrodes.

[0301] Next, a method for forming the oxide semiconductor film included in the measurement sample will be described.

[0302] The target was In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]). The deposition gases used were argon gas at 30 sccm and oxygen gas at 15 sccm. The conditions were set as follows: pressure 0.4 Pa, substrate temperature 400°C, and DC power 0.5 kW. Next, an oxide semiconductor film was formed by a sputtering method using a nitrogen atmosphere at 450° C. After heating in an oxygen atmosphere at 450°C for 1 hour, the oxide semiconductor film was A treatment for desorbing hydrogen from the oxide semiconductor film and a treatment for supplying oxygen to the oxide semiconductor film were performed. The oxide semiconductor film is a CAAC-OS film.

[0303] Next, the measurement sample having the oxide semiconductor film was subjected to CPM measurement. The photocurrent value is set to be constant when a voltage is applied between a pair of electrodes in contact with the semiconductor film. The amount of light irradiated onto the sample surface between the terminals is adjusted as shown in Fig. 1, and the absorbance is calculated from the amount of irradiated light within the desired wavelength range. The coefficient of expansion was derived.

[0304] The absorption coefficient due to the band tail was subtracted from the absorption coefficient obtained by CPM measurement of each measurement sample. The absorption coefficient, i.e., the absorption coefficient due to defects, is shown in FIG. 12. In FIG. 12, the horizontal axis is the absorption coefficient The vertical axis of FIG. 12 represents the number of times the oxide semiconductor film is heated, and the vertical axis represents the light energy. The lower end of the conduction band is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. The curve shows the relationship between the absorption coefficient and the light energy, and corresponds to the defect level.

[0305] In the curve shown in Figure 12, the absorption coefficient due to the defect level is 5.86 × 10 -4 cm -1 in That is, the CAAC-OS film has an absorption coefficient due to defect levels of 1×10 -3 / cm , preferably 1 x 10 -4 / cm, which means that the film has a low defect level density.

[0306] Regarding the oxide semiconductor film, X-ray reflectometry (XRR) was used. The film density of the oxide semiconductor film was measured using a TEM (electron spectroscopy). m 3 That is, the CAAC-OS film has a high film density.

[0307] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0308] (Embodiment 5) A semiconductor device having a display function using the transistor and the capacitor described as an example in the above embodiment A semiconductor device (display device) can be manufactured. The entire display unit or the entire display unit is integrally formed on the same substrate as the pixel unit to form a system-on-panel. In this embodiment, a display using the transistors shown as examples in the above embodiment modes can be realized. An example of the device will be described with reference to Figures 29 to 31. Note that Figure 30 is a diagram of the device shown in Figure 29(B). 30 is a cross-sectional view showing the cross-sectional configuration of the portion indicated by the dashed line MN. Therefore, only a part of the structure of the pixel portion is shown.

[0309] In FIG. 29(A), a pixel portion 902 provided on a first substrate 901 is surrounded by a A sealant 905 is provided, and the substrate is sealed with a second substrate 906. 9, the area surrounded by the sealing material 905 on the first substrate 901 is different from the area surrounded by the sealing material 905 on the first substrate 901. A second driving layer formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate is formed in the region. A first driving circuit 903 and a second driving circuit 904 are mounted on the substrate. 03, various signals and potentials applied to the first driver circuit 904 or the pixel portion 902 are FPC(Flexible printed circuit)918a, FPC918 It is supplied by b.

[0310] The first driver circuit 904 functions as a scanning line driver circuit. The driving circuit 903 has a function as a signal line driving circuit.

[0311] 29(B) and 29(C), a pixel portion 90 provided on a first substrate 901 A sealant 905 is provided so as to surround the first driver circuit 902 and the first driver circuit 904. A second substrate 906 is provided over the pixel portion 902 and the first driver circuit 904. The pixel portion 902 and the first driver circuit 904 are formed by the first substrate 901 and the sealing material 905. The display element is sealed with the second substrate 906. In FIG. 9(C), the area surrounded by the sealing material 905 on the first substrate 901 and In a different region, a second driving layer formed of a separately prepared single crystal semiconductor or polycrystalline semiconductor is formed. In FIG. 29(B) and FIG. 29(C), the second driving circuit 903 is implemented. Various signals and signals are applied to the driving circuit 903, the first driving circuit 904, or the pixel portion 902. The potential is supplied from FPC918.

[0312] In addition, in FIG. 29(B) and FIG. 29(C), a second driving circuit 903 is separately formed. 1, an example in which the first substrate 901 is mounted is shown, but the present invention is not limited to this configuration. The drive circuit may be formed separately and mounted, or may be part of the second drive circuit or the first drive circuit. Alternatively, only a part of the above may be formed separately and mounted.

[0313] The method of connecting the separately formed drive circuit is not particularly limited, and may be ip On Glass) method, wire bonding method, or TCP (Tape Car A method of implementing the RIER Package can be used. This is an example in which a second driving circuit 903 and a first driving circuit 904 are implemented using the COG method. FIG. 29(B) shows an example in which the second driving circuit 903 is mounted by the COG method. C) is an example in which the second driving circuit 903 is implemented as a TCP.

[0314] The display device also includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs, etc., including the above are mounted.

[0315] In this specification, the term "display device" refers to an image display device or a display device. In addition, it can function as a light source (including a lighting device) instead of a display device. Connector, for example, a module with an FPC or TCP attached, a printer at the end of the TCP A module with a printed wiring board or a display element is mounted with an IC (integrated circuit) by the COG method. ) is also included in the display device.

[0316] The pixel portion and the first driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be applied to this.

[0317] A liquid crystal element, a light-emitting element, or the like can be used as a display element provided in the display device. An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be constructed by a pair of electrodes and a liquid crystal layer. The optical modulation effect of the liquid crystal is achieved by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field or oblique electric field). The liquid crystal element is controlled by a voltage (including an electric field in the direction of the arrow). Nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermo tropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (P DLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, banana-shaped liquid crystal, etc. As a method for driving the liquid crystal, there are TN (Twisted Nem) atic mode, STN (Super Twisted Nematic) mode, I PS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode ld Switching) mode, MVA (Multi-domain Vertic) mode al Alignment) mode, PVA(Patterned Vertical) mode Alignment mode, ASV (Advanced Super View) mode ASM(Axially Symmetric aligned Micro-ce ll) mode, OCB (Optically Compensated Birefringence ngence) mode, ECB (Electrically Controlled B refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) Liquid Crystal mode, PNLC (Polymer Network Liquid Crystal) Iquid Crystal mode, guest host mode, Blue Phase However, it is not limited to these, and the liquid crystal element and its driving method The luminance of the light-emitting element is controlled by a current or a voltage. This category includes elements that are used in the field of inorganic EL (Electro Luminescence) Also, electronic inks and other electrically-activated devices are included. A display medium whose contrast changes depending on the light source can also be applied. An example of a liquid crystal display device using a liquid crystal element will be shown below.

[0318] 30 is a cross-sectional view of a vertical electric field type liquid crystal display device. The connecting terminal electrode 915 and the terminal electrode 916 is electrically connected to a terminal of the FPC 918 via an anisotropic conductive agent 919 .

[0319] The connection terminal electrode 915 is formed from the same conductive film as the first electrode 930, and the terminal electrode 916 is The source and drain electrodes of the transistors 910 and 911 are formed of the same conductive film. are.

[0320] The pixel portion 902 and the first driver circuit 904 provided on the first substrate 901 are A transistor 910 included in a pixel portion 902 has a plurality of transistors, and a first driving circuit The transistor 910 and the transistor 911 included in the circuit 904 are illustrated. The insulating film 129, the insulating film 131, and the insulating film 140 shown in Embodiment 1 are formed on the transistor 911. An insulating film 924 corresponding to the insulating film 132 is provided. An insulating film 934 is provided to cover the insulating film 923. The insulating film 923 is an insulating nitride film.

[0321] In this embodiment, the transistor 910 is the same as that of the pixel 101 described in Embodiment 1. The transistor 911 can be a transistor provided in the above The transistor provided in the first driver circuit 104 described in Embodiment 1 is applied. Note that although the transistor 911 includes the conductive film 917, The conductive film 917 may not be provided.

[0322] The oxide semiconductor film 927, the insulating film 924, the insulating film 934, and the first electrode 930 are The oxide semiconductor film 927 is used to form a capacitor 936. The capacitor line 929 is electrically connected to the gate electrodes of the transistors 910 and 911. The capacitor 936 is formed from the same conductive film as the electrode. However, capacitors shown in other embodiments may be used as appropriate. do.

[0323] The transistor 910 provided in the pixel portion 902 is electrically connected to the display element, and The display element is not particularly limited as long as it can display, and various display elements can be used. You can be there.

[0324] The liquid crystal element 913, which is a display element, includes a first electrode 930, a second electrode 931, and a liquid crystal layer. The liquid crystal layer 908 is sandwiched between insulating films 932 which function as alignment films. and an insulating film 933 are provided. The second electrode 931 is provided on the second substrate 906 side. The first electrode 930 and the second electrode 931 are overlapped with each other via the liquid crystal layer 908. It has become.

[0325] A first electrode 930 and a second electrode 931 ( The direction of the light to be extracted and the electrodes are set The transparency or reflectivity can be selected depending on the location and the electrode pattern structure. do.

[0326] The first electrode 930 and the second electrode 931 are the same as the pixel electrode 121 shown in Embodiment 1. The above materials can be used appropriately.

[0327] The spacer 935 is a columnar spacer obtained by selectively etching an insulating film. and in order to control the distance (cell gap) between the first electrode 930 and the second electrode 931, It should be noted that a spherical spacer may also be used.

[0328] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, etc. The liquid crystals that can be used include polymer dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, the liquid crystal material can be in a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0329] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing a chiral agent is used for the liquid crystal layer. The organic resin contains hydrogen or water. Therefore, there is a risk that the electrical characteristics of the transistors in the semiconductor device may be deteriorated. By using a blue phase as the layer, it is possible to manufacture a semiconductor device according to one embodiment of the present invention without using an organic resin. Therefore, a highly reliable semiconductor device can be obtained.

[0330] The first substrate 901 and the second substrate 906 are fixed together by a sealing material 925. The cooling material 925 may be an organic resin such as a thermosetting resin or a photosetting resin. The sealing material 925 is in contact with the insulating film 924. The sealing material 925 is Equivalent to material 905.

[0331] The sealing material 925 is provided over the insulating film 924. The insulating film 934 is The uppermost layer of the insulating film 924 is a nitride insulating film, which is resistant to water from the outside. On the other hand, the insulating film 934 is moisture-permeable. Therefore, the insulating film 934 is provided inside the sealant 925, and the sealant is formed on the insulating film 924. By providing the 925 insulating material, the intrusion of impurities such as hydrogen and water from the outside is suppressed, and the transistor Therefore, the fluctuation of the electrical characteristics of the transistor 910 and the transistor 911 can be suppressed.

[0332] In addition, in liquid crystal display devices, black matrices (light-shielding films), polarizing members, phase difference members, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. Circularly polarized light produced by a retardation substrate may also be used. Either may be used.

[0333] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0334] 31, in the liquid crystal display device shown in FIG. 30, the second electrode 93 provided on the substrate 906 9 shows an example in which a common connection portion (pad portion) for electrically connecting to the substrate 901 is formed on the substrate 901. vinegar.

[0335] The common connection portion is arranged at a position overlapping the sealing material for bonding the substrate 901 and the substrate 906. The sealing material is electrically connected to the second electrode 931 via conductive particles contained in the sealing material. Alternatively, a common connection part is provided in a place that does not overlap with the sealing material (excluding the pixel part), and the common connection A paste containing conductive particles is provided separately from the sealing material so as to overlap the connecting portion, forming a second electrode 93. 1 may be electrically connected to the

[0336] The right side of FIG. 31A is a cross-sectional view of a transistor 910 provided in a pixel portion. The left side of (A) is a common connection that can be formed using the same process as the transistor. The common connection part shown in FIG. 31(A) is a cross-sectional view of the common connection part shown in FIG. 31(B). This corresponds to the cross section of IJ in the top view.

[0337] The common potential line 975 is provided on the gate insulating film 922 and is connected to the source potential of the transistor 910. The electrode 971 or the drain electrode 973 is fabricated using the same material and the same process.

[0338] The common potential line 975 is covered with the insulating film 924 and the insulating film 934. The insulating film 934 has a plurality of openings at positions overlapping the common potential line 975. The port is connected to one of the source electrode 971 or the drain electrode 973 of the transistor 910 and the first The contact hole is fabricated using the same process as that for connecting the electrode 930.

[0339] The common potential line 975 and the common electrode 977 are provided on the insulating film 924 and the insulating film 934. The common electrode 977 is provided on the insulating film 934. The same material and process as those for the connection terminal electrode 915 and the first electrode 930 of the pixel section are used. It is made by

[0340] In this way, the common connection portion is fabricated by the same fabrication process as the switching element of the pixel portion 902. It is possible.

[0341] The common electrode 977 is an electrode that comes into contact with the conductive particles contained in the sealing material, and is Electrical connection is made with the second electrode 931 .

[0342] 31(C), the common potential line 985 is connected to the gate electrode of the transistor 910. It may be manufactured using the same materials and processes as those described above.

[0343] In the common connection portion shown in FIG. 31(C), the common potential line 985 is connected to the gate insulating film 922, the insulating film The insulating film 922, the insulating film 924, and the insulating film 934 are provided below the insulating film 922, the insulating film 924, and the insulating film 934. The insulating film 934 has a plurality of openings at positions overlapping the common potential line 985. One of the source electrode 971 or the drain electrode 973 of the transistor 910 and the first electrode 9 30, the insulating film 924 and the insulating film 93 are formed by the same process as that for forming the contact holes. 4, and then selectively etching the gate insulating film 922. will be done.

[0344] The common potential line 985 and the common electrode 987 are connected to the gate insulating film 922, the insulating film 924, and the The common electrode 987 is electrically connected to the insulating film 934 through an opening formed in the insulating film 934. The film 934 is provided with the same material as the connection terminal electrode 915 and the first electrode 930 of the pixel portion. and are made using the same process.

[0345] As described above, by using the transistor and the capacitor described in the above embodiment, It is possible to provide a semiconductor device having a capacitance element with an increased charge capacity while increasing the efficiency. As a result, a semiconductor device with excellent display quality can be obtained.

[0346] In addition, oxygen vacancies are reduced in an oxide semiconductor film, which is a semiconductor film included in a transistor, and water is Since impurities such as silicon are reduced, the semiconductor device according to one embodiment of the present invention has good This results in a semiconductor device with good electrical properties.

[0347] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0348] (Sixth embodiment) In this embodiment, a semiconductor device according to one embodiment of the present invention can be used to process image information. The configuration of an information processing device capable of displaying the above information will be described with reference to FIGS. 32 and 33. Reveal.

[0349] Specifically, the G signal for selecting pixels is set to a frequency of 30 Hz (30 times per second) or more, preferably The frequency is between 60Hz (60 times per second) and 960Hz (960 times per second). The first mode is 11.6μHz (once a day) or more and 0.1Hz (0.1 times per second) Frequency less than 1Hz (once per second) and preferably 0.28mHz (once per hour) or more An information processing device having a second mode in which output is performed with full frequency will be described.

[0350] When a still image is displayed using an information processing device according to one embodiment of the present invention, the refresh rate is 1H z or less, preferably 0.2 Hz or less, and the display and use are easy on the user's eyes. It is possible to provide a display that reduces eye fatigue and does not strain the eyes of the user. In addition, the display image can be refreshed at an optimum frequency depending on the characteristics of the image displayed on the display unit. Specifically, compared to when displaying video smoothly, the refresh rate is lower. By using this method, it is possible to display still images with less flicker. This also has the effect of reducing power consumption.

[0351] FIG. 32 is a block diagram illustrating a configuration of an information processing device having a display function of one embodiment of the present invention. is.

[0352] FIG. 33 is a block diagram illustrating a structure of a display portion included in a display device of one embodiment of the present invention. .

[0353] The information processing device 600 having a display function described in this embodiment includes a display device 640, a computing device The device 620 includes an input means 500 (see FIG. 32).

[0354] The display device 640 includes a display unit 630 and a control unit 610 (see FIG. 32). Signal 625_V and primary control signal 625_C may be provided to a display device 640. The device 640 can display the image information on the display unit 630 .

[0355] The primary image signal 625_V includes not only the gradation information (which can also be called luminance information) of the image, but also, for example, chromaticity information. This includes information, etc.

[0356] The primary control signal 625_C controls, for example, the timing of the scanning operation of the display device 640. This includes signals for

[0357] The power supply potential and the like are supplied to the control unit 610 and the display unit 630 of the display device 640 .

[0358] The control unit 610 has a function of controlling the display unit 630. For example, the secondary image signal 615 V and / or secondary control signals 615_C, etc.

[0359] For example, the control unit 610 may be configured to include a polarity determination circuit. The polarity of can be reversed every frame.

[0360] The polarity determination circuit notifies the timing for inverting the polarity of the secondary image signal 615_V, and The control unit 610 has a function of inverting the polarity of the secondary image signal 615_V according to the timing. The polarity of the secondary image signal 615_V may be controlled in the control unit 610. It may be inverted, or inverted in the display unit 630 according to a command from the control unit 610. Good too.

[0361] The polarity determination circuit has a counter and a signal generation circuit, and generates the secondary image signal 6 using the synchronization signal. It may also have a function to determine the timing for reversing the polarity of 15_V.

[0362] The counter has a function of counting the number of frame periods using pulses of the horizontal synchronization signal. The signal generating circuit also determines the timing for inverting the polarity of the secondary image signal 615_V as follows: The counter has a function of notifying the control unit 610. Using the information on the number of periods, the polarity of the secondary image signal 615_V is calculated for each of the consecutive multiple frame periods. The gender can be reversed.

[0363] The secondary image signal 615_V may include image information.

[0364] For example, the control unit 610 generates a secondary image signal 615_V from a primary image signal 625_V. , the secondary image signal 615_V may be output.

[0365] The control unit 610 also sets the difference between the primary image signal 625_V and the reference potential Vsc as the amplitude, and A signal whose property is inverted for each frame may be generated as the secondary image signal 615_V.

[0366] The secondary control signal 615_C includes a first drive circuit (also called a G drive circuit 632) of the display unit 630. A signal for controlling the second driver circuit (also called S driver circuit 633) A signal for detecting the presence of a signal may be included.

[0367] For example, the control unit 610 may generate primary control signals including synchronization signals such as a vertical synchronization signal and a horizontal synchronization signal. The secondary control signal 615_C may be generated from the signal 625_C.

[0368] The secondary control signal 615_C includes, for example, a start pulse signal SP, a latch signal LP, a pulse width This includes a control signal PWC, a clock signal CK, and the like.

[0369] Specifically, the secondary control signal 615_C includes an S drive circuit 633 that controls the operation of the S drive circuit 633. Start pulse signal SP for the circuit, clock signal CK for the S drive circuit, latch signal LP, etc. Also, a star for the G drive circuit that controls the operation of the G drive circuit 632 can be included. It includes the clock signal SP for the G drive circuit, the clock signal CK for the G drive circuit, and the pulse width control signal PWC. It can be done.

[0370] The display portion 630 includes a pixel portion 631, a first driver circuit (also referred to as a G driver circuit 632), and a third driver circuit (also referred to as a G driver circuit 633). The image sensor 600 includes a second driver circuit (also referred to as an S driver circuit 633).

[0371] The pixel section 631 does not include light with a wavelength shorter than 420 nm in the display light, and has a resolution of 150 ppi or more. and wiring connecting the pixels. Each pixel 631p is connected to at least one of the scanning lines G and at least one of the signal lines S. The type and number of wirings depend on the configuration and number of pixels 631p. and placement dependent.

[0372] For example, when the pixels 631p are arranged in the pixel section 631 in a matrix of x columns and y rows, In this case, the signal lines S1 to Sx and the scanning lines G1 to Gy are arranged in the pixel portion 631. (See FIG. 33(A-1)). A plurality of scanning lines (G1 to Gy) supply G signals for each row. A plurality of signal lines (S1 to Sx) can supply S signals to a plurality of pixels. can be done.

[0373] The G driving circuit 632 controls the supply of the G signal 632_G to select the scanning line G (see FIG. 3 See 2).

[0374] For example, the pixel section 631 may be divided into a plurality of regions (specifically, a first region 631a, a second region 631b, and a The first and second regions 631a and 631b may be divided and driven (see FIG. 33(A-2)).

[0375] Each region includes a plurality of pixels 631p, a plurality of scanning lines for selecting the pixels 631p for each row, and line G as well as a plurality of signal lines S for supplying S signals 633_S to selected pixels 631p. can be set up.

[0376] In addition, a plurality of G drive circuits (specifically, a first G drive circuit 632a, a second G drive circuit 632b and a third G driving circuit 632c).

[0377] The G driving circuit controls the supply of the G signal 632_G to drive the scanning lines G (specifically, Specifically, the first G driving circuit 632a drives the scanning lines G1 to Gj, and the second G driving circuit 632b drives the scanning lines G1 to Gj. Gj+1 to G2j and the third G drive circuit 632c selects the scan lines G2j+1 to Gy can.

[0378] The G drive circuit outputs a first drive signal (also called a G signal) 632_G that selects the pixel circuit 634. to the pixel circuit 634. The G driving circuit 632 outputs a G signal 632_ G is applied to each scanning line at a frequency of 30Hz (30 times per second) or more, preferably 60Hz ( The first mode outputs at a frequency of 60 times per second or more but less than 960Hz (960 times per second), and the second mode outputs at a frequency of 100Hz or more but less than 960Hz (960 times per second). A frequency of 1.6 μHz (once a day) or more but less than 0.1 Hz (0.1 times per second), preferably The frequency is 0.28mHz (once per hour) or more but less than 1Hz (once per second). It has two modes.

[0379] The G drive circuit 632 can switch between a first mode and a second mode. For example, the secondary control signal 615_C or the secondary control signal 615_ The first mode of the G driving circuit 632 is started using a start pulse for the G driving circuit included in C. Specifically, the G drive output from the control unit 610 can be switched between the first and second modes. The frequency of output of the start pulse for the circuit may be controlled.

[0380] The G signal 632_G is generated by the G driving circuit 632. The G signal 632_G is generated for each row. The signal is output to the pixel 631p, and the pixel 631p is selected row by row.

[0381] The display unit 630 may include an S drive circuit 633. The S drive circuit generates a second drive signal (also referred to as S signal 633_S) is generated from the secondary image signal 615_V, and the S signal 633 _S to the signal lines S (specifically, S1 to Sx).

[0382] The S signal 633_S includes image gradation information, etc. The S signal 633_S is connected to the G signal 632_G. It is supplied to the selected pixel 631p.

[0383] The pixel section 631 has a plurality of pixels 631p.

[0384] The pixel 631p includes a display element 635 and a pixel circuit 634 including the display element 635 ( See Figure 32).

[0385] The pixel circuit 634 holds the supplied S signal 633_S and displays the image information on the display element 635. A part of the image is displayed by selecting a configuration according to the type or driving method of the display element 635. It can be used in the element circuit 634.

[0386] As an example of the pixel circuit 634, a configuration in which a liquid crystal element 635LC is applied to a display element 635 is shown. 33(B-1).

[0387] The pixel circuit 634 has a gate electrode to which a G signal 632_G is input and a second gate electrode to which an S signal is input. a transistor 634t having a first electrode and a second electrode of the transistor 634t; A liquid crystal element 635 having a first electrode connected to a common potential and a second electrode to which a common potential is supplied. LC and

[0388] The pixel circuit 634 includes a transistor that controls the supply of the S signal 633_S to the display element 635. It has 634t.

[0389] The gate of the transistor 634t is connected to one of the scanning lines G1 to Gy. One of the source and drain of the transistor 634t is connected to the signal line S1. Sx, and the other of the source and drain of the transistor 634t is , connected to the first electrode of the display element 635.

[0390] Pixel 631p controls transistor 634t to input S signal 633_S to pixel 631p. In addition, multiple transistors are used as a single switching element. The above-mentioned plurality of transistors may be connected in parallel to form a single transistor. They can be used as switching elements, connected in series, or in a combination of series and parallel. A shared connection may also be used.

[0391] The pixel 631p maintains the voltage between the first electrode and the second electrode of the liquid crystal element 635LC as needed. In addition to the capacitor element 634c for the The second electrode of the display element 635 may include other circuit elements such as an inductor. A predetermined common potential Vcom is applied.

[0392] The capacitance of the capacitor 634c may be adjusted as appropriate. For example, in the second mode described later, , when the S signal 633_S is held for a relatively long period (specifically, 1 / 60 seconds or more) A capacitor 634c is provided in the pixel circuit. The capacitance of the circuit 634 may be adjusted. may be stacked to substantially form a capacitance element.

[0393] As another example of a pixel circuit, a configuration in which an EL element 635EL is applied to a display element 635 is shown in FIG. 3(B-2) is shown.

[0394] The pixel circuit 634EL has a gate electrode to which a G signal 632_G is input and a gate electrode to which an S signal is input. a first electrode electrically connected to the first electrode of the capacitor 634c; and a second electrode electrically connected to the first electrode of the capacitor 634c. The first transistor 634t_1 has a first gate. a gate electrode electrically connected to the second electrode of the capacitor 634c; The first electrode is electrically connected to the first electrode of the EL element 635EL. and a second electrode of the second transistor 634t_2. A power supply potential is supplied to a second electrode of the second transistor 634t_2 and a first electrode of the second transistor 634t_2. A common potential is supplied to the second electrode of the EL element 635EL. The potential difference between the common potential and the potential of the EL element 635EL is greater than the light emission start voltage of the EL element 635EL.

[0395] In the pixel circuit 634, the transistor 634t adjusts the potential of the signal line S to the potential of the display element 635. It controls whether or not to apply it to the first electrode.

[0396] Note that a transistor using an oxide semiconductor is suitable for a display device of one embodiment of the present invention. For details of a transistor using an oxide semiconductor, see The descriptions in embodiments 1 and 2 can be referred to.

[0397] A transistor using an oxide semiconductor film has a low leakage current between the source and drain in an off state. The current (off-state current) is extremely low compared to conventional silicon transistors. A transistor with extremely low off-state current can be used in the pixel portion of the display unit. This makes it possible to reduce the frame frequency while suppressing the occurrence of flicker.

[0398] The display element 635 is not limited to the liquid crystal element 635LC, and may be, for example, a liquid crystal element that emits luminescence when a voltage is applied. OLED elements that generate electroluminescence and electrophoresis Various display elements can be applied, such as electronic ink that uses motion.

[0399] For example, the transmittance of polarized light through the liquid crystal element 635LC is controlled by the potential of the S signal 633_S. This allows for gradation to be displayed.

[0400] For example, when a transmissive liquid crystal element is applied to the display element 635, the light supply unit 650 is The light supply unit 650 has a light source. The control unit 610 controls the light supply unit 6 50. Light is supplied to a pixel portion 631 provided with a liquid crystal element. It functions as a backlight.

[0401] The light source of the light supply unit 650 may be a cold cathode fluorescent lamp, a light emitting diode (LED), an OLE D elements, etc. can be used.

[0402] In particular, it is preferable that the intensity of the blue light emitted by the light source is weaker than the intensity of the light of other colors. The blue light contained in the light emitted by the eye reaches the retina without being absorbed by the cornea or lens of the eye. This can lead to long-term effects on the retina (e.g., age-related macular degeneration) and exposure to blue light late at night. Circadian rhythms during exposure to hm) can be reduced. Specifically, it is 400 nm or less, preferably 420 nm or less. It does not contain light with a wavelength of 440 nm or less (also known as UVA) A light source that emits light is preferred.

[0403] Note that in the pixel of the semiconductor device of one embodiment of the present invention, light having the above wavelengths is absorbed and transmitted. Therefore, even if a light source that emits light having the above wavelength is used, By using the semiconductor device according to one embodiment of the present invention, light having the above wavelengths can be reduced or blocked. It is possible.

[0404] The computing device 620 receives a primary image signal 625_V and a primary control signal including a mode switching signal. Generate No. 625_C.

[0405] The mode switching signal may be generated by a command from the user of the information processing device 600 .

[0406] The user of the information processing device 600 can use the input means 500 to issue a command to switch the display. The image switching signal 500_C is supplied to the arithmetic unit 620. may be configured to output a primary control signal 625_C that includes a mode switching signal.

[0407] A primary control signal 625_C including a mode switching signal is sent to the control unit 610 of the display device 640. The control unit outputs a secondary control signal 615_C including a mode switching signal.

[0408] For example, a secondary control including a mode switching signal for switching from the second mode to the first mode. When the signal 615_C is supplied to the G drive circuit 632, the G drive circuit 632 operates in the second mode. Then, the G driving circuit 632 outputs the G signal for one frame or more. output, then switch to the second mode.

[0409] Specifically, when the input means 500 detects a page turning operation, the image switching signal 5 00_C may be output to the arithmetic unit 620.

[0410] The computing device 620 generates a primary image signal 625_V including a page turning operation, A primary control signal 625_C including a mode switching signal is output together with the image signal 625_V. .

[0411] The control unit 610 to which the primary image signal 625_V and the primary control signal 625_C are supplied is , a secondary control signal 615_C including a mode switching signal, and a secondary image control signal 615_C including a page turning operation. The image signal 615_V is supplied.

[0412] The G drive circuit 632, to which the secondary control signal 615_C including the mode switching signal is supplied, The mode switches from the second mode to the first mode, and the G signal 632_G is output with high frequency.

[0413] The S driver circuit 633 receives the secondary image signal 615_V including the page turning operation. An S signal 633 _S generated from the secondary image signal 615 _V is output to a pixel circuit 634 .

[0414] This allows pixel 631p to capture a large number of frame images, including page-turning actions, at a high frequency. As a result, the secondary image signal 615_V including the page turning operation can be It can be displayed smoothly.

[0415] The computing device 620 determines whether the primary image signal 625_V output to the display unit 630 is a moving image or a still image. and outputs a primary control signal 625_C including a mode switching signal according to the result of the determination. It may be configured to output.

[0416] Specifically, when the primary image signal 625_V is a moving image, the arithmetic unit 620 outputs a switching signal to select the first mode, and in the case of a still image, Alternatively, the computing device 620 may output a switching signal to select the second mode.

[0417] In addition, as a method for determining whether an image is a moving image or a still image, If the difference between the signal of a frame and the frames before and after it is greater than a predetermined difference, When the image quality is high, it is determined to be a moving image, and when it is low, it is determined to be a still image.

[0418] When the control unit 610 switches the operation mode of the G drive circuit from one mode to another mode (For example, when switching from the second mode to the first mode) the G drive circuit After outputting 2_G a predetermined number of times, the mode may be switched to another mode. .

[0419] The input means 500 may be a touch panel, a touch pad, a mouse, a joystick, a A rack ball, a data glove, an imaging device, etc. can be used. This allows the electrical signal input from the input means 500 to be associated with the coordinates of the display unit. This allows the user to input commands to process the information displayed on the display. can.

[0420] The information input by the user through the input means 500 is, for example, an image displayed on the display unit. Drag to change the display position, advance the displayed image and display the next image swipe to move, scroll to move through strips of images, and Instructions for selecting images, pinch in and pinch out to change the size of the image to display In addition to commands to write, commands to input handwritten characters can also be given.

[0421] The illuminance is the amount of light incident on a unit area of ​​an illuminated surface per unit time, taking into account the spectral sensitivity of the eye. is the amount of light received.

[0422] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0423] (Embodiment 7) In this embodiment, a data processing method of a data processing device using a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIG.

[0424] Specifically, an image that can be displayed on a display portion of a data processing device using the semiconductor device of one embodiment of the present invention In particular, we will explain how to rewrite the image displayed on the display unit to another image. A method of switching images that is easy on the user's eyes, and a method of switching images that reduces eye fatigue This section explains how to change the image without straining the user's eyes.

[0425] FIG. 34 is a block diagram illustrating a configuration of a data processing device using a semiconductor device of one embodiment of the present invention. 1A and 1B are schematic diagrams for explaining image data.

[0426] One aspect of the present invention is a method for gradually rewriting a display image on a display unit of an information processing device. is.

[0427] This reduces the strain on the user's eyes when switching between displays. It is possible to provide a novel information processing method that can display images containing information processed by a unit in a manner that is easy on the eyes.

[0428] Rapidly switching between images can cause eye strain. For example, This includes scenes where significantly different scenes are switched between, and scenes where different still images are switched between. .

[0429] When switching between different images, the display should be switched gradually rather than instantaneously. It is preferable to switch images quietly and naturally.

[0430] For example, when switching the display from a first still image to a second still image, the first still image and A moving image in which the first still image fades out and is displayed between the second still images and / or It is preferable to insert a moving image in which the first still image and the second still image fade in. As the image fades out, a second still image fades in (crossfade). A moving image in which both images are superimposed may be inserted, as in the case of the first still image. A moving image that shows the image gradually changing (also known as morphing) into a second still image. You can insert it.

[0431] It should be noted that the first still image data is displayed at a low refresh rate, and then the image is switched. After displaying the image for the first time at a high refresh rate, the second still image data is displayed at a lower refresh rate. It may also be displayed in fresh rate.

[0432] An example of a method for switching between images A and B that are different from each other will be described below.

[0433] FIG. 34(A) is a block diagram showing the configuration of a display unit capable of switching images. The display unit shown in FIG. 34(A) includes a calculation unit 701, a storage unit 702, a control unit 703, and and a display unit 704.

[0434] In the first step, the calculation unit 701 receives the data of the image A and the image B from an external storage unit or the like. The data is stored in the storage unit 702.

[0435] In the second step, the calculation unit 701 divides the image A into 2 parts according to a preset division number. New image data is generated sequentially based on the image data of image A and image B.

[0436] In the third step, the generated image data is output to the control unit 703. The input image data is displayed on the display unit 704 .

[0437] FIG. 34(B) shows the generated image when switching from image A to image B in stages. FIG. 2 is a schematic diagram for explaining image data.

[0438] In FIG. 34(B), N (N is a natural number) pieces of image data are generated from image A to image B. When each image data is displayed for f frames (f is a natural number), Therefore, the period from image A to image B is f × N frames. It becomes mu.

[0439] Here, the parameters such as N and f mentioned above can be freely set by the user. The calculation unit 701 acquires these parameters in advance and calculates the value according to the parameters. , and generate image data.

[0440] The image data generated for the i-th time (i is an integer between 1 and N) is the image data of image A and image B. It can be generated by weighting and adding the image data of image B. For example, for a pixel, when image A is displayed, the brightness (gradation) is a, and when image B is displayed, the brightness (gradation) is a. When the brightness (gradation) of the image data generated for the i-th time is displayed, the brightness (gradation) of the image data generated for the i-th time is The brightness (gradation) c of the pixel is the value shown in Equation 1. Gradation is the gray level displayed by the display unit. An image that has only two levels of black and white is called an image with two levels of gradation. For example, the display unit of a conventional personal computer can display red, green, and blue. Each sub-pixel has 256 levels of gray to display different colors. The signal is input.

[0441]

number

[0442] Image data generated in this way can be used to switch from image A to image B. This allows for gradual (quiet) and natural transitions between discontinuous images.

[0443] In Equation 1, when a = 0 for all pixels, the image gradually switches from black to image B. Also, when b = 0 for all pixels, it corresponds to a fade-in where image A is replaced by image B. This corresponds to a fade-out, where the image gradually switches from black to black.

[0444] Above we have described how to switch between two images by temporarily overlapping them. However, a method that does not overlap may also be used.

[0445] If two images do not overlap, when switching from image A to image B, A black image may be inserted. In this case, when transitioning from image A to a black image or when transitioning from a black image to a When transitioning to image B, or both, the image switching method described above can be used. In addition, the image to be inserted between image A and image B is not limited to a black image, but can be a single image such as a white image. A color image may be used, or a multicolor image different from image A and image B may be used.

[0446] By inserting another image, especially a single color image such as a black image, between image A and image B, the image The timing of image switching can be perceived more naturally by the user, reducing stress on the user. You can switch images without feeling any discomfort.

[0447] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0448] (Embodiment 8) In this embodiment, a structure of a data processing device using a semiconductor device of one embodiment of the present invention will be described. This will be explained with reference to FIGS.

[0449] FIG. 35 is a diagram illustrating the effect of the information processing device.

[0450] FIG. 36 is a block diagram illustrating the configuration of an information processing device.

[0451] There are two types of eye fatigue: nervous fatigue and muscular fatigue. Shown in Figure 35(A).

[0452] Nervous system fatigue can be caused by looking at the light emitted by the display or a flashing screen for a long time, and the brightness of the screen can be It stimulates the retina, nerves, and brain, causing fatigue. The phenomenon in which the display blinks rapidly is called flicker, and this type of flicker is caused by nervous system fatigue. causes labor.

[0453] Muscle fatigue is caused by overworking the ciliary muscles used for focusing. It is something that can be done.

[0454] FIG. 35(A-1) shows a schematic diagram of a conventional display unit. The image is rewritten 60 times in one sitting. , which may stimulate the retina, nerves or brain of the user's eyes, causing eye fatigue.

[0455] Also, as shown in FIG. 35(A-2), when the size of one pixel is large (for example, when the resolution is 1 If the resolution is less than 50ppi, the outlines of characters displayed on the display will be blurred. If you continue to look at a displayed image with blurred outlines for a long time, the ciliary muscles will constantly lose focus. You will have to keep moving and straining your eyes in an attempt to align them, which can put strain on your eyes.

[0456] Methods for quantitatively measuring eye fatigue are being considered. For example, evaluation of nervous system fatigue. As an index, the critical flicker frequency (CFF) is used. On) Frequency) are also known as evaluation indices for muscle fatigue. The adjustment time and the near point distance are known as factors.

[0457] Other methods for assessing eye fatigue include electroencephalography, thermography, and blinking. Measurement, tear volume evaluation, pupil contraction reaction speed evaluation, and questionnaire to investigate subjective symptoms There are also

[0458] In order to solve the above problem, one aspect of the present invention is to provide a method for controlling the illuminance of a work environment and a display device. The following embodiment focuses on the gradation of the background of the image information. This includes one aspect of the present invention that was created by focusing on the gradation information in the background of the image information.

[0459] The image information processing and display method according to one aspect of the present invention includes: a step of acquiring background gradation information of the image information to be displayed; The display light does not include light with a wavelength shorter than 420 nm and has a resolution of 150 ppi or more. and displaying the image on a display unit having a plurality of pixels. This allows the display of information at a brightness appropriate for the lighting of the environment. It is possible to provide a novel method for processing and displaying image information that allows for a display that is easy on the eyes.

[0460] An information processing device to which the image information processing and display method of one embodiment of the present invention can be applied An example of a block diagram is shown in FIG.

[0461] The information processing device 330 includes a calculation unit 311, a storage unit 312, and a transmission path 314. The circuit 314 connects the calculation unit 311, the storage unit 312, and the input / output interface 315 to each other. These components cannot be clearly separated, and one component can be connected to another. For example, a touch panel may be a display unit. It is also an input means.

[0462] The input / output device 320 is connected to the transmission line 314 via the input / output interface 315. The input / output device 320 inputs information from outside the arithmetic device 310 or receives information from outside the arithmetic device 310. It is a device for outputting information to a

[0463] The input / output device 320 may be a communication device, a network connection device, a hard disk, An example of this is a writable external storage unit such as a removable memory. do.

[0464] The input means 321 is a human input such as a keyboard, a mouse, or a touch panel. Interface devices, cameras such as digital cameras and digital video cameras, scanners Examples include read-only external storage devices such as CD-ROMs and DVD-ROMs. For example, the user of the information processing device 330 can input a page turning command from the input means 321. You can enter orders, etc.

[0465] As output devices, in addition to the display unit 322, speakers, printers, etc. can be connected. .

[0466] The information processing device 330 according to one embodiment of the present invention includes a display unit 322. In particular, the display unit 322 includes: The display light does not contain light with a wavelength shorter than 420 nm, and preferably light with a wavelength shorter than 440 nm. The display area is provided with a resolution of 150 ppi or more, preferably 200 ppi or more. It is preferable to provide a plurality of pixels with a uniform color. This makes it possible to provide a display that is easy on the eyes. In this specification, the display light is a light emitted by a display unit of an information processing device to display an image. Refers to light emitted or reflected toward the user.

[0467] The display light of the display unit according to one aspect of the present invention reaches the retina without being absorbed by the cornea or the crystalline lens of the eye. It does not contain light that has long-term effects on the retina or adverse effects on circadian rhythms. Generally, the light for displaying an image is 400 nm, preferably 420 nm, and more preferably 440 nm. It does not contain light with the following wavelengths (also known as UVA):

[0468] The data processing device 330 of one embodiment of the present invention can include a semiconductor device of one embodiment of the present invention. In the pixel of the semiconductor device, light having the above wavelength is absorbed and hardly passes through. Therefore, even if a light source that emits light having the above wavelength is used, one aspect of the present invention can be realized. By using such a semiconductor device, it is possible to reduce or block light having the above wavelengths. can.

[0469] Furthermore, the resolution of the pixels included in the display unit according to one embodiment of the present invention is 150 ppi, preferably 20 0ppi or more, and the size of each pixel is small, which reduces fatigue of the user's eye muscles. is reduced.

[0470] FIG. 35(B) is a schematic diagram illustrating the effect of reducing eye fatigue of an information processing device according to one embodiment of the present invention. ) shown.

[0471] The information processing device according to one embodiment of the present invention can change the frequency of outputting a signal for selecting a pixel. In particular, by using a transistor with extremely low off-state current in the pixel portion of the display unit, It is possible to reduce the frame frequency while suppressing flicker. For example, for 5 seconds Since the image can be rewritten once per image, the same image can be viewed, and the user This reduces the perceived flicker of the screen, which can be harmful to the retina, nerves, or brain of the user's eyes. This reduces the stimulation received by the nervous system, thereby alleviating fatigue (see Figure 35(B-1)).

[0472] An example of a transistor with extremely low off-state current is a transistor using an oxide semiconductor. A transistor, particularly a transistor using a CAAC-OS, is preferable.

[0473] In the data processing device of one embodiment of the present invention, the size of one pixel is small. It is possible to display high-resolution images with a resolution of 200 ppi or more. It also allows for a detailed and smooth display. This allows the ciliary muscles to focus. This reduces muscle fatigue of the user (see Figure 35(B-2)). Resolution is expressed using pixel density (ppi: pixels per inch). Pixel density is the number of pixels per inch. Pixels make up an image. It is a unit.

[0474] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. .

[0475] (Embodiment 9) The semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including gaming machines). The electronic devices include television sets, computer monitors, and Digital cameras, digital video cameras, digital photo frames, mobile phones, game consoles , portable game machines, portable information terminals, sound reproduction devices, gaming machines (pachinko machines, slot machines) Examples of these electronic devices are shown in Figs. 37 and 38.

[0476] 37A shows a table 9000 having a display unit. The display unit 9003 is incorporated in the camera 01, and the display unit 9003 can display images. It is possible. In addition, the structure in which the housing 9001 is supported by four legs 9002 is shown. The housing 9001 also has a power cord 9005 for power supply.

[0477] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Therefore, the display quality of the display portion 9003 can be improved.

[0478] The display unit 9003 has a touch input function, and the display unit 9003 of the table 9000 By touching the displayed display button 9004 with a finger or the like, the screen can be operated or information can be input. It can also communicate with other home appliances or control them, improving the quality of images. It may also be used as a control device to control other home appliances by touch panel operation. If a semiconductor device having a sensor function or an image sensor function is used, the display portion 9003 can be It can have input functionality.

[0479] In addition, the screen of the display unit 9003 can be vertically fixed to the floor by a hinge provided in the housing 9001. It can also be set upright and used as a television set. If you install a large screen television, the free space will be narrow, but it is possible to install it on a table. If the display unit is built in, the space in the room can be used more effectively.

[0480] FIG. 37(B) shows a television device. The television device 9100 has a housing 9 The display unit 9103 is incorporated in the 101, and the display unit 9103 can display images. In this example, a configuration in which the housing 9101 is supported by a stand 9105 is shown. is doing.

[0481] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by the remote controller 9110. The channel and volume can be controlled by the operation keys 9109. 3. The remote controller 9110 can also be used to A display unit 9107 for displaying information output from the remote controller is provided. That's fine.

[0482] A television device 9100 shown in FIG. 37(B) includes a receiver, communication means, and the like. The television device 9100 can receive general television broadcasts using a receiver. Furthermore, by connecting to a wired or wireless communication network via a communication means, It can be one-way (sender to receiver) or two-way (between sender and receiver, or between receivers). It is also possible to carry out information communication such as

[0483] The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107. Therefore, the display quality of the television device can be improved.

[0484] FIG. 37C shows a computer 9200, which includes a main body 9201, a housing 9202, a display unit 92 03, keyboard 9204, external connection port 9205, pointing device 9206 Includes:

[0485] The semiconductor device described in any of the above embodiments can be used for the display portion 9203. Therefore, the display quality of the computer 9200 can be improved.

[0486] The display unit 9203 has a touch input function, and the display buttons displayed on the display unit 9203 are used to input a By touching the screen with your fingers, you can operate the screen and input information. Information can be entered using a keyboard or voice.

[0487] Figure 38(A) and Figure 38(B) show a foldable tablet terminal. ) is in an open state, and the tablet terminal includes a housing 9630, a display unit 9631a, a display part 9631b, a display mode changeover switch 9034, a power switch 9035, a power saving mode It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0488] The semiconductor device described in any of the above embodiments has a display portion 9631a and a display portion 9631b. Therefore, it is possible to improve the display quality of tablet devices. do.

[0489] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638, data can be input. In 1a, for example, half of the area has a display function only, and the other half The display unit 963 has a touch panel function, but is not limited to this. The entire area of ​​the display unit 96 may have a touch panel function. The entire surface of 31a is displayed as a keyboard button to serve as a touch panel, and the display part 9631b is displayed. It can be used as a screen.

[0490] In addition, in the display unit 9631b, as in the display unit 9631a, a part of the display unit 9631b The area 9632b of the touch panel can be used as the keyboard of the touch panel. By touching the area where the display switch button 9639 is displayed with your finger or a stylus, A keyboard can be displayed on the display portion 9631b.

[0491] In addition, touch panel area 9632a and touch panel area 9632b can be touched simultaneously. You can also input characters using the touchpad.

[0492] The display mode switch 9034 is used to change the display orientation, such as portrait or landscape. You can switch between black and white and color display. The Switch 9036 detects external light during use using a light sensor built into the tablet device. The tablet device can optimize the display brightness according to the amount of light in the room. In addition to sensors, other detection devices such as gyros and acceleration sensors that detect tilt are also included. It may be built-in.

[0493] FIG. 38A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other, and the display For example, one display panel may be capable of displaying images with higher resolution than the other. It may also be possible to use the following.

[0494] FIG. 38(B) shows the tablet terminal in a closed state, in which the solar cell 96 is mounted on the housing 9630. 33, a charge / discharge control circuit 9634 may be provided. An example of the circuit 9634 is a structure having a battery 9635 and a DC-DC converter 9636. This shows the composition of the

[0495] In addition, since the tablet device can be folded in half, the housing 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected. This makes it possible to provide a tablet terminal that is highly durable and reliable even when used for a long period of time.

[0496] In addition, the tablet terminals shown in Figures 38(A) and 38(B) can be used in various Functions that display information (still images, videos, text images, etc.), calendars, dates, or times The function to display the information on the display, and the function to touch input or edit the information displayed on the display. It has touch input function, function to control processing by various software (programs), etc. It is possible.

[0497] The solar cell 9633 attached to the surface of the tablet terminal supplies power to the touch panel, The solar cell 9633 can be supplied to a display unit, a video signal processor, or the like. It can be installed on one or both sides of the housing 9630, and can efficiently charge the battery 9635. It is possible to use a lithium-ion battery as the battery 9635. This has the advantage of being able to reduce the size.

[0498] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. 38(B) are shown in FIG. A block diagram is shown and explained. In FIG. 39(A), a solar cell 9633, a battery 9635 , a DC-DC converter 9636, a DC-DC converter 9637, switches SW1 to SW 3. The load (display unit 9631, etc.) is shown, along with the battery 9635 and the DC / DC converter. The inverter 9636, the DC-DC converter 9637, and the switches SW1 to SW3 are shown in FIG. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

[0499] First, an example of operation when power is generated by the solar cell 9633 will be described. The power generated by the pond is converted into a voltage for charging the battery 9635 by the DC-DC converter. The voltage is increased or decreased by the inverter 9636. Then, the operation of the load (display unit 9631, etc.) When power is supplied from the solar cell 9633, switch SW1 is turned on and the DC / DC converter Converter 9637 steps up or down the voltage required for the load (display 9631, etc.). When power is not supplied to the load (display unit 9631, etc.), SW1 is turned The configuration is to turn it off and turn SW2 on to charge the battery 9635.

[0500] In addition, when power is always supplied to the load (display unit 9631, etc.) via the battery 9635, In this case, the switch SW1 may be omitted as shown in FIG. 39(B).

[0501] Also, if the voltage range of the battery 9635 is the same as the voltage of the appropriate voltage range to be supplied to the load, As shown in Figure 39(C), the DC-DC converter 9637 may be omitted. stomach.

[0502] The solar cell 9633 is shown as an example of a power generating means, but is not particularly limited thereto. Other power generation methods such as piezoelectric elements and thermoelectric conversion elements (Peltier elements) For example, the battery 9635 may be charged wirelessly (contactlessly). A wireless power transmission module that receives and charges, or a structure that combines other charging methods It may also be composed.

[0503] Note that the structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. You can be there. [Explanation of symbols]

[0504] 100 pixel unit 101 pixels 102 Circuit Board 103 Transistor 104 Drive circuit 105 Capacitive element 106 Drive circuit 107 scan lines 108 Liquid crystal element 109 Signal Line 110 Undercoat insulating film 111 Semiconductor film 113 Conductive film 115 Capacitance Line 117 Aperture 118 Nitride insulating film 119 Semiconductor Film 121 pixel electrode 127 Gate insulating film 129 insulating film 130 insulating film 131 insulating film 132 insulating film 135 Boundary 154 Counter electrode 188a Oxide semiconductor film 188b Oxide semiconductor film 199a Oxide semiconductor film 199b Oxide semiconductor film 199c Oxide semiconductor film 223 Transistor 227 Gate electrode 229 Wiring 231 Semiconductor Film 233 Wiring 241 Conductive Film 310 Arithmetic equipment 311 Arithmetic unit 312 Storage section 314 Transmission Line 315 Input / Output Interface 320 Input / Output Devices 321 Input Method 322 Display section 330 Information Processing Equipment 500 Input Method 500_C signal 600 Information Processing Devices 610 Control Unit 615_C Secondary control signal 615_V Secondary image signal 620 Arithmetic equipment 625_C Primary control signal 625_V Primary image signal 630 Display section 631 Pixel section 631a area 631b area 631c area 631p pixels 632 G drive circuit 632_G G signal 632a G drive circuit 632b G drive circuit 632c G drive circuit 633 S drive circuit 633_S S signal 634 pixel circuit 634c Capacitor 634EL pixel circuit 634t transistor 634t_1 Transistor 634t_2 transistor 635 Display element 635EL EL element 635LC liquid crystal element 640 Display device 650 Light supply unit 701 Arithmetic unit 702 Storage section 703 Control Unit 704 Display section 901 Circuit Board 902 Pixel section 903 Drive circuit 904 Drive Circuit 905 Sealing material 906 Circuit Board 908 Liquid crystal layer 910 Transistor 911 Transistor 913 Liquid crystal element 915 Connection terminal electrode 916 Terminal electrode 917 Conductive Film 918 FPC 918b FPC 919 Anisotropic conductive agent 922 Gate insulating film 923 Insulating Film 924 insulating film 925 sealing material 926 Capacitor 927 Oxide semiconductor film 929 Capacitance Line 930 electrode 931 Electrode 932 Insulating film 933 Insulating Film 934 Insulating film 935 Spacer 936 Capacitor 971 Source electrode 973 Drain electrode 975 Common potential line 977 Common electrode 985 Common potential line 987 Common electrode 9000 tables 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Tools 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9100 Television equipment 9101 Housing 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote Controller 9200 Computer 9201 Main Unit 9202 Housing 9203 Display section 9204 keyboard 9205 External connection port 9206 Pointing Device 9630 chassis 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / Discharge Control Circuit 9635 Battery 9636 DC / DC Converter 9637 DC / DC Converter 9638 Operation key 9639 Button

Claims

1. A display device having a transistor and a capacitor in a pixel, a first insulating film, a first oxide semiconductor film, a second oxide semiconductor film, a first conductive film, a second conductive film, a third conductive film, a second insulating film, a fourth conductive film, a third insulating film, and a fifth conductive film; the first insulating film has a region in contact with the first oxide semiconductor film and a region in contact with the second oxide semiconductor film; the first oxide semiconductor film has a region in contact with the first conductive film, a region in contact with the second insulating film, and a region in contact with the second conductive film; the first oxide semiconductor film includes a channel formation region of the transistor, the first conductive film has a region that functions as one of a source electrode and a drain electrode of the transistor, the second conductive film has a region that functions as the other of the source electrode and the drain electrode of the transistor, the second oxide semiconductor film has a region in contact with the third conductive film, the second oxide semiconductor film has a region that functions as an electrode of the capacitor, the second insulating film has a region in contact with the fourth conductive film and a region in contact with the third insulating film; the second insulating film has a region that functions as a gate insulating film of the transistor, the fourth conductive film has a region in contact with the third insulating film, the fourth conductive film has a region that functions as a gate electrode of the transistor, the third insulating film has a region in contact with the fifth conductive film, the fifth conductive film has a region that functions as a pixel electrode, the fifth conductive film is electrically connected to the second conductive film, the second oxide semiconductor film has a region overlapping with the fifth conductive film via the third insulating film but not via the second insulating film.

2. A display device having a transistor and a capacitor in a pixel, a first insulating film, a first oxide semiconductor film, a second oxide semiconductor film, a first conductive film, a second conductive film, a third conductive film, a second insulating film, a fourth conductive film, a third insulating film, and a fifth conductive film; the first insulating film has a region in contact with the first oxide semiconductor film and a region in contact with the second oxide semiconductor film; the first oxide semiconductor film has a region in contact with the first conductive film, a region in contact with the second insulating film, and a region in contact with the second conductive film; the first oxide semiconductor film includes a channel formation region of the transistor, the first conductive film has a region that functions as one of a source electrode and a drain electrode of the transistor, the second conductive film has a region that functions as the other of the source electrode and the drain electrode of the transistor, the second oxide semiconductor film has a region in contact with the third conductive film, the second oxide semiconductor film has a region that functions as an electrode of the capacitor, the second insulating film has a region in contact with the fourth conductive film and a region in contact with the third insulating film; the second insulating film has a region that functions as a gate insulating film of the transistor, the fourth conductive film has a region in contact with the third insulating film, the fourth conductive film has a region that functions as a gate electrode of the transistor, the third insulating film has a region in contact with the fifth conductive film, the fifth conductive film has a region that functions as a pixel electrode, the fifth conductive film is electrically connected to the second conductive film, the second oxide semiconductor film has a region overlapping with the fifth conductive film via the third insulating film but not via the second insulating film; the fifth conductive film does not overlap with the first oxide semiconductor film in a plan view of the pixel.

3. In claim 1 or claim 2, The display device, wherein the first oxide semiconductor film and the second oxide semiconductor film contain In.

4. In claim 1 or claim 2, The display device, wherein the first oxide semiconductor film and the second oxide semiconductor film contain indium oxide.

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