Display system, display system control method, and driver circuit mounted on the display system

Abstract

To provide a display system with which it is possible to reduce noise.SOLUTION: A display system comprises: a display device that includes a plurality of column signal lines arrayed in the horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arrayed in the vertical direction, a plurality of first image elements arranged at the intersections of the first row and the column signal lines, and a plurality of second image elements arranged at the intersections of the second row and the column signal lines; and a driver circuit that includes a plurality of first drive circuits, provided for each of the first row signal lines, that supply charges to the first image elements in a first period via the corresponding first row signal lines and extract charges from the first image elements in a second period that is different from the first period, and a plurality of second drive circuits, provided for each of the second row signal lines, that supply charges, via the corresponding second row signal lines, to the second image elements in a third period that at least partly overlaps the second period and extract charges from the second image elements in a fourth period that at least partially overlaps the first period.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display system, and more particularly to a display system, a control method for a display system, and a driver circuit mounted on the display system. [Background technology]

[0002] Conventionally, display systems with flat display surfaces, such as liquid crystal displays, have been known. In such display systems, picture elements are arranged at the intersections of a plurality of column signal lines arranged horizontally and a plurality of row signal lines arranged vertically on the plane, and a driver circuit is further provided for charging and discharging the picture elements. The display system displays an image by sequentially driving each row signal line with the driver circuit and applying the charge applied to the column signal line to the corresponding picture element.

[0003] In this regard, Patent Document 1 discloses a liquid crystal display device that includes a liquid crystal display panel in which pixel elements are arranged at the intersections of a plurality of gate lines and a plurality of source lines that are arranged orthogonal to each other, and a gate driver that drives the plurality of gate lines. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2014 / 007199 Brochure Summary of the Invention [Problem to be solved by the invention]

[0005] Recently, as display systems have become larger and higher-resolution, the load capacitance of row signal lines has increased, leading to an increase in magnetic field noise and electric field noise emitted from the row signal lines. Furthermore, the driving frequency of row signal lines has also increased, shortening the generation cycle of magnetic field noise and electric field noise. Such magnetic field noise and electric field noise can cause malfunctions and reduced accuracy in various electronic components, such as sensors, installed in the display system.

[0006] The present invention has been made in view of the above problems, and its object is to provide a display system capable of reducing noise, a control method for the display system, and a driver circuit to be mounted on the display system. [Means for solving the problem]

[0007] In order to solve the above problem, a first display system according to the present invention includes a display device having a plurality of column signal lines arranged in a horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arranged in a vertical direction, a plurality of first image elements arranged at intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at intersections of the second row signal lines and the column signal lines, and a driver circuit having a plurality of first drive circuits provided for each of the first row signal lines and driving the first image elements via the corresponding first row signal lines, and a plurality of second drive circuits provided for each of the second row signal lines and driving the second image elements via the corresponding second row signal lines, wherein the first drive circuits supply charges to the first image elements in a first period and extract charges from the first image elements in a second period different from the first period, and the second drive circuit supplies charges to the second image elements in a third period that at least partially overlaps with the second period, or extracts charges from the second image elements in a fourth period that at least partially overlaps with the first period.

[0008] Furthermore, the display system according to the second aspect of the present invention further comprises a first clock line that supplies a first clock to the first drive circuit and a second clock line that supplies a second clock to the second drive circuit, wherein the first drive circuit either supplies or draws charge to the first image element in accordance with the alternation of the first clock, and the second drive circuit either supplies or draws charge to the second image element in accordance with the alternation of the second clock, and the first clock line and the second clock line are arranged parallel to and adjacent to each other.

[0009] Furthermore, a third display system according to the present invention further comprises a first clock line that supplies a first clock to the first drive circuit and a second clock line that supplies a second clock to the second drive circuit, wherein the first drive circuit either supplies or draws charge to the first image element in accordance with the alternation of the first clock, and the second drive circuit either supplies or draws charge to the second image element in accordance with the alternation of the second clock, and the first clock line and the second clock line are arranged so as to intersect with each other at a fixed distance.

[0010] Furthermore, in a display system according to a fourth aspect of the present invention, the first drive circuit and the second drive circuit are alternately connected in series, the first drive circuit holds information indicated by a signal output from the second drive circuit connected in the previous stage, and outputs a signal including the information held during the first period to the second drive circuit connected in the next stage, the second drive circuit holds information indicated by a signal output from the first drive circuit connected in the previous stage, and outputs a signal including the information held during the third period to the first drive circuit connected in the next stage, the first drive circuit initializes the information it holds in accordance with a signal output from the first drive circuit connected in the stage after or a signal output from the second drive circuit connected in the stage after or, and the second drive circuit initializes the information it holds in accordance with a signal output from the first drive circuit connected in the stage after or a signal output from the second drive circuit connected in the stage after or

[0011] In addition, in a display system according to a fifth aspect of the present invention, the plurality of first drive circuits are alternately connected in series, the first drive circuit holds information indicated by a signal output from the first drive circuit connected in the previous stage, and outputs a signal including the information held during the first period to the first drive circuit connected in the next stage, and the plurality of second drive circuits are alternately connected in series, the second drive circuit holds information indicated by a signal output from the second drive circuit connected in the previous stage, and outputs a signal including the information held during the third period to the second drive circuit connected in the next stage.

[0012] In addition, a display system according to a sixth aspect of the present invention further includes a position indicator having a resonant circuit, a drive coil for supplying power to the position indicator, and a position detector having an electromagnetic induction type detection coil for detecting the position indicated by the position indicator.

[0013] In addition, in a seventh display system according to the present invention, the driver circuit is arranged between the position detector and the drive coil and on the side of the display device, the first clock line and the second clock line are arranged between the position detector and the drive coil and on the side of the driver circuit opposite the display device, the position detector is arranged on the display surface side of the display device relative to the display device, the driver circuit, the first clock line and the second clock line, and the drive coil is arranged on the back side of the display device relative to the display device, the driver circuit, the first clock line and the second clock line.

[0014] In addition, in a display system according to an eighth aspect of the present invention, the display device has a touch sensor in which a plurality of detection electrodes are arranged in a plane.

[0015] In addition, in a ninth display system according to the present invention, the driver circuit is arranged on the side of the display device and on the back side of the touch sensor, the first clock line and the second clock line are arranged on the back side of the touch sensor and on the side of the driver circuit opposite the display device, and the touch sensor is arranged on the display surface side of the display device relative to the display device, the driver circuit, the first clock line and the second clock line.

[0016] A tenth aspect of the present invention provides a driver circuit for driving the first image elements and the second image elements in a display device having a plurality of column signal lines arranged in a horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arranged in a vertical direction, a plurality of first image elements arranged at intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at intersections of the second row signal lines and the column signal lines, the driver circuit comprising: a plurality of first drive circuits provided for each of the first row signal lines and driving the first image elements via the corresponding first row signal lines; and a plurality of second drive circuits provided for each of the second row signal lines and driving the second image elements via the corresponding second row signal lines, wherein the first drive circuits supply charges to the first image elements in a first period and extract charges from the first image elements in a second period different from the first period, and the second drive circuit supplies charges to the second image elements in a third period that at least partially overlaps with the second period, or extracts charges from the second image elements in a fourth period that at least partially overlaps with the first period.

[0017] A control method for a display system according to an eleventh aspect of the present invention is a control method for a display system including a plurality of column signal lines arranged in a horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arranged in a vertical direction, a plurality of first image elements arranged at intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at intersections of the second row signal lines and the column signal lines, the control method comprising: supplying charges to the first image elements via the first row signal lines in a first period; four extracting charges from the second image elements via the second row signal lines during a period different from the first period; extracting charges from the first image elements via the first row signal lines during a second period different from the first period; and extracting charges from the first image elements via the first row signal lines during a third period at least partially overlapping with the second period. three supplying charges to the second picture element via the second row signal line for a period of time. [Effects of the Invention]

[0018] According to the present invention, the display system can reduce noise. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 illustrates an example of a display system. [Figure 2] FIG. 2 is a diagram illustrating an example of an image element. [Figure 3A] FIG. 2 is a diagram showing an example of a circuit configuration of a clock line and a gate driver circuit. [Figure 3B] FIG. 2 is a diagram illustrating an example of a circuit configuration of a first shift register. [Figure 3C] FIG. 2 is a diagram illustrating an example of a circuit configuration of a block. [Figure 4] FIG. 2 is a diagram illustrating an example of a circuit configuration of a drive circuit. [Figure 5A] FIG. 10 is a diagram illustrating a second example of the arrangement of clock lines. [Figure 5B] FIG. 10 is a diagram illustrating a third example of the arrangement of clock lines. [Figure 5C] FIG. 10 is a diagram illustrating a fourth example of a clock line arrangement. [Figure 6] 10 is a timing chart showing a first example of transition of potentials of each clock in the display system. [Figure 7] 10 is a timing chart showing an example of transition of the potential of each signal in a drive circuit. [Figure 8] 10 is a timing chart showing a second example of transition of the potential of each clock in the display system. [Figure 9A] FIG. 10 is a cross-sectional view showing a fourth example of a display system. [Figure 9B] FIG. 10 is a cross-sectional view showing a fifth example of a display system. [Figure 10] 10 is a graph showing the relationship between clock alternation and electromotive force generated in a position detector. [Figure 11] 10 is a flowchart showing an example of a series of operational flow of the display system. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, an embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components and steps in each drawing will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0021] ---First embodiment--- First, the first embodiment will be described.

[0022] <Configuration> FIG. 1 is a diagram showing an example of a display system 1A according to a first embodiment. The display system 1A is a computer, a monitor, or a television set held by a user, such as a tablet. t Examples of the display system 1A include a display device 10, a smartphone, a monitor of a personal computer, a television receiver, etc. In this example, a liquid crystal display will be described. The display system 1A includes, for example, the display device 10, a gate driver circuit 20, a source driver circuit 30, a control circuit 40, and clock lines WCL1 to WCL8 (see FIG. 3). A (see reference).

[0023] The display device 10 is, for example, a liquid crystal display. The display device 10 includes, for example, a display module 11 and a backlight module 12.

[0024] The display module 11 includes row signal lines GL1 to GLn arranged in the vertical direction, column signal lines SL1 to SLm arranged in the horizontal direction, and image elements 110 arranged at each intersection of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm. The display module 11 drives a corresponding one of the row signal lines GL1 to GLn in accordance with gate signals VG1 to VGn transmitted from a gate driver circuit 20, and drives each image element 110 corresponding to the source signals VS1 to VSm transmitted from a source driver circuit 30 at a luminance indicated by the source signals VS1 to VSm.

[0025] The row signal lines GL1 to GLn are, for example, gate lines, and n lines are arranged in the vertical direction in the display device 10. The row signal lines GL1 to GLn are driven by corresponding gate signals VG1 to VGn transmitted from a gate driver circuit 20, and relay the exchange of charges between the gate electrodes of the image elements 110 at the intersections with the column signal lines SL1 to SLm and the gate driver circuit 20.

[0026] The column signal lines SL1 to SLm are, for example, source lines, and m of them are arranged in the horizontal direction in the display device 10. The column signal lines SL1 to SLm are driven by corresponding source signals VS1 to VSm transmitted from the source driver circuit 30, and relay the exchange of charges between the source driver circuit 30 and the source electrodes of the image elements 110 that are located at the intersections with the row signal lines GL1 to GLn.

[0027] The picture elements 110 are, for example, liquid crystal picture elements, and a total of n×m of them are arranged at the intersections of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm in the display device 10. In each picture element 110, one of the row signal lines GL1 to GLn is connected to a gate electrode, and one of the column signal lines SL1 to SLm is connected to a source electrode. When an electric charge is supplied to the gate electrode via the row signal lines GL1 to GLn connected to the gate electrode, the picture element 110 displays a corresponding image with a brightness according to the electric potential of the column signal lines SL1 to SLm connected to the source electrode.

[0028] The backlight module 12 is a light source disposed on the rear side of the display module 11, and irradiates the display module 11 with light from the rear side.

[0029] The gate driver circuit 20 drives the row signal lines GL1 to GLn, and is disposed on the left side of the display device 10 when the display system 1A is viewed from the display surface side. The gate driver circuit 20 drives the row signal lines GL1 to GLn in order by outputting gate signals VG1 to VGn to the corresponding row signal lines GL1 to GLn at timings according to clocks CLK1 to CLK8 output from the control circuit 40. The gate driver circuit 20 also supplies and extracts electric charges to and from the gate electrodes of the corresponding image elements 110 via the driven row signal lines GL1 to GLn.

[0030] The source driver circuit 30 is a circuit that drives the column signal lines SL1 to SLm, and is disposed below the display device 10 when the display system 1A is viewed from the display surface side. The source driver circuit 30 drives the column signal lines SL1 to SLm at timings determined by the control circuit 40. The source driver circuit 30 outputs source signals VS1 to VSm, each having a potential that is set for each of the column signal lines SL1 to SLm by the control circuit 40, to the corresponding column signal lines SL1 to SLm. m The source driver circuit 30 supplies the potential of the source signals VS1 to VSm corresponding to the image elements 110 to the source electrodes of the image elements 110 corresponding to the intersections of the row signal lines GL1 to GLn and the column signal lines SL1 to SLm driven by the gate driver circuit 20.

[0031] The control circuit 40 is a circuit for controlling the display device 10. The control circuit 40 controls the row signal lines GL1 to GL2 by the gate driver circuit 20. n When starting driving of the gate driver circuit 20, the control circuit 40 generates start signals ST1 to ST4 which indicate the start of driving, and outputs the start signals ST1 to ST4 to the gate driver circuit 20. Furthermore, the control circuit 40 generates clocks CLK1 to CLK8 for operating the gate driver circuit 20, and outputs the clocks CLK1 to CLK8 to the gate driver circuit 20 via clock lines WCL1 to WCL8.

[0032] Furthermore, the control circuit 40 generates a clock for operating the source driver circuit 30 and outputs the clock to the source driver circuit 30. The control circuit 40 also sets a potential to be supplied to the source electrode of the corresponding image element 110 via the column signal lines SL1 to SLm, and outputs a signal containing information about the set potential to the source driver circuit 30.

[0033] 2 is a diagram showing an example of an image element 110 according to the first embodiment. As shown in Fig. 2, the image element 110 includes, for example, a thin film transistor TFT, a liquid crystal electrode Clc, and a capacitance element Cpx.

[0034] The thin film transistor TFT functions as a switching element in the image element 110. The thin film transistor TFT has a gate electrode connected to a row signal line GL, a source electrode connected to a column signal line SL, and a drain electrode connected to the liquid crystal electrode Clc and one end of the capacitance element Cpx. When charge is supplied to the gate electrode via the row signal line GL, the thin film transistor TFT brings the state between the source electrode and the drain electrode into a conductive state. When charge is extracted from the gate electrode via the row signal line GL, the thin film transistor TFT brings the state between the source electrode and the drain electrode into a non-conductive state. Furthermore, the thin film transistor TFT maintains the state between the source electrode and the drain electrode when there is no change in the potential applied to the gate electrode.

[0035] The liquid crystal electrode Clc is an electrode for supplying a potential to the liquid crystal. One end of the liquid crystal electrode Clc is connected to the drain electrode of the thin film transistor TFT and one end of the capacitance element Cpx, and the other end is connected to the common electrode COM via the liquid crystal. The liquid crystal electrode Clc supplies the potential supplied from the capacitance element Cpx to the liquid crystal.

[0036] The capacitive element Cpx is, for example, a capacitor, and holds a potential to be supplied to the liquid crystal electrode Clc. One end of the capacitive element Cpx is connected to the drain electrode of the thin film transistor TFT and one end of the liquid crystal electrode Clc, and the other end is connected to the common electrode COM. When the thin film transistor TFT is in a conductive state, the capacitive element Cpx holds a potential supplied from the column signal line SL. When the thin film transistor TFT is in a non-conductive state, the capacitive element Cpx supplies the held potential to the liquid crystal electrode Clc.

[0037] When charge is supplied to the gate electrode of the thin-film transistor TFT via the row signal line GL, the image element 110 configured as described above turns on the thin-film transistor TFT, supplies the potential of the column signal line SL to the capacitance element Cpx, and holds the potential supplied via the column signal line SL in the capacitance element Cpx. Furthermore, when charge is extracted from the gate electrode of the thin-film transistor TFT via the row signal line GL, the image element 110 turns off the thin-film transistor TFT, supplies the potential held by the capacitance element Cpx to the liquid crystal electrode Clc, and controls the state of the liquid crystal to a state according to the supplied potential.

[0038] 3A is a diagram showing an example of the circuit configuration of clock lines WCL1 to WCL8 according to the first embodiment and the gate driver circuit 20. As shown in Fig. 3A, the gate driver circuit 20 is configured to include, for example, n drive circuits DRV.

[0039] In the gate driver circuit 20, n drive circuits DRV are provided for each of n row signal lines GL1 to GLn, and output gate signals VG to the corresponding ones of the row signal lines GL1 to GLn at timings according to the corresponding ones of the clocks CLK1 to CLK8 supplied from the control circuit 40 to the clock lines WCL1 to WCL8.

[0040] Furthermore, the drive circuit DRV is combined with other drive circuits DRV to form a shift register 201 (see FIG. 3B). In this embodiment, the gate driver circuit 20 is configured to include four shift registers 201, each of which is made up of a group of different drive circuits DRV. Furthermore, the drive circuit DRV is configured to include four shift registers 201, each of which is made up of a group of different drive circuits DRV. 201 The drive circuits DRV of the first shift register 201 to the drive circuits DRV of the fourth shift register 201 are arranged in the vertical direction in the gate driver circuit 20 in the order from the frontmost stage to the last stage of the shift register 201.

[0041] Furthermore, the drive circuit DRV has a clock terminal CK connected to a corresponding one of the clock lines WCL1 to WCL8, an input terminal I connected to the output terminal O of the drive circuit DRV of the previous stage, an output terminal O connected to a corresponding one of the row signal lines GL1 to GLn, the input terminal I of the drive circuit DRV of the next stage, and a reset terminal R of the second-to-last stage, and the reset terminal R connected to the output terminal O of the drive circuit DRV of the second-to-next stage. Note that the input terminal I of the drive circuit DRV of the first stage in each shift register 201 is connected to the control circuit 40 instead of the output terminal O of the drive circuit DRV of the previous stage, and a corresponding one of the start signals ST1 to ST4 output from the control circuit 40 is input. Furthermore, in each shift register 201, the reset terminal R of the drive circuit DRV for which there is no second-to-next stage is connected to the control circuit 40, and a reset signal RST output from the control circuit 40 is input.

[0042] Here, the shift register 201 will be described with reference to Fig. 3B. Fig. 3B is a diagram showing an example of the circuit configuration of the first shift register 201 according to the first embodiment. As shown in Fig. 3B, the shift register 201 includes, for example, driving circuits DRV1, DRV5, DRV9...DRVn -3 It is composed of:

[0043] 3B, the driving circuit DRV1 outputs a gate signal VG1 including information indicated by the start signal ST1 input to the input terminal I to the driving circuit DRV5 from the output terminal O at a timing according to the clock CLK1. -3 is the input terminal I Gate signals VG5, VG9...VGn containing information indicated by the signals input to -3 is output from the output terminal O to the subsequent driver circuit DRV.

[0044] Next, the block 202 will be described with reference to Fig. 3C. Fig. 3C is a diagram showing an example of the circuit configuration of the block 202 according to the first embodiment. As shown in Fig. 3C, the block 202 is configured to include, for example, drive circuits DRV1 to DRV4.

[0045] As shown in FIG. 3C, the driving circuits DRV1 to DRV4 output gate signals VG1 to VG4 from the output terminal O, which include information indicated by the start signal ST1 input to the input terminal I, at timings according to the clocks CLK1 to CLK4, respectively.

[0046] 3A, the clock lines WCL1 to WCL8 are signal lines for supplying clocks CLK1 to CLK8 output from the control circuit 40 to the gate driver circuit 20. When the display system 1A is viewed from the display surface side, the eight clock lines WCL1 to WCL8 are arranged horizontally to the left of the gate driver circuit 20 in the order of clock lines WCL1, WCL5, WCL2, WCL6, WCL3, WCL7, WCL4, and WCL8 from left to right.

[0047] The clock line WCL1 supplies a clock CLK1 input from the control circuit 40 to clock terminals CK of the odd-numbered stage driver circuits DRV1, DRV9 . . . DRVn-7 in the first of the four shift registers 201.

[0048] The clock line WCL5 supplies a clock CLK5 input from the control circuit 40 to clock terminals CK of the even-numbered driving circuits DRV5, DRV13, ..., DRVn-3 in the first shift register 201 of the four shift registers 201. The clock CLK5 is generated by the control circuit 40 so that its phase is opposite to that of the clock CLK1.

[0049] The clock line WCL2 supplies the clock CLK2 input from the control circuit 40 to the clock terminals CK of the odd-numbered driving circuits DRV2, DRV10 . . . DRVn-6 in the second shift register 201 of the four shift registers 201.

[0050] The clock line WCL6 supplies a clock CLK6 input from the control circuit 40 to the clock terminals CK of the even-numbered driving circuits DRV6, DRV14...DRVn-2 in the second shift register 201 out of the four shift registers 201. The clock CLK6 is generated by the control circuit 40 so that its phase is opposite to that of the clock CLK2.

[0051] The clock line WCL3 supplies the clock CLK3 input from the control circuit 40 to the clock terminals CK of the odd-numbered driving circuits DRV3, DRV11 . . . DRVn-5 in the third shift register 201 of the four shift registers 201.

[0052] The clock line WCL7 supplies a clock CLK7 input from the control circuit 40 to the clock terminals CK of the even-numbered driving circuits DRV7, DRV15, ... DRVn-1 in the third shift register 201 among the four shift registers 201. The clock CLK7 is generated by the control circuit 40 so that its phase is opposite to that of the clock CLK3.

[0053] The clock line WCL4 supplies the clock CLK4 input from the control circuit 40 to the clock terminals CK of the odd-numbered driving circuits DRV4, DRV12 . . . DRVn-4 in the fourth of the four shift registers 201.

[0054] The clock line WCL8 supplies a clock CLK8 input from the control circuit 40 to clock terminals CK of the even-numbered driving circuits DRV8, DRV16...DRVn in the fourth shift register 201 out of the four shift registers 201. The clock CLK8 is generated by the control circuit 40 so that its phase is opposite to that of the clock CLK4.

[0055] Fig. 4 is a diagram showing an example of the circuit configuration of the drive circuit DRV according to the first embodiment. As shown in Fig. 4, the drive circuit DRV includes transistors TR1 to TR8 and a capacitance element Cd.

[0056] The transistors TR1 to TR8 are, for example, NMOS transistors. On the other hand, when the potential difference between the gate terminal and the source terminal of the transistors TR1 to TR8 is equal to or greater than a predetermined value, the state between the drain terminal and the source terminal of the transistors TR1 to TR8 is conductive. On the other hand, when the potential difference between the gate terminal and the source terminal of the transistors TR1 to TR8 is less than the predetermined value, the state between the drain terminal and the source terminal of the transistors TR1 to TR8 is non-conductive. Note that, in this embodiment, the case where the transistors TR1 to TR8 are NMOS transistors has been described, but the present invention is not limited to this, and the transistors TR1 to TR8 may also be PMOS transistors.

[0057] The transistor TR1 has its drain terminal and gate terminal connected to the input terminal I of the drive circuit DRV in a diode connection, and while the potential of the gate terminal and drain terminal is higher than the potential of the source terminal, the transistor TR1 supplies the charge supplied from the input terminal I to the capacitive element Cd from the source terminal via the node BT. The transistor TR1 has its gate terminal and drain terminal connected to the input terminal I of the drive circuit DRV, and its source terminal connected to the node BT.

[0058] The transistor TR2 has its drain terminal and gate terminal connected to the power supply line W_VGH in a diode connection, and while the potentials of the gate terminal and drain terminal are higher than the potential of the source terminal, the potential supplied from the power supply line W_VGH is supplied from the source terminal to the gate terminals of the transistors TR4 and TR5. The transistor TR2 has its gate terminal and drain terminal connected to the power supply line W_VGH, and its source terminal connected to the drain terminal of the transistor TR3 and the gate terminals of the transistors TR4 and TR5.

[0059] The transistor TR3 supplies the potential of the reference line W_VGL connected to the source terminal from the drain terminal to the gate terminals of the transistors TR4 and TR5 in accordance with the potential of the node BT input to the gate terminal. 3 has a gate terminal connected to the node BT, a drain terminal connected to the source terminal of the transistor TR2 and the gate terminals of the transistors TR4 and TR5, and a source terminal connected to the reference line W_VGL.

[0060] The transistor TR4 supplies the potential of the reference line W_VGL connected to the source terminal from the drain terminal to the node BT in accordance with the potential input to the gate terminal. The transistor TR4 has a gate terminal connected to the source terminal of the transistor TR2, the drain terminal of the transistor TR3, and the gate terminal of the transistor TR5, a drain terminal connected to the node BT, and a source terminal connected to the reference line W_VGL.

[0061] The transistor TR5 supplies the potential of the reference line W_VGL connected to the source terminal from the drain terminal to the output terminal O of the drive circuit DRV in accordance with the potential input to the gate terminal. The transistor TR5 has a gate terminal connected to the source terminal of the transistor TR2, the drain terminal of the transistor TR3, and the gate terminal of the transistor TR4, a drain terminal connected to the output terminal O of the drive circuit DRV, and a source terminal connected to the reference line W_VGL.

[0062] The transistor TR6 supplies the potential of the reference line W_VGL connected to the source terminal from the drain terminal to the node BT in accordance with the potential input to the gate terminal. The transistor TR6 has a gate terminal connected to the reset terminal R of the drive circuit DRV, a drain terminal connected to the node BT, and a source terminal connected to the reference line W_VGL.

[0063] The transistor TR7 supplies the potential of the reference line W_VGL connected to the source terminal from the drain terminal to the output terminal O of the drive circuit DRV in accordance with the potential input to the gate terminal. The transistor TR7 has a gate terminal connected to the reset terminal R of the drive circuit DRV, a drain terminal connected to the output terminal O of the drive circuit DRV, and a source terminal connected to the reference line W_VGL.

[0064] The transistor TR8 controls the potential of the clock CLK supplied from the clock terminal CK of the driver circuit DRV connected to the drain terminal in accordance with the potential input to the gate terminal. sauce The transistor TR8 has a gate terminal connected to the node BT, a drain terminal connected to the clock terminal CK of the driver circuit DRV, and a source terminal connected to the output terminal O of the driver circuit DRV.

[0065] The capacitance element Cd is, for example, a capacitor, and holds the potential of the node BT by storing charge supplied from the source terminal of the transistor TR1 via the node BT. One end of the capacitance element Cd is connected to the node BT, and the other end is connected to the output terminal O of the drive circuit DRV.

[0066] In the driver circuit DRV configured as described above, when the potentials of the reset terminal R and the node BT are the potential VGL (low level) of the reference line W_VGL, the transistors TR3, TR6, TR7, and TR8 are each in a non-conductive state. Accordingly, the potential of the source terminal of the transistor TR2, which is diode-connected to the power supply line W_VGH, becomes the potential VGH (high level) of the power supply line W_VGH, and the transistors TR4 and TR5 are in a conductive state. With the transistors TR4 and TR5 in a conductive state, the node BT and the output terminal O are short-circuited to the reference line W_VGL via the transistors TR4 and TR5, respectively, and the potentials of the node BT and the output terminal O become low level. Therefore, the driver circuit DRV outputs a gate signal VG from the output terminal O with a low level potential.

[0067] Subsequently, when a high-level potential is supplied to the input terminal I while the potential of the node BT is low, the transistor TR1 supplies charge to one end of the capacitance element Cd via the node BT, charging the capacitance element Cd. When the capacitance element Cd is charged and the potential of the node BT reaches high, the states of the transistors TR1, TR3, and TR8 become "non-conductive state," "conductive state," and "conductive state," respectively. Accordingly, the states of the transistors TR4 and TR5 become non-conductive states. Therefore, the driver circuit DRV uses the clock CLK input from the clock terminal CK as the gate signal VG and outputs the gate signal VG from the output terminal O.

[0068] Subsequently, when a high-level potential is supplied to the reset terminal R while the potential of the node BT is high, the transistors TR6 and TR7 each become conductive. Accordingly, the node BT and the output terminal O are shorted to the reference line W_VGL via the transistors TR6 and TR7, respectively, and the potentials of the node BT and the output terminal O become low. Furthermore, the transistors TR3 and TR8 become non-conductive, and accordingly the transistors TR4 and TR5 become conductive. Therefore, the drive circuit DRV outputs the gate signal VG from the output terminal O with the potential at low level.

[0069] Furthermore, if a low-level potential is supplied to the reset terminal R while the potential of the node BT is low, the transistors TR6 and TR7 are both turned off. Since the transistors TR4 and TR5 remain in the non-conductive state, the driver DRV continues to output the gate signal VG at a low level from the output terminal O.

[0070] <Flow of a Series of Operations Related to Display System 1A> This concludes the description of the configuration of the display system 1. Next, a detailed description will be given of potential transitions of the clocks CLK1 to CLK8 in the display system 1A. Fig. 6 is a timing chart showing a first example of potential transitions of the clocks CLK1 to CLK8 in the display system 1A according to the first embodiment.

[0071] At time t61, the control circuit 40 causes the potential of the clock CLK1 to transition from low to high, and also causes the potential of the clock CLK5 to transition from high to low.

[0072] At time t62, the control circuit 40 causes the potential of the clock CLK2 to transition from low to high, and also causes the potential of the clock CLK6 to transition from high to low.

[0073] At time t63, the control circuit 40 causes the potential of the clock CLK3 to transition from low to high, and also causes the potential of the clock CLK7 to transition from high to low.

[0074] At time t64, the control circuit 40 causes the potential of the clock CLK4 to transition from low to high, and causes the potential of the clock CLK8 to transition from high to low.

[0075] At time t65, the control circuit 40 causes the potential of the clock CLK1 to transition from high to low, and also causes the potential of the clock CLK5 to transition from low to high.

[0076] At time t66, the control circuit 40 causes the potential of the clock CLK2 to transition from high to low, and also causes the potential of the clock CLK6 to transition from low to high.

[0077] At time t67, the control circuit 40 causes the potential of the clock CLK3 to transition from high to low, and also causes the potential of the clock CLK7 to transition from low to high.

[0078] At time t68, the control circuit 40 causes the potential of the clock CLK4 to transition from high to low, and also causes the potential of the clock CLK8 to transition from low to high.

[0079] After time t69, the control circuit 40 transitions the potentials of the clocks CLK1 to CLK8 in the same manner as from time t61 to time t68.

[0080] In this example, the control circuit 40 generates the clocks CLK1 to CLK8 so that the phases of the clocks CLK1 to CLK4 input to the odd-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 are opposite to the phases of the clocks CLK5 to CLK8 input to the even-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 and corresponding to the clocks CLK1 to CLK4, respectively, but this is not limited to this. The control circuit 40 may also set the phases of the clocks CLK5 to CLK8 to be shifted from the opposite phase to the phase of the clocks CLK1 to CLK4 within a period until the image elements 110 driven by the drive circuits DRV to which the clocks CLK1 to CLK4 are supplied via the row signal lines GL complete charging or discharging.

[0081] The above has described the transition of the potentials of the clocks CLK1 to CLK8 in the display system 1A. Next, the transition of the potentials of the signals in the drive circuit DRV of the display system 1A will be described in detail. FIG. 7 is a timing chart showing an example of the transition of the potentials of the signals in the drive circuit DRV according to the first embodiment. In FIG. 7, nodes BT(1), BT(5), and BT(9) are the nodes BT of the drive circuits DRV1, DRV5, and DRV9 in the first to third stages of the shift register 201, respectively.

[0082] At time t70, the control circuit 40 sets the potential of the start signal ST1 to high level and outputs the start signal ST1 to the input terminal I of the first-stage drive circuit DRV1. At time t70, as the high-level potential is supplied to the input terminal I, the capacitance element Cd in the first-stage drive circuit DRV1 is charged, and the potential of the node BT(1) transitions to high level.

[0083] At time t71, the control circuit 40 transitions the potential of the clock CLK1 from low to high and outputs the clock CLK1 to the clock terminals CK of the first- and third-stage drive circuits DRV1 and DRV9. At time t71, as the high-level potential is supplied to the clock terminal CK, the potential of one end of the capacitance element Cd in the first-stage drive circuit DRV1 is raised, and the potential of the node BT(1) begins to transition from high to a potential twice the high level. Also at time t71, the potential of the gate signal VG1 output from the first-stage drive circuit DRV1 to the row signal line GL1 and the input terminal I of the second-stage drive circuit DRV5 begins to transition from low to high.

[0084] Also, at time t71, the control circuit 40 transitions the potential of the clock CLK5 from high to low and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t71, as the gate signal VG1 is input from the first-stage drive circuit DRV1 to the input terminal I of the second-stage drive circuit DRV5, the potential of the node BT(5) starts to transition from low to high.

[0085] At time t72, the potential of gate signal VG1 reaches high level. Accordingly, at time t72, the potential of node BT(1) reaches a potential twice the high level. Furthermore, at time t72, the potential of node BT(5) reaches high level.

[0086] At time t73, the control circuit 40 transitions the potential of the clock CLK1 from high to low and outputs the clock CLK1 to the clock terminals CK of the first- and third-stage drive circuits DRV1 and DRV9. Also at time t73, the control circuit 40 transitions the potential of the start signal ST1 from high to low. At time t73, as the low-level potential is supplied to the clock terminal CK, the potential of one end of the capacitance element Cd in the first-stage drive circuit DRV1 is pulled down, and the potential of the node BT(1) begins to transition from a potential twice the high level to a high level. Also at time t73, the potential of the gate signal VG1 output from the first-stage drive circuit DRV1 to the row signal line GL1 and the input terminal I of the second-stage drive circuit DRV5 begins to transition from high to low.

[0087] Also, at time t73, the control circuit 40 transitions the potential of the clock CLK5 from low to high and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t73, as the high-level potential is supplied to the clock terminal CK, the potential of one end of the capacitance element Cd in the second-stage drive circuit DRV5 is raised, and the potential of the node BT(5) begins to transition from high to a potential twice the high level. Also, at time t73, the potential of the gate signal VG5 output from the second-stage drive circuit DRV5 to the row signal line GL5 and the input terminal I of the third-stage drive circuit DRV9 begins to transition from low to high.

[0088] Furthermore, at time t73, as the gate signal VG5 is input from the second-stage drive circuit DRV5 to the input terminal I of the third-stage drive circuit DRV9, the potential of the node BT(9) starts to transition from low level to high level.

[0089] At time t74, the potential of gate signal VG1 reaches low level. Accordingly, at time t74, the potential of node BT(1) reaches high level. Also, at time t74, the potential of gate signal VG5 reaches high level. Accordingly, at time t74, the potential of node BT(5) reaches a potential that is twice the high level. Furthermore, at time t74, the potential of node BT(9) reaches high level.

[0090] At time t75, the control circuit 40 transitions the potential of the clock CLK1 from low to high and outputs the clock CLK1 to the clock terminals CK of the first-stage and third-stage drive circuits DRV. At time t75, as the gate signal VG9 is input to the reset terminal R, the potential of the node BT(1) starts to transition from high to low.

[0091] At time t75, the control circuit 40 changes the potential of the clock CLK5 from high to low, and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. of potential As the voltage is supplied, the potential at one end of the capacitance element Cd in the second-stage driving circuit DRV5 is pulled down, and the potential at the node BT(5) starts to transition from a potential twice the high level to the high level.

[0092] Furthermore, at time t75, in response to the input of the gate signal VG5 to the input terminal I, the potential of one end of the capacitance element Cd in the third-stage driving circuit DRV9 is raised, and the potential of the node BT(9) starts to transition from a high level to a potential twice the high level. Also, at time t75, the third-stage driving circuit DRV9 is connected to the row signal line GL9 and the fourth-stage driving circuit DRV1. 3 The potential of the gate signal VG9 output to the input terminal I of the first stage driver circuit DRV1 and the reset terminal R of the first stage driver circuit DRV1 starts to transition from low level to high level.

[0093] At time t76, the potential of gate signal VG1 remains low. At time t76, the potential of gate signal VG5 reaches low. Accordingly, at time t76, the potential of node BT(5) reaches high. Also, at time t76, the potential of gate signal VG9 reaches high. Accordingly, at time t76, the potential of node BT(1) reaches low. Furthermore, at time t76, the potential of node BT(9) reaches a potential that is twice the high level.

[0094] At time t77, the control circuit 40 changes the potential of the clock CLK1 from high to low, and outputs the clock CLK1 to the clock terminals CK of the first-stage and third-stage drive circuits DRV1 and DRV9.

[0095] Also, at time t77, the control circuit 40 transitions the potential of the clock CLK5 from low to high and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. At time t77, as the gate signal VG13 is input to the reset terminal R, the potential of the node BT(5) starts to transition from high to low.

[0096] Furthermore, at time t77, a low-level of potential As the voltage is supplied, the potential at one end of the capacitance element Cd in the third-stage driving circuit DRV9 is lowered, and the potential at the node BT(9) starts to transition from a potential twice the high level to the high level. 7 Then, the potential of the gate signal VG9 starts to transition from high level to low level.

[0097] At time t78, the potentials of gate signals VG1 and VG5 remain low. Also at time t78, the potential of gate signal VG9 reaches low. Furthermore, at time t78, the potential of gate signal VG13 reaches low, and the potential of node BT(5) reaches low.

[0098] At time t79, the control circuit 40 transitions the potential of the clock CLK1 from low to high and outputs the clock CLK1 to the clock terminals CK of the first-stage and third-stage drive circuits DRV1 and DRV9. Also at time t79, the control circuit 40 transitions the potential of the clock CLK5 from high to low and outputs the clock CLK5 to the clock terminal CK of the second-stage drive circuit DRV5. Furthermore, at time t79, as the gate signal VG17 is input to the reset terminal R, the potential of the node BT(9) begins to transition from high to low.

[0099] At time t80, the potentials of the gate signals VG1, VG5, and VG9 remain at low level. Also at time t80, the potential of the gate signal VG17 reaches low level, and the potential of the node BT(9) reaches low level.

[0100] In this example, the control circuit 40 generates the clocks CLK1 and CLK5 so that the phase of the clock CLK1 input to the odd-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 is opposite to the phase of the clock CLK5 input to the even-numbered drive circuits DRV of the shift register 201 in the gate driver circuit 20 and corresponding to the clock CLK1, but this is not limited to this. The control circuit 40 may set the phase of the clock CLK5 to a phase that is shifted from the opposite phase to the phase of the clock CLK1 within a period until the image element 110 driven by the drive circuits DRV1 and DRV9 to which the clock CLK1 is supplied via the row signal lines GL1 and GL9 completes charging or discharging.

[0101] The transition of the potential of each signal in the drive circuit DRV of the display system 1A has been described above. Next, the flow of a series of processes in the display system 1A will be described in detail. Fig. 11 is a flowchart showing an example of the flow of a series of processes in the display system 1A according to the first embodiment.

[0102] (Step SP10) The control circuit 40 determines whether the current time is the timing to rise the clock (clock CLK1 in FIG. 7) supplied to the odd-numbered drive circuit DRV in any one of the shift registers 201 in the gate driver circuit 20, or the first timing (times t71, t75, and t79 in FIG. 7) to fall the clock (clock CLK5 in FIG. 7) supplied to the even-numbered drive circuit DRV in that shift register 201. On the other hand, if the determination is positive, the process proceeds to step SP12. On the other hand, if the determination is negative, the process proceeds to step SP14.

[0103] (Step SP12) The control circuit 40 has a first period (the period from time t75 to time t76 in FIG. 7) for supplying electric charges to the image elements 110 (first image elements) corresponding to the odd-numbered drive circuits DRV, and a second period for extracting electric charges from the image elements 110 (second image elements) corresponding to the even-numbered drive circuits DRV. four The drive circuit DRV drives the corresponding row signal line GL so that the period (the period from time t75 to t76 in FIG. 7) overlaps with the period (the period from time t75 to t76 in FIG. 7). As a result, the control circuit 40 charges the image element 110 (first image element) and discharges the image element 110 (second image element). Then, the process proceeds to step SP14.

[0104] (Step SP14) The control circuit 40 determines whether the current time is the timing to fall the clock (clock CLK1 in FIG. 7) supplied to the odd-numbered drive circuit DRV in any one of the shift registers 201 of the gate driver circuit 20, or the second timing (times t73 and t77 in FIG. 7) that is the timing to rise the clock (clock CLK5 in FIG. 7) supplied to the even-numbered drive circuit DRV in that shift register 201. On the other hand, if the determination is positive, the process proceeds to step SP16. On the other hand, if the determination is negative, the series of processes shown in FIG. 11 ends.

[0105] (Step SP16) The control circuit 40 extracts electric charges from the image elements 110 (first image elements) corresponding to the odd-numbered drive circuits DRV during a second period (the period from time t73 to time t74 in FIG. 7) and supplies electric charges to the image elements 110 (second image elements) corresponding to the even-numbered drive circuits DRV during a third period (the period from time t74 to time t75 in FIG. 7). three The driving circuit DRV drives the corresponding row signal line GL so that the period (the period from time t73 to t74 in FIG. 7) overlaps with the period (the period from time t74 to t75 in FIG. 7). As a result, the control circuit 40 discharges the image element 110 (first image element) and charges the image element 110 (second image element).

[0106] <Effects> As described above, in the first embodiment, the display system 1A includes a plurality of column signal lines SL1 to SLm arranged in the horizontal direction and a plurality of row signal lines GL (first row signal lines: GL1 to GL4, GL9 to GL1) arranged in the vertical direction. 2, ...GLn-7 to GLn-4) and a plurality of row signal lines GL (second row signal lines: GL5 to GL8, GL13 to GL16, ...GLn-3 to GLn), a plurality of image elements 110 (first image elements) arranged at intersections of the first row signal lines and column signal lines SL1 to SLm, and a plurality of image elements 110 (second image elements) arranged at intersections of the second row signal lines and column signal lines SL1 to SLm. The display system 1A also includes a gate driver circuit 20 (driver circuit) having a plurality of drive circuits DRV (first drive circuits) provided for each of the first row signal lines and driving the first image elements via the corresponding first row signal lines, and a drive circuit DRV (second drive circuit) provided for each of the second row signal lines and driving the second image elements via the corresponding second row signal lines. Furthermore, in display system 1A, the first drive circuit supplies charge to the first image element during a first period (times t75 to t76 in FIG. 7) and extracts charge from the first image element during a second period (times t73 to t74 in FIG. 7) different from the first period. Also, in display system 1A, the second drive circuit supplies charge to the second image element during a third period (times t73 to t74 in FIG. 7) that at least partially overlaps with the second period, and extracts charge from the second image element during a fourth period (times t75 to t76 in FIG. 7) that at least partially overlaps with the first period.

[0107] With this configuration, in the display system 1A, at least a portion of the magnetic field noise and electric field noise generated from the display system 1A during the first period when charge is supplied to the first image element is offset by the magnetic field noise and electric field noise generated from the display system 1A during the third period when charge is extracted from the second image element, and further, at least a portion of the magnetic field noise and electric field noise generated from the display system 1A during the second period when charge is extracted from the first image element is offset by the magnetic field noise and electric field noise generated from the display system 1A during the fourth period when charge is supplied to the second image element. Thus, the display system 1A can reduce the noise generated by the display system 1A.

[0108] In this embodiment, the display system 1A further includes first clock lines WCL1 to WCL4 that supply first clocks CLK1 to CLK4 to the first drive circuit and second clock lines WCL5 to WCL8 that supply second clocks CLK5 to CLK8 to the second drive circuit. In the display system 1A, the first drive circuit either supplies or extracts electric charge to the first image elements in accordance with the alternation of the first clocks CLK1 to CLK4. In the display system 1A, the second drive circuit either supplies or extracts electric charge to the second image elements in accordance with the alternation of the second clocks CLK5 to CLK8. In the display system 1A, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are arranged parallel to and adjacent to each other.

[0109] According to this configuration, the display system 1A includes the first clock lines WCL1 to WCL At least a part of the magnetic field noise and electric field noise generated from the first clock lines WCL1 to WCL4 is guided to the second clock lines WCL5 to WCL4 that are arranged parallel to and adjacent to the first clock lines WCL1 to WCL4. WCL The magnetic noise and electric field noise generated from the second clock lines WCL5 to 8 are cancelled out. WCL At least a part of the magnetic field noise and electric field noise generated from the first clock lines WCL1 to 8 is also transmitted to the first clock lines WCL2 to 8. WCL The noise generated by the display system 1A is cancelled out by the magnetic field noise and electric field noise generated by the display system 1A.

[0110] In this embodiment, the first drive circuits and the second drive circuits are alternately connected in series, and the first drive circuits hold information indicated by gate signals (VG5 to VG8, VG13 to VG16, ... VGn-11 to VGn-8) output from the second drive circuit connected in the preceding stage, and output gate signals (VG9 to VG12, VG17 to VG20, ... VGn-11 to VGn-8) including the information held during the first period. V Gn-7~ VGn-4) to the second driving circuit connected in the next stage. Also, the second driving circuit outputs the gate signals (VG1 to VG4, VG9 to VG12, ...VGn- 15 ~VGn- 12 ) and outputs gate signals (VG5 to VG8, VG13 to VG16, ... VGn-11 to VGn-8) including the information held during the third period to the first drive circuit connected to the next stage. Furthermore, the first drive circuit initializes the information it holds in accordance with gate signals (VG9 to VG12, ... VGn-7 to VGn-4) output from the first drive circuit connected to the stage after next, or gate signals (VG13 to VG16, ... VGn-3 to VGn) output from the second drive circuit connected to the stage after next. Furthermore, the second drive circuit initializes the information it holds in accordance with gate signals (VG13 to VG16, ... VGn-3 to VGn) output from the second drive circuit connected to the stage after next, or gate signals (VG17 to VG20, ... VGn-7 to VGn-4) output from the first drive circuit connected to the stage after next.

[0111] With this configuration, the display system 1A performs initialization in accordance with the gate signal VG output from the first drive circuit or the second drive circuit connected in the second or subsequent stage, respectively, which allows the display system 1A to secure a sufficient margin period between when the first drive circuit and the second drive circuit drive the first row signal line and the second row signal line and when initialization is performed.

[0112] --- Second embodiment --- Next, a second embodiment will be described.

[0113] <Configuration> FIG. 5A shows the clock lines WCL1 and W 5B is a diagram showing a second example of the arrangement of clock lines WCL1 and CL5. W 5C is a diagram showing a third example of the arrangement of clock lines WCL1 and CL5. W5A, 5B, and 5C, the clock lines WCL2 to WCL8 are also arranged in the same manner as the clock lines WCL1 and WCL5. W The display system 1B is assumed to be arranged in the same manner as the display system 1A in the first embodiment except for the arrangement of the clock lines WCL1 to WCL8, and therefore a description of the similar parts will be omitted.

[0114] As shown in FIGS. 5A, 5B, and 5C, in the display system 1B, the clock lines WCL1 and WCL5 are arranged adjacent to each other and parallel to each other, and cross each other at regular intervals.

[0115] In FIG. 5A, in display system 1B, clock line WCL5 is arranged on a layer above the layer on which clock line WCL1 is arranged. Clock lines WCL1 and WCL5 are arranged in display system 1B in a rectangular wave pattern that moves back and forth between the right lane and the left lane at regular intervals. Clock lines WCL1 and WCL5 are arranged so that the vertical positions of their horizontal lines overlap when moving to the opposite lane. While this example describes a case where clock line WCL5 is arranged on a layer above the layer on which clock line WCL1 is arranged, this is not limiting, and clock line WCL1 may also be arranged on a layer above the layer on which clock line WCL5 is arranged.

[0116] In FIG. 5B, in display system 1B, clock line WCL5 is arranged on a layer above the layer on which clock line WCL1 is arranged. Clock lines WCL1 and WCL5 are arranged in display system 1B in a trapezoidal wave pattern that moves back and forth between the right lane and the left lane at regular intervals. Clock lines WCL1 and WCL5 are arranged so that the vertical positions at which they transition to the opposing lane are the same. While this example describes a case in which clock line WCL5 is arranged on a layer above the layer on which clock line WCL1 is arranged, this is not limiting, and clock line WCL1 may also be arranged on a layer above the layer on which clock line WCL5 is arranged.

[0117] In FIG. 5C, in the display system 1B, the clock lines WCL1 and WCL5 are formed by lower layer lines arranged on the lower layer, upper layer lines arranged on the upper layer, and vias Via that electrically connect the lower layer lines and the upper layer lines.

[0118] The lower layer line extends downward from its upper end along the right lane, then extends downward to the left until it reaches the left lane, and then extends downward along the left lane to its lower end. The lower and upper ends of the lower layer line are connected to the upper and lower ends of the upper layer line via vias, respectively.

[0119] The upper layer line extends downward from its top end along the left lane, then extends downward to the right to the right lane, and then extends downward along the right lane to its bottom end. The top and bottom ends of the upper layer line are connected to the top and bottom ends of the lower layer line via vias, respectively.

[0120] Furthermore, in the display system 1B, the clock lines WCL1 and WCL5 are arranged so that the lower layer line of the clock line WCL1 intersects with the upper layer line of the clock line WCL5, and the upper layer line of the clock line WCL1 intersects with the lower layer line of the clock line WCL5.

[0121] <Effects> As described above, in the second embodiment, the display system 1B further includes first clock lines WCL1 to WCL4 that supply first clocks CLK1 to CLK4 to the first drive circuit and second clock lines WCL5 to WCL8 that supply second clocks CLK5 to CLK8 to the second drive circuit. In addition, in the display system 1B, the first drive circuit either supplies or extracts electric charge to the first image elements in accordance with the alternation of the first clocks CLK1 to CLK4. Furthermore, in the display system 1B, the second drive circuit either supplies or extracts electric charge to the second image elements in accordance with the alternation of the second clocks CLK5 to CLK8. Furthermore, in the display system 1B, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are arranged so as to intersect with each other at regular intervals.

[0122] According to the configuration shown in FIG. 5A, the display system 1B has the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 crossing each other at regular intervals, thereby further reducing the noise emitted from the display system 1B compared to when the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 do not cross each other.

[0123] Furthermore, according to the configuration shown in FIG. 5B, the display system 1B has a smaller overlapping area between the upper and lower layers of the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8, which further reduces the noise emitted from the display system 1B compared to the configuration shown in FIG. 5A.

[0124] Furthermore, according to the configuration shown in FIG. 5C, the display system 1B uses the upper layer only in a portion of the area where the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 intersect with each other, and therefore, compared to the configurations shown in FIGS. 5A and 5B, the variation in electrical characteristics (wiring resistance) due to the difference between the upper and lower layers can be reduced.

[0125] ---Third embodiment--- Next, a third embodiment will be described.

[0126] <Flow of a Series of Operations Related to Display System 1C> 8 is a timing chart showing an example of transitions in the potentials of the clocks CLK1 to CLK8 in a display system 1C according to the third embodiment. In the display system 1C, a gate signal VG output from a drive circuit DRV connected in the next or subsequent stage in the shift register 201 is input to a reset terminal R of the drive circuit DRV in the gate driver circuit 20 (not shown). Compared to the first embodiment, the display system 1C is similar to the display system 1A in the first embodiment except that the phase difference between the clocks CLK1 to CLK8 is different and that the drive circuit DRV that outputs the gate signal VG input to the reset terminal R of the drive circuit DRV is different. Therefore, a description of the similar parts will be omitted.

[0127] At time t81, the control circuit 40 transitions the potential of the clock CLK1 from low to high, transitions the potential of the clock CLK4 from high to low, and transitions the potential of the clock CLK7 from low to high.

[0128] At time t82, the control circuit 40 transitions the potential of the clock CLK2 from low to high, transitions the potential of the clock CLK5 from high to low, and transitions the potential of the clock CLK8 from low to high.

[0129] At time t83, the control circuit 40 causes the potential of the clock CLK3 to transition from low to high, and causes the potential of the clock CLK6 to transition from high to low.

[0130] At time t84, the control circuit 40 transitions the potential of the clock CLK1 from high to low, transitions the potential of the clock CLK4 from low to high, and transitions the potential of the clock CLK7 from high to low.

[0131] At time t85, the control circuit 40 transitions the potential of the clock CLK2 from high to low, transitions the potential of the clock CLK5 from low to high, and transitions the potential of the clock CLK8 from high to low.

[0132] At time t86, the control circuit 40 changes the potential of the clock CLK3 from high to low, and also changes the potential of the clock CLK 6 The potential of the signal line 111 is changed from a low level to a high level.

[0133] From time t87 onwards, the control circuit 40 transitions the potentials of the clocks CLK1 to CLK8 in the same manner as from time t81 to time t86.

[0134] <Effects> As described above, in the third embodiment, in the display system 1C, a plurality of drive circuits DRV (first drive circuits) are alternately connected in series, hold information indicated by gate signals (VG1, VG5, ... VGn-7) output from the first drive circuit connected in the preceding stage, and output gate signals (VG5, VG9, ... VGn-3) including information held in a first period to the first drive circuit connected in the succeeding stage. Also, in the display system 1C, a plurality of drive circuits DRV (second drive circuits) are alternately connected in series, and the second drive circuits hold information indicated by gate signals (VG4, VG8, ... VGn-4) output from the second drive circuit connected in the preceding stage, and output gate signals (VG8, VG12, ... VGn) including information held in a third period to the second drive circuit connected in the succeeding stage.

[0135] According to this configuration, in display system 1C, the first drive circuits are connected in series, the second drive circuits are connected in series, and the period in which the first drive circuit supplies and extracts charge to the first image elements overlaps with the period in which the second drive circuit supplies and extracts charge to the second image elements. Since display system 1C has different connection systems for the first drive circuits and the second drive circuits, it can have a larger time margin for the timing of initializing the information held by the first drive circuits and the information held by the second drive circuits.

[0136] ---Fourth embodiment--- Next, a fourth embodiment will be described.

[0137] <Configuration> 9A is a cross-sectional view showing a display system 1D according to a fourth embodiment. As shown in FIG. 9A, the display system 1D further includes a drive coil 13, a position detector 14, and a position indicator 50.

[0138] The drive coil 13 transmits a signal having a predetermined frequency to the position indicator 50 for detecting the position of the position indicator 50. The drive coil 13 is provided in a planar shape on the rear side of the display device 10 so as to include at least the range of the display surface of the display module 11 when the display system 1D is viewed from the display surface side.

[0139] The position indicator 50 is a pointing device that indicates a predetermined position on the display module 11. The position indicator 50 includes a resonant circuit 51 that is made up of an inductive element such as a coil and a capacitive element such as a capacitor. The resonant circuit 51 resonates in response to a signal transmitted from the drive coil 13, and the position indicator 50 transmits a resonant signal generated by the resonance to the position detector 14, thereby transmitting the predetermined position on the display module 11 indicated by the position indicator 50 to the position detector 14.

[0140] The position detector 14 is, for example, an electromagnetic induction (EMR: Electro Magnetic Resonance) sensor, and receives a resonance signal transmitted from the position indicator 50 to detect a predetermined position on the display module 11 indicated by the position indicator 50. The position detector 14 includes a plurality of electromagnetic induction type detection coils provided in a planar shape on the display surface side of the display device 10 so as to include at least the range of the display surface of the display module 11 when the display system 1D is viewed from the display surface side. The position detector 14 detects the position of the detection coil that receives the largest signal level as the predetermined position on the display module 11 indicated by the position indicator 50.

[0141] FIG. 10 is a graph showing the relationship between the alternation of the clocks CLK1 and CLK5 and the electromotive force generated in the position detector 14 in the display system 1D.

[0142] At time t101, the control circuit 40 changes the potential of the clock CLK1 from low to high. Accordingly, the current ICLK1 flowing through the clock line WCL1 rises sharply, then gradually falls, and returns to zero. Furthermore, the electromotive force dI / dt(CLK1) generated in the detection coil of the position detector 14 in response to the change in the value of the current flowing through the clock line WCL1 falls, rises, and falls again before returning to zero.

[0143] At time t102, the control circuit 40 changes the potential of the clock CLK5 from high to low. Accordingly, the current ICLK5 flowing through the clock line WCL5 drops sharply, then rises gradually, and returns to zero. Furthermore, as shown in graph g1, the electromotive force dI / dt(CLK5) generated in the detection coil of the position detector 14 increases, decreases, and then increases again before returning to zero as the value of the current flowing through the clock line WCL5 changes.

[0144] Graph g2 is a graph showing the electromotive force generated in the detection coil of the position detector 14 when the rising timing (time t101) of clock CLK1 and the falling timing (time t102) of clock CLK5 are closer than those in graph g1. Furthermore, graph g3 is a graph showing the electromotive force generated in the detection coil of the position detector 14 when the rising timing (time t101) of clock CLK1 and the falling timing (time t102) of clock CLK5 are closer than those in graph g2.

[0145] Also, on the right side of FIG. 10, the electromotive force obtained by adding up the electromotive force generated in the detection coil due to the rising edge of the clock CLK1 and the electromotive force generated in the detection coil due to the falling edge of the clock CLK1 is shown.

[0146] As shown in FIG. 10, as the rising edge of clock CLK1 (time t101) and the falling edge of clock CLK5 (time t102) approach each other, the electromotive force generated in the detection coil by the alternation of clocks CLK1 and CLK5 decreases.

[0147] <Effects> As described above, in the fourth embodiment, the display system 1D further includes a position indicator 50 having a resonant circuit 51, a drive coil 13 for supplying power to the position indicator 50, and a position detector 14 having an electromagnetic induction type detection coil for detecting the position indicated by the position indicator 50.

[0148] According to this configuration, the display system 1D is configured such that at least a part of the magnetic field noise generated from the display system 1D during a first period in which electric charges are supplied to the first image element draws electric charges from the second image element. four and a second period during which the magnetic field noise is offset by the magnetic field noise emitted from the display system 1D, and a second period during which the magnetic field noise is at least partially offset by the magnetic field noise emitted from the display system 1D, which draws charge from the first image element. threeTherefore, the display system 1D can improve the accuracy of the position detection of the position indicator 50 by the position detector 14 by reducing the magnetic field noise.

[0149] In the fourth embodiment, the gate driver circuit 20 is disposed between the position detector 14 and the drive coil 13 and on a side surface of the display device 10. In the display system 1D, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are disposed between the position detector 14 and the drive coil 13 and on a side surface of the gate driver circuit 20 facing away from the display device 10. In the display system 1D, the position detector 14 is disposed on the display surface side of the display device 10 with respect to the display device 10, the gate driver circuit 20, the first clock lines WCL1 to WCL4, and the second clock lines WCL5 to WCL8. In the display system 1D, the drive coil 13 is disposed on the rear surface side of the display device 10 with respect to the display device 10, the gate driver circuit 20, the first clock lines WCL1 to WCL4, and the second clock lines WCL5 to WCL8.

[0150] According to this configuration, the display system 1D can suppress magnetic field noise caused by the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8, which occurs near the side surfaces of the gate driver circuit 20. reduction This makes it possible to improve the accuracy of the position detector 14 in detecting the position of the position indicator 50 near the side surface of the gate driver circuit 20.

[0151] --- Fifth embodiment --- Next, a fifth embodiment will be described.

[0152] <Configuration> 9B is a cross-sectional view showing the arrangement of the display system 1E when the display system 1E includes the touch sensor 15. As shown in FIG. 9B, the display system 1E further includes the touch sensor 15 and a stylus 60.

[0153] The touch sensor 15 detects the position of the stylus 60 or finger 61 when the stylus 60 or finger 61 touches or approaches the touch sensor 15. The touch sensor 15 includes a plurality of detection electrodes provided in a planar shape on the display surface side of the display device 10 so as to include at least the range of the display surface of the display module 11 when the display system 1E is viewed from the display surface side. The touch sensor 15 detects the position of the detection electrode that receives the largest signal level as the predetermined position on the display module 11 that is being pointed to by the stylus 60 or finger 61.

[0154] The stylus 60 is a pointing device for indicating a predetermined position on the touch sensor 15. The stylus 60 operates when it receives a signal transmitted from a detection electrode of the touch sensor 15, and transmits a signal for indicating a position from the tip of the stylus 60 to the detection electrode, thereby transmitting position information to the touch sensor 15.

[0155] <Effects> As described above, in the fifth embodiment, the display device 10 has a touch sensor 15 formed by arranging a plurality of detection electrodes in a planar manner. Furthermore, in the display system 1E, the gate driver circuit 20 is arranged on a side surface of the display device 10 and on the rear surface side of the touch sensor 15. Furthermore, in the display system 1E, the first clock lines WCL1 to WCL4 and the second clock lines WCL5 to WCL8 are arranged on the rear surface side of the touch sensor 15 and on the side surface side of the gate driver circuit 20 opposite the display device 10. Furthermore, in the display system 1E, the touch sensor 15 is arranged on the display surface side of the display device 10 with respect to the display device 10, the gate driver circuit 20, the first clock lines WCL1 to WCL4, and the second clock lines WCL5 to WCL8.

[0156] According to this configuration, the display system 1E is configured such that at least a part of the electric field noise generated from the display system 1E during the first period in which electric charges are supplied to the first image element draws electric charges from the second image element. fourFurthermore, at least a part of the electric field noise generated from the display system 1E during the second period of time that draws out the electric charge from the first image element is offset by the electric field noise generated from the display system 1E during the second period of time that draws out the electric charge from the first image element. three This is offset by the electric field noise emitted from the display system 1E during this period. Therefore, the display system 1E can improve the accuracy of the touch sensor 15 in detecting the position of the stylus 60 or finger 61 by reducing the electric field noise.

[0157] --- Variation --- The present invention is not limited to the above-described embodiments. In other words, variations of the above-described embodiments, which are appropriately modified by a person skilled in the art, are also included within the scope of the present invention as long as they include the features of the present invention. Furthermore, the elements of the above-described embodiments and the modifications described below can be combined to the extent technically possible, and such combinations are also included within the scope of the present invention as long as they include the features of the present invention.

[0158] For example, in the above embodiment, the gate driver circuit 20 is provided on one side of the display device 10, but this is not limiting. For example, the gate driver circuit 20 may be provided on both side of the display device 10.

[0159] With this configuration, the display system 1 can reduce noise when the gate driver circuits 20 are located on both side surfaces of the display device 10.

[0160] Furthermore, in the above embodiment, eight clock lines WCL are provided, but the number of clock lines WCL is not limited to eight and any number may be provided.

[0161] With this configuration, the display system 1 can reduce noise regardless of the number of clock lines WCL. [Explanation of symbols]

[0162] 1A...display system, 10...display device, 20...driver circuit, DRV...drive circuit, 110...image element, GL...row signal line, SL...column signal line

Claims

1. a display device having a plurality of column signal lines arranged in a horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arranged in a vertical direction, a plurality of first image elements arranged at intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at intersections of the second row signal lines and the column signal lines; a driver circuit including: a plurality of first drive circuits provided for the first row signal lines, each connected in series to the other, and driving the first image elements via the corresponding first row signal lines; and a plurality of second drive circuits provided for the second row signal lines, each connected in series to the other, and driving the second image elements via the corresponding second row signal lines; Equipped with the first driving circuit supplies charge to the first picture element during a first period and removes charge from the first picture element during a second period different from the first period; the first drive circuit holds information indicated by a signal output from the first drive circuit connected to a previous stage, and outputs a signal including the information held during the first period to the first drive circuit connected to a next stage; the second drive circuit supplies charge to the second picture element during a third period that at least partially overlaps with the second period, or withdraws charge from the second picture element during a fourth period that at least partially overlaps with the first period; the second driving circuit holds information indicated by a signal output from the second driving circuit connected to a preceding stage, and outputs a signal including the information held during the third period to the second driving circuit connected to a succeeding stage. Display system.

2. a first clock line that supplies a first clock to the first driving circuit; a second clock line that supplies a second clock to the second driving circuit; Furthermore, the first driving circuit supplies or extracts electric charges from the first image element in accordance with alternations of the first clock; the second driving circuit supplies or extracts electric charges from the second image element in accordance with alternations of the second clock; the first clock line and the second clock line are arranged parallel to and adjacent to each other; The display system of claim 1 .

3. a first clock line that supplies a first clock to the first driving circuit; a second clock line that supplies a second clock to the second driving circuit; Furthermore, the first driving circuit supplies or extracts electric charges from the first image element in accordance with alternations of the first clock; the second driving circuit supplies or extracts electric charges from the second image element in accordance with alternations of the second clock; the first clock line and the second clock line are arranged so as to intersect with each other at regular intervals. The display system of claim 1 .

4. a position indicator having a resonant circuit; a drive coil for supplying power to the position indicator; a position detector having an electromagnetic induction type detection coil for detecting a position indicated by the position indicator; The display system according to claim 2 or 3, further comprising:

5. the driver circuit is disposed between the position detector and the drive coil and on a side surface of the display device; the first clock line and the second clock line are arranged between the position detector and the drive coil and on a side of the driver circuit opposite to the display device, the position detector is disposed on a display surface side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line; the drive coil is disposed on the rear side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line; The display system of claim 4 .

6. The display device has a touch sensor in which a plurality of detection electrodes are arranged in a planar shape.

4. A display system according to claim 2 or 3.

7. the driver circuit is disposed on a side surface of the display device and on a rear surface of the touch sensor; the first clock line and the second clock line are arranged on a rear surface side of the touch sensor and on a side surface of the driver circuit opposite to the display device; the touch sensor is disposed on a display surface side of the display device with respect to the display device, the driver circuit, the first clock line, and the second clock line; The display system of claim 6.

8. A driver circuit for driving the first image elements and the second image elements in a display device having a plurality of column signal lines arranged in a horizontal direction, a plurality of first row signal lines and a plurality of second row signal lines arranged in a vertical direction, a plurality of first image elements arranged at intersections of the first row signal lines and the column signal lines, and a plurality of second image elements arranged at intersections of the second row signal lines and the column signal lines, a plurality of first driving circuits provided for the first row signal lines, connected alternately in series, and configured to drive the first image elements via the corresponding first row signal lines; a plurality of second driving circuits provided for the second row signal lines, connected alternately in series, and configured to drive the second image elements via the corresponding second row signal lines; Equipped with the first driving circuit supplies charge to the first picture element during a first period and removes charge from the first picture element during a second period different from the first period; the first drive circuit holds information indicated by a signal output from the first drive circuit connected to a previous stage, and outputs a signal including the information held during the first period to the first drive circuit connected to a next stage; the second drive circuit supplies charge to the second picture element during a third period that at least partially overlaps with the second period, or withdraws charge from the second picture element during a fourth period that at least partially overlaps with the first period; the second driving circuit holds information indicated by a signal output from the second driving circuit connected to a preceding stage, and outputs a signal including the information held during the third period to the second driving circuit connected to a succeeding stage. Driver circuit.

Images