Array substrate and display panel

Abstract

Embodiments of the present application disclose an array substrate and a display panel. The array substrate includes a base substrate, an active layer, a first electrode layer, a first insulating layer, and a second electrode layer that are sequentially arranged. The sum of the orthographic projections of the first electrode layer and the second electrode layer on the base substrate covers the orthographic projection of the active layer on the base substrate. In the present application, the first electrode layer and the second electrode layer jointly protect the active layer, thereby avoiding the influence of external light on the active layer and ensuring the stability of the array substrate.

Description

[Technical Field]

[0001] The present application relates to the display field, and in particular to an array substrate and a display panel. [Background technology]

[0002] With the development of display technology, research into the stability of active layers in array substrates has become increasingly important. Metal oxide thin film transistors (MO-TFTs), particularly indium gallium zinc oxide (IGZO) TFTs, have been widely used in the flat panel display industry due to their excellent uniformity, high mobility, low drain current, and suitability for large-scale industrial manufacturing. However, during the current array substrate manufacturing process, IGZO is susceptible to external light exposure, which can cause the active layer to become unstable. This can lead to unstable performance of the array substrate in the presence of external light. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present application provide an array substrate and a display panel that can solve the problem of the low stability of conventional array substrates in an environment where external light is present. [Means for solving the problem]

[0004] An embodiment of the present application provides an array substrate, the substrate comprising: A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer that is away from the base substrate, the first electrode layer and the active layer being connected to each other while partially overlapping each other; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein the orthogonal projection of the second electrode layer on the base substrate at least partially covers the orthogonal projection of the active layer on the base substrate, and the sum of the orthogonal projections of the first electrode layer and the second electrode layer on the base substrate covers the orthogonal projection of the active layer on the base substrate.

[0005] Preferably, in some embodiments of the present application, the orthogonal projection of the second electrode layer on the base substrate covers the orthogonal projection of the active layer on the base substrate.

[0006] Preferably, in some embodiments of the present application, the sum of the light-shielding area of ​​the second electrode layer with respect to the active layer and the light-shielding area of ​​the first electrode layer with respect to the active layer is equal to the area of ​​the orthogonal projection of the active layer on the base substrate.

[0007] Preferably, in some embodiments of the present application, the first electrode layer includes a first electrode, which overlaps and is connected to one end of the active layer; a first opening is formed in the first insulating layer, which exposes the other end of the active layer; and the second electrode layer includes a second electrode, which overlaps and is connected to the other end of the active layer via the first opening.

[0008] Preferably, in some embodiments of the present application, the first electrode is a drain and the second electrode is a source.

[0009] Preferably, in some embodiments of the present application, the first electrode is a source and the second electrode is a drain.

[0010] Preferably, in some embodiments of the present application, the first electrode layer includes a source and a drain overlapping and connected to the active layer, and the second electrode layer includes a light-shielding electrode, the orthogonal projection of the light-shielding electrode on the base substrate covers the orthogonal projection of the active layer on the base substrate.

[0011] Preferably, in some embodiments of the present application, the array substrate comprises: a gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, and an orthogonal projection of the gate on the base substrate covering an orthogonal projection of the active layer on the base substrate; The semiconductor device further includes a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covering the gate layer.

[0012] Preferably, in some embodiments of the present application, the array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a second opening formed therein, the second opening penetrating the third insulating layer and the first insulating layer along a thickness direction of the array substrate, and the second opening exposing the first electrode; The third insulating layer further includes a pixel electrode layer disposed on a side thereof facing away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening.

[0013] Preferably, in some embodiments of the present application, the array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a third opening that exposes the second electrode; The third insulating layer further includes a pixel electrode layer disposed on a side thereof facing away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening.

[0014] Preferably, in some embodiments of the present application, the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening is opened on the third insulating layer at a position corresponding to the common electrode, and the connection electrode is electrically connected to the common electrode through the fourth opening.

[0015] Preferably, in some embodiments of the present application, the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening is opened on the third insulating layer at a position corresponding to the common electrode, and the connection electrode is electrically connected to the common electrode through the fourth opening.

[0016] Preferably, in some embodiments of the present application, the material of the second electrode layer is a non-transparent conductive material.

[0017] Accordingly, an embodiment of the present application further provides a display panel, which includes the array substrate according to any one of the above claims.

[0018] Accordingly, an embodiment of the present application further provides an array substrate, the substrate comprising: A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer that is away from the base substrate, the first electrode layer and the active layer being connected to each other while partially overlapping each other; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein an orthogonal projection of the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate; Here, the first electrode layer includes a first electrode, which is connected to and overlaps one end of the active layer, a first opening is formed in the first insulating layer, and the first opening exposes the other end of the active layer, and the second electrode layer includes a second electrode, which is connected to and overlaps the other end of the active layer through the first opening.

[0019] Preferably, in some embodiments of the present application, the first electrode is a drain and the second electrode is a source.

[0020] Preferably, in some embodiments of the present application, the first electrode is a source and the second electrode is a drain.

[0021] Preferably, in some embodiments of the present application, the array substrate comprises: a gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, and an orthogonal projection of the gate on the base substrate covering an orthogonal projection of the active layer on the base substrate; The semiconductor device further includes a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covering the gate layer.

[0022] Preferably, in some embodiments of the present application, the array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a second opening formed therein, the second opening penetrating the third insulating layer and the first insulating layer along a thickness direction of the array substrate, and the second opening exposing the first electrode; The third insulating layer further includes a pixel electrode layer disposed on a side thereof facing away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening.

[0023] Preferably, in some embodiments of the present application, the array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a third opening that exposes the second electrode; The third insulating layer further includes a pixel electrode layer disposed on a side thereof facing away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening. [Effects of the Invention]

[0024] In an embodiment of the present application, the array substrate includes a base substrate, an active layer, a first electrode layer, a first insulating layer, and a second electrode layer, wherein the active layer is disposed on the base substrate, the first electrode layer is disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer are connected to each other in a partially overlapping manner, the first insulating layer is disposed on a side of the first electrode layer away from the active layer, the second electrode layer is disposed on a side of the first insulating layer away from the first electrode layer, the orthogonal projection of the second electrode layer on the base substrate at least partially covers the orthogonal projection of the active layer on the base substrate, and the sum of the orthogonal projections of the first electrode layer and the second electrode layer on the base substrate covers the orthogonal projection of the active layer on the base substrate. In the present application, the first electrode layer and the second electrode layer are arranged so that the sum of their orthogonal projections on the base substrate covers the orthogonal projection of the active layer on the base substrate, so that the first electrode layer and the second electrode layer can jointly provide protection for the active layer, preventing the active layer from being affected by external light, thereby ensuring the stability of the array substrate. [Brief explanation of the drawings]

[0025] In order to more clearly explain the technical solutions in the embodiments of the present application, the drawings necessary for describing the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without exerting any creative efforts.

[0026] [Figure 1] 1 is a structural schematic diagram of an array substrate according to an embodiment of the present application; [Figure 2] FIG. 10 is a structural schematic diagram of another array substrate according to an embodiment of the present application. [Figure 3] FIG. 10 is a structural schematic diagram of another array substrate according to an embodiment of the present application. [Figure 4] 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application. [Figure 5] 5 is a flowchart of step S300 in FIG. 4 according to an embodiment of the present application. [Figure 6] FIG. 6 is a structural schematic diagram of step S330a in FIG. 5 according to an embodiment of the present application. [Figure 7] 5 is another flowchart of step S300 in FIG. 4 according to an embodiment of the present application. [Figure 8] FIG. 8 is a structural schematic diagram of step S330b in FIG. 7 according to an embodiment of the present application. [Figure 9] 1 is a structural schematic diagram of a display panel according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. Based on the embodiments of the present application, all other embodiments that a person skilled in the art can come up with without any creative effort fall within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only intended to explain and interpret the present application, and are not intended to limit the present application. In this application, unless otherwise stated, the terms "up" and "down" used in the directions generally refer to the up and down of the device in its actual use or operating state, specifically in the direction of the paper in the drawings, and "inside" and "outside" refer to the directions relative to the contour of the device.

[0028] The embodiments of the present application provide an array substrate, a display panel, and a manufacturing method of the array substrate, which will be described in detail below. Note that the order of description of the embodiments below does not limit the preferred order of the embodiments.

[0029] First, an embodiment of the present application provides an array substrate. As shown in Figures 1 to 3, the array substrate 100 includes a base substrate 110, which serves as a support structure for the array substrate 100, supporting other functional structural layers of the array substrate 100 and ensuring the structural stability of the array substrate 100. Here, the base substrate 110 may be a glass substrate or other types of materials, and is not particularly limited herein.

[0030] The array substrate 100 includes an active layer 140, which is disposed on a base substrate 110. The active layer 140 is an important component of the thin film transistor and is used to form a conductive trench. The conductive trench in the active layer 140 can be controlled to control the conduction state of the thin film transistor.

[0031] The array substrate 100 includes a first electrode layer 150, which is disposed on the side of the active layer 140 that faces away from the base substrate 110, and the first electrode layer 150 and the active layer 140 are partially overlapping and connected. By arranging the first electrode layer 150 and the active layer 140 to overlap and connect, the input signal on the array substrate 100 can be transmitted between the active layer 140 and the first electrode layer 150, and the array substrate 100 can be used normally.

[0032] The array substrate 100 includes a first insulating layer 160, which is disposed on the side of the first electrode layer 150 away from the active layer 140, thereby isolating the first electrode layer 150 from the subsequent functional layer, and preventing the first electrode layer 150 and the subsequent functional layer from directly overlapping and connecting with each other, causing mutual interference and further affecting the normal use of the array substrate 100.

[0033] Here, the first insulating layer 160 includes a passivation layer 162 and a planarization layer 163 stacked one on top of the other, and the passivation layer 162 mainly serves to insulate. When forming the first electrode layer 150, the first electrode layer 150 needs to be patterned, which reduces the surface flatness after the passivation layer 162 is formed. Therefore, forming an additional planarization layer 163 on the passivation layer 162 helps to improve the flatness of the entire surface, which is useful for the fabrication of subsequent film layers and ensures the structural stability of the entire array substrate 100.

[0034] The array substrate 100 further includes a second electrode layer 170, which is disposed on a side of the first insulating layer 160 away from the first electrode layer 150. The orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110, i.e., when the first electrode layer 150 and the active layer 140 are overlapped and connected, the active layer 140 is at least partially orthogonal projection of the active layer 140 on the base substrate 110. 40, and is arranged so that the orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110. In this way, the first electrode layer 150 and the second electrode layer 170 can protect the active layer 140 and prevent external light from affecting the active layer 140, thereby ensuring the stability of the array substrate 100.

[0035] In the embodiment of the present application, the array substrate 100 includes a base substrate 110, an active layer 140, a first electrode layer 150, a first insulating layer 160, and a second electrode layer 170, which are arranged in this order, and the first electrode layer 150 and the active layer 140 are connected in a partially overlapping manner, the orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110. In the present application, the orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110. This allows the first electrode layer 150 and the second electrode layer 170 to jointly protect the active layer 140, preventing external light from affecting the active layer 140 and thereby ensuring the stability of the array substrate 100.

[0036] Preferably, the orthogonal projection of the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110, i.e., when forming the second electrode layer 170 and patterning the second electrode layer 170, the orthogonal projection of the part of the second electrode layer 170 corresponding to the active layer 140 on the base substrate 110 can directly cover the orthogonal projection of the active layer 140 on the base substrate 110, thereby eliminating the need to consider the light-shielding area of ​​the first electrode layer 150 for the active layer 140, and the second electrode layer 170 itself can achieve light-shielding for the active layer 140, which helps simplify the patterning design of the second electrode layer 170.

[0037] In another embodiment, when the second electrode layer 170 is formed and patterned, the area of ​​the active layer 140 and the light-shielding area of ​​the first electrode layer 150 relative to the active layer 140 may be combined so that the orthogonal projection of the second electrode layer 170 on the base substrate 110 of the portion of the second electrode layer 170 corresponding to the active layer 140 only covers the portion of the active layer 140 that is not shaded by the first electrode layer 150. That is, the light-shielding area of ​​the second electrode layer 170 relative to the active layer 140 and the light-shielding area of ​​the first electrode layer 150 are equal to the area of ​​the orthogonal projection of the active layer 140 on the base substrate 110, thereby making full use of the light-shielding effects of the first electrode layer 150 and the second electrode layer 170, further reducing the use of the second electrode layer 170 and reducing the overall weight of the array substrate 100, and realizing a lightweight design for the array substrate 100.

[0038] Here, the specific design form of the second electrode layer 170 can be adjusted according to actual design needs, and is not particularly limited herein as long as the installation of the first electrode layer 150 and the second electrode layer 170 can ensure light blocking for the active layer 140 and prevent the active layer 140 from being affected by external light, thereby ensuring the stability of the array substrate 100.

[0039] In some embodiments, as shown in FIG. 1 , the first electrode layer 150 includes a first electrode 151, which overlaps and connects to one end of the active layer 140; the first insulating layer 160 has a first opening 161, which exposes the other end of the active layer 140; the second electrode layer 170 includes a second electrode 171, which overlaps and connects to the other end of the active layer 140 through the first opening 161. That is, the first electrode 151 and the second electrode 171 are components of a thin film transistor, and the first electrode 151 and the second electrode 171 are respectively overlapped and connected to both ends of the active layer 140, allowing charge carriers to flow between the first electrode 151 and the second electrode 171 through the conductive trench in the active layer 140, thereby realizing normal use of the array substrate 100. At the same time, the second electrode 171 also plays a light-shielding role on the active layer 140, thereby preventing external light from affecting the active layer 140, and thereby ensuring the stability of the array substrate 100.

[0040] Here, the first electrode 151 is the drain and the second electrode 171 is the source, or the first electrode 151 is the source and the second electrode 171 is the drain. The definition of the source and drain can be adjusted according to actual design needs and is not particularly limited here. By controlling the conduction or cutoff between the source and drain, it is possible to control the conduction or cutoff of the thin film transistor.

[0041] 3 , the first electrode layer 150 includes a source 152 and a drain 153 that overlap and are connected to the active layer 140, and the second electrode layer 170 includes a light-shielding electrode 172, the orthogonal projection of which on the base substrate 110 covers the orthogonal projection of which on the base substrate 110 covers the active layer 140. That is, the first electrode layer 150 simultaneously forms the source 152 and the drain 153 of the thin film transistor, and the portion of the second electrode layer 170 that corresponds to the active layer 140 only serves a light-shielding function, preventing external light from affecting the active layer 140 and thereby ensuring the stability of the array substrate 100. This structural arrangement allows the thin film transistor and the light-shielding electrode 172 to be independent of each other, preventing the light-shielding electrode 172 from interfering with the thin film transistor, thereby ensuring the stability of the array substrate 100 during use.

[0042] In addition, the material of the second electrode layer 170 is a non-transparent conductive material, which simultaneously fulfills the purpose of the second electrode layer 170 blocking light from the active layer 140 and overlapping and connecting the corresponding second electrode 171 and the active layer 140 in the embodiment shown in Figures 1 and 2, thereby realizing the transmission of control signals in the array substrate 100.

[0043] Preferably, the array substrate 100 includes a gate layer 120, which is disposed between the base substrate 110 and the active layer 140. The gate layer 120 includes a gate 121 disposed corresponding to the active layer 140, and the orthogonal projection of the gate 121 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110. Here, the gate 121 is a component of a thin film transistor. When a control signal is input to the gate 121, a sensitive charge is generated in the active layer 140 to form a conductive trench, thereby realizing conduction between the source and drain of the thin film transistor. By arranging the orthogonal projection of the gate 121 on the base substrate 110 to cover the orthogonal projection of the active layer 140 on the base substrate 110, the gate 121 can simultaneously shield the side of the active layer 140 facing the base substrate 110 from light, thereby realizing light shielding on both sides of the active layer 140 and further preventing external light from affecting the active layer 140 and ensuring the stability of the array substrate 100.

[0044] The array substrate 100 further includes a second insulating layer 130, which is disposed between the gate layer 120 and the active layer 140 and covers the gate layer 120 to isolate the gate layer 120 from the active layer 140 and avoid interference between the gate layer 120 and the active layer 140, thereby ensuring the normal operation of the thin film transistor.

[0045] Preferably, the array substrate 100 further includes a third insulating layer 180 and a pixel electrode layer 190, where the third insulating layer 180 is disposed on a side of the second electrode layer 170 that is away from the first insulating layer 160, and the pixel electrode layer 190 is disposed on a side of the third insulating layer 180 that is away from the second electrode layer 170. The third insulating layer 180 is used to isolate the second electrode layer 170 and the pixel electrode layer 190 from each other to avoid mutual interference between the pixel electrode layer 190 and the second electrode layer 170, thereby ensuring the normal use of the array substrate 100.

[0046] 1 , a second opening 181 is formed in the third insulating layer 180. The second opening 181 penetrates the third insulating layer 180 and the first insulating layer 160 along the thickness direction of the array substrate 100. The second opening 181 exposes the first electrode 151. The pixel electrode layer 190 includes a pixel electrode 191, which is electrically connected to the first electrode 151 through the second opening 181. The first electrode 151 is part of a thin film transistor, and electrically connects the pixel electrode 191 to the first electrode 151, thereby achieving electrical connection between the pixel electrode 191 and the thin film transistor. During use of the array substrate 100, the conduction status of the signal on the pixel electrode 191 can be controlled by controlling the conduction and blocking of the thin film transistor, and further the light emission mode of the light-emitting pixel can be controlled, thereby meeting various display needs.

[0047] 2 , a third opening 182 is formed in the third insulating layer 180, and the third opening 182 exposes the second electrode 171. The pixel electrode layer 190 includes a pixel electrode 191, and the pixel electrode 191 is electrically connected to the second electrode 171 through the third opening 182. The second electrode 171 is part of a thin film transistor, and electrically connects the pixel electrode 191 to the second electrode 171, thereby achieving electrical connection between the pixel electrode 191 and the thin film transistor. During use of the array substrate 100, the conduction status of the signal on the pixel electrode 191 can be controlled by controlling the conduction and blocking of the thin film transistor, and further the light emission mode of the light-emitting pixel can be controlled, thereby meeting various display needs.

[0048] In addition, during use of the array substrate 100, the pixel electrode 191 is electrically connected to the drain of the thin film transistor, and when the pixel electrode 191 is electrically connected to the first electrode 151, the first electrode 151 is the drain, and when the pixel electrode 191 is electrically connected to the second electrode 171, the second electrode 171 is the drain.

[0049] Preferably, the second electrode layer 170 further includes a common electrode 173, that is, when forming the second electrode layer 170 and patterning the second electrode layer 170, the second electrode 171 and the common electrode 173 can be formed simultaneously, or the light-shielding electrode 172 and the common electrode 173 can be formed simultaneously, thereby eliminating the need to separately manufacture a photomask for the common electrode 173, and further simplifying the process of the array substrate 100 and reducing production costs.

[0050] The pixel electrode layer 190 further includes a connecting electrode 192, that is, when forming the pixel electrode layer 190 and patterning the pixel electrode layer 190, the pixel electrode 191 and the connecting electrode 192 can be formed simultaneously, thereby eliminating the need to separately manufacture a photomask for the connecting electrode 192, and further simplifying the process of the array substrate 100 and reducing production costs.

[0051] Here, a fourth opening 183 is formed on the third insulating layer 180 at a position corresponding to the common electrode 173, and the connection electrode 192 is electrically connected to the common electrode 173 through the fourth opening 183. In addition, a common electrode line (not shown) is further provided on the array substrate 100, and the common electrode line can be provided on the same layer as the gate 121. That is, when the gate layer 120 is formed and patterned, the gate 121 and the common electrode line can be formed simultaneously, thereby simplifying the process of the array substrate 100.

[0052] In addition, the connecting electrode 192 is electrically connected to the common electrode 173, and is also electrically connected to the common electrode line at the same time. That is, when the array substrate 100 is in use, a corresponding control signal is input to the common electrode line, and the control signal is transmitted to the common electrode 173 via the connecting electrode 192, thereby controlling the light emitting mode of the corresponding light emitting pixel and meeting various display needs.

[0053] Next, an embodiment of the present application provides a display panel, which includes an array substrate, and the specific structure of the array substrate can be referred to the above embodiments. The display panel adopts all the technical solutions of all the above embodiments, and therefore has at least all the beneficial effects brought by the technical solutions of the above embodiments, and the description thereof will be omitted here.

[0054] 9, the display panel 10 includes an array substrate 100, a light emitting device 200, and a packaging assembly 300. The light emitting device 200 is mounted on the array substrate 100, which is electrically connected to the light emitting device 200 to control the light emitting mode of the light emitting device 200 and thereby control the display mode of the entire display panel 10. The packaging assembly 300 is mounted on the light emitting device 200 to protect the internal structures of the light emitting device 200 and the array substrate 100 and prevent external moisture or oxygen from entering and corroding the internal structures of the light emitting device 200 or the array substrate 100, thereby ensuring the overall performance and display effect of the display panel 10.

[0055] It should be noted that the application range of the display panel 10 in the embodiments of the present application is very wide, and various display and lighting related display devices such as televisions, computers, mobile phones, foldable and rollable displays, and wearable devices such as smart bracelets and smart watches are all within the scope of application of the display panel 10 in the embodiments of the present application.

[0056] Finally, the embodiment of the present application further provides a method for manufacturing an array substrate, as shown in FIG. 4, the method for manufacturing an array substrate mainly includes the following steps:

[0057] S100, a base substrate 110 is provided.

[0058] When manufacturing the array substrate 100, it is necessary to first provide a base substrate 110 and clean the base substrate 110 to remove any contaminants thereon, thereby facilitating the manufacture of subsequent film layers. The base substrate 110 serves as a support structure for the array substrate 100, supporting other functional structural layers of the array substrate 100 and ensuring the structural stability of the array substrate 100. Here, the base substrate 110 may be a glass substrate or other types of materials, and is not particularly limited herein.

[0059] In S200, the active layer 140 is formed on the base wafer 110.

[0060] After the base substrate 110 is prepared, a layer of active layer 140 is deposited on the base substrate 110, and then a patterning process is performed on the active layer 140. The active layer 140 is an important component of the thin film transistor in the array substrate 100 and is used to form a conductive trench, and the conductive state of the thin film transistor can be controlled by controlling the conductive trench in the active layer 140.

[0061] S300: Forming a first electrode layer 150, a first insulating layer 160, and a second electrode layer 170, in that order, on the side of the active layer 140 away from the base substrate 110, so that the first electrode layer 150 and the active layer 140 are connected by partially overlapping each other, and so that the orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and so that the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110.

[0062] After completing the manufacturing of the active layer 140, a first electrode layer 150, a first insulating layer 160, and a second electrode layer 170 are deposited in that order on the side of the active layer 140 facing away from the base substrate 110, and the first electrode layer 150 and the second electrode layer 170 are each patterned so that the first electrode layer 150 and the active layer 140 are connected in a partially overlapping manner, so that the orthogonal projection of the second electrode layer 170 on the base substrate 110 at least partially covers the orthogonal projection of the active layer 140 on the base substrate 110, and the sum of the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110.

[0063] Here, by arranging the first electrode layer 150 and the active layer 140 so as to overlap and connect, input signals on the array substrate 100 can be transmitted between the active layer 140 and the first electrode layer 150, and the normal use of the array substrate 100 can be realized. The first insulating layer 160 is used to isolate the first electrode layer 150 and the second electrode layer 170, so as to prevent the first electrode layer 150 and the second electrode layer 170 from directly overlapping and connecting, which would cause mutual interference and further affect the normal use of the array substrate 100. The first insulating layer 160 includes a passivation layer 162 and a planarization layer 163 stacked one on top of the other. The passivation layer 162 mainly serves to insulate the electrode layer 150. When the first electrode layer 150 is formed, the first electrode layer 150 needs to be patterned, which reduces the surface flatness after the passivation layer 162 is formed. Therefore, forming an additional planarization layer 163 on the passivation layer 162 helps to improve the overall surface flatness, which is beneficial for the fabrication of subsequent film layers and ensures the structural stability of the entire array substrate 100.

[0064] Furthermore, when the first electrode layer 150 overlaps and connects with the active layer 140, it partially covers the active layer 140. Through the cooperation of the first electrode layer 150 and the second electrode layer 170, the orthogonal projections of the first electrode layer 150 and the second electrode layer 170 on the base substrate 110 jointly cover the orthogonal projection of the active layer 140 on the base substrate 110, thereby protecting the active layer 140 and preventing external light from affecting the active layer 140, thereby ensuring the stability of the array substrate 100.

[0065] In some embodiments, as shown in FIG. 5, step S300 mainly includes the following content:

[0066] S310a: A first electrode layer 150 is formed on the side of the active layer 140 that is away from the base substrate 110, and the first electrode layer 150 is patterned to form a first electrode 151 that overlaps and is connected to one end of the active layer 140.

[0067] In step S320a, a first insulating layer 160 is formed on the side of the first electrode layer 150 that faces away from the active layer 140, and a first opening 161 is formed in the first insulating layer 160 to expose the other end of the active layer 140.

[0068] S330a: forming a second electrode layer 170 on the side of the first insulating layer 160 away from the first electrode layer 150, and patterning the second electrode layer 170 to form a second electrode 171 that overlaps and is connected to the other end of the active layer 140, so that the orthogonal projection of the second electrode 171 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110.

[0069] 6 , during the manufacturing process of the array substrate 100, the first electrode layer 150 is patterned to form the first electrode 151, and the second electrode layer 170 is patterned to form the second electrode 171, making the first electrode 151 and the second electrode 171 components of a thin film transistor. The first electrode 151 and the second electrode 171 are respectively overlapped and connected to both ends of the active layer 140, allowing charge carriers to flow between the first electrode 151 and the second electrode 171 through the conductive trench in the active layer 140, thereby realizing the normal use of the array substrate 100. At the same time, the orthogonal projection of the second electrode 171 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110. The second electrode 171 also provides a light-shielding effect to the active layer 140, preventing external light from affecting the active layer 140 and ensuring the stability of the array substrate 100.

[0070] Here, the first electrode 151 is the drain and the second electrode 171 is the source, or the first electrode 151 is the source and the second electrode 171 is the drain. The definition of the source and drain can be adjusted according to actual design needs and is not particularly limited here. By controlling the conduction or cutoff between the source and drain, it is possible to control the conduction or cutoff of the thin film transistor.

[0071] In some other embodiments, as shown in FIG. 7, step S300 mainly includes:

[0072] In step S310b, a first electrode layer 150 is formed on the side of the active layer 140 that faces away from the base substrate 110, and the first electrode layer 150 is patterned to form a source 152 and a drain 153 that overlap and are connected to the active layer 140.

[0073] S320b: forming a first insulating layer 160 on the side of the first electrode layer 150 away from the active layer 140;

[0074] S330b: A second electrode layer 170 is formed on the side of the first insulating layer 160 away from the first electrode layer 150, and the second electrode layer 170 is patterned to form a light-shielding electrode 172, so that the orthogonal projection of the light-shielding electrode 172 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110.

[0075] 8, in the process of manufacturing the array substrate 100, the first electrode layer 150 is patterned to form the source 152 and drain 153 that overlap and are connected to the active layer 140, and the second electrode layer 170 is patterned to form the light-shielding electrode 172, so that the first electrode layer 150 simultaneously forms the source 152 and drain 153 of the thin film transistor, and the portion of the second electrode layer 170 that corresponds to the active layer 140 only serves a light-shielding function, preventing external light from affecting the active layer 140 and thereby ensuring the stability of the array substrate 100. This structural installation method allows the thin film transistor and the light-shielding electrode 172 to be independent of each other, preventing the light-shielding electrode 172 from interfering with the thin film transistor, thereby ensuring the stability of the array substrate 100 during use.

[0076] Preferably, in the process of manufacturing the array substrate 100, before manufacturing the active layer 140, a gate layer 120 and a second insulating layer 130 are first deposited in sequence on the base substrate 110, and the gate layer 120 is patterned to form a gate 121 corresponding to the active layer 140, so that the orthogonal projection of the gate 121 on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110.

[0077] The gate 121 is disposed such that its orthogonal projection on the base substrate 110 covers the orthogonal projection of the active layer 140 on the base substrate 110, so that the gate 121 can simultaneously shield the side of the active layer 140 facing the base substrate 110, thereby realizing light shielding on both sides of the active layer 140, further preventing external light from affecting the active layer 140, and ensuring the stability of the array substrate 100. The second insulating layer 130 is disposed between the gate layer 120 and the active layer 140, and covers the gate layer 120 to isolate the gate layer 120 from the active layer 140 and prevent interference between them, thereby ensuring the normal operation of the thin film transistor.

[0078] Preferably, after completing the fabrication of the second electrode layer 170, the fabrication method of the array substrate 100 further includes: sequentially depositing a third insulating layer 180 and a pixel electrode layer 190 on the side of the second electrode layer 170 away from the first insulating layer 160, opening a second opening 181 in the third insulating layer 180 to expose the first electrode 151, and patterning the pixel electrode layer 190 to form a pixel electrode 191 connected to the first electrode 151.

[0079] Here, the third insulating layer 180 is used to isolate the second electrode layer 170 and the pixel electrode layer 190 to prevent mutual interference between the pixel electrode layer 190 and the second electrode layer 170, thereby ensuring the normal use of the array substrate 100. The pixel electrode 191 can be electrically connected to the first electrode 151, thereby realizing an electrical connection between the pixel electrode 191 and the thin film transistor. During use of the array substrate 100, the conduction status of the signal on the pixel electrode 191 can be controlled by controlling the conduction and cut-off of the thin film transistor, and further the light emission mode of the light-emitting pixel can be controlled, thereby meeting various display needs.

[0080] In addition, when patterning the second electrode layer 170, the second electrode 171 and the common electrode 173 can be formed simultaneously, or the light-shielding electrode 172 and the common electrode 173 can be formed simultaneously, thereby eliminating the need to separately manufacture a photomask for the common electrode 173, further simplifying the manufacturing process of the array substrate 100 and reducing production costs.

[0081] The above has introduced in detail the array substrate, display panel, and array substrate manufacturing method according to the embodiments of the present application, and in this specification, specific examples have been used to describe the principles and embodiments of the present application. However, the explanation of the above examples is only for understanding the method of the present application and its core idea. It should be understood that a person skilled in the art can modify the specific embodiment and application scope based on the idea of ​​the present application. In short, it should be understood that the contents of this specification are not intended to limit the present application.

Claims

1. An array substrate, A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer being connected to each other in a partially overlapping manner; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein an orthogonal projection of the second electrode layer on the base substrate at least partially covers an orthogonal projection of the active layer on the base substrate, and a sum of orthogonal projections of the first electrode layer and the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate; the first electrode layer and the second electrode layer are made of a non-transparent conductive material; the first electrode layer includes a first electrode, the first electrode being connected to and overlapping one end of the active layer; a first opening is formed in the first insulating layer, the first opening exposing the other end of the active layer; the second electrode layer includes a second electrode, the second electrode being connected to and overlapping the other end of the active layer through the first opening; The array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a second opening formed therein, the second opening penetrating the third insulating layer and the first insulating layer along a thickness direction of the array substrate, the second opening exposing the first electrode, and the third insulating layer isolating the second electrode layer from the second opening; a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening.

2. The array substrate according to claim 1 , wherein an orthogonal projection of the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate.

3. 2. The array substrate according to claim 1, wherein a sum of a light-shielding area of ​​the second electrode layer for the active layer and a light-shielding area of ​​the first electrode layer for the active layer is equal to an area of ​​an orthogonal projection of the active layer on the base substrate.

4. 2. The array substrate according to claim 1, wherein the first electrode is a drain and the second electrode is a source.

5. 2. The array substrate of claim 1, wherein the first electrode layer includes a source and a drain overlapping and connected to the active layer, the second electrode layer includes a light-shielding electrode, and an orthogonal projection of the light-shielding electrode on the base substrate covers an orthogonal projection of the active layer on the base substrate.

6. The array substrate comprises: a gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, and an orthogonal projection of the gate on the base substrate covering an orthogonal projection of the active layer on the base substrate; 2. The array substrate according to claim 1, further comprising: a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covering the gate layer.

7. 2. The array substrate of claim 1, wherein the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening is opened on the third insulating layer at a position corresponding to the common electrode, and the connection electrode is electrically connected to the common electrode through the fourth opening.

8. An array substrate, A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer being connected to each other in a partially overlapping manner; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein an orthogonal projection of the second electrode layer on the base substrate at least partially covers an orthogonal projection of the active layer on the base substrate, and a sum of orthogonal projections of the first electrode layer and the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate; the first electrode layer and the second electrode layer are made of a non-transparent conductive material; the first electrode layer includes a first electrode, the first electrode being connected to and overlapping one end of the active layer; a first opening is formed in the first insulating layer, the first opening exposing the other end of the active layer; the second electrode layer includes a second electrode, the second electrode being connected to and overlapping the other end of the active layer through the first opening; The array substrate comprises: a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, the third insulating layer having a third opening formed therein, the third opening exposing the second electrode; a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening.

9. 9. The array substrate of claim 8, wherein the second electrode layer further includes a common electrode, the pixel electrode layer further includes a connection electrode, a fourth opening is opened on the third insulating layer at a position corresponding to the common electrode, and the connection electrode is electrically connected to the common electrode through the fourth opening.

10. An array substrate, A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer being connected to each other in a partially overlapping manner; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein an orthogonal projection of the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate; wherein the first electrode layer includes a first electrode, the first electrode being connected to and overlapping one end of the active layer; a first opening is formed in the first insulating layer, the first opening exposing the other end of the active layer; the second electrode layer includes a second electrode, the second electrode being connected to and overlapping the other end of the active layer through the first opening; the first electrode layer and the second electrode layer are made of a non-transparent conductive material; The array substrate comprises: a third insulating layer disposed on a side of the second electrode layer that is away from the first insulating layer, the third insulating layer having a second opening formed therein, the second opening penetrating the third insulating layer and the first insulating layer along a thickness direction of the array substrate, the second opening exposing the first electrode, and the third insulating layer isolating the second electrode layer from the second opening; a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the first electrode through the second opening.

11. 11. The array substrate according to claim 10, wherein the first electrode is a drain and the second electrode is a source.

12. The array substrate comprises: a gate layer disposed between the base substrate and the active layer, the gate layer including a gate disposed corresponding to the active layer, and an orthogonal projection of the gate on the base substrate covering an orthogonal projection of the active layer on the base substrate; The array substrate according to claim 10 , further comprising: a second insulating layer disposed between the gate layer and the active layer, the second insulating layer covering the gate layer.

13. An array substrate, comprising: A base substrate; an active layer disposed on the base substrate; a first electrode layer disposed on a side of the active layer away from the base substrate, the first electrode layer and the active layer being connected to each other in a partially overlapping manner; a first insulating layer disposed on a side of the first electrode layer away from the active layer; a second electrode layer disposed on a side of the first insulating layer away from the first electrode layer, wherein an orthogonal projection of the second electrode layer on the base substrate covers an orthogonal projection of the active layer on the base substrate; wherein the first electrode layer includes a first electrode, the first electrode being connected to and overlapping one end of the active layer; a first opening is formed in the first insulating layer, the first opening exposing the other end of the active layer; the second electrode layer includes a second electrode, the second electrode being connected to and overlapping the other end of the active layer through the first opening; the first electrode layer and the second electrode layer are made of a non-transparent conductive material; The array substrate comprises: a third insulating layer disposed on a side of the second electrode layer away from the first insulating layer, the third insulating layer having a third opening formed therein, the third opening exposing the second electrode; a pixel electrode layer disposed on a side of the third insulating layer away from the second electrode layer, the pixel electrode layer including a pixel electrode, the pixel electrode being electrically connected to the second electrode through the third opening.

14. A display panel comprising the array substrate according to any one of claims 1 to 13.

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