QBIT DEVICE, METHOD FOR FABRICATING A QBIT DEVICE, AND CONTACT LAYER FOR THE METHOD - Patent application

Abstract

To provide a method for fabricating a qubit device and a contact layer for fabricating a qubit device.SOLUTION: A qubit device 100 includes first and second superconductor layers 102a, 102b, respectively including a first and second superconductor material, a capacitor 132, and first and second interconnects 108a, 108b. The first superconductor material is a first anisotropic layered material having covalently bonded atomic layers 126 and a first c-axis perpendicular to the covalently bonded atomic layers of the first superconductor material. A second superconductor layer is disposed on the first superconductor layer to form a Josephson junction 120 between the first and second superconductor materials, with the first and second c-axes aligned at the Josephson junction intersecting both superconductor layers. The capacitor includes first and second electrodes 130a, 130b. The first and second interconnects electrically connect the first and second electrodes and the first and second superconductor layers, respectively.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to qubit devices that use high temperature superconductors such as d-wave superconductors, and in particular to qubit devices of the transmon type and similar. [Background technology]

[0002] The modern microelectronics industry is experiencing rapid growth with a trend toward widespread use of qubits, which provide the foundation for quantum computing. Quantum computing has attracted significant attention over the past few years due to the promise of super-fast factoring and the possibility of efficient simulation of quantum dynamics. There are many different architectures for quantum computers based on various physical systems for implementing qubits. These include atom and ion trap quantum computing, superconducting charge and flux qubits, nuclear magnetic resonance, spin and charge-based quantum dots, nuclear spin quantum computing, and optical quantum computing. All of these systems have their own advantages in quantum information processing. However, while some precursors, such as ion trap and superconducting quantum computing, may currently exist, no physical implementation appears to have a clear advantage over the others at this time.

[0003] Conventional superconducting qubit devices comprise Josephson junctions between low-temperature superconductor materials such as Al or Nb. Qubit devices can be flexibly designed to match required parameters. Their macroscopic size allows for strong coupling, resulting in fast gates and measurements. Transmon superconducting qubits are the most common hardware implementation of quantum technology and are used in conventional superconducting quantum processors such as those developed by Google or IBM. The main drawback of transmons is their coupling with the electric field in the capacitor, which reduces the coherence time and introduces crosstalk between qubits, resulting in computational errors.

[0004] The coherence time of such conventional superconductor-based qubits, which comprise Josephson junctions between low-temperature superconductor materials, approaches 1 millisecond. However, despite their high quality, qubits based on low-temperature superconductors have inherent limitations. For example, these qubits are strongly affected by magnetic fields due to the intrinsic superconducting properties of low-temperature superconductors, such as their small superconducting gap and extremely low critical temperature of about 1 K.

[0005] Superconducting qubits using high-temperature superconductors have the potential to overcome some of these limitations. However, the actual physical implementation of qubits using high-temperature superconductor Josephson junctions is technically challenging because, unlike low-temperature superconductors such as Al or Nb, lithographic structuring or deposition techniques are not currently available for these materials. When lithographic structuring or deposition techniques used in the fabrication of conventional qubit devices are applied to high-temperature superconductors, they cause a significant density of defects therein and degradation of the high-temperature superconductor material.

[0006] WO 2022 / 197482 describes a transmon type qubit in which the conductive layer of the capacitor is made of van der Waals material. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2022 / 197482 Summary of the Invention [Problem to be solved by the invention]

[0008] In view of the above technical problems, there is a need for improved qubits, which problem is solved by a qubit device according to claim 1, a method for manufacturing a qubit device according to claim 9, and a contact layer for manufacturing a qubit device according to claim 15. The dependent claims relate to preferred embodiments. [Means for solving the problem]

[0009] In a first aspect, a qubit device includes a first superconductor layer, a second superconductor layer, a capacitor, a first interconnect, and a second interconnect. The first superconductor layer includes a first superconductor material. The first superconductor material is a first anisotropic layered material having covalently bonded atomic layers and a first c-axis perpendicular to the covalently bonded atomic layers of the first superconductor material. The second superconductor layer includes a second superconductor material. The second superconductor material is a second anisotropic layered material having covalently bonded atomic layers and a second c-axis perpendicular to the covalently bonded atomic layers of the second superconductor material. The second superconductor layer is disposed on the first superconductor layer to form a Josephson junction between the first and second superconductor materials. The first c-axis and the second c-axis are aligned with each other at the Josephson junction. The first and second c-axes aligned at the Josephson junction intersect both the first superconductor layer and the second superconductor layer. The capacitor includes a first electrode and a second electrode. A first interconnect electrically connects the first electrode and the first superconductor layer. A second interconnect electrically connects the second electrode and the second superconductor layer. The capacitor is positioned at a vertical position that exceeds the vertical positions of both the first superconductor layer and the second superconductor layer.

[0010] This structure allows the Josephson junctions to be designed and provided independently of the capacitors, and vice versa, resulting in a fully optimized qubit device. Compared to low-temperature superconductor materials, superconductor layers, including anisotropic layered materials, can vary (e.g., with respect to their size or shape) during fabrication. An advantage of the qubit devices herein is that fabrication variations of the superconductor layers (and / or the Josephson junctions, respectively) do not translate into variations in the capacitors; instead, they can be compensated for by a tailored design of the capacitors. The capacitors can be fabricated using conventional lithographic structuring or deposition techniques, providing high structural precision.

[0011] The structure is a direct result of implementing the fabrication techniques or providing the contact layers, respectively, as described in detail below, and the resulting structure, i.e., the (first and second) superconductor materials, have a significantly lower defect density than structures, or (higher critical temperature) superconductor materials therein, respectively, fabricated using lithographic structuring or deposition techniques.

[0012] The Josephson junction may, in particular embodiments, be referred to as a van der Waals Josephson junction, and the first and / or second superconductor materials are van der Waals materials.

[0013] The first and / or second anisotropic layered materials may be cleavable materials, such as materials that can be cleaved using adhesive tape.

[0014] The first superconductor layer may be composed of a first superconductor material.

[0015] The second superconductor layer may be composed of a second superconductor material.

[0016] The first c-axis may refer to a natural crystallographic axis of the first superconductor material.

[0017] The second c-axis may refer to a natural crystallographic axis of the second superconductor material.

[0018] The first and / or second superconductor materials may comprise a layered atomic and / or crystalline structure, and the first (and / or second) c-axis may be perpendicular to the covalently bonded layers and / or to the van der Waals gap of the layered atomic and / or crystalline structure of the first (and / or second) superconductor materials.

[0019] The first and / or second superconductor materials may be van der Waals materials. Any of the anisotropic layered materials may be isotropic on an atomic scale and / or with respect to their electronic, optical, and / or mechanical properties, e.g., when in single crystalline form.

[0020] The capacitor may be disposed on the Josephson junction.

[0021] The vertical line may intersect both the first superconductor layer and the first electrode.

[0022] The vertical line may intersect both the second superconductor layer and the second electrode.

[0023] The qubit device may further comprise an electrical isolation element.

[0024] The electrical insulating element may be disposed at a vertical position between the vertical position of the capacitor and the vertical position of the first superconductor layer and / or the second superconductor layer.

[0025] Each electrical insulating element ensures that the second superconductor layer and the first electrode are electrically insulated from one another and / or that the first superconductor layer and the second electrode are electrically insulated from one another, and furthermore, the electrical insulating element provides a matrix for the first and / or second interconnects.

[0026] An electrical insulating element may be disposed between the first superconductor layer and the second electrode.

[0027] An electrical insulating element may be disposed between the second superconductor layer and the first electrode.

[0028] An electrical insulating element may be disposed between the first superconductor layer and the first electrode.

[0029] An electrical insulating element may be disposed between the second superconductor layer and the second electrode.

[0030] At least a section of the first interconnect may be disposed within the electrically insulating element.

[0031] The first interconnect may be disposed within the electrically insulating element.

[0032] At least a section of the second interconnect may be disposed within the electrically insulating element.

[0033] The second interconnect may be disposed within the electrically insulating element.

[0034] The first interconnect and / or the second interconnect may extend through the electrically insulating element, optionally from a bottom surface thereof to a top surface thereof.

[0035] The electrically insulating element may include or consist of silicon carbide, silicon nitride, or amorphous silicon.

[0036] Each material provides sufficient electrical insulation, and when provided as a sufficiently thin layer (e.g., 600 nm or less), they are mechanically flexible, which is beneficial for fabrication of the respective qubit devices.

[0037] The lateral extension of the electrical insulation element may completely cover the lateral extension of the first superconductor layer and the lateral extension of the second superconductor layer.

[0038] In each embodiment, the electrical insulation element also provides mechanical protection for the first and / or second superconductor layers, and in some embodiments provides a seal against, for example, moisture or reactive gases such as oxygen.

[0039] The electrically insulating element may have a thickness along the vertical direction in the range of 300 nm to 600 nm.

[0040] The qubit device may further comprise an encapsulation of the Josephson junction, such as a watertight, moisture-proof, oxygen-tight and / or airtight encapsulation, which encapsulation comprises an electrically insulating element and, optionally, a substrate on which the Josephson junction is disposed.

[0041] The first superconductor material may have a first orientation parallel to its covalently bonded atomic layers. The second superconductor material may have a second orientation parallel to its covalently bonded atomic layers. The first and second superconductor materials in the Josephson junction may be arranged at an angle between the first and second orientations corresponding to a predetermined angle.

[0042] The device parameters of the qubit device may be tailored to the needs of a particular device application using the angle between the orientations of the superconductor material, for example, tuning each angle may provide a qubit device with a particularly long coherence time.

[0043] In the Josephson junction, the first superconductor material and the second superconductor material may be arranged such that the angle between the first orientation and the second orientation is in the range of 38 to 44.9°.

[0044] Each angle is particularly important for BSCCO (i.e., Bi2Sr2Ca n-1 Cu n O 2n+4+x ), to maximize the coherence time of the qubit device.

[0045] The first c-axis may correspond to a fundamental lattice vector of the first superconductor material.

[0046] The second c-axis may correspond to the fundamental lattice vector of the second superconductor material.

[0047] The first orientation may correspond to a first primitive lattice vector perpendicular to the first c-axis, in particular to the direction of the first primitive lattice vector perpendicular to the first c-axis.

[0048] The second orientation may correspond to a second primitive lattice vector perpendicular to the second c-axis, in particular to a direction of the second primitive lattice vector perpendicular to the first c-axis.

[0049] The covalently bonded atomic layers of the first superconductor material and / or the second superconductor material may be separated by a van der Waals gap.

[0050] The first orientation may correspond to a lattice vector of the first superconductor material parallel to the covalently bonded atomic layers of the first superconductor material, and the second orientation may correspond to a corresponding lattice vector of the second superconductor material parallel to the covalently bonded atomic layers of the second superconductor material.

[0051] The first orientation may refer to the direction of a node in the d-wave electronic spectrum of the respective superconductor material.

[0052] The first superconductor material and the second superconductor material may have the same crystal structure and / or the same crystalline unit cell and / or may be the same superconductor material.

[0053] The first superconductor material and / or the second superconductor material may in particular be a high temperature superconductor material having a critical temperature of at least 4K, or at least 8K, or at least 15K, or at least 30K, or at least 50K, or at least 70K, or at least 78K.

[0054] The first superconductor material and / or the second superconductor material may be a Type II superconductor material.

[0055] The first superconductor material and / or the second superconductor material may be a d-wave superconductor material.

[0056] The first superconductor material and / or the second superconductor material may in particular comprise at least 20 atomic % or up to at least 30 atomic % oxygen or chalcogenide.

[0057] The first and / or second superconductor material may have the chemical composition Bi2Sr2Ca, in particular with n=1, or 2, or 3, or 4. n-1 Cu n O 2n+4+x may include:

[0058] The distance between the first and second superconductor materials in the Josephson junction may be at least 0.2 nm, particularly at least 0.25 nm, particularly at least 0.3 nm, particularly at least 0.35 nm, particularly at least 0.4 nm, particularly at least 0.45 nm, or at least 0.5 nm.

[0059] The distance between the first and second superconductor materials in the Josephson junction may be at most 10 nm, particularly at most 8 nm, particularly at most 6 nm, particularly at most 4 nm, particularly at most 3 nm, particularly at most 2 nm, particularly at most 1 nm.

[0060] A spacer material may be disposed between the first and second superconductor materials in the Josephson junction, and optionally the spacer material includes or consists of an anisotropic layered material.

[0061] The spacer material can help ensure the correct distance between the superconductor materials in the Josephson junction.

[0062] The area of ​​the overlap region between the first superconductor material and the second superconductor material in the Josephson junction is at least 0.1 μm 2 , especially at least 0.3 μm 2 , especially at least 0.5 μm 2 , or at least 1 μm 2 may be.

[0063] The area of ​​the overlap region between the first and second superconductor materials in a Josephson junction is up to 50 μm 2 , or up to 1 μm 2 may be.

[0064] The qubit device may further comprise a microwave resonator.

[0065] Each microwave resonator facilitates readout of the qubit device, for example, in the form of distributed readout.

[0066] The microwave resonator may optionally be capacitively coupled to a capacitor along the horizontal direction.

[0067] The microwave resonator may be positioned at a vertical position above the vertical positions of both the first superconductor layer and the second superconductor layer.

[0068] Each microwave resonator may be advantageously fabricated in the same process step as the capacitor, so that each qubit device may be fabricated in a few steps, and therefore efficiently and economically.

[0069] The microwave resonator may include or consist of a superconductor material, such as a low temperature superconductor material, or an elemental or nitride superconductor material, such as Al, Nb, NbN, or TiN.

[0070] The respective choice of material facilitates the fabrication of the respective components using conventional lithographic structuring or deposition techniques, thus improving the structural precision during fabrication.

[0071] The resonant frequency of the microwave resonator may be in the range of 1 GHz to 10 GHz.

[0072] The capacitance of the capacitor may be in the range of 4 femtofarads to 500 femtofarads, or in the range of 4 femtofarads to 400 femtofarads, or in the range of 70 femtofarads to 400 femtofarads.

[0073] The first electrode and / or the second electrode, and / or the first interconnect and / or the second interconnect may comprise or consist of a superconductor material, such as a low temperature superconductor material, or an elemental or nitride superconductor material, such as Al, Nb, NbN, or TiN.

[0074] In a second aspect, a method for fabricating a qubit device includes providing a Josephson junction between a first superconductor material and a second superconductor material and providing a contact layer separate from the Josephson junction. The contact layer comprises an electrical insulating element, a first interconnect, and a second interconnect. The first interconnect extends through the electrical insulating element. The second interconnect extends through the electrical insulating element. The method further includes disposing the contact layer over the Josephson junction to form electrical contact between the first interconnect and the first superconductor material and to form electrical contact between the second interconnect and the second superconductor material.

[0075] This manufacturing method ensures that damage to the Josephson junction or to the first and second superconductor materials during fabrication is minimized by providing the contact layer separately from the Josephson junction and placing it thereon in a later step.

[0076] The contact layer provided separately from the Josephson junction may comprise a capacitor disposed on the electrically insulating element. In a corresponding embodiment, the capacitor may comprise a first electrode and a second electrode, and the first interconnect may be electrically connected to the first electrode and / or the second interconnect may be electrically connected to the second electrode.

[0077] The contact layer, provided separately from the Josephson junction, may comprise a microwave resonator disposed on the electrically insulating element, optionally capacitively coupled to a capacitor.

[0078] The method may further include cooling the Josephson junction to a temperature below a first temperature while the contact layer is disposed on the Josephson junction, the first temperature being 0°C, or 250K, or 230K, or 210K, or 190K, or 170K, or 150K, or 130K.

[0079] Cooling further reduces damage to the Josephson junctions or to the first and second superconductor materials, respectively, during fabrication.

[0080] Disposing the contact layer on the Josephson junction can include attaching a transfer device to the contact layer and cooling the transfer device to a temperature below a second temperature to attach the transfer device to the contact layer. The transfer device can be adapted to provide strong adhesion when the temperature of the transfer device is below the second temperature and to provide weak adhesion when the temperature of the transfer device is above the second temperature or above a third temperature that is greater than the second temperature.

[0081] Each transfer device allows for reliable pick-up and placement of the contact layer at reduced manufacturing temperatures (ie, below the first temperature).

[0082] The transfer device may include or be constructed from an elastomer.

[0083] The second temperature and / or the third temperature may be above the glass transition temperature of the elastomer.

[0084] The third temperature may correspond to the glass transition temperature of the elastomer.

[0085] The elastomer may be PTFE or PDMS.

[0086] The second temperature may be less than or equal to the first temperature.

[0087] Disposing the contact layer on the Josephson junction can include releasing the transfer device from the contact layer, where releasing the transfer device from the contact layer can include heating the transfer device to a temperature between a second temperature and the first temperature, each of which can exceed a third temperature, where the third temperature exceeds both the first temperature and the second temperature.

[0088] The first superconductor material may be a first anisotropic layered material having covalently bonded atomic layers and a first c-axis perpendicular to the covalently bonded atomic layers of the first superconductor material, and the second superconductor material may be a second anisotropic layered material having covalently bonded atomic layers and a second c-axis perpendicular to the covalently bonded atomic layers of the second superconductor material.

[0089] In each embodiment, the Josephson junction may be provided such that the first c-axis and the second c-axis are aligned with each other at the Josephson junction, and / or such that both the first c-axis and the second c-axis intersect both the first superconductor material and the second superconductor material at the Josephson junction.

[0090] Providing a Josephson junction between the first superconductor material and the second superconductor material may include disposing a first superconductor layer of a first anisotropic layered material on a substrate, and disposing a second superconductor layer of a second anisotropic layered material on the first superconductor layer to create the Josephson junction.

[0091] Providing a Josephson junction between the first and second superconductor materials may include, prior to disposing the first and second superconductor layers, cleaving a first anisotropic layered material to produce a first superconductor layer and / or cleaving a second anisotropic layered material to produce a second superconductor layer, and optionally maintaining the first anisotropic layered material at a temperature below the first temperature during cleaving the first anisotropic layered material and / or maintaining the second anisotropic layered material at a temperature below the first temperature during cleaving the second anisotropic layered material.

[0092] Cleaving the first anisotropic layered material, and / or cleaving the second anisotropic layered material, and / or disposing the first superconductor layer on the substrate, and / or disposing the second superconductor layer on the first superconductor layer may be performed using a transfer device that includes or is composed of an elastomer.

[0093] The electrically insulating element may be provided with a thickness that is sufficiently thin to be mechanically flexible, such as a thickness of 300 nm to 600 nm.

[0094] According to a third aspect, a contact layer for fabricating a qubit device includes an electrical insulating element, a capacitor, a first interconnect, and a second interconnect. The capacitor includes a first electrode and a second electrode disposed on the electrical insulating element. The first interconnect is electrically connected to the first electrode and extends through the electrical insulating element from its bottom surface to its top surface. The second interconnect is electrically connected to the second electrode and extends through the electrical insulating element from its bottom surface to its top surface. Each of the first electrode, second electrode, first interconnect, and second interconnect includes a respective superconductor material.

[0095] The electrically insulating element may have a thickness that is sufficiently thin to be mechanically flexible, such as a thickness of 300 nm to 600 nm.

[0096] The contact layer may comprise a microwave resonator disposed on the electrically insulating element, optionally the microwave resonator being capacitively coupled to the capacitor.

[0097] According to a further aspect, a method for altering a state of a qubit device includes coupling a first microwave having a first microwave frequency to the qubit device, the first microwave frequency being related to an energy difference between a third excited state and a ground state of the qubit device; coupling a second microwave having a second microwave frequency to the qubit device, the second microwave frequency being related to an energy difference between the third excited state and the second excited state of the qubit device; and coupling a third microwave having a third microwave frequency to the qubit device, the third microwave frequency being related to an energy difference between the second excited state and the first excited state of the qubit device.

[0098] The method allows for the state of a qubit device to be reliably changed even when the transition between the ground state and the first excited state of the qubit device has an extremely low transition probability, or when the ground state and the first excited state are (nearly) degenerate.

[0099] According to one embodiment, the first microwave frequency is mismatched to the energy difference between the third excited state and the ground state of the qubit device, e.g., by at least 0.01% and at most 5%. Alternatively, or additionally, the second microwave frequency can be mismatched to the energy difference between the third excited state and the second excited state of the qubit device, e.g., by at least 0.01% and at most 5%. Alternatively, or additionally, the third microwave frequency can be mismatched to the energy difference between the second excited state and the first excited state of the qubit device, e.g., by at least 0.01% and at most 5%. In a corresponding embodiment, the first microwave, second microwave, and third microwave may be coupled to the qubit device simultaneously.

[0100] According to another embodiment, the method includes first coupling a first microwave and a third microwave to a qubit device (optionally, the first microwave and the third microwave may be coupled to the qubit device as a π pulse), then coupling a second microwave to the qubit device (optionally, the second microwave may be coupled to the qubit device according to a predetermined phase difference between the ground state and the first excited state), and then coupling the first microwave and the third microwave to the qubit device (optionally, the first microwave and the third microwave may be coupled to the qubit device as a π pulse). In a corresponding embodiment, the first microwave frequency may be matched to the energy difference between the third excited state and the ground state of the qubit device, e.g., within 0.01%. Alternatively, or additionally, the second microwave frequency may be matched to the energy difference between the third excited state and the second excited state of the qubit device, e.g., within 0.01%. Alternatively, or additionally, the third microwave frequency may be matched to the energy difference between the second excited state and the first excited state of the qubit device, for example, to within 0.01%.

[0101] The qubit device may be a qubit device according to any of the embodiments described above.

[0102] The first microwave frequency may be in the range of 7 GHz to 15 GHz.

[0103] The second microwave frequency may be in the range of 1 GHz to 2 GHz.

[0104] The third microwave frequency may be in the range of 6 GHz to 13 GHz.

[0105] The method may further include analyzing the changed state of the qubit using distributed readout.

[0106] The coupling of the first, second, and / or third microwaves to the qubit device and / or the distributed readout may use the microwave resonators described above. [Brief explanation of the drawings]

[0107] The techniques of the present disclosure and their associated advantages will become better apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings. [Figure 1] FIG. 1 is a cross-sectional view of a qubit device according to one embodiment. [Figure 2a] FIG. 1 is a cross-sectional view of a qubit device according to another embodiment. [Figure 2b] FIG. 1 is a cross-sectional view of a qubit device according to another embodiment. [Figure 2c] FIG. 1 is a cross-sectional view of a qubit device according to another embodiment. [Figure 3] FIG. 1B is a top view of a qubit device according to another embodiment. [Figure 4a] FIG. 1 is a perspective view of a qubit device according to another embodiment. [Figure 4b] FIG. 4b is a cross-sectional view of the qubit device of FIG. 4a. [Figure 5a] FIG. 2 is a perspective view showing a second superconductor layer disposed on a first superconductor layer to form a Josephson junction. [Figure 5b] 5b is a top view showing a second superconductor layer disposed on the first superconductor layer according to FIG. 5a. [Figure 6] 1A-1C illustrate a method for forming a qubit device. [Figure 7] 1A-1D illustrate process steps for providing a contact layer. [Figure 8] 2 is a cross-sectional view of a contact layer according to one embodiment. [Figure 9] FIG. 1 illustrates the process step of depositing a second superconductor layer onto a first superconductor layer to form a Josephson junction. [Figure 10]FIG. 1 illustrates a method for altering the state of a qubit device, according to one embodiment. [Figure 11] FIG. 10 illustrates a method for altering the state of a qubit device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0108] FIG. 1 is a cross-sectional view of a qubit device 100 according to a first embodiment.

[0109] The qubit device 100 comprises a first superconductor layer 102a. It further comprises a second superconductor layer 102b disposed on the first superconductor layer 102a to form a Josephson junction 120.

[0110] The first superconductor layer 102a and the second superconductor layer 102b each comprise a superconductor material that is an anisotropic layered material, as is typical of high temperature critical superconductor materials or d-wave superconductor materials, respectively.

[0111] The thickness of the superconductor layers 102a and 102b is usually within the range of 30 nm to 90 nm.

[0112] Close-up 124' shows the anisotropic layered material. This is a close-up of the structure of second superconductor layer 102b in region 124. The distance between covalently bonded atomic layers 126 in close-up 124' corresponds to 1-5 nm, depending on the particular superconductor material. The covalently bonded atomic layers 126 of the second superconductor material are separated from each other by van der Waals gaps 128. Axis c is perpendicular to the covalently bonded atomic layers 126 or to the van der Waals gaps 128, respectively.

[0113] Close-up 124' shows the structure of the second superconductor material of second superconductor layer 102b. However, the first superconductor material of first superconductor layer 102a has a similar structure with covalently bonded atomic layers 126 and a van der Waals gap 128.

[0114] Examples of respective anisotropic layered superconductor materials are BSCCO (i.e., Bi2Sr2Ca n-1 Cu n O 2n+4+x , where n=2, 3, 4), or iron-based high-temperature superconductors (e.g., FeSe, potassium-doped FeSe, FeSexTe1-x).

[0115] Furthermore, a capacitor 132 is disposed on the first and second superconductor layers 102a, 102b, that is, at a position in the vertical direction z that exceeds the respective positions of the first and second superconductor layers 102a, 102b.

[0116] The capacitor 132 comprises two electrodes 130a, 130b arranged in close proximity to each other.

[0117] In the illustrated embodiment, the electrodes 130a, 130b are coupled horizontally, i.e., with minimal spacing between the electrodes 130a, 130b, and the surface normal of at least one or each of the electrodes 130a, 130b is horizontal and points toward the other of the electrodes 130a, 130b. In other embodiments (e.g., FIG. 2a), the electrodes 130a, 130b are coupled vertically.

[0118] The first interconnect 108a electrically connects the first superconductor layer 102a and the first electrode 130a.

[0119] The second interconnect 108b electrically connects the second superconductor layer 102b and the second electrode 130b.

[0120] Preferably, the electrodes 130a, 130b and interconnects 108a, 108b are composed of their respective superconductor materials, either low-temperature critical superconductor materials (e.g., elemental superconductors such as Al, Nb, TiN, or their nitrides) or high-temperature critical superconductor materials (e.g., the anisotropic layered superconductor materials described above). Electrodes 130a, 130b and interconnects 108a, 108b made from low-temperature critical superconductor materials facilitate high-precision manufacturing.

[0121] FIG. 2a shows a cross-sectional view of a qubit device 100 according to an embodiment similar to that of FIG.

[0122] However, in the embodiment of FIG. 2a, the electrodes 130a, 130b are vertically coupled, i.e., when the electrodes 130a, 130b exhibit their minimum separation, the surface normal of at least one of the or each of the electrodes 130a, 130b is vertical and points towards the other of the electrodes 130a, 130b.

[0123] FIG. 2b shows a cross-sectional view of a qubit device 100 according to an embodiment similar to that of FIG.

[0124] However, the interconnects 108a, 108b in FIG. 2b extend along the vertical and horizontal directions, whereas the interconnects 108a, 108b in FIG. 1 extend only along the vertical direction.

[0125] As a result, the interconnects 108a, 108b in Figure 1 are shorter, which may be beneficial in some applications, while the electrodes 130a, 130b in Figure 2a may be positioned in the device configuration independently of the superconductor layers 102a, 102b, providing greater design flexibility, which may be beneficial in some applications.

[0126] FIG. 2c shows a cross-sectional view of a qubit device 100 according to an embodiment similar to that of FIG.

[0127] In the embodiment of FIG. 2c, an electrical insulating element 114 is disposed between the superconductor layers 102a, 102b and the electrodes 130a, 130b.

[0128] In particular, the electrical insulating element 114 ensures electrical insulation of the electrode 130a from the superconductor layer 102b and of the electrode 130b from the superconductor layer 102a.

[0129] The electrical insulating element 114 is made of silicon or a nitride, carbide, or oxide material. More specifically, it can be made of silicon carbide, silicon nitride, or amorphous silicon.

[0130] The electrical insulating element 114 is used in some embodiments to cap or seal the superconductor layers 102a, 102b, particularly in combination with a substrate 140, described below (FIG. 6). In such embodiments, the electrical insulating element 114 and the substrate 140 together enclose the superconductor layers 102a, 102b (disposed between the electrical insulating element 114 and the substrate 140) in a watertight, moisture-proof, or airtight manner.

[0131] 2c, a spacer material 116 is provided between the first and second superconductor layers 102a, 102b. The spacer material 116 ensures an appropriate distance between the superconductor layers 102a, 102b to form the Josephson junction 120. In some embodiments, the spacer material 116 is comprised of an anisotropic layered material, such as hexagonal boron nitride. A spacer material can also be provided in a qubit device 100 according to any of the other embodiments.

[0132] FIG. 3 shows a top view of qubit device 100 according to some embodiments.

[0133] In a vertical (xz) cross section along line 134, qubit device 100 of Figure 3 is similar to the embodiment of Figure 1 or Figure 2c. In other words, Figure 3 shows a top view of qubit device 100 of Figure 1 or Figure 2c, according to some embodiments.

[0134] 3 shows a particular shape of capacitor 132 in the horizontal x,y plane. Alternative shapes are possible. However, a capacitance of capacitor 132 in the range of 70 to 400 femtofarads has been found to be beneficial.

[0135] The resulting capacitance energy E C =e 2 / 2C (where e is the electron charge) is the typical Josephson energy E of a Josephson junction 120 J is more than 100 times smaller than

[0136] In FIG. 3, area 136 is shown.

[0137] Figures 4a and 4b show qubit device 100 according to another embodiment. Figure 4a is a perspective view, where region 136 corresponds to region 136 in Figure 3. Figure 4b is a cross-sectional view, more specifically, a vertical (x-z) cross-section of region 136 in Figures 3 and 4a, taken along line 134 shown in Figure 3.

[0138] The qubit device 100 of Figures 4a and 4b includes a capacitor 132, a microwave resonator 138, capacitively coupled to one of the electrodes 130a, 130b.

[0139] The resonant frequency of the microwave resonator 138 is in the range of 1 to 15 GHz.

[0140] Microwave resonator 138 is suitable for distributed readout of qubit device 100 .

[0141] The capacitor 132 and the microwave resonator 138 have a thickness in the range of 40 to 80 nm.

[0142] The overall size (length and / or width along the horizontal direction) of quantum bit device 100 or electrical insulating element 114 is each in the range of 0.5 to 1 mm.

[0143] 5a and 5b show details of the second superconductor layer 102b disposed on the first superconductor layer 102a to form the Josephson junction 120. FIG. 5a shows a perspective view, and FIG. 5b shows a top view, of the superconductor layers 102a and 102b and the Josephson junction 120. The detailed descriptions of the superconductor layers 102a and 102b and the Josephson junction 120 in FIGs. 5a and 5b also apply to the superconductor layers 102a and 102b and the Josephson junction 120 of the qubit device 100 according to any of the various embodiments described above.

[0144] The first superconductor layer 102a and the second superconductor layer 102b overlap in a region 110. In other words, the region 110 forms an overlap region 110 (i.e., of the superconductor layers 102a, 102b). More specifically, in the overlap region 110, a first section 112a of the first surface 106a of the first superconductor layer 102a faces a second section 112b of the second surface 106b of the second superconductor layer 102b, and vice versa.

[0145] The superconductor layers 102 a , 102 b are separated by a distance d, specifically at an overlap region 110 .

[0146] The first superconductor material, i.e., the superconductor material of the first superconductor layer 102a, has a first orientation 118a. In Figures 5a and 5b, the first orientation 118a is represented by the arrow 118a in the horizontal plane. In other words, the first orientation 118a is parallel to the first section 112a of the first surface 106a.

[0147] The second superconductor material, ie, the superconductor material of second superconductor layer 102b, has a corresponding second orientation 118b.

[0148] The orientations 118a, 118b may be defined by any one or any combination of the following criteria:

[0149] According to a first definition, the orientations 118a, 118b correspond to the primitive lattice vectors of the first / second superconductor material, such as the respective in-plane primitive lattice vectors, or to the projection of the primitive lattice vectors of the respective (first / second) superconductor material onto a horizontal plane, or to the projection onto the first surface 106a, or to the projection onto the second surface 106b, respectively.

[0150] Alternatively, the orientations 118a, 118b are defined by the crystal facets of the first / second superconductor materials.

[0151] The orientations 118a, 118b are alternatively defined by the reciprocal lattice vectors of the first / second superconductor materials, i.e., by the in-plane reciprocal lattice vectors or by the projection of the reciprocal lattice vectors onto a horizontal plane, or onto the first surface 106a, or onto the second surface 106b, respectively.

[0152] Alternatively, the orientations 118a, 118b are defined by the electron orbitals 114a, 114b or by the crystal momentum of the Bloch states of the first and second superconductor materials. According to some embodiments, the first and second superconductor materials are d-wave superconductors or superconductors with a d-wave superconducting gap, respectively. In this case, the orientations 118a, 118b may be associated with the d-wave electronic spectrum, particularly the d-wave nodal electronic spectrum 114a.

[0153] The first orientation 118a and the second orientation 118b are disposed at an angle θ according to a predetermined angle.

[0154] In particular, when the angle θ is in the range of 38 to 44.9°, the single Cooper pair tunneling E J , i.e., the Josephson energy E J The inventors have investigated the properties of BSCCO, more specifically, Bi2Sr2CaCu2O 8+x Using simulations on the suppressed Josephson energy E JThe same is expected for other d-wave superconductors (or high critical temperature superconductors, respectively, or superconductors containing anisotropic layered superconductor materials, respectively) in which the angle between the fundamental lattice vectors perpendicular to the axis c is about 90°.

[0155] The Josephson energy is E J =I c Critical current I of Josephson junction as Φ0 / 2π c where Φ = h / 2e is the flux quantum.

[0156] In this situation, two Cooper pair tunneling is still possible, and the two Cooper pair tunneling energy E k is the Josephson energy E J The two Cooper pair tunneling terms are E κ cos(2φ), forming a double-well potential. In preferred embodiments, the two corresponding lowest-energy eigenstates are used to provide a two-level system for the qubit device. The energy difference between each of the two eigenstates is small, i.e., within an energy / frequency difference of up to 2 GHz, and in some embodiments up to 1 GHz. Therefore, each eigenstate is said to be quasi-degenerate.

[0157] The degeneracy is coupled with, and thus indicates, a dramatic reduction in dielectric losses and crosstalk between qubit devices (i.e., between the quantum mechanical states of the respective two-level systems). These dielectric losses and crosstalk are the main limitations of conventional transmon qubits. Therefore, the relaxation time of the described qubit device is significantly improved compared to that of conventional qubit devices, for example of the transmon type. Simulations performed by the inventors show that the improvement can reach a factor of 10,000, resulting in a coherence time of up to 1 second.

[0158] FIG. 6 illustrates a method 400 for fabricating qubit device 100.

[0159] In step 402, a Josephson junction 120 between a first superconductor material and a second superconductor material is provided.

[0160] In step 404 , the contact layer 104 is provided separately from the Josephson junction 120 .

[0161] The contact layer 104 includes an electrical insulating element 114, a first interconnect 108a, and a second interconnect 108b. The first interconnect 108a extends through the electrical insulating element 114. The second interconnect 108b extends through the electrical insulating element 114.

[0162] In some embodiments (not shown), the contact layer 104 is provided with additional optional electrical elements disposed thereon, such as a capacitor 132 comprising a first electrode 130a and a second electrode 130b disposed on the electrical insulating element 114, or a microwave resonator 138 disposed on the electrical insulating element 114. In some embodiments having the capacitor 132, the first interconnect 108a is connected to the first electrode 130a and the second interconnect 108b is electrically connected to the second electrode 130b.

[0163] In step 406, a contact layer 104 is disposed on the Josephson junction 120 to form electrical contact between the first interconnect 108a and the first superconductor material and to form electrical contact between the second interconnect 108b and the second superconductor material.

[0164] In some embodiments, in step 402, a substrate 140 is provided.

[0165] In some embodiments, in step 402, the first (and / or second) superconductor material is arranged on the substrate in the form of a first (and / or second) superconductor layer 102a (102b). For this purpose, for example, a previously prepared first (and / or second) superconductor layer 102a (102b) is transferred onto the substrate 140, as will be explained in detail in the context of FIG. 9. Alternatively, the first (or second) superconductor material may be deposited (e.g., reactively) on the substrate 140 from the gas phase or using a vacuum deposition technique such as chemical vapor deposition or molecular beam epitaxy.

[0166] In some embodiments, in step 406, the contact layer 104 is cooled with liquid nitrogen to a temperature below −85° C. (in other words, below a second temperature of −85° C.) and placed on the Josephson junction 120 while at that low temperature. To this end, the contact layer 104 is placed on a PDMS stamp 412, which functions as a transfer device 412. The contact layer 104 and transfer device 412 are cooled 406 below the second temperature. Below the second temperature, the PDMS stamp 412 provides strong adhesion to the contact layer 104.

[0167] The positioned PDMS stamp 412 and contact layer 104 are then placed over and in physical contact with the substrate 140 and the Josephson junctions 120 thereon, such that the contact layer 104 is positioned 406 over the Josephson junctions 120.

[0168] In an optional additional step, the PDMS stamp 412 is removed from the contact layer 104. To this end, the PDMS stamp 412 is heated to a temperature higher than the second temperature, preferably lower than −30° C. In other words, the PDMS stamp 412 is heated to a third temperature higher than the second temperature, preferably lower than −30° C. This reduces the adhesion of the PDMS stamp 412. As a result, the PDMS stamp can be removed, leaving the contact layer 104 disposed above the Josephson junctions 120.

[0169] To avoid thermal damage to the first layer 102a, the temperature of the first layer 102a is kept below 0° C. (the first temperature) while the contact layer 104 is being disposed thereon. This is achieved by keeping the temperature of the PDMS stamp 412 below the first temperature while the PDMS stamp 412 is in contact with the substrate 140 and / or the Josephson junctions 120.

[0170] The decreased adhesion of the PDMS stamp 412 at elevated temperatures (compared to the second temperature of -85°C) is related to the amorphous molecular structure of PDMS, which has a glass transition temperature of approximately -100°C. Consequently, the third temperature is higher than the glass transition temperature of PDMS. The second temperature corresponds to at least the glass transition temperature of PDMS. Above the glass transition temperature, the adhesion of the elastomeric polymer decreases with increasing temperature. In other words, alternative materials, particularly elastomeric polymers, may be used in place of PDMS for the transfer device 412, as long as their glass transition temperatures are below the second temperature (and the third temperature).

[0171] FIG. 7 shows details of step 404 of providing contact layer 104 separate from Josephson junction 120 according to one embodiment.

[0172] According to the illustrated embodiment, the electrical insulating element 114 is provided by depositing a layer of insulating material 114 on a second substrate 500 separate from the substrate 140 .

[0173] An opening 508 is etched through the electrical insulating element 114 .

[0174] A metallization layer 510 is deposited over and into the openings 508, thereby forming interconnects 108a, 108b through the openings 508 and down to the bottom surface of the electrical isolation element 114.

[0175] According to some embodiments (not shown), the metallization layer 510 is also used to form additional electrical components on the electrically insulating element 114, such as the capacitor 132, or the first and second electrodes 130a, 130b, respectively, and / or the microwave resonator 138.

[0176] Next, trenches 514 are formed in the electrical insulating element 114. Each trench 514 extends to the bottom surface of the electrical insulating element 114 or extends all the way through the electrical insulating element 114. The trenches 514 are interrupted laterally by sections of insulating material of the electrical insulating element 114 that act as anchor points (tethers).

[0177] A deeper trench 518 (than trench 514) is then formed to reach the second substrate 500 and / or any sacrificial layer (not shown) between the second substrate 500 and the electrical insulation element 114. In other words, if a separate sacrificial layer is not present, the (top) sacrificial portion of the second substrate 500 serves as the sacrificial layer.

[0178] An isotropic etch is then performed to remove the sacrificial layer and / or sacrificial portion of the second substrate 500 beneath the electrical isolation element 114 in the lateral regions within the deep trench 518. As a result, the resulting contact layer 104 is free-standing relative to the second substrate 500. The resulting contact layer 104 is mechanically flexible as long as the electrical isolation element 114 is sufficiently thin. A thickness of the electrical isolation element 114 in the range of 300-600 nm has been found to be beneficial for this purpose.

[0179] Before or after the isotropic etching, the PDMS stamp 412 is attached (transferred) to the electrical insulating element 114 having the opening 508 (which may now be completely filled with the metallization layer 510). The PDMS stamp 412 is cooled to a temperature below the second temperature, which may be performed before or after transferring the PDMS stamp 412 onto the electrical insulating element 114 having the opening 508.

[0180] The cooled PDMS stamp 412 is removed from the second substrate 500 as it cools. PDMS cooled below the second temperature provides strong adhesion. As a result, upon removal of the PDMS stamp 412 from the second substrate 500, the contact layer 104 lifts off the second substrate 500 because the contact layer 104 is strongly adhered to the PDMS stamp 412.

[0181] As a result, the contact layer 104 remains disposed on the PDMS stamp 412 and is separated from the substrate 500, as shown in the last panel of FIG.

[0182] Optionally, the contact layer 104 is cleaned on its bottom surface (the surface opposite the PDMS stamp 412) using, for example, wet and / or dry cleaning steps such as etching, ion milling, etc. If applied, the cleaning step is preferably performed immediately before placing the contact layer 104 on the substrate 140.

[0183] FIG. 8 shows the contact layer 104 used in the method 400 of FIG. 6 and obtained by the method 404 of FIG.

[0184] The contact layer 104 of Figure 8 is formed with an optional capacitor 132 and with an optional microwave resonator 138. The top view of the contact layer 104 corresponds to the top view of Figure 3 (but without the Josephson junction 120 and the first and second superconductor layers 102a, 102b), and the perspective view of the contact layer 104 corresponds to the perspective view of Figure 4.

[0185] In an alternative embodiment (not shown, see the description in the context of FIG. 7), the contact layer 104 is formed without the capacitor 132 and / or without the microwave resonator 138 .

[0186] FIG. 9 illustrates a process step 402 for providing a Josephson junction 120 between a first superconductor material and a second superconductor material, according to one embodiment.

[0187] This method is optionally applied in the method of FIG. 6 to extend or replace process step 402 thereof.

[0188] In step 602, a superconductor material is provided in the form of a superconductor layer 102a on a substrate 140. The superconductor material is an anisotropic layered material.

[0189] The anisotropic layered material of superconductor layer 102a has a crystalline orientation 620. Crystal orientation 620 corresponds to a direction parallel to covalently bonded atomic layers 126 or to van der Waals gap 128, respectively, as described in the context of FIG. 1. For example, crystalline orientation 620 corresponds to a primitive lattice vector parallel to covalently bonded atomic layers 126 or to van der Waals gap 128, respectively, or corresponds to a projection of the primitive lattice vector of the anisotropic layered material onto covalently bonded atomic layers 126 or onto van der Waals gap 128, respectively.

[0190] In step 604, a transfer device 412 in the form of a PDMS stamp 412 is attached (transferred) to the superconductor layer 102a and substrate 140, similar to the description of attaching the PDMS stamp 412 to the electrical insulating element 114 in FIG.

[0191] The PDMS stamp 412 is cooled to a temperature below the second temperature mentioned above, which may be performed before or after transferring the PDMS stamp 412 onto the superconductor layer 102 a and substrate 140 .

[0192] In step 606, the cooled PDMS stamp 412 is removed from the substrate 140 while it is cooling. PDMS cooled below the second temperature provides a strong bond. As a result, when the PDMS stamp 412 is removed from the substrate 140, a portion of the superconductor layer 102a adheres to the PDMS stamp 412. Another portion of the superconductor layer 102a remains on the substrate 140. In other words, the superconductor layer 102a is cleaved.

[0193] Cleavage of the anisotropic layered material, and therefore the superconductor layer 102a, typically occurs along the van der Waals gap 128 between the covalently bonded atomic layers 126 of the anisotropic layered material, such that the surfaces of the newly prepared superconductor layers 102a, 102b upon cleavage are parallel to the covalently bonded atomic layers 126 and / or to the crystallographic planes of the layered material, respectively.

[0194] In step 608, the portion of the superconductor layer 102a that remains on the substrate 140 forms the first superconductor layer 102a. Hereinafter, only this remaining superconductor layer 102a will be referred to as the first superconductor layer 102a.

[0195] The portions of superconductor layer 102a adhered to PDMS stamp 412 form second superconductor layer 102b. According to the illustrated embodiment, second superconductor layer 102b is made of the same material as first superconductor layer 102a. However, by applying the process described above in the context of steps 602, 604, and 606 to a different superconductor material, second superconductor layer 102b made of a different superconductor material can be provided. The portions of the different superconductor material adhered to the respective PDMS stamps are then used as second superconductor layer 102b.

[0196] Still referring to step 608, the PDMS stamp 412 with the second superconductor layer 102b adhered thereto is then oriented and positioned relative to the substrate 140 and the first superconductor layer 102a.

[0197] According to the illustrated embodiment, the positioning and orientation includes a rotation 610 about an axis 612 perpendicular to the second superconductor layer 102b, rotating (twisting) the crystalline orientation 622 of the second superconductor layer 102b relative to the crystalline orientation 620 of the first superconductor layer 102a.

[0198] Referring to step 614, the PDMS stamp 412 with the second superconductor layer 102b attached thereto is transferred onto the first superconductor layer 102a and the substrate 140 according to the position and orientation described in the context of step 608.

[0199] In particular, the PDMS stamp 412 is transferred onto the substrate 140 such that the first superconductor layer 102a and the second superconductor layer 102b overlap to form the overlap region 110 and / or Josephson junction 120 described above.

[0200] Referring to step 616, to reduce the adhesion of the PDMS stamp 412, the PDMS stamp 412 is heated to a temperature above the second temperature, preferably above the third temperature mentioned above.

[0201] The PDMS stamp 412 is then removed from the substrate 140 .

[0202] Due to the degradation of adhesion of the PDMS at a second temperature, preferably above the third temperature, the PDMS stamp 412 releases the first and second superconductor layers 102 a, 102 b, which remain on the substrate 140.

[0203] In step 618, providing 402 the Josephson junction 120 is completed.

[0204] 10 and 11 illustrate two different embodiments of methods for changing the state of qubit device 100.

[0205] Before going into the details of the individual embodiments, features common to both embodiments will be described.

[0206] In general, qubits implement quantum mechanical two-level systems. Ideally, quantum mechanical two-level systems result in exactly two distinguishable quantum states. In practice, quantum mechanical two-level systems typically have many distinguishable quantum states.

[0207] Qubit device 100 implements a respective quantum mechanical two-level system.

[0208] 10 and 11 show four quantum states of the quantum mechanical two-level system or qubit device 100: the ground state |0>, the first excited state |1>, the second excited state |2>, and the third excited state |3>, respectively.

[0209] The target state of the quantum bit device 100 refers to a superposition of the ground state |0> and the first excited state |1>.

[0210] Microwaves 702, 704, and 706 having three different frequencies are coupled into qubit device 100 to change the state of the qubit device.

[0211] The first microwave frequency of the first microwave 702 is related to the energy difference between the third excited state |3> and the ground state |0>. The first microwave frequency is in the range of 7 GHz to 15 GHz.

[0212] The second microwave frequency of the second microwave 704 is related to the energy difference between the third excited state |3> and the second excited state |2>. The second microwave frequency is in the range of 1 GHz to 2 GHz.

[0213] The third microwave frequency of the third microwave 706 is related to the energy difference between the second excited state |2> and the first excited state |1>. The third microwave frequency is in the range of 6 GHz to 13 GHz.

[0214] Microwaves 702, 704, and 706 drive the transition of a quantum mechanical two-level system, for example, from a ground state |0> to a superposition of the ground state |0> and a first excited state |1>. The transition can occur resonantly (FIG. 10) or non-resonantly (FIG. 11) via coupling to a second excited state |2> and a third excited state |3>.

[0215] After each alteration of the state of the quantum mechanical two-level system or qubit device 100, the altered state is analyzed using distributed readout, for example, using the microwave resonator 138 described above.

[0216] 10 illustrates a resonant transition where at least one, at least two, or all of the first, second, and third microwave frequencies are matched to within 0.01% of their respective energy difference.

[0217] 10 , the first microwave 702 and the third microwave 706 are initially coupled to the qubit device as π pulses, thereby shifting the occupation and phase of the ground state |0> and the first excited state |1> to the second excited state |2> and the third excited state |3>. The second microwave 704 is then coupled to the qubit device as a control pulse to define a superposition of the second excited state |2> and the third excited state |3> required by the application using the qubit device. The first microwave 702 and the third microwave 706 are then coupled to the qubit device as π pulses, thereby shifting the superposition of the second excited state |2> and the third excited state |3> to the ground state |0> and the first excited state |1>.

[0218] 11 illustrates a non-resonant transition 708. In this case, at least one, at least two, or all of the first, second, and third microwave frequencies are mismatched by a respective energy difference, e.g., by at least 0.01% and / or at most 5% of the respective energy difference. In a corresponding embodiment, microwaves 702, 704, and 706 are synchronously coupled to qubit device 100. The induced transition generally corresponds to that in the resonant case, but is a single non-resonant Raman-type multi-photon transition. The intensity of microwaves 702, 704, and 706 is generally higher in the non-resonant case of FIG. 11 than in the resonant case of FIG. 10. [Explanation of symbols]

[0219] 100 qubit device 102a, 102b First and second superconductor layers 126 Covalently bonded atomic layers 128 Van der Waals Gap cc axis 120 Josephson junction 132 capacitor 130a, 130b First and second electrodes 124 areas 124' Close-up of area 124 108a, 108b First and second interconnection portions 2B First fixing element 114 Electrical insulating elements 140 Base material 118a, 118b First and second orientations parallel to the covalently bonded atomic layers 114a,114b electron d orbital 106a, 116b Surfaces of the first and second superconductor materials 110 Overlapping area 112a, 112b Opposite surfaces of the first and second superconductor materials in the Josephson junction / overlap region d Distance between the first and second superconductor materials in a Josephson junction 134 Lines / Planes 136 areas 138 Microwave Resonator 412 Transfer device, PDMS stamp 602 Providing a first superconductor material on a substrate 604 Attaching the PDMS stamp to the substrate with the first superconductor material 606 Cleaving the first superconductor material to produce a first superconductor layer and a second superconductor layer 608 Align and position the second superconductor layer placed on the PDMS stamp 610 rotations 612 axes 614 Attach the PDMS stamp and the second superconductor layer disposed thereon to the substrate with the first superconductor layer. 616 Removing the PDMS stamp 618 Substrate with first and second superconductor layers 620,622 Crystal orientation of the first and second superconductor materials 702, 704, 706 First, second and third microwaves 708 Non-resonant / Raman transitions

Claims

1. A qubit device (100), comprising: a first superconductor layer (102a) comprising a first superconductor material, the first superconductor material being a first anisotropic layered material having covalently bonded atomic layers (126) and a first c-axis perpendicular to the covalently bonded atomic layers (126) of the first superconductor material; a second superconductor layer (102b) comprising a second superconductor material, the second superconductor material being a second anisotropic layered material having covalently bonded atomic layers (126) and a second c-axis perpendicular to the covalently bonded atomic layers (126) of the second superconductor material; Equipped with the second superconductor layer (102b) is disposed on the first superconductor layer (102a) to form a Josephson junction (120) between the first superconductor material and the second superconductor material; the first c-axis and the second c-axis are aligned with each other at the Josephson junction (120); the aligned first and second c-axes at the Josephson junction (120) intersect both the first superconductor layer (102a) and the second superconductor layer (102b); The quantum bit device (100) a capacitor (132) comprising a first electrode (130a) and a second electrode (130b); a first interconnection portion (108a) electrically connecting the first electrode (130a) and the first superconductor layer (102a) from above; a second interconnection portion (108b) electrically connecting the second electrode (130b) and the second superconductor layer (102b) from above; an electrically insulating element (114) on which at least a section of the first interconnection portion (108a) is disposed and on which at least a section of the second interconnection portion (108b) is disposed; Further provided with the capacitor (132) is positioned at a vertical position above the vertical positions of both the first superconductor layer (102a) and the second superconductor layer (102b); A quantum bit device (100).

2. The electrically insulating element (114) comprises or is composed of silicon carbide, silicon nitride, or amorphous silicon. The qubit device (100) of claim 1.

3. Further comprising a sealant for the Josephson junction (120), the sealant comprising the electrical insulating element (114). The qubit device (100) of claim 2.

4. the first superconductor material comprises a first orientation (118a, 620) parallel to the covalently bonded atomic layers (126) of the first superconductor material, the second superconductor material comprises a second orientation (118b, 622) parallel to the covalently bonded atomic layers (126) of the second superconductor material, and the first and second superconductor materials at the Josephson junction (120) are arranged at an angle (θ) between the first orientation (118a, 620) and the second orientation (118b, 622) corresponding to a predetermined angle; The qubit device (100) of claim 1 or 2.

5. the first and second superconductor materials in the Josephson junction (120) are arranged such that an angle (θ) between the first orientation (118a, 620) and the second orientation (118b, 622) is in the range of 38 to 44.9 degrees; The qubit device (100) of claim 4.

6. At least one of the first superconductor material and the second superconductor material contains oxygen or a chalcogenide. The qubit device (100) of claim 1 or 2.

7. Further comprising a microwave resonator (138); The microwave resonator (138) is capacitively coupled to the capacitor (132). The qubit device (100) of claim 1 or 2.

8. at least one of the first electrode (130a), the second electrode (130b), the first interconnect (108a), and the second interconnect (108b) comprises or is composed of a superconductor material; The qubit device (100) of claim 1 or 2.

9. A method (400) for fabricating a qubit device (100), the method comprising: Providing (402) a Josephson junction (120) between a first superconductor material and a second superconductor material, comprising: the first superconductor material is a first anisotropic layered material having covalently bonded atomic layers (126) and a first c-axis perpendicular to the covalently bonded atomic layers (126) of the first superconductor material; the second superconductor material is a second anisotropic layered material having covalently bonded atomic layers (126) and a second c-axis perpendicular to the covalently bonded atomic layers (126) of the second superconductor material; a second superconductor layer (102b) disposed on the first superconductor layer (102a) to form a Josephson junction (120) between the first superconductor material and the second superconductor material; a step (402) in which the first c-axis and the second c-axis are aligned with each other at the Josephson junction (120); Providing (404) a contact layer (104) separate from the Josephson junction (120), the contact layer (104) comprising: an electrical insulating element (114); a first interconnect (108a) extending through said electrical insulating element (114); a second interconnect (108b) extending through said electrical insulating element (114); a capacitor (132) comprising a first electrode (130a) and a second electrode (130b); Step (404) comprising: and disposing the contact layer (104) on the Josephson junction (120) to form electrical contact between the first interconnect (108a) and the first superconductor material and to form electrical contact between the second interconnect (108b) and the second superconductor material, such that the first interconnect (108a) electrically connects the first electrode (130a) and the first superconductor layer (102a), the second interconnect (108b) electrically connects the second electrode (130b) and the second superconductor layer (102b), and the capacitor (132) is disposed at a vertical position above the vertical positions of both the first superconductor layer (102a) comprising the first superconductor material and the second superconductor layer (102b) comprising the second superconductor material. method.

10. and cooling the Josephson junction (120) to a temperature lower than a first temperature while the contact layer (104) is disposed on the Josephson junction (120), wherein the first temperature is 0°C, or 250K, or 230K, or 210K, or 190K, or 170K, or 150K, or 130K.

10. The method of claim 9.

11. the step of disposing the contact layer (104) on the Josephson junction (120) comprises: attaching a transfer device (412) to the contact layer (104); cooling the transfer device (412) to a temperature below a second temperature to attach the transfer device (412) to the contact layer (104); Including, the transfer device (412) is adapted to provide strong adhesion when the temperature of the transfer device (412) is lower than the second temperature and to provide weak adhesion when the temperature of the transfer device (412) is higher than the second temperature; The method of claim 10.

12. disposing the contact layer (104) on the Josephson junction (120) includes releasing the transfer device (412) from the contact layer (104), and releasing the transfer device (412) from the contact layer (104) includes heating the transfer device (412) to a temperature between the second temperature and the first temperature. The method of claim 11.

13. the first superconductor material is a first anisotropic layered material having covalently bonded atomic layers (126) and a first c-axis perpendicular to the covalently bonded atomic layers (126) of the first superconductor material; the second superconductor material is a second anisotropic layered material having covalently bonded atomic layers (126) and a second c-axis perpendicular to the covalently bonded atomic layers (126) of the second superconductor material; The Josephson junction (120) is provided such that the first c-axis and the second c-axis are aligned with one another at the Josephson junction (120), and such that both the first c-axis and the second c-axis intersect both the first superconductor material and the second superconductor material at the Josephson junction (120). The method of claim 10.

14. providing the Josephson junction (120) between the first superconductor material and the second superconductor material; disposing a first superconductor layer (102a) of said first anisotropic layered material on a substrate (140); disposing a second superconductor layer (102b) of the second anisotropic layered material on the first superconductor layer (102a) to create the Josephson junction (120); Including, The method of claim 13.

15. A contact layer (104) for fabricating a qubit device (100), the contact layer (104) comprising: an electrical insulating element (114); a capacitor (132) having a first electrode (130a) and a second electrode (130b) disposed on the electrically insulating element (114); a first interconnect (108a) electrically connected to the first electrode (130a) and extending through the electrical insulating element (114) from a bottom surface of the electrical insulating element (114) to a top surface of the electrical insulating element (114); a second interconnect (108b) electrically connected to the second electrode (130b) and extending through the electrical insulating element (114) from the bottom surface of the electrical insulating element (114) to the top surface of the electrical insulating element (114); Equipped with the first interconnect (108a) is electrically isolated from the second interconnect (108b); each of the first electrode (130a), the second electrode (130b), the first interconnect (108a), and the second interconnect (108b) comprises a respective superconductor material; A contact layer (104).

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