Chip Package, Electronic Device and Method (Fatigue Damage Durable Electronic Package)

Abstract

To provide a chip package that reduces temperature-induced stresses.SOLUTION: A chip package 100 comprises a chip 102 having a chip temperature sensor 108. The chip temperature sensor is configured to measure a temperature of the chip in a localized area around the chip temperature sensor. The chip package also includes a chip carrier 104 coupled to the chip via a plurality of interconnections 106. The chip carrier includes a carrier temperature sensor 112 vertically aligned with the chip temperature sensor. The carrier temperature sensor is configured to measure a temperature of the chip carrier in a localized area around the carrier temperature sensor. The chip carrier further includes a localized heater element 114 located near the carrier temperature sensor and configured to generate heat in response to a detected difference based on comparison of the temperature of the chip and the temperature of the chip carrier. The localized heater element adjusts the detected difference in the localized area around the chip temperature sensor.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Electronic packages, also referred to herein as chip packages, are typically formed from subcomponents such as chips, laminates, interconnects, and lids. These subcomponents are often formed from different materials with different coefficients of thermal expansion (CTE). During operation of the electronic package, the chip dissipates heat, causing different temperatures in the package subcomponents. The different temperatures and different thermal expansion coefficients of the materials can lead to differential expansion in the package components, causing warpage and stress. Stresses can be greatest near the corners of the chip. Repeated cycling of temperature can lead to fatigue failure of the components. The interconnects between the chip and the chip carrier are particularly susceptible to fatigue failure. Summary of the Invention [Problem to be solved by the invention]

[0002] Aspects of the present disclosure may include chip packages, electronic devices, and methods for reducing temperature-induced stress in chip packages. [Means for solving the problem]

[0003] An example of a chip package includes a chip having a first temperature sensor disposed on a back-end level of the chip. The first temperature sensor is configured to measure a first temperature of the chip in a localized area around the first temperature sensor. The chip package also includes a chip carrier coupled to the chip via a plurality of solder connections. The chip carrier includes a second temperature sensor vertically aligned with the first temperature sensor on the chip. The second temperature sensor is configured to measure a second temperature of the chip carrier in a localized area around the second temperature sensor. The chip carrier further includes a local heating element disposed near the second temperature sensor and configured to generate heat in response to a difference detected based on a comparison between the first temperature and the second temperature, such that the detected difference is regulated in the localized area around the first temperature sensor. [Brief explanation of the drawings]

[0004] Example embodiments will be described with additional specificity and detail through the use of the accompanying drawings, with the understanding that the drawings illustrate example embodiments only and therefore should not be construed as limiting the scope.

[0005] [Figure 1A] FIG. 1 is a high-level block diagram of a cross-sectional view of an exemplary embodiment of an improved chip package.

[0006] [Figure 1B] FIG. 1B is a high-level block diagram of a top view of an exemplary embodiment of the improved chip package in FIG. 1A.

[0007] [Figure 2] FIG. 2 is a high-level block diagram of a cross-sectional view of another exemplary embodiment of an improved chip package.

[0008] [Figure 3] FIG. 1 is a high-level block diagram of an exemplary electronic device.

[0009] [Figure 4]FIG. 2 is a circuit diagram of one embodiment of a temperature sensor.

[0010] [Figure 5] 1 is a flow chart illustrating one embodiment of an exemplary method for reducing temperature-induced stress in a chip package.

[0011] In accordance with common practice, the various illustrated features are not drawn to scale, emphasizing specific features relevant to the exemplary embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which are shown, by way of illustration, specific exemplary embodiments. However, it is to be understood that other embodiments may be used and that logical, mechanical, and electrical changes may be made. Furthermore, the methods illustrated in the drawings and the specification should not be construed as limiting the order in which individual steps may be performed. Accordingly, the following detailed description is not to be taken in a limiting sense.

[0013] FIG. 1A is a high-level block diagram of a cross-section of an exemplary embodiment of an improved chip package 100. FIG. 1B is a high-level block diagram of a top view of the exemplary embodiment of the improved chip package 100. It should be understood that the improved chip package 100 is a simplified diagram, and that an improved chip package according to embodiments described herein may include other components not shown in FIGS. 1A and 1B. For example, FIG. 2 shows a more detailed cross-sectional view of an improved chip package 200.

[0014] The improved chip package 100 includes a chip 102 physically attached to a chip carrier 104 via connections 106 (also referred to herein as interconnections or cross-connects). The interconnections 106 are implemented as a Controlled Collapse Chip Connection (also known as a C4 connection) using multiple solder balls, as known to those skilled in the art. It should also be understood that the chip 102 includes multiple electronic circuits, such as resistors, transistors, capacitors, inductors, or diodes, or combinations thereof, which are not shown in FIGS. 1A or 1B for ease of illustration and description. As known to those skilled in the art, the electronic circuits may include analog or digital circuits, or both. During operation, current flows through the multiple electronic circuits, which can cause temperature variations within the chip 102 at locations where the current flows within the chip 102.

[0015] In some embodiments, the chip 102 is constructed of a first material having a first coefficient of thermal expansion (CTE), and the chip carrier 104 is constructed of a second material having a second CTE, where the second CTE is different from the first CTE. For example, in some such embodiments, the chip 102 is constructed of a silicon material having a CTE of approximately 2.6 parts per million (ppm) per degree Celsius (C), and the chip carrier 104 is constructed of one or more organic laminate materials having a composite CTE of approximately 13-17 ppm / C. In other embodiments, the chip carrier 104 may be constructed of a material having a CTE closer to the CTE of the chip 102. For example, in some embodiments, the chip carrier 104 may be constructed of a ceramic material having a CTE of approximately 3 ppm / C.

[0016] As described above, temperature variations may occur in the chip 102 and the chip carrier 104 during assembly and / or operation of the chip 102. The temperature variations are not uniform throughout the enhanced chip package 100. For example, the temperature in the chip carrier 104 may be different from the temperature of the chip 102. Also, different portions of the chip 102 and / or the chip carrier 104 may be at different temperatures than other portions of the chip 102 and / or the chip carrier 104, respectively. For example, when more current flows through a particular portion of the chip 102 than through other portions, the temperature of the chip 102 varies based on the location of the current flow. Also, the temperature of the chip 102 may be different from the temperature of the chip carrier 104 due to the current flowing through the chip 102.

[0017] In conventional chip packages, these temperature variations cause stresses on the components of the conventional chip package, for example, due to CTE mismatches between the components. As the temperature of the package components cycles up and down, the stresses induced in the package components may also cycle up and down, which can lead to fatigue failure of the package components. The interconnects 106 between the chip 102 and the chip carrier 104, which may be formed of a solder material, are particularly vulnerable to fatigue failure.

[0018] Conventional techniques for attempting to minimize stress in package interconnects may include attempting to minimize component CTE mismatch through material selection, locally stiffening the substrate or chip carrier, or using epoxy underfill material around the interconnects to reduce shear stress at the corners of the chip, or a combination of these.

[0019] Unlike the prior art, embodiments of the improved chip package 100 reduce stress in the interconnects 106 by responding to and adjusting to temperature variations in the components of the chip package 100. In particular, one or more chip temperature sensors 108 and one or more chip heating elements 110 are included on the chip 102. Also, one or more carrier temperature sensors 112 and one or more carrier heating elements 114 are included on the chip carrier 104. The one or more carrier temperature sensors 112 are vertically aligned with each of the one or more chip temperature sensors 108. By vertically aligning the carrier temperature sensors 112 with their respective chip temperature sensors 108, local temperature variations across the interconnects 106 may be measured at specific locations within the improved chip package 100.

[0020] 1A and 1B, the chip temperature sensors 108 are positioned at the corners of the chip 102. Accordingly, to vertically align the carrier temperature sensors 112 with the chip temperature sensors 108, the carrier temperature sensors 112 are positioned on the chip carrier 104 at locations corresponding to the corners of the chip 102. In this manner, the sensors may be positioned at interconnect locations that are expected to experience more stress. For example, the corners of the chip 102 often experience more stress than the center of the chip 102. However, it should be understood that the embodiments described herein are not limited to positioning the sensors 108 / 112 at the corners of the chip 102. For example, in other embodiments, the sensors 108 / 112 may be positioned at locations corresponding to the edges of the chip 102.

[0021] 1A and 1B, the chip heating elements 110 are also disposed at the corners of the chip 102. Similarly, in this embodiment, the carrier heating elements 114 are also vertically aligned with the chip heating elements 110 and are disposed at positions corresponding to the corners of the chip 102. However, it should be understood that in some embodiments, the chip heating elements 110 are omitted and only the chip temperature sensors 108 are included on the chip 102. In some such embodiments, the carrier heating elements 114 are disposed near the respective carrier temperature sensors 112, which are vertically aligned with the chip temperature sensors 108. The carrier 104 in this example also includes a central core 116, a front-side level or upper portion (also referred to as the FC level) 118, and a bottom-side level or lower portion (also referred to as the BC level) 120. In this example, the carrier temperature sensors 112 and the carrier heating elements 114 are disposed in the FC level 118, which is closer to the chip 102, and the chip temperature sensors 108 are embedded in the back-end of the chip (BEOL) level.

[0022] The chip temperature sensors 108 are configured to measure the temperature of the chip 102 at their respective locations, such as during assembly and / or operation of the chip 102. Similarly, the carrier temperature sensors 112 are configured to measure the temperature of the carrier 106 at their respective locations, such as during assembly and / or operation of the chip 102.

[0023] Thus, the improved chip package 100 is configured to enable measurement of the value of the local temperature difference between the chip 102 and the chip carrier 104. As used herein, the terms local or localized refer to a subportion of the chip 102 and a corresponding area of ​​the chip carrier 104 in the area around the temperature sensor 108 / 112, where the subportion is smaller than the entire chip 102 or chip carrier 104.

[0024] Additionally, the improved chip package 100 is configured to reduce stresses acting on the interconnects 106 of the improved chip package 100 by selectively activating local heating elements 110 / 114 to adjust the local temperature of the chip 102 and / or the chip carrier 104. For example, if a particular pair of vertically aligned temperature sensors 108 / 112 identifies a temperature difference between the temperature of a subportion of the chip 102 and the temperature of a corresponding portion of the chip carrier 104 in that localized region as being outside a predetermined range, the heating element 114 and / or the heating element 110 in that localized region may be activated to adjust the temperature of the chip carrier 104 and / or the chip 102 until the measured temperature difference is brought within the predetermined range. Once the temperature difference is within the predetermined range, the heating element 114 and / or the heating element 110 may be deactivated or turned off. In some embodiments, minimizing the temperature difference is desirable. Thus, in such embodiments, the predetermined range may be a range around zero. In other embodiments, it may be necessary to increase the localized temperature difference to reduce stress on the interconnect. In some such embodiments, the predetermined range may be a range around a non-zero value, or may be a range that excludes values ​​around zero. The specific range used will vary based on the implementation details of the improved chip package.

[0025] In this manner, a control loop is employed to reduce stress acting on the interconnects 106. It should be appreciated that by employing multiple localized, vertically aligned temperature sensors 108 / 112 and heating elements 110 / 114, the improved chip package can reduce both vertical temperature variation induced stress and lateral temperature variation induced stress. That is, the improved chip package 100 can distinguish between temperature variations occurring in both the vertical direction (e.g., between the chip 102 and the chip carrier 104) and lateral direction (e.g., between different portions of the chip 102 and / or different portions of the chip carrier 104).

[0026] In some embodiments, the enhanced chip package 100 is configured to adjust for the measured temperature difference, such as when the CTE of the chip 102 closely matches the CTE of the chip carrier 104. In other embodiments, the enhanced chip package 100 is configured to modify the measured temperatures to adjust for the difference between the products of the measured temperatures and the respective corresponding CTE values, such as when the CTE of the chip 102 does not closely match the CTE of the chip carrier 104.

[0027] The comparison of temperature values, the modification of temperature values, and the control of the heating elements 110 / 114 may be implemented using analog or digital electronic circuitry, or both, coupled to the temperature sensors 108 / 112 and the heating elements 110 / 114. For example, but not limited to, transistors may be interconnected to form logic gates, such as AND gates, OR gates, XOR gates, etc. In addition to comparing the outputs of the temperature sensors 108 / 112, the logic gates may perform the above functions, such as controlling current to the heating elements 110 / 114 to activate / deactivate the heating elements 110 / 114 based on the comparison of the outputs of the temperature sensors 108 / 112. Thus, as described above, the enhanced chip package 100 is configured to dynamically reduce temperature-induced stress on the components of the enhanced chip package 100 by using localized, vertically aligned temperature sensors 108 / 112 and corresponding heating elements 110 / 114.

[0028] It should also be understood that the embodiments of FIGS. 1A and 1B are shown by way of example only, and that different embodiments may be implemented differently. For example, in some embodiments, the heating element 110 on the chip 102 is omitted because the chip 102 typically has a higher temperature during operation than the chip carrier 104 due to the current flowing through the circuitry on the chip 102. Furthermore, it should be understood that the relative sizes of the components of the improved package 100 shown in FIGS. 1A and 1B are shown for illustrative purposes only and should not be construed as limiting. In particular, it should be understood that a variety of component sizes may be used. For example, in some embodiments, the chip 102 is approximately 25 mm by 29 mm, and the chip carrier 104 is approximately 68.5 mm by 68.5 mm. However, it should be understood that other sizes of the chip 102 and chip carrier 104 may be used in other embodiments.

[0029] Furthermore, in some embodiments, the heating element 110 / 114 is 0.5 mm x 0.5 mm. In other embodiments, larger or smaller sized heating elements 110 / 114 are used, such as, but not limited to, 1 mm x 1 mm or 20 μm x 20 μm. The heating elements 110 / 114 may be implemented as resistors that generate heat when a current is applied to the resistor. In such embodiments, the required resistance of the heating elements 110 / 114 varies based on various factors, such as the size of the heating elements 110 / 114, the voltage level used, and the amount of power to be dissipated. For example, in one embodiment using a 1.2 V voltage and a 0.5 mm x 0.5 mm heating element, the heating element is selected to have a resistance of approximately 50-100 ohms. In another embodiment using a 1.2 V voltage and a 1 mm x 1 mm heating element, the heating element is selected to have a resistance of approximately 30-60 ohms. Thus, the size and resistivity of the heating elements 110 / 114 will vary based on the particular implementation.

[0030] As noted above, the enhanced chip package 100 of Figures 1A and 1B is a high-level block diagram for purposes of illustration, and other components may be included. An example enhanced chip package 200 showing additional components is displayed in Figure 2. While the enhanced chip package 200 includes more components than the enhanced chip package 100, it should be understood that the enhanced chip package 200 is also simplified for purposes of illustration and explanation, and that additional elements may be included, omitted, or both, in implementations of the embodiments described herein.

[0031] The improved chip package 200 includes a chip 202, a chip carrier 204, and interconnects 206 similar to the chip 102, chip carrier 104, and interconnects 106 described above. The improved chip package 200 also includes one or more chip temperature sensors 208, one or more chip heating elements 210, one or more carrier temperature sensors 212 vertically aligned with the one or more chip temperature sensors 208, and one or more carrier heating elements 214 similar to the chip temperature sensor 108, chip heating element 110, carrier temperature sensor 112, and carrier heating element 114 described above.

[0032] The improved chip package 200 shown in FIG. 2 also includes a lid 216 connected to the chip carrier 204, covering the chip 202. In particular, as known to those skilled in the art, the lid 216 is separated from the chip 202 via a thermal interface material (TIM) 218, and the lid 216 is connected to the chip carrier 204 via a seal 220. As known to those skilled in the art, the specific materials used for the TIM 218 and the seal 220 will vary based on the implementation of the chip package 200. FIG. 2 also shows an underfill material 222 around the interconnects 206. Suitable materials and uses for the underfill material 222 are known to those skilled in the art.

[0033] The example shown in FIG. 2 also shows the enhanced chip package 200 coupled to a printed circuit board (PCB) 224 via a solder ball grid array (BGA) 226. Coupling a chip package to a PCB via solder balls is known to those skilled in the art and will not be described in further detail herein. The example of FIG. 2 also includes a PCB cutout 228, which provides space for additional backside components, such as a capacitor 230, coupled to the bottom-side level of the chip carrier 204. Thus, the enhanced chip package 200 may be integrated with one or more components of an electronic device. Other examples of interconnections of a chip package to a PCB are a land grid array (LGA) or a pin grid array (PGA).

[0034] Such components may include, but are not limited to, multi-core processors, application specific integrated circuits (ASICs), and memory modules such as dynamic random access memory (DRAM) chips. For example, FIG. 3 is a high-level block diagram illustrating one embodiment of an electronic device 301 using an improved chip package. The electronic device 301 may be implemented as any suitable electronic device, such as, but not limited to, a personal computer, a server, a mobile device, a tablet, etc. As described above, by using one or more improved chip packages, the operational life of the components of the electronic device may be increased due to the ability of the improved chip package to reduce temperature-induced stresses, such as corner stresses, which in turn can reduce cyclic fatigue failure of the interconnects.

[0035] 3, electronic device 301 includes PCB 324 having coupled thereto processor package 331 and memory module 332. Processor package 331 is implemented using an enhanced chip package, such as enhanced chip package 100 described above. Similarly, memory module 332 is implemented using an enhanced chip package, such as enhanced chip package 100. PCB 324 also includes a number of connectors 334 configured to connect to one or more additional components, such as a power supply 336 and one or more input / output devices 338. In some embodiments, power supply 336 is configured to provide the power necessary to supply electrical current to heating elements and temperature sensors, such as heating elements 110 / 114 and temperature sensors 108 / 112, to reduce temperature-induced stress.

[0036] FIG. 4 is a circuit diagram illustrating one embodiment of a temperature sensor 405 that may be used to implement the temperature sensors 108 / 112 described above. The temperature sensor 405 is a pn-junction-based on-chip temperature sensor diode (OCTS). As described above, in some embodiments, the power supply 336 may provide a supply voltage VDD. As known to those skilled in the art, in a diode, when the ratio of currents I1 and I2 is constant, the differential output voltage VEE is proportional to temperature. Those skilled in the art are familiar with OCTSs, and further details of the operation of the OCTS 405 will not be described herein. It should be understood that the OCTS 405 shown in FIG. 4 is provided for illustrative purposes only, and that in other embodiments, other temperature sensors, such as, but not limited to, a metal wire resistance temperature detector (RTD) and / or a thermistor, may be used.

[0037] 5 is a flow chart illustrating one embodiment of a method 500 for reducing temperature-induced stress in interconnects in a chip package, such as the improved chip package 100. At 502, a local temperature of a portion of a chip is measured using a local temperature sensor. In some embodiments, the temperature sensor may be located at a corner of the chip. In other embodiments, the temperature sensor may be located along an edge of the chip. Furthermore, in some embodiments, multiple temperature sensors are included, such as at each corner of the chip, as described above. Also, in some embodiments, one or more temperature sensors are embedded in a back-end of line (BEOL) level of the chip.

[0038] At 504, the local temperature of a portion of the chip carrier is measured using a local temperature sensor disposed on the chip carrier. As described above, the temperature sensor on the chip carrier is vertically aligned with the temperature sensor on the chip. Thus, the temperature sensor on the chip carrier may be located, for example, at a corner of the chip or at a corresponding location along an edge of the chip. Also, as described above, in some embodiments, the temperature sensor on the chip carrier is embedded in the front side level of the chip carrier. The measured temperature values ​​from the multiple temperature sensors may be combined in a suitable mathematical algorithm, for example, all measurements may be averaged.

[0039] At 506, the measured local temperature of the chip is compared to the measured local temperature of the chip carrier. For example, in some embodiments, a difference in the measured temperatures may be calculated. At 508, as described above, it is determined whether the difference based on the comparison of the measured local temperature of the chip to the measured local temperature of the chip carrier is within a predetermined range. In some embodiments, the difference may be the difference in the measured temperatures. In other embodiments, the difference may be the difference in the product of the respective CTEs and the measured temperatures. Furthermore, in some embodiments, the range may be set to zero so that any detected difference is outside the range.

[0040] If the difference is within range at 508, the local heating element is deactivated at 510, if previously activated. Method 500 then returns to 502 to continue measuring the local temperatures of the chip and chip carrier. As described above, if the difference is not within the predetermined range at 508, the local heating element is activated at 512 based on the comparison. For example, if the comparison determines that the chip carrier is cooler than the chip, the local heating element of the chip carrier may be activated to bring the measured difference within the predetermined range. As described above, the heating element may be activated by providing a current to the heating element. Similarly, the heating element may be deactivated by removing the current to the heating element. Method 500 then returns to 502 to continue measuring the local temperatures of the chip and chip carrier.

[0041] 5 may be implemented differently. For example, measuring the local temperature at 502 may occur simultaneously with measuring the local temperature at 504. Furthermore, it should be understood that in some embodiments, method 500 may be implemented using analog or digital circuitry or both implemented on a chip. In other embodiments, method 500 may be implemented in firmware embedded on a chip, where measurements are provided to circuitry configured to process instructions to act on the measured temperature values.

[0042] It should also be understood that method 500 may be performed independently for each of multiple pairs of vertically aligned temperature sensors. For example, an improved chip package may include multiple temperature sensors on a chip and multiple corresponding temperature sensors on a chip carrier. Thus, method 500 may be performed for each pair of vertically aligned temperature sensors to provide local temperature regulation to reduce local temperature-induced stress. Thus, the embodiments described herein can reduce temperature-induced stress through the novel use of vertically aligned local temperature sensors and heating elements, which may improve the operational life of electronic components by reducing interconnect failures of electronic components due to temperature-induced stress.

[0043] Although specific embodiments have been shown and described herein, those skilled in the art will recognize that any configuration which is intended to achieve the same purpose may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.

Claims

1. A chip package comprising: a chip having a plurality of first temperature sensors disposed at a plurality of corners and / or a plurality of edges of the chip, the plurality of first temperature sensors being configured to measure a plurality of first temperatures of the chip in a plurality of first localized regions around the plurality of first temperature sensors; a chip carrier coupled to the chip via a plurality of solder connections, the chip carrier including a plurality of second temperature sensors respectively aligned vertically with the plurality of first temperature sensors disposed at the corners and / or edges of the chip, each of the plurality of second temperature sensors configured to measure a plurality of second temperatures of the chip carrier in a second localized region around each of the plurality of second temperature sensors; The chip carrier further includes a plurality of first local heating elements arranged near each of the plurality of second temperature sensors, the plurality of first local heating elements being configured to be activated when each difference detected based on a comparison between the plurality of first temperatures and each of the corresponding plurality of second temperatures is not within a predetermined range, and to generate heat so that the each difference is within the predetermined range, so that the each detected difference is regulated in the plurality of first local regions around the plurality of first temperature sensors.

2. 2. The chip package of claim 1, wherein each of the detected differences is a temperature difference between the plurality of first temperatures and a corresponding one of the plurality of second temperatures.

3. 3. The chip package of claim 1, wherein each of the detected differences is based on a difference between a first product of a first coefficient of thermal expansion (CTE) of the chip and the plurality of first temperatures and a second product of a second CTE of the chip carrier and the plurality of second temperatures.

4. 4. The chip package of claim 1, wherein the chip further includes a plurality of second local heating elements arranged near each of the plurality of first temperature sensors, the plurality of second local heating elements configured to generate heat in response to the respective detected differences, such that the detected differences are adjusted in the plurality of first local regions around the plurality of first temperature sensors.

5. 5. The chip package of claim 4, wherein the plurality of second local heating elements are configured to be activated when the detected respective differences are not within a predetermined range and to generate heat to bring the respective differences within the predetermined range.

6. The chip package of claim 4 or 5, wherein the plurality of second localized heating elements are resistors configured to generate heat in response to an electrical current applied to the resistors.

7. the plurality of first temperature sensors are provided on the same surface within the chip at four corners and / or four edges of the chip; the plurality of second temperature sensors of the chip carrier are aligned vertically with the plurality of first temperature sensors provided at the four corners and / or the four edges, and the plurality of second temperature sensors and the plurality of first localized heating elements are provided on the same plane within the chip carrier; The chip package according to claim 6 , wherein the plurality of first local heating elements are further disposed inside the chip carrier than the plurality of second temperature sensors in a top view of the chip carrier.

8. the plurality of first temperature sensors and the plurality of second localized heating elements are disposed on the same surface within the chip; 8. The chip package of claim 7, wherein each of said plurality of second localized heating elements of said chip is vertically aligned with each of said plurality of first localized heating elements of said chip carrier.

9. A chip package described in any one of claims 1 to 8, wherein the plurality of first temperature sensors are on-chip temperature sensor diodes (OCTS) and the plurality of second temperature sensors are OCTS.

10. A chip package as described in any one of claims 1 to 9, wherein the plurality of first local heating elements are resistors configured to generate heat in response to a current applied to the resistors.

11. 11. The chip package of claim 1, further comprising: an analog circuit, a digital circuit, or both, configured to compare the plurality of first temperatures with each of the plurality of corresponding second temperatures and detect the respective differences.

12. the chip carrier having a central core, a front side level, and a bottom side level; The chip package of claim 1 , wherein each of the plurality of second temperature sensors is disposed on the front side level.

13. The chip package of claim 1 , wherein the plurality of first temperature sensors are located at a back-end level of the chip.

14. 1. An electronic device comprising: a printed circuit board; An electronic device comprising: a chip package according to claim 1 coupled to the printed circuit board via a solder ball grid array.

15. 1. A method for reducing temperature-induced stress in a chip package, comprising: measuring a plurality of first local temperatures at the corners and / or edges of the chip in the chip package using a plurality of first local temperature sensors embedded in the corners and / or edges of the chip, respectively; measuring a plurality of second local temperatures of the chip carrier coupled to the chip using a plurality of second local temperature sensors embedded in the chip carrier, the plurality of second local temperature sensors being vertically aligned with the plurality of first local temperature sensors, respectively; comparing the plurality of first local temperatures of the chip with each of the plurality of corresponding second local temperatures of the chip carrier; determining, based on the comparison, that each difference is not within a predetermined range; and in response to determining that the respective differences are not within the predetermined range, activating a heating element of at least one of the chip or the chip carrier to generate heat so as to adjust the differences to be within the predetermined range.

16. 16. The method of claim 15, wherein determining that the respective differences based on the comparison are not within the predetermined range comprises determining that a temperature difference between each of the plurality of first local temperatures and a corresponding each of the plurality of second local temperatures is not within the predetermined range.

17. 17. The method of claim 15 or 16, wherein determining that the respective differences based on the comparison are not within the predetermined range includes determining that the respective differences are not within the predetermined range based on a difference between a first product of a first coefficient of thermal expansion (CTE) of the chip and the plurality of first local temperatures and a second product of a second CTE of the chip carrier and the plurality of second local temperatures.

18. 18. The method of claim 17, wherein the chip is constructed of a silicon material having a CTE of about 2.6 parts per million (ppm) per degree Celsius (C), and the chip carrier is constructed of one or more organic laminate materials having a composite CTE of about 15 ppm / C.

19. 19. The method of claim 15, wherein the plurality of first local temperature sensors are on-chip temperature sensor diodes (OCTS), and the plurality of second local temperature sensors are OCTS.

20. 20. The method of claim 15, wherein activating the heating element of at least one of the chip or the chip carrier comprises applying a current to a resistor, the resistor configured to generate heat in response to the applied current.

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