Double magnetic tunnel junction devices

Abstract

A technique for providing a double magnetic tunnel junction device structure having two spacers including a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conducting layer, a first dielectric spacer on a side of the top magnetic tunnel junction stack and a portion of a top surface of the spin conducting layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel junction device includes a top magnetic tunnel junction stack having a width that is smaller than a width of the bottom magnetic tunnel junction stack.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor memory device technology, and more particularly to magnetoresistive random access memory devices. [Background technology]

[0002] Conventional MRAM devices include a magnetic tunnel junction (MTJ) structure in which a magnetic (e.g., ferromagnetic) layer is separated by an intermediate nonmagnetic tunnel barrier layer. Digital information can be stored in the memory element and represented by the direction of the magnetization vector. Depending on the voltage applied to the MTJ, the magnetic memory element exhibits different resistance values, allowing the MRAM device to provide the information stored in the magnetic memory element. MRAM technology has evolved to include two vertically aligned MTJs within an MRAM device. A double MTJ (DMTJ), with the bottom MTJ wider than the top MTJ, provides dual spin current sourcing (DSTT) in MRAM devices. Summary of the Invention

[0003] One aspect of the present invention includes a double magnetic tunnel junction device including a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conducting layer, first dielectric spacers on side surfaces of the top magnetic tunnel junction stack and a portion of the top surface of the spin conducting layer, and a second dielectric spacer on the first dielectric spacer, wherein the double magnetic tunnel junction device includes the top magnetic tunnel junction stack having a width smaller than that of the bottom magnetic tunnel junction stack.

[0004] Another aspect of the present invention includes a method for forming a double magnetic tunnel junction device, including forming a via in a via dielectric over a portion of a metal layer of a back-end semiconductor structure and depositing a stack of material layers for the double magnetic tunnel junction device over the via and the via dielectric. The method includes patterning and selectively etching portions of a hard mask and an organic mask over a top portion of the stack of material layers. The method includes etching portions of the etch stop layer, the top magnetic tunnel junction, and the top portion of the spin conduction layer in the stack of material layers using one or more of an ion beam etching process and a reactive ion etching process. The method includes depositing a first spacer material over the back-end semiconductor structure and depositing a second spacer material over the first spacer material. The method further includes removing horizontal portions of the first spacer material and the second spacer material. The method includes removing a first spacer, a spin conducting layer in a stack of material layers for a double magnetic tunnel junction device, a portion of a bottom magnetic tunnel junction, and a portion of a surface of a via dielectric using one or more of an ion beam etching process and a reactive ion etching process, wherein the removed portions are not protected by sidewalls of the second spacer.

[0005] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 2 is a cross-sectional view of a structure after forming a via on a metal layer according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a structure after depositing a stack of material layers for a double MTJ, according to one embodiment of the present invention. [Figure 3] 3A illustrates a cross-sectional view of a structure after etching a hard mask layer of a stack of material layers, in accordance with one embodiment of the present invention. [Figure 4]1 is a cross-sectional view of the structure after removing a portion of the stack of material layers to form a top MTJ, according to one embodiment of the present invention. [Figure 5] 2 is a cross-sectional view of a semiconductor structure after depositing a first spacer on a top surface of the structure, according to one embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view of the structure after removing the top portion of the first spacer, according to one embodiment of the present invention. [Figure 7] FIG. 2 is a cross-sectional view of a structure after depositing a second spacer on the first spacer, according to one embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view of the structure after removing horizontal portions of the first and second spacers, according to one embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view of the structure after etching a portion of the bottom MTJ and via dielectric material according to one embodiment of the present invention. [Figure 10] 2 is a cross-sectional view of a semiconductor structure after depositing an encapsulating dielectric layer over the structure, according to one embodiment of the present invention. [Figure 11] FIG. 2 is a cross-sectional view of a structure after chemical mechanical polishing (CMP), according to one embodiment of the present invention. [Figure 12] FIG. 10 is a cross-sectional view of the structure after forming a bit line over the dual MTJ according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] Magnetoresistive random access memory ("MRAM") devices using magnetic tunnel junctions ("MTJs") are one option to replace existing embedded DRAM technology. MRAM is a non-volatile memory. Embodiments of the present invention recognize that current MRAM MTJ structures are relatively slow, and the only way to reach MTJ write target speeds (approximately 5 ns) comparable to embedded DRAM is to use double magnetic tunnel junctions ("DMTJs"). DMTJ devices typically reduce write current by a factor of two.

[0008] Embodiments of the present invention recognize that in some DMTJ devices, an improved DMTJ device with a wide base is used to improve the switching efficiency of the MTJ by eliminating both the area resistance ("RA") and magnetoresistance ("MR") penalties associated with standard DMTJs in which the top and bottom MTJ stacks have similar critical dimensions ("CD"). Embodiments of the present invention recognize that the improved DMTJ with a wide base is fabricated using a bottom MTJ stack that is wider than the top MTJ stack. Embodiments of the present invention recognize that the improved DMTJ device with a bottom MTJ stack that is wider than the top MTJ stack provides the advantage of dual-spin current sourcing ("DSTT"). In the improved DMTJ device with a wide base, the bottom barrier layer can have a relatively high RA. The improved DMTJ device with a wide base can utilize spin diffusion transport in a non-magnetic ("NM") metal layer to achieve a reduced charge current density through the bottom barrier layer. The bottom NM layer can also act as an additional boron drain conduit during the annealing process. In some improved DMTJ devices with wide bases, a nonmagnetic spin conductor (e.g., Cu, CuN, Ag, AgSn, etc.) is used between the two MTJ stacks. During the fabrication of these improved DMTJ devices, an in-situ stack deposition process is desired to ensure stack integrity and avoid unexpected loss of spin conductance that can occur during ex-situ processes such as oxidation or CMP.

[0009] Embodiments of the present invention recognize that various problems can arise during the patterning and etching of the bottom layers of wide-base improved DMTJ devices. Embodiments of the present invention recognize that spacer erosion can occur during the patterning and etching of wide-base improved DMTJ devices, resulting in a reduction in the width of the bottom MTJ stack. Embodiments of the present invention recognize that typical spacer materials, such as SiN, used in forming spacers on wide-base improved DMTJs can erode during the etching process used to form the wide-base improved DMTJs, resulting in a reduction in the width of the bottom MTJ stack. Reducing the width of the bottom MTJ stack reduces the CD of the bottom MTJ stack, adversely affecting switching efficiency by increasing both the area resistance (“RA”) penalty and magnetoresistance (“MR”). Furthermore, embodiments of the present invention recognize that, in some cases, variations in the microstructure and / or composition of the SiN spacer can result in non-uniform spacer erosion, resulting in a non-uniform or asymmetric shape of the bottom MTJ stack, adversely affecting the performance of the wide-base improved DMTJ device.

[0010] Embodiments of the present invention recognize that during the etching process used to form improved wide-base DMTJ devices, small portions of the spin conduction layer sidewalls may be attacked or removed due to spacer erosion. Careless etching or unintentional removal of the spin conduction layer can result in inefficient spin conduction. Additionally, embodiments of the present invention recognize that, in some cases, extrusion of copper or copper-nickel from the spin conduction layer may occur if the spin conduction layer is not properly protected by a spacer during the etching process. If this extrusion occurs into other layers in the back-end (BEOL) process, it could potentially reduce BEOL reliability. For these reasons, embodiments of the present invention recognize that providing better protection for the spin conduction layer and bottom MTJ stack during the formation of improved wide-base DMTJs with non-magnetic bases is desirable. Embodiments of the present invention recognize that a new semiconductor structure with a new spacer material that provides better protection for the bottom MTJ stack and spin conduction layer would be beneficial to the performance of improved wide-base DMTJs with non-magnetic bases.

[0011] Embodiments of the present invention provide a semiconductor structure and a method for forming a semiconductor structure that protects the bottom MTJ stack and spin conduction layer during an etching process by adding a second spacer composed of a material that can protect the bottom MTJ stack and spin conduction layer during the etching process. Embodiments of the present invention provide a second spacer composed of a material that is more resistant to the IBE or RIE etching process. Embodiments of the present invention form a second spacer on top of a first spacer. The first spacer can be composed of a conventional spacer material, such as SiN. Generally, embodiments of the present invention provide a second spacer that has a lower etching rate than the material of the first spacer. Embodiments of the present invention use a second spacer composed of a metal material or a metal compound material with a high atomic number metal.

[0012] The second spacer is deposited and formed on top of the first spacer to provide additional protection for the bottom MTJ stack and spin conduction layer in embodiments of the present invention. The second spacer prevents or reduces erosion of the first spacer, bottom MTJ stack, and spin conduction layer. In doing so, the addition of the second spacer maintains the CD of the bottom MTJ stack in the wide, non-magnetic-base improved DMTJ. Creating and maintaining a wider CD of the bottom MTJ stack compared to the top MTJ stack reduces or eliminates the area-resistance ("RA") and magnetoresistance ("MR") penalties that occur in DMTJs with the same sized top and bottom MTJs. Embodiments of the present invention include materials and methods for forming the second spacer on the wide-base improved DMTJ device.

[0013] Detailed embodiments of the claimed structures and methods are disclosed herein. The structures shown and disclosed herein are semiconductor structures at the back end of a semiconductor chip. The method steps described below do not form a complete process flow for manufacturing an integrated circuit, such as a semiconductor device. The embodiments can be implemented with integrated circuit manufacturing techniques currently used in the art for magnetic tape heads, and only commonly implemented process steps necessary for understanding the described embodiments are included. The figures represent cross-sectional portions of a fabricated MRAM device and are not drawn to scale, but instead are drawn to illustrate features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art how to variously use the disclosed methods and structures. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0014] References herein to "one embodiment," "another embodiment," "another embodiment," "an embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly stated.

[0015] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "atop," "over," "on," "positioned on," or "positioned atop" mean that a first element is present on a second element, and that intervening elements, such as interfacial structures, may be present between the first and second elements. The term "direct contact" means that a first element and a second element are connected without any intermediate conductive, insulating, or semiconducting layers at the interface of the two elements.

[0016] In the following detailed description, some of the processing steps, materials, or operations known in the art may be combined for presentation and illustration purposes, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. Additionally, for the sake of brevity and to maintain focus on the unique features of the elements of the present invention, descriptions of previously discussed materials, processes, and structures may not be repeated with respect to subsequent figures. In other cases, some known processing steps or operations may not be described. It should be understood that the following description instead focuses on the unique features or elements of various embodiments of the present invention.

[0017] Generally, the various processes used to form semiconductor chips fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, physical vapor deposition ("PVD"), chemical vapor deposition ("CVD"), electrochemical deposition ("ECD"), molecular beam epitaxy ("MBE"), and more recently, atomic layer deposition ("ALD"). Another deposition technique is plasma-enhanced chemical vapor deposition ("PECVD"), a process that uses the energy of a plasma to induce reactions at the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0018] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate and the subsequent transfer of that pattern to a substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called a photoresist. The pattern created by lithography or photolithography is typically used to define or protect selected surfaces and portions of a semiconductor structure during subsequent etching processes.

[0019] Removal is any process that removes material from a wafer, such as etching or chemical-mechanical planarization ("CMP"). Examples of etching processes include wet (e.g., chemical) or dry etching processes. One example of a removal or dry etching process is ion beam etching ("IBE"). Generally, IBE (or milling) refers to dry plasma etching methods that utilize a remote broad-beam ion / plasma source to remove substrate material by physical inert gas means, chemically reactive gas means, or both. Like other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry etching process is reactive ion etching ("RIE"). Generally, RIE uses a chemically reactive plasma to remove material deposited on a wafer. High-energy ions from the RIE plasma attack the wafer surface and react with and remove the surface material.

[0020] Implementation of embodiments of the invention may take a variety of forms, and details of exemplary implementations are described below with reference to the figures. The invention will now be described in detail with reference to the drawings.

[0021] FIG. 1 is a cross-sectional view of a structure 100 after forming a via 104 on Mx 102, according to one embodiment of the present invention. As shown, FIG. 1 includes a dielectric 101, Mx 102, a via 104, and a via dielectric 106. Mx 102 is a metal layer above a semiconductor substrate (not shown). Mx 102 can be a middle-of-line (MOL) metal layer or a back-end-of-line (BEOL) metal layer. For example, Mx 102 can be part of the M2 or M3 metal layer, such as a line or contact in the M2 or M3 metal layer.

[0022] Mx 102 may be composed of, but is not limited to, Cu, TaN, Ta, Ti, TiN, or combinations thereof. As shown, dielectric 101 surrounds Mx 102. Dielectric 101 may be composed of a dielectric material such as, but not limited to, SiOx, SiNx, SiBCN, low-κ dielectric materials, nitrogen-doped barrier low-κ materials (NBLOK), or any other suitable dielectric material. Mx 102 and dielectric 101 can be deposited and formed using known metal and dielectric material deposition, optional planarization, and etching processes for semiconductor manufacturing.

[0023] A via dielectric 106 is deposited on the dielectric 101 and Mx 102. The via dielectric 106 can be the same or a different dielectric material as the dielectric 101. The via dielectric 106 can be patterned using known photolithography and etched, for example, using an RIE process, to form the via 104. A metal layer is deposited on the exposed portions of the via dielectric 106 and Mx 102. The metal layer can be deposited using one or more of a CVD process, a PVD process, and an ALD process. The metal layer forming the via 104 can be composed of one or more of tungsten (W), copper (Cu), tantalum nitride (TaN), Ta, titanium (Ti), TiN, TiOCN, or TaON.

[0024] After metal deposition, CMP can be performed to planarize the surface of structure 100 and form vias 104. CMP removes excess metal above the top surface of via dielectric 106. As shown in FIG. 1, some of the deposited metal, such as W, remains in via dielectric 106 to form vias 104.

[0025] FIG. 2 is a cross-sectional view of a structure 200 after deposition of a stack of material layers for a double MTJ according to one embodiment of the present invention. As shown, FIG. 2 includes the elements of FIG. 1 plus the stack of material layers for a double MTJ, which is comprised of a bottom MTJ stack 204, a spin conduction layer (SCL) 208, a top MTJ stack 210, an etch stop 214, a hard mask (HM) 216, and a dielectric / organic hard mask (HM) 218. As known to those skilled in the art, in other embodiments, more, fewer, or different material layers can comprise the stack of material layers for a double MTJ. In some embodiments, the dielectric / organic HM 218 is an organic mask or photoresist. In some embodiments, a cap layer may be deposited on top of the top MTJ stack 210. Using conventional MRAM materials and deposition processes, each layer of the stack of material layers is deposited sequentially in structure 200, starting with bottom MTJ stack 204, followed by SCL 208, then top MTJ stack 210, etch stop 214, HM 216, and dielectric / organic HM 218. For example, each layer of the stack of material layers can be deposited by ALD, PECVD, PVD, or another suitable deposition process.

[0026] In various embodiments, the bottom MTJ stack 204 and the top MTJ stack 210 each include a reference layer, a first tunnel barrier layer, a first free layer, a metal spacer layer, a second free layer, and a second tunnel barrier layer. Generally, for the MTJ stacks (i.e., the bottom MTJ stack 204 and the top MTJ stack 210), information is stored in the magnetic orientation of the free layer film in conjunction with the magnetic orientation of the reference layer (described in further detail herein). The reference layer may be a single layer or multiple layers. In one embodiment, the reference layer of the MTJ stack is a synthetic antiferromagnetic ("SAF") layer. In some embodiments, the reference layer of the MTJ stack includes multiple sublayers (e.g., 20 or more sublayers).

[0027] In forming any of the MTJ stacks, a first tunnel barrier layer is formed on the reference layer. In one embodiment, the first tunnel barrier layer is a barrier, such as a thin insulating layer, between two conductive materials. Electrons (or quasiparticles) pass through the tunnel barrier by the process of quantum tunneling. In various embodiments, the first tunnel barrier layer includes at least one sublayer composed of MgO or another suitable tunnel barrier material.

[0028] The free layer is a magnetization-free layer adjacent to the first tunnel barrier layer and facing the reference layer. The magnetization-free layer has a reversible magnetic moment or magnetization. The second tunnel barrier layer is formed on the free layer. In some embodiments, the second tunnel barrier layer includes an outermost sublayer (or some other sublayer) made of the same material as the first tunnel barrier layer (e.g., MgO).

[0029] As known to those skilled in the art, each of the layers in either the bottom MTJ stack 204 or the top MTJ stack 210 can include any number of sublayers, can include additional layers, or in other examples, can omit some layers, or can include combinations thereof. Furthermore, the composition of the layers and / or sublayers can be different between the bottom MTJ stack 204 and the top MTJ stack 210. In some embodiments, the bottom MTJ stack 204 and the top MTJ stack 210 are formed by a self-aligned patterning process.

[0030] 2, an etch stop 214 is formed on the top MTJ stack 210. The etch stop 214 may be composed of, but is not limited to, ruthenium (Ru). In some embodiments, a cap layer (not shown) is formed between the top MTJ stack 210 and the etch stop 214.

[0031] The HM216 can be formed on the etch stop 214 using a metal hard mask material. For example, the HM216 may be composed of, but is not limited to, W, TaN, or TiN. The metal material of the HM216 can be any suitable top electrode metal used in MRAM devices. A dielectric / organic HM218 can be formed on the HM216. The organic / dielectric HM218 can be composed of an organic planarization layer ("OPL") material, a photoresist material, SiNx, or SiOx, where x indicates the number of nitrogen or oxygen atoms, respectively.

[0032] FIG. 3 is a cross-sectional view of a structure 300 after etching HM216 and dielectric / organic HM218, according to one embodiment of the present invention. HM216 and dielectric / organic HM218 may be patterned, for example, by lithography and etched using RIE. As shown, HM216 and dielectric / organic HM218 are etched to form pillars of HM216 and dielectric / organic-dielectric / organic HM218. The width of the pillars formed by the remaining HM216 and dielectric / organic HM218 can be in the range of 10-500 nm, but is not limited to this range.

[0033] Figure 4 is a cross-sectional view of a structure 400 after removing portions of the stack of material layers to form the top MTJ stack 210, according to one embodiment of the present invention. As shown, Figure 4 includes the elements of Figure 3 after removing the dielectric / organic HM 218 and portions of each of SCL 208, top electrode stack 210, etch stop 214, and HM 216.

[0034] IBE, RIE, or a combination of IBE and RIE can be used to remove portions of the etch stop 214, the top stack 210, and the SCL 208. In some embodiments, the dielectric / organic HM 218 is a resist material or OPL on top of the HM 216 that is removed after etching. The etching of the etch stop 214, the top MTJ stack 210, and the SCL 208 can extend into the top portion of the SCL 208. As shown in FIG. 4, the etching process stops near the top of the SCL 208. As shown in FIG. 4, a portion of the top surface of the SCL 208 is curved or has a curved cross-sectional profile near where the SCL 208 abuts the top MTJ stack 210. In some embodiments, the etching process using IBE and / or RIE stops at the top surface of the SCL 208, leaving the vertical side of the top MTJ stack 210 exposed. In these embodiments, by modifying the etching parameters (e.g., etch angle, etch time, etch energy, etc.), the top surface of the SCL 208 around the top MTJ stack 210 is flat rather than curved as shown in FIG.

[0035] At this stage of the fabrication process, the critical dimension (CD) of the top MTJ stack 210 is smaller than the critical dimension of the bottom MTJ stack 204, as shown in Figure 4. Furthermore, the CD of the SCL 208 is gradually varied throughout the thickness of the layer of the SCL 208. The layer of the SCL 208 remains on top of the bottom MTJ stack 204.

[0036] 4 shows a tapered shape with a fairly consistent slope (i.e., at least substantially up to the SCL 208) for the combination of the HM 216, etch stop 214, and top MTJ stack 210. However, it should be understood that in other embodiments, the lateral surfaces or sidewalls of the HM 216, etch stop 214, and top MTJ stack 210 have vertical (or nearly vertical) profiles. The slope or angle of the sidewalls of the HM 216, etch stop 214, and top MTJ stack 210 relative to the horizontal plane of the bottom MTJ stack 204 or the surface of the semiconductor substrate (not shown) can vary from 70 degrees to 90 degrees, but is not limited to these angles or slopes.

[0037] After patterning the top MTJ stack 210, optional processes such as controlled in-situ oxidation or air break may be performed. Controlled in-situ oxidation can be a process in which the wafer (e.g., structure 400) is exposed to a fixed oxygen pressure, e.g., 1 mTorr to 500 Torr. Air break is an ex-situ process in which the wafer is removed from the etching chamber and exposed to air. Controlled in-situ oxidation and air break can reduce partial short circuit failures of MRAM cells associated with metal redeposition around the top tunnel barrier.

[0038] FIG. 5 is a cross-sectional view of a structure 500 after depositing first spacers 404 on the top surface of the structure 400, according to one embodiment of the present invention. As shown, FIG. 5 includes the elements of FIG. 4 plus the first spacers 404. An optional plasma process pretreatment can be used prior to deposition of the first spacers 404. For example, the plasma pretreatment is performed using one or more of oxygen, hydrogen, nitrogen, or a combination of these elements (i.e., NH3) in a plasma. The first spacers 404 can be deposited by, but are not limited to, PVD, ALD, or PECVD. The first spacers 404 may be composed of, but are not limited to, SiN, oxides of Si, Ti, or Al (i.e., SiOx, TiOx, or ALOx), boron nitride (BN), or SiBCN.

[0039] FIG. 6 is a cross-sectional view of a structure 600 after removing a top portion of the first spacer 404, according to one embodiment of the present invention. As shown, FIG. 6 includes the element of FIG. 5 after partial etching of the first spacer 404. For example, using low-angle IBE, RIE, or a combination of low-angle IBE and RIE, portions of the first spacer 404 are removed from the periphery of the sloped side of the HM 216, from the top surface of the first spacer 404 above the top of the HM 216, and from the top surface of the first spacer 404 above and on the SCL 208. As shown, after partial etching using low-angle IBE or RIE, a layer of the first spacer 404 remains on the SCL 208, the periphery of the top MTJ stack 210, the etch stop 214, the periphery of the HM 216, and on the HM 216. The thickness of the first spacers 404 after partial etching can be in the range of 5 to 100 nm, but is not limited to this range.

[0040] FIG. 7 illustrates a cross-sectional view of the structure 700 after depositing second spacers 707 on the remaining portions of the first spacers 404, according to one embodiment of the present invention. In various embodiments, the second spacers 707 are composed of a material that has a lower etch rate in low-angle IBE or RIE than the material of the first spacers 404. The second spacers 707 may be composed of, but are not limited to, one or more high atomic number metals, such as Ta, palladium (Pd), metal compounds containing high atomic number metals, such as TaN, or hard materials, such as diamond (carbon). The second spacers 707 on top of the first spacers 404 provide additional protection to the SCL 208 and the bottom MTJ stack 204 during subsequent etching processes. In this way, the second spacers 707 prevent asymmetry or a reduction in the diameter of the bottom MTJ stack 204, for example, if the etching of the first spacers 404 is uneven due to changes in the microstructure or composition of the first spacers 404. Non-uniform etching of the SCL 208, which may result in portions of the SCL 208 being attacked or removed, results in inefficient spin transport. ALD or PECVD can be used to deposit the second spacer 707 layer on the first spacer 404, but these deposition processes are not limited to these. The thickness of the second spacer 707 can be in the range of 5 to 30 nm, but is not limited to this range.

[0041] 8 is a cross-sectional view of a structure 800 after removing second spacers 707 and horizontal portions of first spacers 404, according to one embodiment of the present invention. In various embodiments, one or more of a low-angle IBE process and / or RIE process are used to remove second spacers 707 and horizontal portions of first spacers 404 over a portion of the top horizontal surface of SCL 208. In some embodiments, a combination of IBE and RIE is used to remove second spacers 707 and horizontal portions of first spacers 404.

[0042] As shown, the sides or sidewalls of the second spacer 707 and the first spacer 404 are sloped and essentially or nearly parallel to the sidewalls of the HM 216, the etch stop 214, and the top MTJ stack 210. After removing the horizontal portion of the second spacer 707, a small horizontal portion of the first spacer 404 remains below the bottom of the second spacer 707. The small horizontal portion of the first spacer 404 abuts the top portion of the SCL 208. The second spacer 707 is separated from the horizontal or curved surface of the SCL 208 by the first spacer 404 (e.g., to prevent shorting). As shown, the top portion of the HM 216 is exposed after etching. The conical shape or angle of the top surfaces of the second spacer 707 and the first spacer 404 may vary depending on the etching process and etching process parameters used. In some cases, a depression or dip may occur in the top surface of the first spacer 404 (not shown). As shown in FIG. 8, the first spacer 404 and the second spacer 707 cover the side of the top MTJ stack 210, the etch stop 214, most of the HM 216, the curved portion of the SCL 208, and possibly a small horizontal top surface of the SCL 208 adjacent to the curved portion of the SCL 208.

[0043] 9 is a cross-sectional view of a structure 900 after another etching process that removes a portion of the bottom MTJ stack 204 and a portion of the via dielectric 106, according to one embodiment of the present invention. As shown, FIG. 9 includes elements of FIG. 8, with some top portions of the SCL 208 not covered by the remaining portions of the first spacer 404 removed, portions of the bottom MTJ stack 204 underlying the removed portions of the SCL 208 also removed, and top portions of the via dielectric 106 adjacent to the remaining bottom edges of the bottom MTJ stack 204 also removed.

[0044] In various embodiments, the structure 900 is formed by removing the exposed portions of the SCL 208 not under the first spacer 404, the portions of the bottom MTJ stack 204, and the top portion of the via dielectric 106 using one or both of a low-angle IBE or RIE process. After the etching process, the structure 900 includes a conical pillar of the HM 216 at the top of the pillar, an etch stop 214 below the HM 216, the top MTJ stack 210 below the etch stop 214, the remaining portions of the SCL 208 below the first spacer 404 and the top MTJ stack 210, and the remaining bottom MTJ stack 204 below the remaining portions of the SCL 208. The first spacer 404 covers the side and curved top surface of the SCL 208 and the side surfaces of the top MTJ stack 210, the etch stop 214, and the HM 216. The second spacer 707 covers the sidewalls of the first spacer 404. After etching, the layer of second spacer 707 covers part of the side of the first spacer 404 and is separated from the curved edge portion of the SCL 208 by the first spacer 404. As shown in FIG. 9, the bottom MTJ stack 204 is larger than the top MTJ 210.

[0045] In various embodiments, the structure 900 is formed using one or a combination of low-angle IBE or RIE processes to remove the exposed portions of the SCL 208 not under the first spacer 404, the portion of the bottom MTJ stack 204, and the top portion of the via dielectric 106. After the etching process, the structure 900 includes a conical pillar of HM 216 at the top of the pillar, an etch stop 214 below the HM 216, the top MTJ stack 210 below the etch stop 214, the remaining portion of the SCL 208 below the first spacer 404 and the top MTJ stack 210, and the remaining bottom MTJ stack 204 below the remaining portion of the SCL 208. The first spacer 404 covers the side and curved top surface of the SCL 208 and the side surfaces of the top MTJ stack 210, the etch stop 214, and the HM 216. The second spacer 707 covers the sidewalls of the first spacer 404. After etching, the layer of second spacers 707 covers part of the side surfaces of the first spacers 404 and is separated from the curved edge portions of the SCLs 208 by the first spacers 404 .

[0046] After the etching process, the sidewalls of the remaining portion of the bottom MTJ stack 204 and the outer sidewalls of the curved top portion of the SCL 208 are parallel to the sidewalls or outer surface of the second spacer 707 and the bottom sidewall of the first spacer 404, forming a conical pillar (e.g., an MRAM pillar with a DMTJ).

[0047] 9, the top surface of each of the HM 216, etch stop 214, top MTJ stack 210, SCL 208, and bottom MTJ stack 204 is smaller than the bottom surface of the respective layer (e.g., the top of the bottom MTJ stack 204 is smaller than the bottom of the bottom MTJ stack 204). The magnitude of the difference between the top and bottom of each layer can vary depending on various etching process parameters (e.g., the IBE etch angle or etch time affect the slope of the side surfaces of the conical pillars). For example, the side surfaces of the cones may be vertical or near-vertical, or in other embodiments, may form an 80-degree angle with respect to the horizontal top surface of the semiconductor substrate (not shown).

[0048] As mentioned above, the conical pillar in FIG. 9 , sometimes known as an MRAM pillar, is comprised of two MTJs (i.e., the bottom MTJ stack 204 and the top MTJ stack 210), a SCL 208, an etch stop 214, and an HM 216. The majority of the sidewalls of the MRAM pillar are covered by a first spacer 404 and a second spacer 707 that covers and protects the first spacer 404. As mentioned above, the angle of the sidewalls of the conical pillar may be different in other examples. As shown in FIG. 9 , the sidewalls of the conical pillar or MRAM pillar include a small portion of the HM 216, a portion of the first spacer 404, the top and side of the second spacer 707, a thin portion of the sidewall of the SCL 208, and the sidewalls of the bottom MTJ stack 204. When the structure 900 is formed using the method described with reference to FIGS. 1-9, the bottom MTJ stack 204 is wider than the top MTJ stack 210. During the etching process described with reference to FIG. 9, the bottom MTJ stack 210 remains protected under the second spacers 707 and the first spacers 404. In particular, the second spacers 707 formed of an IBE / RIE etch-resistant material, such as TaN, can protect both the first spacers 404 and the bottom MTJ stack 210. The use of an etch-resistant material for the second spacers 707 maintains the width or critical diameter of the bottom MTJ stack 210. The use of a material for the second spacers 707 that can be IBE / RIE etch-resistant or that can etch slowly with IBE or RIE protects the CD of the bottom MTJ stack 210. The use of etch-resistant second spacers 707 helps maintain a symmetrical and wider bottom MTJ stack 210, which allows more spins to be funneled into the top free layer. Additionally, the second spacers 707 can protect the SCL 208 from attack and / or extrusion formation during the IBE and / or RIE processes. Protecting the SCL 208 from inadvertent etching or attack maintains efficient spin transport.As mentioned above, preventing SCL208 extrusion improves BEOL reliability.

[0049] After patterning the bottom MTJ stack 204, optional processes such as controlled in-situ oxidation or air break may be performed. Controlled in-situ oxidation can be a process in which the wafer (e.g., structure 900) is exposed to a fixed oxygen pressure, e.g., 1 mTorr to 500 Torr. Air break is an ex-situ process in which the wafer is removed from the etching chamber and exposed to air. Controlled in-situ oxidation and air break can reduce partial short circuit failures of MRAM cells associated with metal redeposition around the top tunnel barrier.

[0050] FIG. 10 is a cross-sectional view of a structure 1000 after deposition of an encapsulation dielectric 806 on the structure 900, according to one embodiment of the present invention. As shown, FIG. 10 includes the elements of FIG. 9, the encapsulation dielectric 806, and an interlayer dielectric (ILD) 808. The encapsulation dielectric 806 can be deposited by, but is not limited to, PVD, ALD, or PECVD. The encapsulation dielectric 806 may be composed of, but is not limited to, AlOx, TiOx, SiOx, BN, SiN, or SiBCN. An optional plasma process pretreatment can be used prior to deposition of the first spacers 404. For example, the plasma pretreatment can be performed using one or more of oxygen, hydrogen, or nitrogen plasma, or a combination of these elements (i.e., NH3) in a plasma. The encapsulation dielectric 806 may be deposited on the via dielectric 106, the bottom MTJ stack 204, the SCL 208, the exposed surface of the first spacer 404, the sides and top of the second spacer 707, and the HM 216. After depositing the encapsulation dielectric 806, a layer of ILD 808 is deposited on the encapsulation dielectric 806 to fill the areas or trenches adjacent to the MRAM pillars. In various embodiments, the ILD 808 extends above the HM 216 in a conical pillar.

[0051] 11 is a cross-sectional view of structure 1100 after CMP according to one embodiment of the present invention. CMP planarizes the top surface of structure 1100 by removing the top portions of ILD 808, encapsulation dielectric 806, HM 216, first spacer 404, and second spacer 707. After CMP, the tops of the conical pillars or MRAM pillars are flat. The flat tops of the conical pillars expose the top portions of HM 216, first spacer 404, second spacer 707, encapsulation dielectric 806, and ILD 808.

[0052] Figure 12 is a cross-sectional view of a structure 1200 after forming bitlines 902 on the tops of the planarized conical pillars formed by the CMP process of Figure 11, in accordance with one embodiment of the present invention. As shown, Figure 12 includes the elements of Figure 11 plus bitlines 902 having liners 905 surrounded by ILD 908. A layer of ILD 908 is deposited on the structure 1100 shown in Figure 11. The ILD 908 can be patterned using photolithography and etched using, for example, RIE or another suitable ILD etch process.

[0053] After etching the ILD 908, a layer of liner material, such as, but not limited to, a tantalum-nitrogen alloy, a titanium-nitrogen alloy, or a tantalum-aluminum-nitrogen alloy, can be deposited by a known liner deposition process (e.g., ALD or PECVD). The liner 905 can be deposited on the ILD 908 and on the exposed top surface of the HM 216, the first spacer 404, the second spacer 707, the encapsulation dielectric 806, and a portion of the ILD 808 adjacent to the top surface of the encapsulation dielectric 806. After depositing the liner 905, a layer of conductive material or metal for the bit line 902 is deposited on the liner 905. The material for the bit line 902 can include, but is not limited to, Ta, TaN, or Cu. CMP is performed to remove excess liner 905 and bit line 902 material from the top surface of the ILD 908. After CMP, the bit line 902 with the liner 905 is formed above the HM 216 on the top MTJ stack 210. The structure 1200 includes a bottom MTJ stack 204 with a wider CD than the top MTJ stack 210, connected to the Mx 102 by a via 104. The wider bottom MTJ stack 204 and the narrower top MTJ stack 210 are separated by a SCL 208 to form a wide-base DMTJ for an MRAM device using a double-spacer process. The double-spacer process uses a first spacer 404 composed of a conventional spacer material such as SiN and a second spacer 707 composed of an etch-resistant material such as TaN. The double-spacer process can use the second spacer 707 to protect the first spacer 404, the SCL 208, and the bottom MTJ stack 204 during various etching processes used to form the wide-base DMTJ shown in the structure 1200.

[0054] In summary, the general description of a method for forming a wide-base DMTJ structure with two spacers shown in FIG. 12 includes the steps described in detail above with respect to FIGS. 1-12. Other embodiments differ in one or more variations in the process, materials, or process sequence. The steps include forming a via 104 on a metal layer (e.g., Mx 102) in a dielectric material 101, depositing a double MTJ material layer stack on the via and the dielectric material, and then patterning and selectively etching at least a portion of a hard mask 216 on one or more portions of the double MTJ material layer stack. The method includes selectively etching an etch stop 214 in the stack of material layers for the double MTJ stack, a portion of the top MTJ stack 210, and a top portion of the SCL 208 using a hard mask 216 in the stack of material layers for the double MTJ stack and one or more of IBE or RIE; and depositing a first spacer material for the first spacer 404 over and around the hard mask 216, the etch stop 214, the remaining portion of the top MTJ stack 210, and over the SCL 208. Partial etching of the first spacer 404 may be performed. Second spacers 707 are deposited on the first spacers 404. Horizontal portions of the second spacers 707 and horizontal portions of the first spacers 404 not covered by the second spacers 707 are etched. Removal of the SCL 208, a portion of the bottom MTJ stack 204, and the top portion of the ILD 106 not under the second spacer 707 and not under the remaining portion of the first spacer 404 is performed using one or more of IBE or RIE etching processes. A layer of encapsulation dielectric 806 is deposited on the exposed surfaces of the ILD 106, the bottom MTJ stack 204, the SCL 208, the first spacer 404, the second spacer 707, and the hard mask 216 using a known spacer deposition process. CMP can be performed to remove the top portion of the encapsulation dielectric 806 and expose the top portions of the hard mask 216, the first spacer 404, and the second spacer 707.A layer of ILD 908 can be deposited on the exposed surfaces of ILD 808, second spacer 707, first spacer 404, and hard mask 216. The encapsulation dielectric 806 can be selectively etched, and a metal layer for liner 905 can be deposited on the exposed top surfaces of ILDs 808 and 908, encapsulation dielectric 806, bottom MTJ stack 204, SCL 208, first spacer 404, second spacer 707, and hard mask 216. A bitline 902 with liner 905 is deposited on the exposed top surfaces of hard mask 216, first spacer 404, second spacer 707, and encapsulation dielectric 806. CMP removes excess bitline metal from the top surface of ILD 908 to form the wide-base DMTJ structure shown in FIG. 12 with two spacers.

[0055] The description of various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications or technical improvements to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0056] The methods described herein can be used in the manufacture of integrated circuit or semiconductor chips. The resulting semiconductor chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the semiconductor chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with either surface wiring or embedded wiring, or both). In either case, the semiconductor chip is integrated with other semiconductor chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing semiconductor chips, ranging from toys and other low-end applications to advanced computer products with displays, memory, keyboards or other input devices, and central processing units.

Claims

1. 1. A double magnetic tunnel junction device, comprising: a bottom magnetic tunnel junction stack; and a spin conducting layer on the bottom magnetic tunnel junction stack; a top magnetic tunnel junction stack on the spin conducting layer, the top magnetic tunnel junction stack having a width smaller than a width of the bottom magnetic tunnel junction stack; a first dielectric spacer on a side surface of the top magnetic tunnel junction stack and a portion of a top surface of the spin conducting layer; a second spacer on the first dielectric spacer; wherein the bottom magnetic tunnel junction stack has sides that are substantially parallel to an outer surface of the second spacer.

2. an etch stop layer on the top magnetic tunnel junction stack; a metal hardmask layer on the etch stop layer, wherein an encapsulation dielectric is on the etch stop layer and the metal hardmask layer; an encapsulation dielectric surrounding a side surface of the bottom magnetic tunnel junction stack, a bottom portion of a side surface of the spin conducting layer, a bottom portion of a side surface of the first dielectric spacer, and a side surface of the second spacer; The double magnetic tunnel junction device of claim 1 further comprising:

3. 2. The dual magnetic tunnel junction device of claim 1, wherein a top surface of the bottom magnetic tunnel junction stack is covered by at least a portion of the spin conducting layer underlying a bottom portion of the first dielectric spacer and a bottom portion of the second spacer up to a side position of the bottom magnetic tunnel junction stack, and the bottom magnetic tunnel junction stack resides on a via.

4. 2. The dual magnetic tunnel junction device of claim 1, wherein a width of the surface of the spin conducting layer is at least substantially the same as a width of the bottom surface of the top magnetic tunnel junction stack, and a width of the bottom surface of the spin conducting layer is at least substantially the same as a width of the top surface of the bottom magnetic tunnel junction stack.

5. The double magnetic tunnel junction device of claim 1 , wherein the second spacer comprises one of tantalum, palladium, or tantalum nitride.

6. The double magnetic tunnel junction device of claim 1 , wherein the second spacer is composed of a material comprising diamond.

7. 2. The double magnetic tunnel junction device of claim 1, wherein the first dielectric spacer comprises at least one material selected from the group consisting of silicon nitride, aluminum oxide, titanium oxide, silicon oxide, boron nitride, and silicon nitride boron carbide.

8. The double magnetic tunnel junction device of claim 1 , wherein a bottom portion of the second spacer resides at a bottom portion of a top surface of the first dielectric spacer.

9. The double magnetic tunnel junction device of claim 1 , wherein the second spacer protects a critical diameter of the bottom magnetic tunnel junction stack.

10. The double magnetic tunnel junction device of claim 1 , wherein the second spacer protects a sidewall of the spin conducting layer on the bottom magnetic tunnel junction stack.

11. a liner over the metal hard mask layer, the first dielectric spacers, the second spacers, and the encapsulation dielectric; a bit line on the liner; The double magnetic tunnel junction device of claim 2 further comprising:

12. A double magnetic tunnel junction device, comprising: a bottom magnetic tunnel junction stack; and a spin conducting layer on the bottom magnetic tunnel junction stack; a top magnetic tunnel junction stack on the spin conducting layer, the top magnetic tunnel junction stack having a width smaller than a width of the bottom magnetic tunnel junction stack; a first dielectric spacer on a side surface of the top magnetic tunnel junction stack and a portion of a top surface of the spin conducting layer; a second spacer on the first dielectric spacer; wherein the second spacer is comprised of a material comprising diamond.

13. 1. A method of forming a double magnetic tunnel junction device, comprising: forming a via in the via dielectric over a portion of the metal layer of the back-end semiconductor structure; depositing a stack of material layers for a double magnetic tunnel junction device over the via and the via dielectric; patterning and selectively etching a portion of the hard mask and organic mask on a top portion of the stack of material layers; Etching a portion of each of an etch stop layer, a top magnetic tunnel junction, and a top portion of a spin conduction layer in the stack of material layers; depositing a first spacer material over the back-end semiconductor structure; depositing a second spacer material over the first spacer material; removing horizontal portions of the first spacer material not under the second spacer material and horizontal portions of the second spacer material; removing the spin conducting layer, a portion of a bottom magnetic tunnel junction, and a portion of a surface of the via dielectric in the stack of material layers for the double magnetic tunnel junction device, the removed portions not protected by sidewalls of the remaining second spacer material; Including, a method.

14. 14. The method of claim 13, wherein forming the via in the via dielectric on the portion of a metal layer of the back-end semiconductor structure further comprises the back-end semiconductor structure being a patterned top magnetic tunnel junction and the hard mask.

15. 14. The method of claim 13, wherein depositing the first spacer material over the back-end semiconductor structure further comprises performing a partial etch of the first spacer material.

16. 14. The method of claim 13, wherein the stack of material layers for the double magnetic tunnel junction device comprises the bottom magnetic tunnel junction, the spin conducting layer on the bottom magnetic tunnel junction, the top magnetic tunnel junction on the spin conducting layer, and an etch stop under a hard mask.

17. depositing an encapsulation dielectric over the back-end semiconductor structure; depositing a first interlayer dielectric over the back-end semiconductor structure; performing chemical mechanical polishing to remove a hard mask layer, the second spacer material, the first spacer material, and a top portion of the first interlayer dielectric to remove a portion of the MRAM stack to form an MRAM pillar; depositing a second interlayer dielectric; forming a bit line, the bit line including a liner; 14. The method of claim 13, further comprising:

18. 14. The method of claim 13, wherein etching the portions of each of the etch stop layer, the top magnetic tunnel junction, and the top portion of the spin conduction layer in the stack of material layers further comprises: using the hard mask remaining after patterning as a mask; and etching the portions of each of the etch stop layer, the top magnetic tunnel junction, and the top portion of the spin conduction layer using one or more of an ion beam etching process or a reactive ion etching process.

19. 14. The method of claim 13, wherein the top magnetic tunnel junction is made smaller than the bottom magnetic tunnel junction by removing the first spacer material, the spin conducting layer, a portion of the bottom magnetic tunnel junction, and the portion of the surface of the via dielectric using one or more of an ion beam etching process or a reactive ion etching process and the second spacer material.

20. 14. The method of claim 13, wherein removing the spin conducting layer in the stack of material layers for the double magnetic tunnel junction device, a portion of the bottom magnetic tunnel junction, and the portion of the surface of the via dielectric further comprises performing one of a controlled in-situ oxidation process or an air break process.

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