Display panel and display device

Abstract

The present invention provides a display panel and a display device, the display panel includes a plurality of pixel driving circuits arranged and distributed along a first direction (X) and a second direction (Y), the first direction (X) intersects with the second direction (Y), the pixel driving circuit includes a driving transistor (T3) and a capacitance (C), a first electrode of the capacitance (C) is connected to a gate of the driving transistor (T3) and a second electrode of the capacitance (C) is connected to a power supply line (VDD), and the display panel further includes a base substrate (90), a second conductive layer and a fifth conductive layer. The second conductive layer is located on one side of the base substrate (90), the second conductive layer includes a plurality of second conductive portions (22), the plurality of second conductive portions (22) are provided in one-to-one correspondence with the plurality of pixel driving circuits, the second conductive portion (22) is used to form a second electrode of a capacitance in the corresponding pixel driving circuit, at least two adjacent second conductive portions (22) distributed in a first direction (X) are connected to form a conductive line (2), the fifth conductive layer is located on the side where the second conductive layer is away from the base substrate (90), the fifth conductive layer includes a plurality of power lines (VDD), the orthogonal projection of the plurality of power lines (VDD) on the base substrate is distributed at intervals along the first direction (X) and extends along the second direction (Y), and at least one conductive line (2) is connected to the plurality of power lines (VDD). The display panel improves excellent display uniformity.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a display panel and a display device. [Background technology]

[0002] In the related art, the display panel provides a power supply terminal to the pixel driving circuit through a power line, but the power line itself has a voltage drop, so there is a voltage difference between the power supply terminals at different positions on the display panel, which further causes the display of the display panel to be uneven.

[0003] It should be noted that the information disclosed in the above background art section is used only to enhance understanding of the background of the present disclosure and may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] One aspect of the present disclosure provides a display panel, the display panel including a plurality of pixel driving circuits arranged and distributed along a first direction and a second direction, the first direction and the second direction intersecting, the pixel driving circuits including a driving transistor and a capacitor, a first electrode of the capacitor connected to a gate of the driving transistor and a second electrode of the capacitor connected to a power line, the display panel further including a base substrate, a second conductive layer, and a fifth conductive layer, the second conductive layer being located on one side of the base substrate, the second conductive layer including a plurality of second conductive portions, the plurality of second conductive portions being provided in one-to-one correspondence with the plurality of pixel driving circuits, the second conductive portions being used to form second electrodes of the capacitors in the corresponding pixel driving circuits, and at least two adjacent second conductive portions distributed in the first direction being sequentially connected to form a conductive line. The fifth conductive layer is located on the side of the second conductive layer away from the base substrate, and the fifth conductive layer includes a plurality of the power supply lines, the orthogonal projections of the plurality of power supply lines onto the base substrate being distributed at intervals along the first direction and extending along the second direction, and at least one of the conductive lines being connected to a plurality of the power supply lines.

[0005] In one embodiment of the present disclosure, the second conductive layer further includes a plurality of first connection portions, each connected between two of the second conductive portions adjacent in the first direction. The display panel further includes a first active layer and a light-shielding layer. The first active layer is located between the base substrate and the second conductive layer, and includes a plurality of third active portions, each of which corresponds one-to-one to a plurality of the pixel driving circuits, and the third active portions are used to form channel regions of the driving transistors in the corresponding pixel driving circuits. a light-shielding layer is located between the base substrate and the first active layer, the light-shielding layer includes a plurality of light-shielding portions and a plurality of second connection portions, and is provided in one-to-one correspondence with a plurality of the pixel driving circuits, the orthogonal projection of the light-shielding portion onto the base substrate covers the orthogonal projection of the third active portion of the corresponding pixel driving circuit onto the base substrate, the second connection portion is connected between two of the light-shielding portions adjacent to each other in the first direction, the size of the orthogonal projection of the second connection portion onto the base substrate in the second direction is smaller than the size of the orthogonal projection of the light-shielding portion onto the base substrate in the second direction, and between two adjacent pixel driving circuits of the same group, the orthogonal projection of the second connection portion onto the base substrate and the orthogonal projection of the first connection portion onto the base substrate at least partially overlap.

[0006] In one embodiment of the present disclosure, the display panel includes a plurality of overlapping units distributed along the first direction and the second direction, each of the overlapping units including two of the pixel driving circuits, the two pixel driving circuits including a first pixel driving circuit and a second pixel driving circuit distributed along the first direction, the first pixel driving circuit and the second pixel driving circuit being arranged in mirror symmetry, the plurality of first connection portions include first sub-connections, the first sub-connections are connected between two of the second conductive portions in the overlapping units adjacent to each other in the first direction, and a size of an orthogonal projection of the first sub-connections onto the base substrate in the second direction is smaller than a size of an orthogonal projection of the second conductive portions onto the base substrate in the second direction.

[0007] In one embodiment of the present disclosure, between two adjacent pixel driving circuits in the same group, the orthogonal projection of the first sub-connection portion onto the base substrate is located at the orthogonal projection of the second connection portion onto the base substrate.

[0008] In an embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor connected to the gate of the driving transistor and a second pole connected to a first initial signal line, a first pole of the second transistor connected to the gate of the driving transistor and a second pole of the second transistor connected to the second pole of the driving transistor, the display panel further includes a second active layer, the second active layer being located between the second conductive layer and the fifth conductive layer, the second active layer including a first active portion and a second active portion, the first active portion being used to form a channel region of the first transistor, and the second active portion being connected to the first active portion and used to form the channel region of the second transistor, the power supply line including a second extension portion, an orthogonal projection of the second extension portion onto the base substrate covering an orthogonal projection of the first active portion onto the base substrate and an orthogonal projection of the second active portion onto the base substrate.

[0009] In one embodiment of the present disclosure, the power supply line further includes a first extension portion and a third extension portion, the second extension portion is connected between the first extension portion and the third extension portion, the size of the orthogonal projection of the second extension portion onto the base substrate in the first direction is larger than the size of the orthogonal projection of the first extension portion onto the base substrate in the first direction, the size of the orthogonal projection of the second extension portion onto the base substrate in the first direction is larger than the size of the orthogonal projection of the third extension portion onto the base substrate in the first direction, the size of the orthogonal projection of the second extension portion onto the base substrate in the first direction is L1, the size of the orthogonal projection of the second extension portion onto the base substrate in the second direction is L2, and L1 / L2 is 1 / 2 or less.

[0010] In one embodiment of the present disclosure, the second extension portion has a notch or an openwork structure formed thereon.

[0011] In one embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor being connected to a data line and a second electrode of the fourth transistor being connected to the first electrode of the driving transistor; the display panel further includes a first active layer, a first conductive layer, and a third conductive layer, the first active layer being located between the base substrate and the second conductive layer, the first active layer including a fourth active portion, the fourth active portion being used to form a channel region of the fourth transistor; the first conductive layer being located between the first active layer and the second conductive layer, the first conductive layer including a second gate line, and an orthogonal projection of the second gate line onto the base substrate covering an orthogonal projection of the fourth active portion onto the base substrate; the second extension portion extends along the first direction, a portion of the second gate line is used to form a gate of the fourth transistor, a third conductive layer is located between the second active layer and a fifth conductive layer, the third conductive layer includes a first reset signal line, an orthogonal projection of the first reset signal line onto the base substrate covers an orthogonal projection of the first active portion onto the base substrate, a portion of the first reset signal line is used to form a gate of the first transistor, the notch is formed on a side edge where the second extension portion faces the fourth active portion, and the orthogonal projection of the notch onto the base substrate is located between the orthogonal projection of the second gate line onto the base substrate and the orthogonal projection of the first reset signal line onto the base substrate.

[0012] In one embodiment of the present disclosure, the plurality of first connection portions further include a second sub-connection portion, and the second sub-connection portion is connected between two of the second conductive portions in the same duplicate unit. The pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor connected to the power supply line and a second pole of the fifth transistor connected to the first pole of the driving transistor. The first active layer includes a fifth active portion and an eighth active portion, the fifth active portion being used to form a channel region of the fifth transistor, and the eighth active portion being connected to a side of the fifth active portion away from the third active portion. The display panel further includes a first conductive layer and a fourth conductive layer, wherein the first conductive layer is located between the first active layer and the second conductive layer, the first conductive layer includes an enable signal line, the orthogonal projection of the enable signal line onto the base substrate extending along the first direction and covering the orthogonal projection of the fifth active portion onto the base substrate, a portion of the enable signal line being used to form a gate of the fifth transistor, the fourth conductive layer is located between the second conductive layer and the fifth conductive layer, and the fourth conductive layer includes a first bridge portion, the first bridge portion being connected to an eighth active portion in the first pixel driving circuit, an eighth active portion in the second pixel driving circuit, and a second sub-connection portion between the first pixel driving circuit and the second pixel driving circuit, respectively, via vias, and the first bridge portion being connected to the power line via vias.

[0013] In one embodiment of the present disclosure, the first bridge portion is formed with an openwork portion.

[0014] In one embodiment of the present disclosure, the orthogonal projection of the openwork portion onto the base substrate and the orthogonal projection of the enable signal line onto the base substrate at least partially overlap.

[0015] In one embodiment of the present disclosure, the second direction is a column direction, one power supply line is provided corresponding to the pixel driving circuit of each column, and the power supply line in the first pixel driving circuit and the power supply line in the second pixel driving circuit are connected to the first bridge portion via vias, respectively. The first bridge portion includes a first via contact portion, a second via contact portion, a third via contact portion, a fourth via contact portion, and a fifth via contact portion, the first via contact portion is connected to the second sub-connection portion via a via, the second via contact portion and the first via contact portion are provided opposite to each other in the second direction and are connected to an eighth active portion in the first pixel driving circuit via a via, the third via contact portion and the first via contact portion are provided opposite to each other in the second direction and are connected to an eighth active portion in the second pixel driving circuit via a via, and the fourth via contact portion is connected between the first via contact portion and the second via contact portion and is connected to a power supply line in the first pixel driving circuit via a via, the fifth via contact portion is connected between the first via contact portion and the third via contact portion and is connected to a power supply line in the second pixel driving circuit via a via, the fifth via contact portion and the fourth via contact portion are arranged opposite each other in the first direction, and the openwork portion is formed by being surrounded by the first via contact portion, the second via contact portion, the third via contact portion, the fourth via contact portion, and the fifth via contact portion.

[0016] In one embodiment of the present disclosure, the first active layer further includes a plurality of ninth active sections, which are arranged in one-to-one correspondence with the plurality of overlapping units, and in the same overlapping unit, the ninth active section is connected between the eighth active section in the first pixel driving circuit and the eighth active section in the second pixel driving circuit.

[0017] In one embodiment of the present disclosure, the first bridge part is mirror symmetrical with respect to a mirror symmetry plane of the first pixel driving circuit and the second pixel driving circuit.

[0018] In one embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a sixth transistor, and a seventh transistor, a first electrode of the fourth transistor connected to a data line, a second electrode of the fourth transistor connected to a first electrode of the driving transistor, a first electrode of the sixth transistor connected to a second electrode of the driving transistor, a first electrode of the seventh transistor connected to a second electrode of the sixth transistor, and a second electrode of the seventh transistor connected to a second initial signal line. The display panel further includes a first active layer and a first conductive layer. a first active layer located between the base substrate and the second conductive layer, the first active layer including a third active portion, a fourth active portion, a sixth active portion, and a seventh active portion, the third active portion being used to form a channel region of the drive transistor, the fourth active portion being connected to one side of the third active portion and being used to form a channel region of the fourth transistor, the sixth active portion being connected to a side of the third active portion away from the fourth active portion and being used to form a channel region of the sixth transistor, the seventh active portion being connected to a side of the sixth active portion away from the third active portion and being used to form a channel region of the seventh transistor, and a first conductive layer being located between the first active layer and the second conductive layer.the first conductive layer includes a second gate line, an enable signal line, a second reset signal line, and a first conductive portion, the orthogonal projection of the second gate line onto the base substrate extends along the first direction and covers the orthogonal projection of the fourth active portion onto the base substrate, a partial structure of the second gate line is used to form a gate of the fourth transistor, the orthogonal projection of the enable signal line onto the base substrate extends along the first direction and covers the orthogonal projection of the sixth active portion onto the base substrate, a partial structure of the enable signal line is used to form the gate of the sixth transistor, the orthogonal projection of the second reset signal line onto the base substrate extends along the first direction and covers the orthogonal projection of the seventh active portion onto the base substrate, a partial structure of the second reset signal line is used to form the gate of the seventh transistor, the orthogonal projection of the first conductive portion onto the base substrate covers the orthogonal projection of the third active portion onto the base substrate, and the first conductive portion is used to form the gate of the drive transistor and the second electrode of the capacitor. Here, in the same pixel driving circuit, the orthogonal projection of the first conductive portion onto the base substrate is located between the orthogonal projection of the second gate line onto the base substrate and the orthogonal projection of the enable signal line onto the base substrate, and the orthogonal projection of the second reset signal line onto the base substrate is located on the side where the orthogonal projection of the enable signal line onto the base substrate is away from the orthogonal projection of the first conductive portion onto the base substrate.

[0019] In one embodiment of the present disclosure, the first direction is a row direction, and the second gate line in the pixel driving circuit of the current row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row.

[0020] In one embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor connected to the gate of the driving transistor and a second pole connected to a first initial signal line, a first pole of the second transistor connected to the gate of the driving transistor and a second pole connected to the second pole of the driving transistor. The display panel further includes a second active layer and a third conductive layer, the second active layer being located between the second conductive layer and the fifth conductive layer, the second active layer including a first active portion and a second active portion, the first active portion being used to form a channel region of the first transistor, and the second active portion being connected to the first active portion and used to form the channel region of the second transistor. a third conductive layer is located between the second active layer and the fifth conductive layer, the third conductive layer including a first reset signal line and a first gate line, the orthogonal projection of the first reset signal line onto the base substrate covering the orthogonal projection of the first active portion onto the base substrate, a portion of the first reset signal line being used to form a top gate of the first transistor, the orthogonal projection of the first gate line onto the base substrate covering the orthogonal projection of the second active portion onto the base substrate, and a portion of the first gate line being used to form a top gate of the second transistor. In the same pixel driving circuit, the orthogonal projection of the first gate line onto the base substrate is located between the orthogonal projection of the first conductive portion onto the base substrate and the orthogonal projection of the second gate line onto the base substrate, and the orthogonal projection of the first reset signal line onto the base substrate is located on a side of the orthogonal projection of the second gate line onto the base substrate away from the orthogonal projection of the first conductive portion onto the base substrate.

[0021] In one embodiment of the present disclosure, the second conductive layer further includes the first initial signal line, a third reset signal line, and a third gate line, wherein the orthogonal projection of the first initial signal line onto the base substrate is located on a side away from the orthogonal projection of the first reset signal line onto the base substrate, the third reset signal line is connected to the first reset signal line through a via, the orthogonal projection onto the base substrate covers the orthogonal projection of the first active portion onto the base substrate, a partial structure of the third reset signal line is used to form a bottom gate of the first transistor, the orthogonal projection of the third gate line onto the base substrate covers the orthogonal projection of the second active portion onto the base substrate, and a partial structure of the third gate line is used to form a bottom gate of the second transistor.

[0022] In one embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the power supply line, a second pole of the fifth transistor is connected to the first pole of the driving transistor, and a gate of the fifth transistor is connected to the enable signal line, the first transistor and the second transistor are N-type transistors, and the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

[0023] In one embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor and a seventh transistor, a first pole of the sixth transistor is connected to a second pole of the driving transistor, a first pole of the seventh transistor is connected to a second pole of the sixth transistor, and a second pole of the seventh transistor is connected to a second initial signal line, and the fourth conductive layer further includes the second initial signal line.

[0024] In one embodiment of the present disclosure, all of the second conductive portions distributed in the first direction are sequentially connected to form the conductive lines, and each of the conductive lines is connected to each of the power supply lines.

[0025] One aspect of the present disclosure provides a display device including the above-described display panel.

[0026] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0027] The drawings herein are incorporated into the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without paying creative labor.

[0028] [Figure 1] FIG. 1 is a schematic diagram illustrating a circuit configuration of a pixel driving circuit in the related art. [Figure 2] 2 is a sequence of each node in the driving method of the pixel driving circuit shown in FIG. 1. [Figure 3] 1 is a configuration diagram of an embodiment of a display panel according to the present disclosure. [Figure 4] FIG. 4 is a diagram showing the configuration of a second conductive layer in FIG. 3. [Figure 5] FIG. 4 is a diagram showing the configuration of a fifth conductive layer in FIG. 3. [Figure 6] FIG. 10 is a configuration diagram of another embodiment of a display panel according to the present disclosure. [Figure 7] FIG. 10 is a configuration diagram of another embodiment of a display panel according to the present disclosure. [Figure 8] FIG. 10 is a configuration diagram of another embodiment of a display panel according to the present disclosure. [Figure 9] FIG. 10 is a configuration diagram of another embodiment of a display panel according to the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating the configuration of a light-shielding layer in FIG. [Figure 11] FIG. 10 is a diagram showing the configuration of a first active layer in FIG. [Figure 12] FIG. 10 is a diagram showing the configuration of a first conductive layer in FIG. [Figure 13] FIG. 10 is a diagram showing the configuration of a second conductive layer in FIG. [Figure 14] FIG. 10 is a diagram showing the configuration of a second active layer in FIG. [Figure 15] FIG. 10 is a diagram showing the configuration of a third conductive layer in FIG. [Figure 16] FIG. 10 is a diagram showing the configuration of a fourth conductive layer in FIG. [Figure 17] FIG. 10 is a diagram showing the configuration of a fifth conductive layer in FIG. [Figure 18] FIG. 10 is a diagram showing the configuration of a light-shielding layer and a first active layer in FIG. [Figure 19] FIG. 10 is a diagram showing the configuration of a light-shielding layer, a first active layer, and a first conductive layer in FIG. [Figure 20] FIG. 10 is a diagram showing the configuration of the light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG. [Figure 21] FIG. 10 is a diagram showing the configuration of the light-shielding layer, first active layer, first conductive layer, second conductive layer, and second active layer in FIG. [Figure 22] FIG. 10 is a diagram showing the configuration of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, and third conductive layer in FIG. 9. [Figure 23] FIG. 10 is a diagram showing the configuration of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in FIG. 9. [Figure 24] 10 is a cross-sectional view of a portion of the display panel of the present disclosure taken along line AA in FIG. 9. [Figure 25] FIG. 10 is a configuration diagram of another embodiment of a display panel according to the present disclosure. [Figure 26] FIG. 26 is a diagram showing the configuration of a fourth conductive layer in FIG. 25. [Figure 27] FIG. 26 is a diagram showing the configuration of a fifth conductive layer in FIG. 25. [Figure 28] 26 is a diagram showing the configuration of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in FIG. 25. FIG. [Figure 29] FIG. 10 is a structural diagram of a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another embodiment of a display panel of the present disclosure. [Figure 30]FIG. 10 is a diagram illustrating the configuration of a light-shielding layer in another embodiment of a display panel according to the present disclosure. [Figure 31] FIG. 10 is a diagram illustrating the configuration of a light-shielding layer in another embodiment of a display panel according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] Next, exemplary embodiments will be described in more detail with reference to the drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood as being limited to the examples described herein. On the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete and to fully convey the concept of the exemplary embodiments to those skilled in the art. Since the same reference numerals in the drawings represent the same or similar structures, detailed descriptions will be omitted.

[0030] The terms "a," "one," and "said" are used to indicate that one or more elements / components / etc. are present; the terms "comprise" and "have" are used to denote an open inclusion, meaning that other elements / components / etc. may be present in addition to the listed elements / components / etc.

[0031] 1 is a schematic diagram of a circuit configuration of a pixel driving circuit in the related art. This pixel driving circuit may include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Here, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2. The first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM. The gate of the driving transistor T3 is connected to node N. The first pole of the second transistor T2 is connected to node N, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1. The sixth transistor T6 has a first electrode connected to the second electrode of the driving transistor T3, a second electrode connected to the first electrode of the seventh transistor T7, and a gate connected to the enable signal terminal EM. The seventh transistor T7 has a second electrode connected to the second initial signal terminal Vinit2, and a gate connected to the second reset signal terminal Re2. The first transistor T1 has a first electrode connected to the node N, a second electrode connected to the first initial signal terminal Vinit1, and a gate connected to the first reset signal terminal Re1. The capacitor C has a first electrode connected to the node N and a second electrode connected to the first power supply terminal VDD. The pixel driving circuit can connect an OLED to drive the OLED to emit light. The OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Here, the first transistor T1 and the second transistor T2 may be N-type transistors, for example, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, which have a small leakage current, so that the node N can be prevented from leaking current through the first transistor T1 and the second transistor T2 during the light-emitting stage.At the same time, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon transistors, which have high carrier mobility and are therefore advantageous for realizing a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual circumstances.

[0032] 2 shows a timing chart of each node in the driving method of the pixel driving circuit of FIG. 1. Here, G1 indicates the timing of the first gate driving signal terminal G1, G2 indicates the timing of the second gate driving signal terminal G2, Re1 indicates the timing of the first reset signal terminal Re1, Re2 indicates the timing of the second reset signal terminal Re2, EM indicates the timing of the enable signal terminal EM, and Da indicates the timing of the data signal terminal Da. This driving method of the pixel driving circuit can include a first reset stage t1, a compensation stage t2, a second reset stage t3, and a light-emitting stage t4. First reset stage t1: The first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. compensation stage t2: the first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Da outputs a driving signal to write a voltage Vdata+Vth (i.e., the sum of voltages Vdata and Vth) to node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3; in the second reset stage t3, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6; light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light according to the voltage Vdata+Vth stored in the capacitor C;

[0033] The equation for the output current of the drive transistor is: I=(μWCox / 2L)(Vgs-Vth) 2

[0034] where I is the output current of the drive transistor, μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, Vgs is the gate-source voltage difference of the drive transistor, and Vth is the threshold voltage of the drive transistor.

[0035] Based on the above formula for the output current of the driving transistor, by introducing the gate voltage Vdata+Vth and the source voltage Vdd of the driving transistor in the pixel driving circuit of the present disclosure into the above formula, the output current I of the driving transistor in the pixel driving circuit of the present disclosure is calculated as follows: I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 This pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current.

[0036] However, in the display panel, the power line for providing the first power end itself has a voltage drop, and there is a voltage difference at the first power end at different positions on the display panel, which causes the display of the display panel to be uneven.

[0037] Based on this, this embodiment provides a display panel, wherein the display panel may include a plurality of pixel driving circuits arranged and distributed along a first direction and a second direction, where the first direction and the second direction intersect, e.g., the first direction is the row direction and the second direction is the column direction. The configuration of the pixel driving circuits in this display panel can be shown in FIG. 1. As shown in FIGS. 3 to 5, this display panel includes a base substrate, a second conductive layer, and a fifth conductive layer. FIG. 3 is a structural diagram of one embodiment of a display panel of the present disclosure, FIG. 4 is a structural diagram of the second conductive layer in FIG. 3, and FIG. 5 is a structural diagram of the fifth conductive layer in FIG. 3. The second conductive layer may be located on one side of the base substrate, the second conductive layer including a plurality of second conductive portions 22 provided in one-to-one correspondence with the plurality of pixel driving circuits, the second conductive portions 22 being used to form second electrodes of the capacitors in the corresponding pixel driving circuits, the plurality of second conductive portions distributed in the first direction X being connected to form conductive lines 2, the fifth conductive layer may be located on the side of the second conductive layer away from the base substrate, the fifth conductive layer including a plurality of power supply lines VDD, the orthogonal projections of the plurality of power supply lines VDD onto the base substrate being distributed along the intervals in the first direction X and extending along the second direction Y, and each conductive line 2 being connectable to a respective power supply line VDD.

[0038] In this embodiment, a plurality of power supply lines VDD and a plurality of conductive lines 2 can form a mesh structure, and the mesh-structured power supply lines have low resistance, which can improve the display uniformity of the display panel.

[0039] 3 and 4, the second conductive layer may further include a plurality of first connection portions 21 connected between adjacent second conductive portions 22 in the first direction. The plurality of second conductive portions 22 distributed at intervals in the first direction X may be connected by the first connection portions to form the conductive line 2. Note that in other exemplary embodiments, the first connection portions 21 may be located in other conductive layers.

[0040] In this embodiment, the power supply line VDD and the conductive line 2 may be connected through a via. As shown in FIG. 3 , the display panel may include a fourth conductive layer that may be located between the second conductive layer and the fifth conductive layer, and the fourth conductive layer may include a plurality of first bridge portions 41. Here, the first bridge portion 41 may be connected to the first connection portion 21 through a via H, the power supply line VDD may be connected to the first bridge portion 41 through the via H, and the power supply line VDD may be connected to the conductive line 2. Note that the black squares in this embodiment represent vias, and only the positions of some of the vias are marked in this embodiment. In addition, in other exemplary embodiments, the power supply line VDD may be directly connected to the second conductive portion through a via.

[0041] In this embodiment, each conductive line 2 can be connected to each power supply line VDD. Note that in other exemplary embodiments, the conductive lines 2 may be connected to only some of the power supply lines VDD. For example, as shown in FIG. 6, which is a structural diagram of another exemplary embodiment of a display panel of the present disclosure, the conductive line 2 in the first row is connected to the power supply lines VDD of the second to fourth columns, and the conductive line 2 in the second row is connected to the power supply lines VDD of the first to third columns, and this display panel can similarly reduce the voltage drop of the power supply lines.

[0042] In this embodiment, all second conductive portions 22 distributed at intervals in the first direction X in the display panel are sequentially connected to form the conductive line 2. Note that in other exemplary embodiments, the conductive line 2 may be formed by connecting only some of the conductive portions 22. For example, FIG. 7 is a structural diagram of another exemplary embodiment of a display panel according to the present disclosure, in which every two adjacent conductive portions 22 in the first direction X are connected to form a conductive line 2. This display panel can similarly reduce the voltage drop of the power supply line. Furthermore, for example, FIG. 8 is a structural diagram of another exemplary embodiment of a display panel according to the present disclosure. Here, a conductive line 2 is formed for every plurality of second conductive portions 22. This display panel includes a plurality of conductive lines 2 distributed along the row and column directions, where the conductive lines 2 in adjacent rows and columns are alternately distributed in the row direction. That is, the orthogonal projection of two conductive lines 2 located in adjacent rows and columns onto the base substrate moves in the column direction to intersect with the covered area. The alternately arranged conductive lines 2 can commonly connect at least two power supply lines VDD. This display panel also reduces the voltage drop in the power cable.

[0043] The display panel of the present disclosure may also include pixel drive circuits with other configurations in which capacitances are connected to the power supply lines, and the corresponding display panel may adopt the above-mentioned configurations to reduce the voltage drop in the power supply lines themselves.

[0044] In this embodiment, it can be understood that the orthogonal projection of a structure onto the base substrate extends in one direction, and the entire orthogonal projection of this structure onto the base substrate extends in that direction; that is, the orthogonal projection of this structure onto the base substrate may extend linearly or be bent along that direction. Different structural portions in a film layer of the same structure (e.g., the second conductive layer, the fifth conductive layer) can be formed by a primary patterning process. It can be understood that structural layer A is located on the side of structural layer B away from the substrate, and structural layer A is formed on the side of structural layer B away from the substrate. When structural layer B is a patterned structure, some structures in structural layer A may be located at the same physical height as structural layer B or may be lower than the physical height of structural layer B, where the substrate is the height reference.

[0045] This embodiment provides another display panel, which includes a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked, and an insulating layer may be provided between the layers. As shown in Figures 9 to 23, Figure 9 is a structural diagram of another embodiment of the display panel of the present disclosure, Figure 10 is a structural diagram of the light-shielding layer in Figure 9, Figure 11 is a structural diagram of the first active layer in Figure 9, Figure 12 is a structural diagram of the first conductive layer in Figure 9, Figure 13 is a structural diagram of the second conductive layer in Figure 9, Figure 14 is a structural diagram of the second active layer in Figure 9, Figure 15 is a structural diagram of the third conductive layer in Figure 9, Figure 16 is a structural diagram of the fourth conductive layer in Figure 9, Figure 17 is a structural diagram of the fifth conductive layer in Figure 9, and Figure 18 is a structural diagram of the light-shielding layer and the first active layer in Figure 9. 19 is a structural diagram of the light-shielding layer, first active layer, and first conductive layer in Fig. 9, Fig. 20 is a structural diagram of the light-shielding layer, first active layer, first conductive layer, and second conductive layer in Fig. 9, Fig. 21 is a structural diagram of the light-shielding layer, first active layer, first conductive layer, second conductive layer, and second active layer in Fig. 9, Fig. 22 is a structural diagram of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, and third conductive layer in Fig. 9, and Fig. 23 is a structural diagram of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in Fig. 9. The display panel can include a plurality of pixel driving circuits shown in Fig. 1. 9, the plurality of pixel driving circuits include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 can be configured as symmetrical mirrors. Here, the first pixel driving circuit P1 and the second pixel driving circuit P2 can form a duplicated unit, and the display panel can include a plurality of duplicated units arranged and distributed in the first direction X and the second direction Y. Here, the first direction X and the second direction Y can intersect, for example, the first direction is the row direction and the second direction is the column direction.

[0046] 9, 10 and 18, the light-shielding layer may include a plurality of light-shielding portions 61 distributed in a first direction X and second connection portions 62 connected between the light-shielding portions 61. The light-shielding layer may have a conductor structure, for example, the light-shielding layer may be a light-shielding metal layer.

[0047] As shown in Figures 9, 11 and 19, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78 and a ninth active portion 79. Here, the third active unit 73 can be used to form the channel region of the driving transistor T3, the fourth active unit 74 can be used to form the channel region of the fourth transistor T4, the fifth active unit 75 can be used to form the channel region of the fifth transistor T5, the sixth active unit 76 can be used to form the channel region of the sixth transistor T6, the seventh active unit 77 can be used to form the channel region of the seventh transistor T7, the eighth active unit 78 is connected to the side of the fifth active unit 75 away from the third active unit 73, and the ninth active unit 79 is connected between the eighth active unit 78 of the first pixel driving circuit P1 and the eighth active unit 78 of the second pixel driving circuit P2. Here, the eighth active region 78 can be used to form the first pole of the fifth transistor. In this embodiment, by connecting the eighth active regions in two adjacent pixel driving circuits via the ninth active region 79, the voltage difference between the first power terminals of the adjacent pixel driving circuits can be reduced. As shown in FIG. 18, the orthogonal projection of the light-shielding region 61 on the base substrate can cover the orthogonal projection of the third active region 73 on the base substrate, thereby reducing the influence of light irradiation on the driving transistor characteristics. The first active region can be formed of a polycrystalline silicon material. Accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0048] As shown in FIGS. 9, 12, and 19, the first conductive layer may include a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2. The second gate line G2 may be used to provide the second gate drive signal terminal of FIG. 1, the enable signal line EM may be used to provide the enable signal terminal of FIG. 1, and the second reset signal line Re2 may be used to provide the second reset signal terminal of FIG. 1. The orthogonal projections of the second gate line G2 onto the base substrate, the orthogonal projections of the enable signal line EM onto the base substrate, and the orthogonal projections of the second reset signal line Re2 onto the base substrate may all extend in the first direction X. Here, the orthogonal projection of the second gate line G2 onto the base substrate covers the orthogonal projection of the fourth active portion 74 onto the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of a fourth transistor. The orthogonal projection of the enable signal line EM onto the base substrate covers the orthogonal projection of the fifth active unit 75 onto the base substrate and the orthogonal projection of the sixth active unit 76 onto the base substrate, and a portion of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthogonal projection of the second reset signal line Re2 onto the base substrate covers the orthogonal projection of the seventh active unit 77 onto the base substrate, and a portion of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthogonal projection of the first conductive unit 11 onto the base substrate covers the orthogonal projection of the third active unit 73 onto the base substrate, and the first conductive unit 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor. The first direction X may be the row direction, and as shown in FIG. 19 , the second gate line G2 in a pixel driving circuit of a current row may be multiplexed as the second reset signal line Re2 in a pixel driving circuit of a previous row. This configuration makes it possible to increase the integration density of the pixel drive circuit and reduce the layout area of ​​the pixel drive circuit.The light-shielding layer can be connected to a stable power supply terminal, for example, the light-shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 1, and the light-shielding portion 61 can act as a constant voltage for the first conductive portion 11, thereby reducing voltage fluctuations at the gate of the driving transistor T3 during the light-emitting phase. Furthermore, in this display panel, the first active layer can be made conductive using the first conductive layer as a mask, that is, the region of the first active layer covered with the first conductive layer can form the channel region of the transistor, and the region not covered with the first conductive layer can form a conductive structure.

[0049] 9, 13, and 20, the second conductive layer may include a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G1, and a plurality of second conductive portions 22. Here, the first initial signal line Vinit1 may be used to provide the first initial signal terminal of FIG. 1, the third reset signal line 2Re1 may be used to provide the first reset signal terminal of FIG. 1, and the third gate line 2G1 may be used to provide the first gate driving signal terminal of FIG. 1. The orthogonal projections of the first initial signal line Vinit1, the third reset signal line 2Re1, and the third gate line 2G1 onto the base substrate may all extend along a first direction X. 13, the second conductive layer may further include a plurality of first connection portions, where the plurality of first connection portions may include a second sub-connection portion 212 connected between two second conductive portions 22 of one overlapping unit and a first sub-connection portion 211 connected between two second conductive portions 22 of an adjacent overlapping unit. As shown in FIG. 20, between two adjacent pixel driving circuits in the same group, the orthogonal projection of the first sub-connection portion 211 onto the base substrate and the orthogonal projection of the second sub-connection portion 62 onto the base substrate may at least partially overlap, and the orthogonal projection of the second sub-connection portion 212 onto the base substrate and the orthogonal projection of the second connection portion 62 onto the base substrate may at least partially overlap. This configuration reduces the light-blocking effect of the first connection portion on the display panel and provides high transmittance for the display panel. Here, the size of the orthogonal projection of the first sub-connection portion 211 onto the base substrate in the second direction Y may be smaller than the size of the orthogonal projection of the second conductive portion 22 onto the base substrate in the second direction Y, and the orthogonal projection of the first sub-connection portion 211 onto the base substrate may be located at the orthogonal projection of the second connecting portion 62 onto the base substrate, which configuration can significantly improve the transmittance of the display panel. In this embodiment, the size of the orthogonal projection of the second sub-connection portion 212 onto the base substrate in the second direction Y is equal to the size of the orthogonal projection of the second conductive portion 22 onto the base substrate in the second direction Y in order to reduce the self-resistance of the conductive strip extending in the row direction formed by the second conductive portion 22.In other exemplary embodiments, the size of the second sub-connection portion 212 in the second direction Y when orthogonally projected onto the base substrate may be smaller than the size of the second conductive portion 22 in the second direction Y when orthogonally projected onto the base substrate. In other embodiments, the first sub-connection portion 211 may not be provided between two second conductive portions 22 in adjacent overlapping units, i.e., the two second conductive portions 22 in adjacent overlapping units may be spaced apart in the first direction X.

[0050] As shown in Figures 9, 14, and 21, the second active layer includes an active portion 81, which includes a first active portion 811 and a second active portion 812, which can be used to form the channel region of the first transistor T1. The second active portion 812 can be used to form the channel region of the second transistor T2. Here, the second active layer can be formed from indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors. The orthogonal projection of the third gate line 2G1 onto the base substrate can cover the orthogonal projection of the second active portion 812 onto the base substrate, and a portion of the structure of the third gate line 2G1 can be used to form the bottom gate of the second transistor T1. The orthogonal projection of the third reset signal line 2Re1 onto the base substrate can cover the orthogonal projection of the first active portion 811 onto the base substrate, and a portion of the structure of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0051] As shown in Figures 9, 15, and 22, the third conductive layer may include a first reset signal line 3Re1 and a first gate line 3G1. The orthogonal projection of the first reset signal line 3Re1 onto the base substrate and the orthogonal projection of the first gate line 3G1 onto the base substrate may both extend in a first direction X. The first reset signal line 3Re1 may be used to provide the first reset signal terminal of Figure 1. The orthogonal projection of the first reset signal line 3Re1 onto the base substrate may cover the orthogonal projection of the first active portion 811 onto the base substrate. A portion of the structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 may be connected to the third reset signal terminal 2Re1 through a via located in a wiring region at the edge of the display panel. The first gate line 3G1 can be used to provide the first gate driving signal terminal in FIG. 1 , and the orthogonal projection of the first gate line 3G1 onto the base substrate can cover the orthogonal projection of the second active portion 812 onto the base substrate. A portion of the first gate line 3G1 can be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 can connect to the third gate line 2G1 through a via located in a wiring region at the edge of the display panel. As shown in FIGS. 9 and 22 , in the same pixel driving circuit, the orthogonal projection of the first conductive portion 11 onto the base substrate can be located between the orthogonal projection of the first gate line 3G1 onto the base substrate and the orthogonal projection of the enable signal line EM onto the base substrate. The orthogonal projection of the first reset signal line 3Re1 onto the base substrate can be located away from the orthogonal projection of the first gate line 3G1 onto the base substrate. The orthogonal projection of the second gate line G2 onto the base substrate can be located between the orthogonal projection of the first gate line 3G1 onto the base substrate and the orthogonal projection of the first reset signal line 3Re1 onto the base substrate. The orthogonal projection of the second reset signal line Re2 onto the base substrate can be located on the side where the orthogonal projection of the enable signal line EM onto the base substrate is away from the orthogonal projection of the first conductive portion 11 onto the base substrate.In addition, this display panel can conduct the second active layer using the third conductive layer as a mask, i.e., the area of ​​the second active layer covered with the third conductive layer can form the channel region of the transistor, and the area not covered with the third conductive layer can form the conductor structure.

[0052] 9, 16, and 23, the fourth conductive layer may include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, and a second initial signal line Vinit2. Here, the first bridge portion 41 may connect the second sub-connection portion 212 through two vias, and may connect the eighth active portion 78 in the first pixel driving circuit P1 to the eighth active portion 78 in the second pixel driving circuit P2 through vias, thereby connecting the first electrode of the fifth transistor to the second electrode of the capacitor C. The first bridge portion 41 may be mirror-symmetrical with respect to the mirror-symmetric plane of the first pixel driving circuit P1 and the second pixel driving circuit P2. The second bridge portion 42 connects the first active layer between the sixth active portion 76 and the seventh active portion 77 through a via, connecting the second pole of the sixth transistor T6 to the first pole of the seventh transistor T7. The second bridge portion 42 can be used to connect the first electrodes of the light-emitting units in the display panel. The third bridge portion 43 connects the first active layer between the sixth active portion 76 and the third active portion 73 and the second active layer on the side of the second active portion 812 away from the first active portion 811 through a via, connecting the second pole of the second transistor T2, the first pole of the sixth transistor T6, and the second pole of the drive transistor T3. The fourth bridge portion 44 connects the second active layer between the first active portion 811 and the second active portion 812 and the first conductive portion 11 through a via, connecting the gates of the first and drive transistors of the second transistor T2. 13, an opening 221 is formed in the second conductive portion 22, and the orthogonal projection of the via connected between the first conductive portion 11 and the fourth bridge portion 44 onto the base substrate is located within the orthogonal projection of the opening 221 onto the base substrate so that the conductive structure in the via and the second conductive portion 22 are insulated from each other. The fifth bridge portion 45 connects the second active layer on the side of the first active portion 811 away from the second active portion 812 to the first initial signal line Vinit1 through the vias, thereby connecting the second pole of the first transistor to the first initial signal terminal.The sixth bridge section 46 can connect the first active layer of the fourth active section 74 away from the third active section 73 through a via to connect the first pole of the fourth transistor. The second initial signal line Vinit2 can be used to provide the second initial signal terminal of FIG. 1, and the second initial signal line Vinit2 can connect the first active layer of the seventh active section 77 away from the sixth active section 76 through a via to connect the second pole of the seventh transistor to the second initial signal terminal.

[0053] As shown in FIGS. 9 and 17, the fifth conductive layer may include a plurality of power lines VDD, a plurality of data lines Da, and a seventh bridge portion 57. Here, the orthogonal projection of the power lines VDD onto the base substrate and the orthogonal projection of the data lines Da onto the base substrate may both extend along the second direction Y. The power lines VDD may be used to provide the first power terminal of FIG. 1, and the data lines Da may be used to provide the data signal terminal of FIG. 1. As shown in FIG. 9, each column of pixel driving circuits may be provided with a corresponding power line. The power line VDD of the first pixel driving circuit P1 may be connected to the first bridge portion 41 through a via, and the power line VDD of the second pixel driving circuit P2 may be connected to the same first bridge portion 41 through a via, and may be connected to the first pole of the fifth transistor and the first power terminal. The data line Da may connect the sixth bridge portion 46 through a via, connecting the first pole of the fourth transistor and the data signal terminal. Here, only a portion of the data line Da is shown, and the orthogonal projection of the data line Da onto the base substrate extends along the second direction Y. The seventh bridge portion 57 can be connected to the second bridge portion 42 through a via to connect the first pole of the seventh transistor, and the seventh bridge portion 57 can be used to connect the first electrode of the light-emitting unit. Note that in other exemplary embodiments, multiple columns of pixel driving circuits can also be configured to correspond to one power line. As shown in FIG. 17 , the power supply line VDD may include a first extension portion VDD1, a second extension portion VDD2, and a third extension portion VDD3, the second extension portion VDD2 being connected between the first extension portion VDD1 and the third extension portion VDD3, and the size of the second extension portion VDD2 in the first direction X when orthogonally projected onto the base substrate may be larger than the size of the first extension portion VDD1 in the first direction X when orthogonally projected onto the base substrate, and the size of the second extension portion VDD2 in the first direction X when orthogonally projected onto the base substrate may be larger than the size of the third extension portion VDD3 in the first direction X when orthogonally projected onto the base substrate.The orthogonal projection of the second extension portion VDD2 onto the base substrate can cover the orthogonal projection of the first active portion 811 onto the base substrate and the orthogonal projection of the second active portion 812 onto the base substrate, and the second extension portion VDD2 can reduce the characteristic effects of light irradiation on the first transistor T1 and the second transistor T2.

[0054] 9 and 23, the black blocks drawn on the side of the fourth conductive layer away from the base substrate indicate vias connected to other layers facing the fourth conductive layer toward the substrate, and the black blocks drawn on the side of the fifth conductive layer away from the base substrate indicate vias connected to other layers facing the fifth conductive layer toward the base substrate. These black blocks indicate only the location of the vias, and different vias indicated by black blocks in different positions can penetrate different insulating layers. For example, a via connected between the first bridge portion 41 and the second sub-connection portion 212 can penetrate the insulating layer between the second conductive layer and the fourth conductive layer, a via connected between the first bridge portion 41 and the eighth active portion 78 can penetrate the insulating layer between the first active layer and the fourth conductive layer, a via connected between the second active layer on the side away from the first active portion 811 of the second active portion 812 and the third bridge portion 43 can penetrate the insulating layer between the fourth conductive layer and the second active layer, a via connected between the fourth bridge portion 44 and the first conductive portion 11 can penetrate the insulating layer between the fourth conductive layer and the first conductive layer, and a via connected between the power supply line VDD and the first bridge portion 41 can penetrate the insulating layer between the fourth conductive layer and the fifth conductive layer. Note that in the following examples, the drawing method and meaning of the vias in the figures are the same as in this example.

[0055] Figure 24 is a partial cross-sectional view of the display panel taken along dashed line AA in Figure 9. As shown in Figure 24, the display panel further includes a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a second dielectric layer 97, a passivation layer 98, and a flat layer 99, in which a base substrate 90, a light-shielding layer, the first insulating layer 91, a first active layer, the second insulating layer 92, a first conductive layer, the third insulating layer 93, a second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the second dielectric layer 97, the fourth conductive layer, the passivation layer 98, the flat layer 99, and the fifth conductive layer are sequentially stacked. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may have a single-layer structure or a multi-layer structure, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 may be at least one of silicon nitride, silicon oxide, and silicon nitride. The first dielectric layer 96, the second dielectric layer 97, and the passivation layer 98 may be silicon nitride layers. The material of the planar layer 99 may be an organic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or silicon-on-glass (SOG). The base substrate 90 may be formed by sequentially stacking a glass substrate, a barrier layer, and a polyimide layer, which may be inorganic materials. The materials of the first conductive layer, the second conductive layer, and the third conductive layer may be one or an alloy of molybdenum, aluminum, copper, titanium, and niobium, or a molybdenum / titanium alloy or laminate, etc. The materials of the fourth conductive layer and the fifth conductive layer may include a metal material, such as one or an alloy of molybdenum, aluminum, copper, titanium, and niobium, or a molybdenum / titanium alloy or laminate, etc., or a titanium / aluminum / titanium laminate, etc. In another exemplary embodiment, only a planar layer may be provided between the fourth and fifth conductive layers in the display panel, and no passivation layer may be provided.

[0056] 25 is a structural diagram of another exemplary embodiment of a display panel of the present disclosure, which may include a plurality of pixel driving circuits shown in FIG. 1, including a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry. The display panel may include a base substrate, a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are stacked in sequence.

[0057] 25 has the same light-shielding layer layout structure as the light-shielding layer layout structure of the display panel shown in Fig. 9, and the light-shielding layer may include two light-shielding portions 61 distributed in the first direction X and a second connection portion 62 connected between the light-shielding portions 61. The light-shielding layer may have a conductor structure, and may be, for example, a light-shielding metal layer.

[0058] The first active layer in the display panel shown in Figure 25 has the same layout structure as the first active layer in the display panel shown in Figure 9, and the first active layer can similarly include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, and a ninth active portion 79.

[0059] The first conductive layer in the display panel shown in Figure 25 has the same layout structure as the first conductive layer in the display panel shown in Figure 9, and the first conductive layer can also include a first conductive portion 11, a second gate line G2, an enable signal line EM, and a second reset signal line Re2.

[0060] The second conductive layer in the display panel shown in Figure 25 has the same layout structure as the second conductive layer in the display panel shown in Figure 9, and the second conductive layer can also include a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G1, and a plurality of second conductive portions 22.

[0061] The second active layer in the display panel shown in Figure 25 has the same layout structure as the second active layer in the display panel shown in Figure 9, and the second active layer can include an active portion 81 which can include a first active portion 811 and a second active portion 812.

[0062] The third conductive layer in the display panel shown in Figure 25 has the same layout structure as the third conductive layer in the display panel shown in Figure 9, and the third conductive layer can also include a first reset signal line 3Re1 and a first gate line 3G1.

[0063] The display panel shown in Fig. 25 differs from the display panel shown in Fig. 9 only in the structural layout of the fourth conductive layer and the fifth conductive layer. As shown in Figs. 26 to 28, Fig. 26 is a configuration diagram of the fourth conductive layer in Fig. 25, Fig. 27 is a configuration diagram of the fifth conductive layer in Fig. 25, and Fig. 28 is a configuration diagram of the light-shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in Fig. 25.

[0064] As shown in Figures 25, 26, and 28, the fourth conductive layer may also include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, and a second initial signal line Vinit2. The first bridge portion 41 in Figure 26 has a different layout configuration from the first bridge portion 41 in Figure 16. As shown in Figure 26, the first bridge portion 41 may have an openwork portion 410, and at least a portion of the area where the openwork portion 410 is located may form a light-transmitting area of ​​the display panel. The light-transmitting area of ​​the display panel can be understood as the area not covered by a light-blocking structure, i.e., the area not covered by the light-blocking layer, first conductive layer, first active layer, second conductive layer, second active layer, third conductive layer, fourth conductive layer, or fifth conductive layer. This configuration can improve the transmittance of the display panel. As shown in Figures 25, 26 and 28, the orthogonal projection of the openwork portion 410 onto the base substrate can also at least partially overlap with the orthogonal projection of the enable signal line EM onto the base substrate, in order to reduce the parasitic capacitance of the enable signal line EM, increase the charging speed of the enable signal line, and increase the response speed of the fifth transistor T5 and the sixth transistor T6.

[0065] 25, 26, and 28, the first bridge portion 41 can include a first via contact portion 411, a second via contact portion 412, a third via contact portion 413, a fourth via contact portion 414, and a fifth via contact portion 415. The first via contact portion 411 can connect the second sub-connection portion 212 through a via, the second via contact portion 412 and the first via contact portion 411 are arranged opposite to each other in the second direction Y and are connected to the eighth active portion 78 in the first pixel driving circuit P1 through a via, the third via contact portion 413 and the first via contact portion 411 are arranged opposite to each other in the second direction Y and are connected to the eighth active portion 78 in the second pixel driving circuit P2 through a via, and the fourth via contact portion 415 can connect the second sub-connection portion 212 through a via, the second via contact portion 412 and the first via contact portion 411 are arranged opposite to each other in the second direction Y and are connected to the eighth active portion 78 in the second pixel driving circuit P2 through a via, and the fourth via contact portion 415 can connect the second sub-connection portion 212 through a via. The via contact 414 is connected between the first via contact 411 and the second via contact 412 and is connected to the power supply line VDD in the first pixel driving circuit P1 through a via, the fifth via contact 415 is connected between the first via contact 411 and the third via contact 413 and is connected to the power supply line VDD in the second pixel driving circuit P2 through a via, and the fifth via contact 415 and the fourth via contact 414 are arranged opposite to each other in the first direction X. Here, the first via contact 411, the second via contact 412, the third via contact 413, the fourth via contact 414, and the fifth via contact 415 can be surrounded to form the openwork portion 410. Here, it can be understood that structure A and structure B are disposed opposite each other in the first direction X, the orthogonal projection of structure A onto the base substrate and the orthogonal projection of structure B onto the base substrate are disposed at an interval in the first direction X, and the area covered by the orthogonal projection of structure A onto the base substrate with infinite movement in the first direction X at least partially overlaps with the area covered by the orthogonal projection of structure B onto the base substrate with infinite movement in the first direction X. Similarly, structure A and structure B are disposed relative to each other in the second direction Y, the orthogonal projection of structure A onto the base substrate and the orthogonal projection of structure B onto the base substrate are disposed at an interval in the second direction Y, and the area covered by the orthogonal projection of structure A onto the base substrate with infinite movement in the second direction Y at least partially coincides with the area covered by the orthogonal projection of structure B onto the base substrate with infinite movement in the second direction Y.

[0066] As shown in FIG. 26 , in the first direction X, the orthogonal projection of the first via contact 411 onto the base substrate, the orthogonal projection of the second via contact 412 onto the base substrate, and the orthogonal projection of the third via contact 413 onto the base substrate can be located between the orthogonal projection of the fourth via contact 414 onto the base substrate and the orthogonal projection of the fifth via contact 415 onto the base substrate, and in the second direction Y, the orthogonal projection of the fourth via contact 414 onto the base substrate and the orthogonal projection of the fifth via contact 415 onto the base substrate can be located between the orthogonal projection of the fourth via contact 414 onto the base substrate and the orthogonal projection of the fifth via contact 415 onto the base substrate. 26 , the orthogonal projection of the fourth via contact 414 onto the base substrate can be located between the orthogonal projection of the first via contact 411 onto the base substrate and the orthogonal projection of the second via contact 412 onto the base substrate, and in the second direction Y, the orthogonal projection of the fourth via contact 414 onto the base substrate and the orthogonal projection of the fifth via contact 415 onto the base substrate can be located between the orthogonal projection of the first via contact 411 onto the base substrate and the orthogonal projection of the third via contact 413 onto the base substrate. The openwork portion 410 can be a closed opening or an open-ring opening. In this embodiment, the openwork portion 410 can be an open opening, and there can be a certain gap between the second via contact 412 and the third via contact 413, as shown in FIG. 26 . In other embodiments, the second via contact 412 and the third via contact 413 can be directly connected to form a closed openwork portion 410.

[0067] As shown in FIGS. 25 and 27, the fifth conductive layer may also include a power supply line VDD, a data line Da, and a seventh bridge portion 57. The fifth conductive layer shown in FIG. 27 differs from the fifth conductive layer shown in FIG. 17 in that the power supply line VDD in FIG. 27 has a different layout structure from the power supply line VDD in FIG. 17. As shown in FIGS. 25 and 27, in the display panel shown in FIG. 25, a notch VDD0 is formed in the second extension portion VDD2, and at least a portion of the region where the notch VDD0 is located can form a light-transmitting region of the display panel to enhance the transmittance of the display panel. The notch VDD0 can be formed on a side of the second extension portion VDD2 facing the fourth active portion 74, and the orthogonal projection of the notch VDD0 onto the base substrate can be located between the orthogonal projection of the second gate line G2 onto the base substrate and the orthogonal projection of the first reset signal line Vinit1 onto the base substrate. In another exemplary embodiment, the notch VDD0 may be formed at another position on the second extension portion VDD2 to improve the transmittance of the display panel. The transmittance of the display panel may also be improved by forming an openwork structure on the second extension portion VDD2. In this embodiment, the power supply line VDD may form a mesh structure with the second conductive portion connected laterally in the first direction X, and the power supply line on the display panel may have low self-resistance. Additionally, in this embodiment, the width of the power supply line VDD may be appropriately reduced to improve the transmittance of the display panel. For example, in this embodiment, the dimension of the second extension portion VDD2 in the first direction X may be appropriately reduced. In this embodiment, the size of the second extension portion VDD2 in the first direction X of the orthogonal projection onto the base substrate is L1, and the size of the second extension portion VDD2 in the second direction Y of the orthogonal projection onto the base substrate is L2, where L1 / L2 may be 1 / 2 or less, for example, L1 / L2 may be 1 / 2, 1 / 3, 1 / 4, etc.

[0068] As shown in FIG. 25, a partial cross-sectional view taken along dashed line AA in FIG. 25 may be the same as the cross-sectional view shown in FIG.

[0069] As shown in Figure 29, this is a structural diagram of a light-shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another illustrative embodiment of a display panel of the present disclosure. The display panel shown in FIG. 29 differs from the display panel shown in FIG. 28 in that the openwork portion 410 on the first bridge portion 41 is a closed circle; two vias that the first bridge portion 41 connects to the second sub-connection portion 212 can be integrated into one, and these two vias can be mirror-symmetrical in the mirror symmetry plane of the first pixel driving circuit and the second pixel driving circuit; the first bridge portion 41 can integrate two vias that respectively connect the eighth active portion in the first pixel driving circuit and the eighth active portion in the second pixel driving circuit, and this integrated via connects the ninth active portion 79 to connect the eighth active portion in the first pixel driving circuit and the eighth active portion in the second pixel driving circuit; and this integrated via can be mirror-symmetrical in the mirror symmetry plane of the first pixel driving circuit and the second pixel driving circuit.

[0070] 30 is a diagram illustrating a configuration of a light-shielding layer in another exemplary embodiment of a display panel according to the present disclosure. In the overlapping unit, the size of the second connection portion 62 connected between two light-shielding portions 61 adjacent in the first direction X when orthogonally projected onto the base substrate in the second direction Y may be L1, and the size of the light-shielding portion 61 when orthogonally projected onto the base substrate in the second direction Y may be L2. L1 may be equal to or greater than 80%*L2 and equal to or less than L2, for example, L1 may be 80%*L2, 90%*L2, L2, etc. This configuration can reduce the voltage drop in the light-shielding layer.

[0071] 31 is a diagram illustrating the configuration of a light-shielding layer in another exemplary embodiment of a display panel of the present disclosure. FIG. 31 differs from FIG. 30 in that an openwork portion 621 is formed in the second connecting portion 62, and there may be one or more openwork portions 621. This configuration can reduce the influence of the light-shielding layer on the transmittance of the display panel.

[0072] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and pitch of each film layer, and the width and pitch of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of sub-pixels per pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams.

[0073] This embodiment also provides a display device including the above-mentioned display panel, which may be a display device for a mobile phone, a tablet, a television, etc.

[0074] Other embodiments of the present disclosure will be readily apparent to those skilled in the art after consideration and practice of the specification and the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure in accordance with the general principles of the present disclosure, including common knowledge or customary technical means known in the art but not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0075] It is to be understood that the present disclosure is not limited to the exact construction described above and illustrated in the drawings, and that various modifications and variations are possible without departing from the scope of the present disclosure, which is defined solely by the appended claims.

Claims

1. A display panel including a plurality of pixel driving circuits arranged and distributed along a first direction and a second direction, the first direction and the second direction intersect, the pixel driving circuit includes a driving transistor and a capacitor, a first electrode of the capacitor is connected to a gate of the driving transistor, and a second electrode of the capacitor is connected to a power supply line; the display panel further includes a base substrate, a second conductive layer, and a fifth conductive layer; the second conductive layer is located on one side of the base substrate; the second conductive layer includes a plurality of second conductive portions; the plurality of second conductive portions are provided in one-to-one correspondence with the plurality of pixel driving circuits, the second conductive portions are used to form second electrodes of the capacitors in the corresponding pixel driving circuits, and at least two adjacent second conductive portions distributed in the first direction are connected to form a conductive line; the fifth conductive layer is located on a side of the second conductive layer that is away from the base substrate, the fifth conductive layer includes a plurality of the power supply lines, Orthogonal projections of the plurality of power supply lines onto the base substrate are distributed at intervals along the first direction and extend along the second direction, and at least one of the conductive lines is electrically connected to the plurality of power supply lines; the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to a first initial signal line, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole of the second transistor is connected to the second pole of the driving transistor; the display panel further includes a second active layer; the second active layer is located between the second conductive layer and the fifth conductive layer, and the second active layer includes a first active portion and a second active portion; the first active portion is used to form a channel region of the first transistor; the second active portion is connected to the first active portion and is used to form a channel region of the second transistor; the power supply line includes a second extending portion, The orthogonal projection of the second extension portion onto the base substrate covers the orthogonal projection of the first active portion onto the base substrate and the orthogonal projection of the second active portion onto the base substrate. A display panel characterized by:

2. the second conductive layer further includes a plurality of first connecting portions; the first connection portion is connected between two of the second conductive portions adjacent in the first direction to form the conductive line; the display panel further includes a first active layer and a light-shielding layer; the first active layer is located between the base substrate and the second conductive layer; the first active layer includes a plurality of third active portions; the plurality of third active units are provided in one-to-one correspondence with the plurality of pixel driving circuits, and the third active units are used to form channel regions of the driving transistors in the corresponding pixel driving circuits; the light-shielding layer is located between the base substrate and the first active layer; the light-shielding layer includes a plurality of light-shielding portions and a plurality of second connection portions; a plurality of light-shielding portions are provided in one-to-one correspondence with the plurality of pixel driving circuits, and orthogonal projections of the light-shielding portions onto the base substrate cover orthogonal projections of the third active portions of the corresponding pixel driving circuits onto the base substrate; the second connection portion is connected between two of the light-shielding portions adjacent to each other in the first direction, and a size of the second connection portion orthogonally projected onto the base substrate in the second direction is smaller than a size of the light-shielding portion orthogonally projected onto the base substrate in the second direction; Between two adjacent pixel driving circuits in the same group, the orthogonal projection of the second connection portion onto the base substrate and the orthogonal projection of the first connection portion onto the base substrate at least partially overlap.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

3. the display panel includes a plurality of overlapping units distributed along the first direction and the second direction, each overlapping unit includes two of the pixel driving circuits, the two pixel driving circuits including a first pixel driving circuit and a second pixel driving circuit distributed along the first direction, the first pixel driving circuit and the second pixel driving circuit being arranged to be mirror-symmetric with respect to an axis of symmetry parallel to the second direction; the plurality of first connection portions include first sub-connection portions; The first sub-connection portion is connected between two of the second conductive portions in the overlapping units adjacent in the first direction, and the size of the orthogonal projection of the first sub-connection portion onto the base substrate in the second direction is smaller than the size of the orthogonal projection of the second conductive portion onto the base substrate in the second direction.

3. The display panel according to claim 2.

4. Between two adjacent pixel driving circuits of the same group, an orthogonal projection of the first sub-connection portion onto the base substrate is located at an orthogonal projection of the second sub-connection portion onto the base substrate.

4. The display panel according to claim 3.

5. the power supply line further includes a first extending portion and a third extending portion, the second extending portion being connected between the first extending portion and the third extending portion; a size of the second extension portion in the first direction when orthogonally projected onto the base substrate is larger than a size of the first extension portion in the first direction when orthogonally projected onto the base substrate, and a size of the second extension portion in the first direction when orthogonally projected onto the base substrate is larger than a size of the third extension portion in the first direction when orthogonally projected onto the base substrate; The size of the orthogonal projection of the second extension portion onto the base substrate in the first direction is L1, the size of the orthogonal projection of the second extension portion onto the base substrate in the second direction is L2, and L1 / L2 is ½ or less.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

6. The second extending portion is provided with a notch or a closed or non-closed opening.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

7. the pixel driving circuit further includes a fourth transistor, a first pole of the fourth transistor is connected to a data line, and a second pole of the fourth transistor is connected to the first pole of the driving transistor; the display panel further includes a first active layer, a first conductive layer, and a third conductive layer; the first active layer is located between the base substrate and the second conductive layer, the first active layer includes a fourth active portion, the fourth active portion is used to form a channel region of the fourth transistor; the first conductive layer is located between the first active layer and the second conductive layer, the first conductive layer includes a second gate line, an orthogonal projection of the second gate line onto the base substrate covers an orthogonal projection of the fourth active portion onto the base substrate and extends along the first direction, and a partial structure of the second gate line is used to form a gate of the fourth transistor; a third conductive layer is located between the second active layer and a fifth conductive layer, the third conductive layer includes a first reset signal line, an orthogonal projection of the first reset signal line onto the base substrate covers an orthogonal projection of the first active portion onto the base substrate, and a structure of a portion of the first reset signal line is used to form a gate of the first transistor; The notch is formed on a side of the second extension portion facing the fourth active portion, and an orthogonal projection of the notch onto the base substrate is located between an orthogonal projection of the second gate line onto the base substrate and an orthogonal projection of the first reset signal line onto the base substrate.

7. The display panel according to claim 6, wherein the first and second electrodes are arranged parallel to each other.

8. the plurality of first connection portions further include second sub-connection portions; the second sub-connection portion is connected between two of the second conductive portions in the same overlapping unit; the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the power supply line, and a second pole of the fifth transistor is connected to the first pole of the driving transistor; the first active layer includes a fifth active portion and an eighth active portion; the fifth active portion is used to form a channel region of the fifth transistor; the eighth active portion is connected to a side of the fifth active portion away from the third active portion, the display panel further includes a first conductive layer and a fourth conductive layer; the first conductive layer is located between the first active layer and the second conductive layer; the first conductive layer includes an enable signal line; an orthogonal projection of the enable signal line onto the base substrate extends along the first direction and covers an orthogonal projection of the fifth active portion onto the base substrate, and a structure of a portion of the enable signal line is used to form a gate of the fifth transistor; the fourth conductive layer is located between the second conductive layer and the fifth conductive layer; the fourth conductive layer includes a first bridge portion; The first bridge portion is connected to an eighth active portion in the first pixel driving circuit, an eighth active portion in the second pixel driving circuit, and a second sub-connection portion between the first pixel driving circuit and the second pixel driving circuit through vias, and the first bridge portion is connected to the power supply line through vias.

4. The display panel according to claim 3.

9. The first bridge portion has a closed or non-closed opening.

9. The display panel according to claim 8.

10. The orthogonal projection of the closed opening or the non-closed opening onto the base substrate and the orthogonal projection of the enable signal line onto the base substrate at least partially overlap with each other.

10. The display panel according to claim 9.

11. the second direction is a column direction, one power supply line is provided corresponding to the pixel drive circuit of each column, the power supply line in the first pixel drive circuit and the power supply line in the second pixel drive circuit are connected to the first bridge portion via vias, the first bridge portion includes a first via contact portion, a second via contact portion, a third via contact portion, a fourth via contact portion, and a fifth via contact portion; the first via contact portion is connected to the second sub-connection portion through a via; the second via contact portion is provided to face the first via contact portion in the second direction and is connected to an eighth active portion in the first pixel driving circuit through a via; the third via contact portion is provided to face the first via contact portion in the second direction and is connected to an eighth active portion in the second pixel driving circuit through a via; the fourth via contact portion is connected between the first via contact portion and the second via contact portion, and is connected to a power supply line in the first pixel driving circuit through a via; the fifth via contact portion is connected between the first via contact portion and the third via contact portion, and is connected to a power supply line in the second pixel driving circuit through a via, the fifth via contact portion and the fourth via contact portion are provided opposite to each other in the first direction, The closed opening or the non-closed opening is formed by being surrounded by the first via contact portion, the second via contact portion, the third via contact portion, the fourth via contact portion, and the fifth via contact portion.

10. The display panel according to claim 9.

12. the first active layer further includes a plurality of ninth active portions, The plurality of ninth active units are provided in one-to-one correspondence with the plurality of overlapping units, and in the same overlapping unit, the ninth active unit is connected between the eighth active unit in the first pixel driving circuit and the eighth active unit in the second pixel driving circuit.

9. The display panel according to claim 8.

13. The first bridge portion is mirror-symmetric with respect to a mirror-symmetry plane of the first pixel driving circuit and the second pixel driving circuit.

9. The display panel according to claim 8.

14. the pixel driving circuit further includes a fourth transistor, a sixth transistor, and a seventh transistor, a first pole of the fourth transistor connected to a data line, a second pole of the fourth transistor connected to a first pole of the driving transistor, a first pole of the sixth transistor connected to a second pole of the driving transistor, a first pole of the seventh transistor connected to a second pole of the sixth transistor, and a second pole of the seventh transistor connected to a second initial signal line; the display panel further includes a first active layer and a first conductive layer; the first active layer is located between the base substrate and the second conductive layer; the first active layer includes a third active portion, a fourth active portion, a sixth active portion, and a seventh active portion; the third active portion is used to form a channel region of the drive transistor; the fourth active portion is connected to one side of the third active portion and is used to form a channel region of the fourth transistor; the sixth active portion is connected to a side of the third active portion away from the fourth active portion and is used to form a channel region of the sixth transistor; the seventh active portion is connected to a side of the sixth active portion away from the third active portion and is used to form a channel region of the seventh transistor; the first conductive layer is located between the first active layer and the second conductive layer; the first conductive layer includes a second gate line, an enable signal line, a second reset signal line, and a first conductive portion; an orthogonal projection of the second gate line onto the base substrate extends along the first direction and covers an orthogonal projection of the fourth active portion onto the base substrate, and a structure of a portion of the second gate line is used to form a gate of the fourth transistor; an orthogonal projection of the enable signal line onto the base substrate extends along the first direction and covers an orthogonal projection of the sixth active portion onto the base substrate, and a structure of a portion of the enable signal line is used to form a gate of the sixth transistor; an orthogonal projection of the second reset signal line onto the base substrate extends in the first direction and covers an orthogonal projection of the seventh active portion onto the base substrate, and a structure of a portion of the second reset signal line is used to form a gate of the seventh transistor; an orthogonal projection of the first conductive portion onto the base substrate covers an orthogonal projection of the third active portion onto the base substrate, and the first conductive portion is used to form a gate of the drive transistor and a first electrode of the capacitor; In the same pixel driving circuit, an orthogonal projection of the first conductive portion onto the base substrate is located between an orthogonal projection of the second gate line onto the base substrate and an orthogonal projection of the enable signal line onto the base substrate; The orthogonal projection of the second reset signal line onto the base substrate is located on a side of the orthogonal projection of the enable signal line onto the base substrate that is away from the orthogonal projection of the first conductive portion onto the base substrate.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

15. The first direction is a row direction, and the second gate line in the pixel driving circuit of the current row is multiplexed as the second reset signal line in the pixel driving circuit of the previous row.

15. The display panel according to claim 14.

16. the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to a first initial signal line, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole of the second transistor is connected to the second pole of the driving transistor; the display panel further includes a second active layer and a third conductive layer; a second active layer located between the second conductive layer and the fifth conductive layer; the second active layer includes a first active portion and a second active portion; the first active portion is used to form a channel region of the first transistor; the second active portion is connected to the first active portion and is used to form a channel region of the second transistor; the third conductive layer is located between the second active layer and the fifth conductive layer; the third conductive layer includes a first reset signal line and a first gate line; an orthogonal projection of the first reset signal line onto the base substrate covers an orthogonal projection of the first active portion onto the base substrate, and a structure of a portion of the first reset signal line is used to form a top gate of the first transistor; an orthogonal projection of the first gate line onto the base substrate covers an orthogonal projection of the second active portion onto the base substrate, and a structure of a portion of the first gate line is used to form a top gate of the second transistor; In the same pixel driving circuit, an orthogonal projection of the first gate line onto the base substrate is located between an orthogonal projection of the first conductive portion onto the base substrate and an orthogonal projection of the second gate line onto the base substrate, and an orthogonal projection of the first reset signal line onto the base substrate is The second gate line is located on a side of the first conductive portion that is away from the orthogonal projection of the second gate line onto the base substrate.

15. The display panel according to claim 14.

17. the second conductive layer further includes a first initial signal line, a third reset signal line, and a third gate line; an orthogonal projection of the first initial signal line onto the base substrate is located on a side of the orthogonal projection of the first reset signal line onto the base substrate that is away from the orthogonal projection of the first conductive portion onto the base substrate; the third reset signal line is connected to the first reset signal line through a via, and its orthogonal projection onto the base substrate covers the orthogonal projection onto the base substrate of the first active portion, and a structure of a part of the third reset signal line is used to form a bottom gate of the first transistor; The orthogonal projection of the third gate line onto the base substrate covers the orthogonal projection of the second active portion onto the base substrate, and a structure of a portion of the third gate line is used to form a bottom gate of the second transistor.

17. The display panel according to claim 16.

18. the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor is connected to the power supply line, a second pole of the fifth transistor is connected to the first pole of the driving transistor, and a gate of the fifth transistor is connected to the enable signal line; The first transistor and the second transistor are N-type transistors, and the drive transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

17. The display panel according to claim 16.

19. the pixel driving circuit further includes a sixth transistor and a seventh transistor; a first pole of the sixth transistor is connected to a second pole of the drive transistor, a first pole of the seventh transistor is connected to a second pole of the sixth transistor, and a second pole of the seventh transistor is connected to a second initial signal line; The fourth conductive layer further includes the second initial signal line.

9. The display panel according to claim 8.

20. All the second conductive portions distributed in the first direction are sequentially connected to form the conductive lines, and each of the conductive lines is connected to a corresponding one of the power supply lines.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

21. The display panel according to any one of claims 1 to 20 A display device characterized by:

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