Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing chatter occurrence.SOLUTION: A semiconductor device includes: a first input to which an input signal is inputted; a second input to which a reference signal is inputted; and a comparison stage which is connected to a current source connected to a first voltage and between a second voltage different from the first voltage and the current source, and includes a first current path part and a second current path part for performing comparison operation according to the input signal and the reference signal. The first current path part and the second current path part include: a first input circuit and a second input circuit respectively connected to the current source; and a first load circuit and a second load circuit respectively connected between the first input circuit, the second input circuit and the second voltage. The first input circuit includes a first signal transistor to which the input signal is inputted and a first reference transistor to which the reference signal is inputted, mutually connected in parallel, and the second input circuit includes a second signal transistor to which the input signal is inputted and a second reference transistor to which the reference signal is inputted, mutually connected in parallel.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a comparator that can suppress fluctuations in input offset voltage even during comparison operations. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-92655 Summary of the Invention [Problem to be solved by the invention]

[0004] Circuits such as analog-to-digital converters, switching power supplies, supervisory circuits, and delta-sigma modulators use comparators to compare the voltages of two nodes. The comparators in these circuits operate in a variety of environments. Various input signal waveforms, such as large-amplitude, steep waveforms, large-amplitude, slow waveforms, or small-amplitude, slow waveforms, are input to the comparator. When noise is superimposed on a slow waveform, the comparator may respond to the noise and produce chattering in its output.

[0005] An object of the present invention is to provide a semiconductor device that can reduce the occurrence of chattering. [Means for solving the problem]

[0006] A semiconductor device according to a first aspect of the present invention comprises a first input to which an input signal is input, a second input to which a reference signal is input, a current source connected to a first potential, and a comparison stage including a first current path section and a second current path section connected between the current source and a second potential different from the first potential and performing a comparison operation in response to the input signal and the reference signal, wherein the first current path section and the second current path section include a first input circuit and a second input circuit connected to the current source, respectively, and a first load circuit and a second load circuit connected between the first input circuit and the second input circuit and the second potential, respectively, the first input circuit includes a first signal transistor connected in parallel to each other and to which the input signal is input and a first reference transistor to which the reference signal is input, and the second input circuit includes a second signal transistor connected in parallel to each other and to which the input signal is input and a second reference transistor to which the reference signal is input,

[0007] In this semiconductor device, an input signal is input to a first signal transistor in a first current path portion and a second signal transistor in a second current path portion. In response to the input signal, the current of the current source is diverted to both the first current path portion and the second current path portion. The current diversion slows the response speed of the comparison operation of the comparison stage, i.e., slows the rate of change of the node voltage. This prevents the comparison stage from responding to waveforms with short durations (e.g., noise). [Effects of the Invention]

[0008] According to the above aspect, it is possible to provide a semiconductor device that can reduce the occurrence of chattering. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram schematically illustrating a comparator according to an embodiment of the present invention. [Figure 2] 2(a) and 2(b) are circuit diagrams showing logic circuits for the output of a comparator according to one embodiment of the present invention. [Figure 3]FIG. 3 is a circuit diagram showing a comparator that does not include a first reference transistor and a second signal transistor. [Figure 4] FIG. 4 is a graph showing the results of a circuit simulation of the comparator shown in FIG. [Figure 5] FIG. 5 is a graph showing the results of a circuit simulation of a comparator according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. In the following description, the same or similar parts will be designated by the same or similar reference numerals to avoid redundant description.

[0011] Fig. 1 is a circuit diagram showing a schematic diagram of a comparator according to an embodiment of the present invention. In Fig. 1, the transistors constituting the comparator are depicted by the circuit symbol of a field-effect transistor for illustrative purposes only. A field-effect transistor has a source electrode, a drain electrode, and a gate electrode, which are commonly referred to as "S," "D," and "G," respectively, in the circuit diagram.

[0012] Comparator 11 includes a first input 13 for receiving an input voltage, a second input 15 for receiving a reference voltage, and a comparison stage 17 .

[0013] The comparison stage 17 includes an output 18, a current source 19, a first current path portion 21, and a second current path portion 23. The first current path portion 21 and the second current path portion 23 are connected to the current source 19, and the current of the current source 19 flows split between the first current path portion 21 and the second current path portion 23.

[0014] The first current path portion 21 and the current source 19 are connected in series between a first potential VH (e.g., a power supply potential) and a second potential VL (e.g., a ground potential) different from the first potential VH, and the second current path portion 23 and the current source 19 are connected in series between the first potential VH and the second potential VL. Specifically, the current source 19 is connected between the first potential VH and the intermediate node MN of the comparison stage 17. The first current path portion 21 and the second current path portion 23 are connected in parallel between the second potential VL and the intermediate node MN of the comparison stage 17.

[0015] The first current path section 21 includes a first input circuit 25 and a first load circuit 26, which are connected in series in order from the current source 19 to the second potential VL. The first input circuit 25 may include a plurality of transistors connected in parallel, which in this embodiment are a first signal transistor 25s and a first reference transistor 25r. Each of the first signal transistor 25s and the first reference transistor 25r is connected in series to the first load circuit 26.

[0016] The second current path section 23 includes a second input circuit 27 and a second load circuit 28, which are connected in series in this order from the current source 19 toward the second potential VL. The second input circuit 27 may include a plurality of transistors connected in parallel, which in this embodiment are a second signal transistor 27s and a second reference transistor 27r. The second signal transistor 27s and the second reference transistor 27r are each connected in series to the second load circuit 28.

[0017] The current source 19, the first input circuit 25 and the second input circuit 27 are connected to one another at an intermediate node M. The comparison stage 17 has a circuit connection that is different from that of the differential amplifier stage described below.

[0018] The transistor size (W R1 / L R1 ) is the transistor size (W R2 / L R2) and the transistor size (W S2 / L S2 ) is the transistor size (W S1 / L S1 Here, the size of a transistor (or transistor size) is defined by the ratio (W / L) of the transistor width (W) of a field effect transistor to the transistor length (L) of the field effect transistor.

[0019] In addition, the transistor size (W R1 / L R1 ) is the transistor size (W S1 / L S1 ) is smaller than the transistor size (W S2 / L S2 ) is the transistor size (W R2 / L R2 ) smaller than

[0020] The first signal transistor 25s and the second signal transistor 27s operate in response to an input signal SIN from the first input 13. The first reference transistor 25r and the second reference transistor 27r operate in response to a reference signal SREF from the second input 15. A comparison operation according to the input signal SIN and the reference signal SREF is performed by the first signal transistor 25s and the second signal transistor 27s to which the input signal SIN is input, and the first reference transistor 25r and the second reference transistor 27r to which the reference signal SREF is input.

[0021] In this comparator 11, an input signal SIN from the first input 13 is provided to a first signal transistor 25s in the first current path portion 21 and a second signal transistor 27s in the second current path portion 23. A reference signal SREF from the second input 15 is provided to a first reference transistor 25r in the first current path portion 21 and a second reference transistor 27r in the second current path portion 23. The current flowing through the current source 19 is split into two portions, one to flow through the first current path portion 21 and the other to flow through the second current path portion 23, in response to the input signal SIN from the first input 13 and the other to the reference signal SREF from the second input 15. This split slows down the rate of change in the voltage of a node within the comparison stage 17. This makes the comparison stage 17 less responsive to waveforms with short durations, such as noise. In other words, it becomes more difficult for the comparison stage 17 to perform a comparison operation in response to noise.

[0022] Specifically, the first signal transistor 25s in the first current path portion 21 and the second signal transistor 27s in the second current path portion 23 both operate in response to the input signal SIN from the first input 13, and the first reference transistor 25r in the first current path portion 21 and the second reference transistor 27r in the second current path portion 23 both operate in response to the reference signal SREF from the second input 15, while the current source 19 determines the total amount of current flowing in the first current path portion 21 and the second current path portion 23. The shunt current to the first signal transistor 25s and the second signal transistor 27s, which operate in response to the input signal SIN from the first input 13, reduces the amount of current flowing in one of the first current path portion 21 and the second current path portion 23. Furthermore, the shunt current to the first reference transistor 25r and the second reference transistor 27r, which operate in response to the signal SREF from the second input 15, reduces the amount of current flowing in one of the first current path portion 21 and the second current path portion 23. This reduction in the amount of current flowing in the first current path portion and the second current path portion slows the change in the voltage waveform at the node of the comparison stage 17. The delay in the change in the voltage waveform prevents the comparison stage 17 from responding to noise, such as small-amplitude spike noise, superimposed on the signal waveform input to the first signal transistor 25s and the second signal transistor 27s. In other words, even if noise is superimposed on the input signal waveform, the comparison stage 17 is prevented from performing a comparison operation in response to the noise.

[0023] Because the first reference transistor 25r and the second reference transistor 27r receive the reference signal SREF from the second input 15, changes in the amount of current in the comparison stage 17 are caused by operation in response to the input signal SIN from the first input 13. The total amount of current in the comparison stage 17 is determined by the current source 19, and is divided depending on the transistor sizes of the first signal transistor 25s, the second signal transistor 27s, the first reference transistor 25r, and the second reference transistor 27r. The division of current depending on the transistor size will be described later.

[0024] 1 , the comparator 11 further includes a reference voltage source 29. The reference voltage source 29 generates a reference signal SREF having a reference voltage. The first reference transistor 25r and the second reference transistor 27r receive the reference signal SREF from the reference voltage source 29. The reference voltage source 29 may include, for example, a bandgap circuit that generates a constant voltage or a resistive voltage divider circuit.

[0025] Comparator 11 further includes an output stage 31 that receives signal opm from output 18 of comparison stage 17. Output stage 31 may be configured to amplify the signal from output 18 of comparison stage 17. Output stage 31 has an input 31a connected to output 18 of comparison stage 17, and an output 31b.

[0026] The comparator 11 includes a logic circuit 33 that converts the output signal outn from the output stage 31 into a logic level signal. The logic circuit 33 can include, for example, a logic gate such as an inverter circuit, or a hysteresis circuit such as a Schmitt trigger circuit. Figures 2(a) and 2(b) show an inverter circuit 35a or a Schmitt trigger circuit 35b, respectively, provided as a CMOS circuit, which can operate as the logic circuit 33.

[0027] The comparator 11 includes a voltage source circuit 37, which may include a current source 37a and a load circuit 37b. The load circuit 37b may include, for example, one or more transistors connected to form a current mirror circuit. The current source 37a generates a constant current IB.

[0028] In the comparison stage 17, the first load circuit 26 and the second load circuit 28 include at least one of (specifically, one, two, or all of) a current mirror circuit, a transistor having a gate and a drain connected to each other (a diode-connected transistor), and a resistor.

[0029] 1, the first load circuit 26 and the second load circuit 28 can be configured by a current mirror circuit CM0. In this comparator 11, the current mirror circuit CM0 can be applied to the load of the comparison stage 17. The current mirror circuit CM0 can transmit a change in the current of the second signal transistor 27s of the second current path portion 23 to the first current path portion 21.

[0030] Each of the first load circuit 26 and the second load circuit 28 may include a transistor having a gate and a drain connected to each other (referred to as a "diode-connected transistor" in the following description), and the conductivity type of this transistor may be different from the conductivity type of the transistors in the first input circuit 25 and the second input circuit 27. According to this comparator 11, a diode-connected transistor can be applied to the load of the comparison stage 17.

[0031] Furthermore, each of the first load circuit 26 and the second load circuit 28 can include a resistor, and the resistor includes at least one of a semiconductor conductive region for the source S and drain D of the transistor, a gate conductive layer for the gate electrode (G), and a specially prepared resistive layer. According to this comparator 11, a resistor can be applied to the load of the comparison stage 17.

[0032] Next, the connections of the transistors in the comparator 11 shown in FIG. 1 will be described.

[0033] The comparison stage 17 includes a first conductivity type (e.g., p-type) transistor (P0) configured to operate as a current source 19, the transistor (P0) having a source S connected to the second potential VH, a gate G receiving a signal vb from the voltage source circuit 37, and a drain D connected to the sources S of parallel-connected first conductivity type transistors (P1M, P2P) in the first input circuit 25 of the first current path section 21. The drains D of the parallel-connected transistors (P1M, P2P) are connected to the drain D of a second conductivity type (e.g., n-type) transistor (N1) in the first load circuit 26.

[0034] In addition, the drain D of the transistor (P0) is connected to the source S of the parallel-connected first conductivity type transistors (P2M, P1P) in the second input circuit 27 of the second current path section 23. The drain D of the parallel-connected transistors (P2M, P1P) is connected to the drain D and gate G of the second conductivity type transistor (N0) in the second load circuit 28. The transistors (N0) and (N1) form a current mirror circuit CM0. The source S of the transistors (N0, N1) is connected to the second potential VL. The node (opp) transmits the amount of current flowing through the second current path section 23 to the first load circuit 26 of the second current path section 21.

[0035] The output stage 31 includes a second conductivity type transistor (N2). The gate G of the transistor (N2) is connected to the output 18 of the comparison stage 17 and receives the output signal (opm). The source S of the transistor (N2) is connected to the second potential VL, and the drain D of the transistor (N2) is connected to the drain D of the second conductivity type transistor (P4). The source S of the transistor (P4) is connected to the first potential VH, and the gate G of the transistor (P4) receives a signal vb from the voltage source circuit 37.

[0036] The voltage source circuit 37 includes a current source 37a that generates a constant current IB and a first conductivity type transistor (P3). The current source 37a is connected to the drain D and gate G of the transistor (P3). The source S of the transistor (P3) is connected to a first potential VH. The gate G of the transistor (P3) provides a signal vb. The transistor (P3) forms a current mirror circuit CM1 together with the transistor (P0) and forms a current mirror circuit CM2 together with the transistor (P4).

[0037] 1, the first signal transistor 25s, the first reference transistor 25r, the second signal transistor 27s, and the second reference transistor 27r are each a p-type MOS transistor. However, the present embodiment is not limited thereto, and the comparator 11 includes the first signal transistor 25s, the first reference transistor 25r, the second signal transistor 27s, and the second reference transistor 27r, which are n-type MOS transistors.

[0038] The current shunting due to the transistor size will be described. As already explained, the transistor size (W S1 / L S1 ) is the transistor size (W S2 / L S2 ) is set larger than

[0039] The transistor size (W S2 / L S2 ) the transistor size (W S1 / L S1 ) size ratio (W S1 / L S1 ) / (W S2 / L S2 ) determines the ratio of the shunt current to the input signal SIN in each of the first current path portion 21 and the second current path portion 23.

[0040] In addition, the transistor size (W R1 / L R1 ) to the second reference transistor 27r (W R2 / L R2 The ratio of current shunting in each of the first current path portion 21 and the second current path portion 23 can also be determined by the size ratio of the transistor sizes of the first current path portion 21 and the second current path portion 23. By providing the first reference transistor 25r in the first current path portion 21, it is possible to compensate for the symmetry of the circuit with the second signal transistor 27s and the second reference transistor 27r in the second current path portion 23. In addition, the transistor size (W R2 / L R2 ) is the transistor size (W R1 / L R1 ) is set larger than

[0041] In the comparison stage 17, in which the second signal transistor 27s is provided in the second current path portion 23 and the first reference transistor 25r is provided in the first current path portion 21, a fixed amount of current from the current source 19 is divided into the first current path portion 21 and the second current path portion 23 according to a current division ratio in response to the input signal SIN. The current division ratio changes, for example, the response speed of the comparison operation of the comparison stage 17. Increasing the transistor size of the second signal transistor 27s in the second current path portion 23 relative to the transistor size of the first signal transistor 25s in the first current path portion 21 slows down the response speed of the comparison operation, and it is possible to slow down changes in the voltage waveforms at the nodes of the comparison stage 17.

[0042] The transistor sizes of the transistors of the first input circuit 25 and the second input circuit 27 of the comparison stage 17 can be set as follows, for example: S1 / L S1 ) is the transistor size (W R2 / L R2 ) is the same as the transistor size (W S2 / L S2 ) is the transistor size (W R1 / L R1 ) is the same as

[0043] The operation of the comparators 11 and 41 will be described with reference to Figures 3, 4 and 5. The reference symbols in the graphs of Figures 4 and 5 are as follows: Ip1m: Drain current (Ids) of transistor (P1M) Ip1p: Drain current (Ids) of transistor (P1P) Ip2m: Drain current (Ids) of transistor (P2M) Ip2p: Drain current (Ids) of transistor (P2P) Ip0: Current of the current source of the comparison stage Vref: Reference voltage value of the comparator

[0044] Fig. 3 is a circuit diagram showing a comparator 41 that does not include the first reference transistor 25r and the second signal transistor 27s. In Fig. 4, for ease of understanding, the circuit symbols and nodes in the differential amplifier stage A0, the output stage A2, and the logic gate X0 are assigned reference symbols corresponding to those in Fig. 1, where possible, and duplicated explanations are omitted.

[0045] 4(a) shows the voltage waveform of the output OUT of the comparator 41 that receives a large-amplitude input voltage Vin (the difference Vpp between the amplitude of the reference voltage Vref and the amplitude of the input voltage Vin is large). The differential amplifier stage A0 of the comparator 41 detects that the input voltage Vin crosses the reference voltage Vref, and the output OUT changes quickly.

[0046] Part (b) of Figure 4 shows the voltage waveform of the output OUT of the comparator 41 when it receives a small-amplitude input voltage Vin (where the difference Vpp between the amplitude of the reference voltage Vref and the amplitude of the input voltage Vin is small). The small-amplitude input voltage Vin mimics noise input to the comparator 41. The output OUT of the comparator 41 changes rapidly during the period when the input voltage Vin crosses the reference voltage Vref. The output OUT exhibits a rectangular pulse waveform.

[0047] Part (c) of FIG. 4 shows the currents (transistor drain currents) flowing through the two current paths of the differential amplifier stage A0 of the comparator 41 that has received the small-amplitude input voltage Vin.

[0048] Part (a) of Figure 5 shows the voltage waveform of the output OUT of the comparator 11 that receives the small amplitude input voltage Vin shown in Figure 4(b). The signal input of the comparator 11 receives the input voltage Vin, which changes in a triangular shape over time. The input voltage Vin is characterized by peak voltage values ​​corresponding to the vertices of the triangle and intervals where the dashed line representing the reference voltage value Vref crosses the triangle. Referring to the waveform in part (a) of Figure 5, there is a crossing period T where the input wave voltage Vin crosses the reference voltage Vref. INT5(a) and 5(b), the output OUT does not change. This indicates that the comparator 11 does not respond to noise-like inputs and can prevent chattering. The comparator 11 changes the output OUT in response to another input voltage having a peak voltage value greater than the waveform in part (a) of FIG. 5 and / or a crossover wider than the waveform in part (a) of FIG. 5.

[0049] From the viewpoint of preventing chattering, multiple triangular input voltages having different peak voltage values ​​and simulating noise are applied to the comparator 11, and the difference voltage between the peak voltage value at which the output OUT of the comparator 11 inverts (referred to as the "inversion voltage value") and the reference voltage value Vref of the reference voltage source 29 is useful in designing the comparator 11.

[0050] Furthermore, when the comparator 11 receives the large amplitude input voltage Vin shown in FIG. 4(a), it can generate the output voltage waveform shown in FIG. 4(a) in response to the input voltage.

[0051] Part (b) of FIG. 5 shows the current division in the transistors (P1P and P1M) of the comparator 11, and part (c) of FIG. 5 shows the current division in the transistors (P2P and P2M) of the comparator 11.

[0052] Based on the results of various circuit simulations related to the design of comparator 11, the following exemplary design guidelines are provided.

[0053] The transistor size (W R1 / L R1 ) and the transistor size (W S1 / L S1 ) size ratio (W S1 / L S1 ):(W R1 / L R1 ) is, for example, 1:3. In this case, the division ratio of the amount of current flowing through the first reference transistor 25r to the amount of current flowing through the first signal transistor 25s can be set to 1:3.

[0054] The transistor size (W S2 / L S2 ) and the transistor size (W R2 / L R2 ) size ratio (W R2 / L R2 ):(W S2 / L S2 ) is, for example, 1:3. In this case, the shunt ratio of the amount of current flowing through the second signal transistor 27s to the amount of current flowing through the second reference transistor 27r can be set to 1:3.

[0055] According to this comparator 11, the size ratio of the transistors in each of the first current path portion 21 and the second current path portion 23 defines the current division ratio in each of the first current path portion 21 and the second current path portion 23.

[0056] Based on the results of various circuit simulations relating to the design of comparator 11, the following exemplary alternative design guidelines are provided.

[0057] The transistor size (W S2 / L S2 ) and the transistor size (W S1 / L S1 ) size ratio (W S1 / L S1 ):(W S2 / L S2 ) is, for example, 3:1. In this case, the division ratio of the amount of current flowing through the second signal transistor 27s to the amount of current flowing through the first signal transistor 25s can be set to 3:1.

[0058] The transistor size (W R1 / L R1 ) and the transistor size (W R2 / L R2 ) size ratio (W R2 / L R2 ):(W R1 / LR1 ) is, for example, 1:3. In this case, the shunt ratio of the amount of current flowing through the first reference transistor 25r to the amount of current flowing through the second reference transistor 27r can be set to 1:3.

[0059] According to this comparator 11, the size ratio of the transistor associated with the first input 13 (input signal input) and the transistor associated with the second input 15 (reference input) determines the current division ratio of the current from the current source 19 between the transistor associated with the signal input and the transistor associated with the reference input.

[0060] As described above, according to the above embodiment, an input signal is input to the first signal transistor in the first current path section and the second signal transistor in the second current path section, and the current of the current source is diverted to both the first current path section and the second current path section in response to the input signal, thereby slowing down the response speed of the comparison operation of the comparison stage, that is, slowing down the rate of change of the voltage at the node. Therefore, the comparison stage does not respond to waveforms with a short duration such as noise, and a comparator capable of reducing the occurrence of chattering can be provided.

[0061] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0062] 11 comparator, 13 first input, 15 second input, 17 comparison stage, 19 current source, 21 first current path section, 23 second current path section, 25 first input circuit, 25r first reference transistor, 25s first signal transistor, 26 first load circuit, 27 second input circuit, 27r second reference transistor, 27s second signal transistor, 28 second load circuit, 29 reference voltage source, 31 output stage, 31a input, 31b output , 33···Logic circuit, 35a···Inverter circuit, 35b···Schmitt trigger circuit, 37···Voltage source circuit, 37a···Current source, 37b···Load circuit, 41···Comparator, CM0, CM1, CM2···Current mirror circuit, D···Drain, G···Gate, S···Source, OUT···Output, SIN···Input signal, SREF···Reference signal, VH···First potential, VL···Second potential, Vin···Input voltage, Vref···Reference voltage (reference voltage value), vb···Signal (voltage signal).

Claims

1. a first input to which an input signal is input; a second input to which a reference signal is input; a comparison stage including a current source connected to a first potential, a first current path portion and a second current path portion connected between the current source and a second potential different from the first potential, and performing a comparison operation in response to the input signal and the reference signal; Equipped with the first current path portion and the second current path portion include a first input circuit and a second input circuit connected to the current source, respectively, and a first load circuit and a second load circuit connected between the first input circuit and the second potential, respectively, and the first input circuit includes a first signal transistor to which the input signal is input and a first reference transistor to which the reference signal is input, the first signal transistor and the first reference transistor being connected in parallel with each other; The second input circuit includes a second signal transistor to which the input signal is input and a second reference transistor to which the reference signal is input, the second signal transistor and the second reference transistor being connected in parallel to each other. Semiconductor device.

2. a transistor size of the first reference transistor is smaller than a transistor size of the second reference transistor; The transistor size of the second signal transistor is smaller than the transistor size of the first signal transistor. The semiconductor device according to claim 1 .

3. a transistor size of the first reference transistor is smaller than a transistor size of the first signal transistor; The transistor size of the second signal transistor is smaller than the transistor size of the second reference transistor.

3. The semiconductor device according to claim 1.

4. 4. The semiconductor device according to claim 1, wherein the response speed of the comparison operation is slow when the input signal is a small-amplitude input voltage.

5. the first load circuit and the second load circuit are provided by current mirror circuits; The semiconductor device according to claim 1 .

6. each of the first load circuit and the second load circuit includes a transistor having a gate and a drain connected to each other; The semiconductor device according to claim 1 .

7. each of the first load circuit and the second load circuit includes a resistor; The semiconductor device according to claim 1 .

8. The semiconductor device according to claim 1 , further comprising a reference voltage source that generates the reference signal.

9. The semiconductor device according to claim 1 , further comprising a voltage source circuit that supplies a voltage to the current source.

10. 10. The semiconductor device according to claim 9, further comprising an output stage that receives the output of the voltage source circuit and the output of the comparison stage, and outputs an output signal in response to the output of the comparison stage.

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