Successive approximation AD conversion circuit

Abstract

This invention provides a successive approximation AD conversion circuit that maximizes the resolution of the ADC even when the amplitude of the analog input signal changes. [Solution] The successive approximation AD conversion circuit (1) compares the first comparison voltage (V1) and the second comparison voltage (V2) with a capacitor type DAC (10) having a capacitor array (11) to obtain a comparison result signal (S CWP The system includes a comparator (20) that generates a reference voltage, a control circuit (30), a sampling switch (50) provided between the comparator (20) and the second reference voltage (VD3), a reference changing capacitor (Ctr) having a first terminal connected to the first comparison wiring (WR1), and a reference changing switch (Str) configured to selectively supply an analog input signal (Ain) or a ground voltage (GND) to the second terminal of the reference changing capacitor (Ctr).

Description

[Technical Field]

[0001] This disclosure relates to a successive approximation AD conversion circuit. [Background technology]

[0002] A successive approximation type AD conversion circuit generally comprises a DAC (digital-to-analog converter), a comparator, and a logic circuit (control circuit) responsible for successive approximation. Capacitive DACs are often used as the DAC (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-80292

[0004] [overview] There is a growing demand to maximize the resolution of ADCs even when the amplitude of analog input signals changes.

[0005] A successive comparison type AD conversion circuit according to one aspect of the present disclosure is configured to convert an analog input signal into a digital output signal. In the successive comparison type AD conversion circuit, it has a capacitor array and a switch array connected to the capacitor array, and by connecting a wiring to which the analog input signal is applied during a sampling period to the capacitor array via the switch array, charges corresponding to the analog input signal are accumulated in each capacitor in the capacitor array. During a successive comparison period after the sampling period, a first comparison voltage based on the stored charge of the capacitor array is generated on a first comparison wiring in a state where a first reference voltage or a ground voltage is supplied to each capacitor in the capacitor array via the switch array; a capacitor type DAC configured to generate the first comparison voltage; a comparator connected to the first comparison wiring and a second comparison wiring to which a second comparison voltage is applied, and configured to compare the first comparison voltage and the second comparison voltage during the successive comparison period to generate a comparison result signal; a control circuit configured to determine the value of the digital output signal while controlling the state of the switch array based on the comparison result signal during the successive comparison period; a sampling switch arranged between the first comparison wiring and a second reference voltage; a reference changing capacitor unit having a first end connected to the first comparison wiring; and a reference changing switch configured to selectively apply the analog input signal or the ground voltage to a second end of the reference changing capacitor unit.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a configuration diagram of an AD converter. [Figure 2] FIG. 2 is a diagram showing the connection relationship between capacitors, switches, and wirings. [Figure 3] FIG. 3 is a diagram showing the connection relationship between a reference changing capacitor, a reference changing switch, and wirings. [Figure 4] FIG. 4 is a diagram showing the capacitance of each capacitor in a capacitor array. [Figure 5] FIG. 5 is a flowchart of an AD conversion operation. [Figure 6]Figure 6 is a flowchart showing an example of the flow of state transition operations. [Figure 7] Figure 7 is a diagram showing the state of the AD converter after the state transition period has ended. [Figure 8] Figure 8 shows the structure of a register. [Figure 9] Figure 9 is a flowchart showing an example of the flow of a sequential comparison operation. [Figure 10] Figure 10 shows an example of the AD converter of this embodiment. [Figure 11] Figure 11 shows the configuration of a reference AD ​​converter. [Figure 12] Figure 12 shows the relationship between the input voltage and the digital output value in the AD converter according to this embodiment. [Figure 13] Figure 13 shows the relationship between the input voltage and the digital output value in a reference AD ​​converter. [Figure 14] Figure 14 is a configuration diagram of the AD converter 1A of the first modified example. [Figure 15] Figure 15 is an enlarged view of the capacity section for changing the reference and the selection switch. [Figure 16] Figure 16 is a configuration diagram of the AD converter according to the second embodiment. [Figure 17] Figure 17 is a diagram showing the configuration of the AD converter in a second modified example.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of this disclosure will be specifically described with reference to the drawings. In each of the referenced drawings, the same parts are denoted by the same reference numerals, and redundant descriptions relating to the same parts are omitted as a general rule. In this specification, for the sake of simplification of description, symbols or reference numerals that refer to information, signals, physical quantities, functional parts, circuits, elements, or components may be indicated, and the names of the information, signals, physical quantities, functional parts, circuits, elements, or components corresponding to such symbols or reference numerals may be omitted or abbreviated.

[0008] Furthermore, "connection" between any circuit element, wiring, or multiple parts forming a circuit includes both mechanical connection and electrical connection, or in other words, a state in which electricity flows. In short, "to connect" includes "to connect electrically."

[0009] Furthermore, "ground" refers to a reference conductive part having a reference potential of 0V (zero volts), or to the potential of 0V itself. The reference conductive part is formed of a conductor such as metal. The potential of 0V is sometimes referred to as the ground voltage GND. In the embodiments of this disclosure, voltages shown without specifying a reference represent voltages relative to the ground voltage GND.

[0010] A switch can be either on or off. When the switch is on, there is conductivity between its two ends. Conversely, when the switch is off, there is no conductivity between its two ends. In the following explanation, the on state and the off state can also be simply referred to as on and off, respectively.

[0011] MOS (Metal Oxide Semiconductor) field-effect transistors are sometimes used as an example of switching elements that make up a switch. A MOS field-effect transistor is a transistor whose gate structure consists of at least three layers: "a layer made of a conductor or a semiconductor with low resistance such as polysilicon," "an insulating layer," and "a P-channel, N-channel, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field-effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0012] <First Embodiment> A first embodiment of this disclosure will be described with reference to the drawings. Figure 1 is a configuration diagram of the AD converter 1. The AD converter 1 shown in Figure 1 is in a state during the sampling period. The AD converter 1 is a successive approximation type AD conversion circuit. An analog input signal Ain is input to the AD converter 1. The AD converter 1 performs an AD conversion operation on the analog input signal Ain. In the AD conversion operation on the analog input signal Ain, the analog input signal Ain is converted into a digital signal by binary search, and the obtained digital signal is output as a digital output signal Dout.

[0013] The digital output signal Dout is an N-bit digital signal. That is, the digital output signal Dout has a total of N bits, from the 1st bit to the Nth bit. N is any integer greater than or equal to 2, for example, 8, 10, 12, 14, or 16. Here, the (i+1)th bit relative to the ith bit is considered the most significant bit. In other words, of the 1st to Nth bits, the 1st bit is the least significant bit and the Nth bit is the most significant bit. i represents any integer and can be understood as a natural number less than N.

[0014] The AD converter 1 includes a DAC 10, a comparator 20, a control circuit 30, a voltage generation circuit 40, and a sampling switch 50. Wiring WR_Ain is an analog input wiring to which the analog input signal Ain is applied.

[0015] Wiring WR_VD1 is a power supply wire to which a predetermined first reference voltage VD1 is applied. Wiring WR_GND is a ground wire to which the ground voltage GND is applied. Wiring WR_GND itself may be considered as ground.

[0016] DAC10 is a capacitive DAC (capacitive digital-to-analog converter). Capacitive DACs are also commonly referred to as capacitive DACs. DAC10 includes a capacitor array 11, a switch array 12, a reference change capacitance section Ct1, and a reference change switch Str. The capacitor array 11 has capacitors C[1] to C[N] arranged in parallel with each other. The switch array 12 has switches S[1] to S[N] arranged in parallel with each other.

[0017] The reference change capacitor section Ct1 is composed of a reference change capacitor Ctr, and will be referred to as the reference change capacitor Ctr in the following description. The reference change capacitor Ctr is arranged in parallel with each of the capacitors C[1] to C[N] of the capacitor array 11. The reference change switch Str is arranged in parallel with each of the switches S[1] to S[N] of the switch array 12.

[0018] In DAC10, capacitors C[1] to C[N] each have a first and second terminal, and charge is stored between the first and second terminals. Similarly, the reference change capacitor Ctr also stores charge between its first and second terminals. The first terminals of capacitors C[1] to C[N] and the reference change capacitor Ctr are all connected to the first comparison wiring WR1.

[0019] Switches S[1] to S[N] are provided for each capacitor C[1] to C[N]. That is, switch S[i] is provided for each capacitor C[i]. Capacitor C[i] corresponds to the i-th bit of the digital output signal Dout. An analog input signal Ain, a first reference voltage VD1, or a ground voltage GND can be applied to the second terminals of capacitors C[1] to C[N] via switches S[1] to C[N].

[0020] Furthermore, a reference change switch Str is provided in conjunction with the reference change capacitor Ctr. An analog input signal Ain or a ground voltage GND can be applied to the second terminal of the reference change capacitor Ctr via the reference change switch Str. The voltage applied to the first comparison wiring WR1 is the first comparison voltage V1.

[0021] Figure 2 shows the connection relationship between capacitor C[i], switch S[i], and wiring WR_Ain, WR_VD1, and WR_GND. Switches S[1] to S[N] each have a common terminal T. COM It also has switching terminals Ta, Tb and Tc. Common terminal T of switches S[1]~S[N] COM These are connected to the second terminals of capacitors C[1] to C[N], respectively. For example, the common terminal T of switch S[1]. COM It is connected to the second terminal of capacitor C[1] and to the common terminal T of switch S[2]. COM This is connected to the second terminal of capacitor C[2]. The same applies to switches S[3], etc. Each switching terminal Ta of switches S[1] to S[N] is connected to the wiring WR_Ain and receives the analog input signal Ain. Each switching terminal Tb of switches S[1] to S[N] is connected to the wiring WR_VD1 and receives the first reference voltage VD1. Each switching terminal Tc of switches S[1] to S[N] is connected to the wiring WR_GND and receives the ground voltage GND.

[0022] Under the control of the control circuit 30, at each of the switches S[1] to S[N], the common terminal T COM It is selectively connected to one of the switching terminals Ta, Tb, and Tc. However, in switch S[i], the common terminal T COM It is also possible that it is not connected to any of the switching terminals Ta, Tb, and Tc.

[0023] In the following, for any switch S[i], the common terminal T COM The states in which the switching terminals Ta, Tb, and Tc are connected correspond to the signal input state, power supply connection state, and ground connection state, respectively. Also, the common terminal T COMThe state where it is not connected to any of the switching terminals Ta, Tb, and Tc is the open state. In the signal input state, power supply connection state, and ground connection state of the switch S[i], the analog input signal Ain, the first reference voltage VD1, and the ground voltage GND are applied to the second end of the capacitor C[i], respectively. In FIG. 1, as an example, all of the switches S[1] to S[N] are shown in the signal input state.

[0024] FIG. 3 is a diagram showing the connection relationship between the reference change capacitor Ctr, the reference change switch Str, and the wirings WR_Ain and WR_GND. The reference change switch Str has a common terminal T COM and the switching terminals Ta and Tc. The common terminal T COM of the reference change switch Str, and the switching terminals Ta and Tc have the same configuration as the common terminal T COM of the switches S[1] to S[N] and the switching terminals Ta and Tc. That is, the common terminal T COM of the reference change switch Str is connected to the second end of the reference change capacitor Ctr. Each switching terminal Ta of the reference change switch Str is connected to the wiring WR_Ain to receive the analog input signal Ain. The switching terminal Tc of the reference change switch Str is connected to the wiring WR_GND to receive the ground voltage GND.

[0025] Under the control of the control circuit 30, in the reference change switch Str, the common terminal T COM is selectively connected to the switching terminal Ta or Tc. However, it may be possible that the common terminal T COM of the reference change switch Str is not connected to any of the switching terminals Ta and Tc. In FIG. 1, as an example, the reference change switch Str is shown in the signal input state.

[0026] The sampling switch 50 is installed in series between the first comparison wiring WR1 and the second reference voltage VD2. The control circuit 30 controls the sampling switch 50 to be on or off. When the sampling switch 50 is on, the second reference voltage VD2 is supplied to the first comparison wiring WR1. When the sampling switch 50 is off, the wiring between the first comparison wiring WR1 and the second reference voltage VD2 is disconnected. In other words, when the sampling switch 50 is off, the second reference voltage VD2 is not supplied to the connecting wiring. In Figure 1, the state in which the sampling switch 50 is on is shown as an example.

[0027] In the AD converter 1, the second reference voltage VD2 is not particularly limited; here, it is set to half the voltage of the first reference voltage VD1 (VD1 / 2), but it may also be the ground voltage GND. By setting the second reference voltage VD2 to half the voltage of the first reference voltage VD1, the second comparison voltage V2 of the comparator 20 can be set to half the voltage of the first reference voltage VD1, making it easier to generate the second comparison voltage V2.

[0028] Each of the switches S[1]~[N], the reference change switch Str, and the sampling switch 50 may be composed of any switching element such as a MOS field-effect transistor. Switches S[1]~[N] and the reference change switch Str may be multiplexers. With respect to any switch, when the control circuit 30 controls the switch to a state of interest, it is equivalent to the control circuit 30 setting the state of the switch to that state of interest.

[0029] The comparator 20 is connected to the first comparison wire WR1 and the second comparison wire WR2. As described above, the first comparison voltage V1 is applied to the first comparison wire WR1. On the other hand, the second comparison voltage V2 is applied to the second comparison wire WR2. The second comparison voltage V2 is half the voltage of the first reference voltage VD1 (VD1 / 2).

[0030] Comparator 20 compares the first comparison voltage V1 and the second comparison voltage V2, and generates and outputs a comparison result signal S indicating the comparison result (high / low relationship) between the first comparison voltage V1 and the second comparison voltage V2. CMP The comparison result signal S CMP is a binary signal having a value of "0" or "1". Comparator 20 has a non-inverting input terminal, an inverting input terminal, and an output terminal. Here, it is assumed that the non-inverting input terminal is connected to the second comparison wiring WR2, and the inverting input terminal is connected to the first comparison wiring WR1.

[0031] That is, when "V1 > V2", comparator 20 outputs a comparison result signal S CMP with a value of "0", and when "V1 < V2", it outputs a comparison result signal S CMP with a value of "1". When "V1 = V2" holds, the comparison result signal S CMP is assumed to have a value of "0".

[0032] The control circuit 30 overall controls the AD conversion operation and outputs the digital output signal Dout obtained by the AD conversion operation. The control circuit 30 receives the comparison result signal S CMP . Based on the comparison result signal S CMP , the control circuit 30 determines the value of the corresponding bit. In this embodiment, when the value of the comparison result signal S CMP is "1", the value of the corresponding bit is set to 1, and when it is "0", the value of the corresponding bit is set to "0". A register 31 is provided in the control circuit 30, and the AD conversion value for each bit is stored in the register 31. Then, the control circuit 30 outputs the data stored in the register 31 as the digital output signal Dout.

[0033] Also, the control circuit 30 individually controls the states of switches S[1] to S[N] by supplying a control signal CNT DAC (DAC input signal) to the DAC10. Further, the control circuit 30 controls the state of the reference change switch Str by supplying the control signal CNT A to the reference change switch Str. The control circuit 30 supplies the control signal CNT SBy supplying this, the state of the sampling switch 50 is controlled.

[0034] The voltage generation circuit 40 generates a second comparison voltage V2 and supplies the generated second comparison voltage V2 to the second comparison wiring WR2. The second comparison voltage V2 is determined by the second reference voltage VD2, which, as described above, is set to half of the first reference voltage VD1.

[0035] Figure 4 shows the capacitance of each capacitor in the capacitor array 11. In the capacitor array 11 in Figure 4, for any integer i, the capacitance of capacitor C[i+1] is greater than the capacitance of capacitor C[i]. Here, as shown in Figure 4, capacitor C[i] in the capacitor array 11 is "2 i-1 It is assumed that the capacitor has a capacitance of "·C". Therefore, as shown in Figure 4, for any integer i, the capacitance of capacitor C[i+1] is twice the capacitance of capacitor C[i]. Here, "C" represents a predetermined unit capacitance. The capacitance of the reference changing capacitor Ctr is "M·C" (where M is a positive integer). Note that the capacitance of the reference changing capacitor Ctr can be the same as the smallest capacitance of the capacitors C[1] to C[N] that make up the capacitor array 11. That is, in the example shown in Figure 4, M is "1" and the capacitance is "C". However, the capacitance of the reference changing capacitor Ctr is not limited to this.

[0036] Next, the AD conversion operation will be explained with reference to the diagram. In the following AD conversion operation, the number of arrays N of the capacitor array 11 and switch array 12 will be assumed to be 4. Figure 5 is a flowchart of the AD conversion operation. In the AD conversion operation, the sampling operation in step S1 is performed first. Next, the sequential comparison operation in step S3 is performed after the state transition operation in step S2. Finally, the result output operation in step S4 is performed. The period during which the sampling operation is performed is called the sampling period, and the period during which the sequential comparison operation is performed is called the sequential comparison period. Also, the operation from the sampling operation to the sequential comparison operation is called the state transition operation, and the period during which the state transition operation is performed is called the state transition period.

[0037] The sampling period has a predetermined duration. During the sampling period, the control circuit 30 controls all switches S[1] to S[N] and the reference change switch Str within the DAC 10 to the signal input state. Simultaneously, the control circuit 30 controls the sampling switch 50 to the ON state.

[0038] During the sampling period, the first comparison wiring WR1 is connected to the application terminal of the second reference voltage VD2 via the sampling switch 50. The first terminals of capacitors C[1]~C[N] and the reference changing capacitor Ctr in the capacitor array 11 are connected to the second reference voltage VD2, and the second terminals are connected to the analog input signal Ain. In other words, as shown in Figure 1, the first terminals of capacitors C[1]~C[N] are subjected to the second reference voltage VD2, i.e., VD1 / 2. Also, the analog input signal Ain is input to the second terminals of capacitors C[1]~C[N]. Therefore, the sampling voltage VS, which is the voltage between the first and second terminals of capacitors C[1]~C[N] and the reference changing capacitor Ctr, is expressed by the following formula (Equation 1).

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[0039] Therefore, charge accumulates in capacitors C[1] to C[N] and the reference changing capacitor Ctr due to the sampling voltage VS. Note that the operation of comparator 20 and voltage generation circuit 40 may be stopped during the sampling period.

[0040] During the sampling period, capacitors C[1] to C[N] and the reference change capacitor Ctr are connected in parallel, and the sampling voltage VS is applied to all capacitors. Therefore, the sampling charge Qsmp accumulated in capacitors C[1] to C[N] and the reference change capacitor Ctr during the sampling period can be expressed by the following formula (Equation 2), where Cdac is the combined capacitance of capacitors C[1] to C[N] and Ca is the capacitance of the reference change capacitor Ctr.

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[0041] Figure 6 is a flowchart showing an example of the state transition operation flow. In the example in Figure 6, during the state transition period, the operations in steps S21 and S22 are executed in this order. The operations in steps S21 and S22 are the transition switching operation and the connection disconnection operation, respectively.

[0042] Figure 7 is a configuration diagram showing the state of the AD converter 1 after the state transition period has ended. In the transition switching operation of step S21, the state of the sampling switch 50 is switched from on to off. After step S21, the sampling switch 50 remains in the off state until the successive comparison operation of step S3 is completed. In the disconnection operation of step S22, the states of switches S[1] to S[N] and the reference change switch Str of the DAC 10 are all switched from the signal input state to the open state. At this time, the sampling charge Qsmp is maintained in capacitors C[1] to C[N] and the reference change capacitor Ctr.

[0043] In the state transition operation, the transition timing of each state of switches S[1] to S[N], the reference change switch Str, and the sampling switch 50 can be changed in various ways. For example, in the state transition operation, multiple steps may be set and executed simultaneously, or the steps may be rearranged.

[0044] As described above, the sampling switch 50 is kept in the off state during the successive comparison period in which the successive comparison operation is performed. Figure 8 shows the structure of register 31. As shown in Figure 8, register 31 has a storage capacity of N bits and stores values ​​Rg[1] to Rg[N]. Each of the values ​​Rg[1] to Rg[N] is either "0" or "1". For any integer i, the value Rg[i+1] is the value of the higher-order bit of the value Rg[i]. In the successive comparison operation, values ​​Rg[1] to Rg[N] are determined one bit at a time from the higher-order bit side, and the determined value Rg[i] becomes the value of the i-th bit in the digital output signal Dout.

[0045] During the successive comparison period, switches S[1] to S[N] are individually set to either a power supply connected state or a ground connected state. The charge accumulated in the capacitor array 11 during the sampling period is distributed to capacitors C[1] to C[N] during the successive comparison period. The distribution state depends on the state of switches S[1] to S[N] during the successive comparison period, and therefore the first comparison voltage V1 changes depending on the state of switches S[1] to S[N] during the successive comparison period. The control circuit 30 receives the comparison result signal S during the successive comparison operation (in other words, during the successive comparison period). CMP Based on this, the state of the switch array 12 is sequentially switched by binary search, and the values ​​Rg[1] to Rg[N] (i.e., the value of the digital output signal Dout) are determined bit by bit.

[0046] After the sampling operation is completed, in the successive comparison operation, at least one of switches S[1] to S[N] is switched to the power-connected state, and the remaining switches and the reference change switch Str are switched to the ground-connected state. During the successive comparison period, the sampling switch 50 is kept in the off state. Therefore, the charge on the first comparison wiring WR1 does not move, and the charge accumulated during the sampling operation is maintained. Therefore, in the successive comparison operation, the first comparison voltage V1 is expressed by the following formula (Equation 3).

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[0047] In successive comparison operation, the comparator 20 compares the first comparison voltage V1 and the second comparison voltage V2 to obtain the comparison result signal S. CMP Output as: Comparison result signal S CMP When the value is "1", that is, when the first comparison voltage V1 is less than the second comparison voltage V2, the control circuit 30 sets the value of the corresponding bit to "1". Also, the comparison result signal S CMP When the value is "0", that is, when the first comparison voltage V1 is greater than or equal to the second comparison voltage V2, the control circuit 30 sets the value of the corresponding bit to "0".

[0048] As described above, the first comparison voltage V1 output during the successive comparison period is determined by the combined capacitance Cdac of capacitors C[1] to C[N], the capacitance Ca of the reference changing capacitor Ctr, the first reference voltage VD1, and the analog input signal Ain.

[0049] In the AD converter 1, the analog input signal Ain is converted to a digital output signal Dout based on the change in the first comparison voltage V1 due to the change in the state of capacitors C[1] to C[N] and the reference changing capacitor Ctr, as described above. The series of operations of the AD converter will be explained with reference to the diagram.

[0050] Figure 9 is a flowchart illustrating an example of the successive comparison operation. In the successive comparison operation shown in Figure 9, the value of N is assigned to the variable j managed by the control circuit 30 (step S31). Subsequently, the control circuit 30 controls switch S[j] to a power-connected state and controls all switches S[1] to S[j-1] to a ground-connected state (step S32). Note that when "N=1", switches S[1] to S[j-1] do not exist, so in the process of step S32, only switch S[1] is controlled to a power-connected state.

[0051] The control circuit 30 receives the current comparison result signal S CMP The value is obtained and the result signal S is compared. CMP Check whether it is "1" or not (step S33). In other words, the comparison result signal S output from comparator 20. CMP The value is obtained and the result signal S is compared. CMP Determine whether the value is "1" or not. Comparison result signal S CMP If the value is "1" (Yes in step S33), the control circuit 30 determines the value Rg[j] to be "1" (step S34). Then, the control circuit 30 maintains the switch S[j] in a power-connected state (step S35). From there, the switch S[j] remains in a power-connected state until the sequential comparison operation shown in Figure 9 is completed. Note that since virtually nothing is done in step S35, step S35 may be omitted.

[0052] Comparison result signal S CMPIf the value is "0" (No in step S33), the control circuit 30 determines the value Rg[j] to be "0" (step S36). Then, the control circuit 30 switches the state of switch S[j] from power supply connected state to ground connected state (step S37). From there, switch S[j] remains in the ground connected state until the sequential comparison operation shown in Figure 9 is completed.

[0053] After maintaining switch S[j] in the power-connected state in step S35, or after switching switch S[j] to the ground-connected state in step S37, the control circuit 30 checks if variable j is 1. If variable j is not 1 (the case of No in step S38), 1 is subtracted from variable j (step S39), and the process returns to step S32 and the subsequent processing is repeated. For example, in the processing of the second step S32, switch S[N-1] will be set to the power-connected state and switches S[1] to S[N-2] will be set to the ground-connected state. At this time, in the first step S33, “S CMP If =1”, in the second step S32, switch S[N] is set to power-connected state, and in the first step S33, “S CMP If the result is "=0", then in the second step S32, switch S[N] is connected to ground.

[0054] The process consisting of steps S32 to S37 is a unit comparison operation. Thus, the successive comparison operation includes the 1st to the Nth unit comparison operation. The unit comparison operation performed when "j=N" is the Nth unit comparison operation, the unit comparison operation performed when "j=N-1" is the (N-1)th unit comparison operation, ..., the unit comparison operation performed when "j=1" is the 1st unit comparison operation. In the jth unit comparison operation, the value Rg[j] is determined, that is, the value of the jth bit of the digital output signal Dout is determined.

[0055] If "j=1" (if Yes is selected in step S38), the sequential comparison operation shown in Figure 9 is completed. At this stage, all values ​​Rg[1] to Rg[N] have been determined.

[0056] In the result output operation of step S4 (see Figure 5), the control circuit 30 outputs a digital signal having the values ​​Rg[1] to Rg[N] determined in the successive comparison operation of step S3 as a digital output signal Dout. The digital output signal Dout is output to any circuit (not shown) that utilizes the digital output signal Dout.

[0057] Here, the features of the AD converter 1 of this embodiment will be explained with reference to the reference AD ​​converter 91 shown in Figure 11, which will be described later. For the sake of simplicity, both AD converters will be described as being capable of outputting a 4-bit digital output signal, i.e., "N=4". Figure 10 is a diagram showing an example of the AD converter 1 of this embodiment. In the example in Figure 10, the AD converter 1 is shown in the sampling state, and switches S[1] to S[4] of the DAC10 are in the signal input state. Also, the reference changing capacitor Ctr is in the signal input state.

[0058] Capacitors C[1] to C[4] in the capacitor array 11 of AD converter 1 and capacitors C[1] to C[4] in the capacitor array 911 of reference AD ​​converter 91 are all capacitors with the same capacitance. In this case, the capacitances of each capacitor C[1] to C[4] are "1C", "2C", "4C", and "8C", respectively, and the combined capacitance of capacitors C[1] to C[4] in capacitor array 11 is "15C". The capacitance of the reference changing capacitor Ctr in AD converter 1 is "1C".

[0059] Figure 11 shows the configuration of the reference AD ​​converter 91. As shown in Figure 11, the reference AD ​​converter 91 includes a DAC 910 having a capacitor array 911 and a switch array 912, a comparator 920, a control circuit 930, a voltage generation circuit 940, and a sampling switch 950. The first terminals of each capacitor in the capacitor array 911 are commonly connected to wiring WR91. A first comparison voltage V91 is applied to wiring WR91. Wiring WR91 is connected to the inverting input terminal of comparator 920.

[0060] Wiring WR92 is connected to the non-inverting input terminal of comparator 920. Voltage generation circuit 940 is connected to wiring WR92, supplying the second reference voltage V92. Sampling switch 950 is placed between the second reference voltage VD2 (=VD1 / 2) and wiring WR91. When sampling switch 950 is on, it supplies the second reference voltage VD2 to wiring WR91. In DAC910, the analog input signal Ain is input via wiring WR_Ain.

[0061] In the reference AD ​​converter 91, during sampling, as shown in Figure 11, the wiring to which the analog input signal Ain is applied via the switch array 912 is connected to the second terminal of each capacitor in the capacitor array 911, thereby accumulating a charge corresponding to the analog input signal Ain in each capacitor of the capacitor array 911. At this time, the sampling switch 950 is turned on, and the sampling voltage VS applied between the first and second terminals of each capacitor in the capacitor array 911 is expressed by the following formula (Equation 4).

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[0062] Subsequently, in the successive approximation operation, with the sampling switch 950 kept off, the first reference voltage VD1 or ground voltage GND is applied to the second terminal of each capacitor in the capacitor array 911 using the switch array 912. The first comparison voltage V1 in the successive approximation operation of the reference AD ​​converter 91 is expressed by the following formula (Equation 5).

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[0063] In successive comparison operation, the control circuit 930 converts the analog input signal Ain into a digital signal by binary search while sequentially switching the state of the switch array 912 based on the comparison result of the first comparison voltage V91 and the second comparison voltage V92 by the comparator 920. The control circuit 930 is also provided with a register 931, which can store the value of the digital output signal Dout.

[0064] Here, the voltage applied to the DAC10 of the AD converter 1 and the capacitor array 911 of the reference AD ​​converter 91 in this embodiment, and the charge accumulated, will be explained. Figure 12 is a diagram showing the relationship between the input voltage and the digital output value in the AD converter 1 according to this embodiment. Figure 13 is a diagram showing the relationship between the input voltage and the digital output value in the reference AD ​​converter 91.

[0065] Figures 12 and 13 both show the analog input signal Ain on the horizontal axis and the digital output signal Dout on the vertical axis. Both AD converter 1 and reference AD ​​converter 91 are capable of converting input data into 4-bit digital data, and the maximum value of the digital output for both is 0b1111.

[0066] As shown in Figure 13, in the reference AD ​​converter 91, the input signal Ain at which the digital output is 0b1111 is VD1, according to equation 5. Here, if the range of the analog input signal Ain when the digital output value changes from the minimum value to the maximum value is defined as the full-scale input voltage, then the full-scale voltage of the reference AD ​​converter 91 is from the ground voltage GND to VD1. In other words, the reference AD ​​converter 91 has a configuration that can convert the analog input signal Ain with a voltage from the ground voltage GND to VD1 into 4-bit data.

[0067] As shown in Figure 12, from equation 3 above, the input signal Ain for which the digital output of AD converter 1 is 0b1111 is [Cdac / (Cdac+Ca)]·VD1. In other words, the full-scale voltage of AD converter 1 is from the ground voltage GND to [Cdac / (Cdac+Ca)]·VD1. Here, if we use the above values ​​as the capacitance of each capacitor C[1] to C[4], the full-scale voltage of AD converter 1 is 15 / 16VD1 from the ground voltage GND. In other words, AD converter 1 has a configuration that can convert an input signal with a voltage in the range of 15 / 16·VD1 from the ground voltage GND into 4-bit data.

[0068] Furthermore, by opening the reference change switch Str and starting the sampling operation, the full-scale voltage of AD converter 1 can be set to the range from ground voltage GND to VD1, similar to the reference AD ​​converter 91.

[0069] In other words, AD converter 1 can compress the full-scale voltage compared to reference AD ​​converter 91, and when the amplitude of the analog input signal Ain is small, using AD converter 1 allows for more effective use of the resolution compared to using reference AD ​​converter 91.

[0070] For example, the amplitude of an analog input signal may not change from the ground voltage GND to VD1. In such cases, some of the 4-bit digital values ​​in the reference AD ​​converter 91 cannot be used.

[0071] On the other hand, in the case of AD converter 1, the full-scale voltage is compressed from the ground voltage GND to 15 / 16VD1, so it is possible to make more effective use of the resolution of AD converter 1 compared to reference AD ​​converter 91.

[0072] As described above, by using a reference changing capacitor Ctr, as in the AD converter 1 of this embodiment, the full-scale voltage of the AD converter 1 can be compressed. Therefore, even when the amplitude of the analog input signal Ain is small, the resolution of the AD converter 1 can be effectively utilized. This makes it possible to output a high-resolution digital output signal Dout.

[0073] <First variation> Figure 14 is a configuration diagram of the first modified AD converter 1A. Figure 15 is an enlarged view of the reference changing capacitance section Ct2 and the selection switch Scot. The AD converter 1A shown in Figure 14 differs from the AD converter 1 in that it has a reference changing capacitance section Ct2 with reference changing capacitors Ctr1, Ctr2, and Ctr3, and a selection switch Scot. The other parts of the AD converter 1A have substantially the same configuration as the AD converter 1. Therefore, the same reference numerals are used for the parts of the AD converter 1A that are the same as those of the AD converter 1, and detailed explanations of these parts are omitted.

[0074] As shown in Figure 14, the AD converter 1A has a reference changing capacitor section Ct2 having multiple (in this case, three) reference changing capacitors Ctr1, Ctr2, and Ctr3, and a selection switch Sct. As shown in Figure 14, in the reference changing capacitor section Ct2, the reference changing capacitors Ctr1, Ctr2, and Ctr3 are connected in parallel. The first end of each of the reference changing capacitors Ctr1, Ctr2, and Ctr3 is connected to the selection switch Sct. The first end of the reference changing capacitors Ctr1, Ctr2, and Ctr3 is connected to the selection switch Sct.

[0075] As shown in Figure 15, the selection switch Sct has the same configuration as switches S[1] to S[N]. In other words, the selection switch Sct has a common terminal T COM It has switching terminals Ta, Tb, and Tc.

[0076] Common terminal T COMIt is connected to the first comparison wiring WR1. Furthermore, the switching terminals Ta, Tb, and Tc are connected to the first terminals of the reference changing capacitors Ctr1, Ctr2, and Ctr3, respectively. The selection switch Sct is connected to the control signal CNT from the control circuit 30. B Based on this, common terminal T COM It operates to connect to one of the switching terminals Ta, Tb, or Tc. Also, with the selection switch Sct, the common terminal T COM This may include an open state where none of the switching terminals Ta, Tb, or Tc are connected. The selection switch Sct selects one reference changing capacitor from the reference changing capacitors Ctr1, Ctr2, and Ctr3. It is also possible to use a multiplexer as the selection switch Sct.

[0077] The capacitance Ca1 of the reference-changing capacitor Ctr1 is greater than the capacitance Ca2 of the reference-changing capacitor Ctr2. Also, the capacitance Ca2 of the reference-changing capacitor Ctr2 is greater than the capacitance Ca3 of the reference-changing capacitor Ctr3. In other words, the relationship Ca1 > Ca2 > Ca3 holds for the capacitances of the reference-changing capacitors Ctr1, Ctr2, and Ctr3. By controlling the selection switch Scot and switching the connected reference-changing capacitors, the capacitance of the reference-changing capacitor section Ct2 can be changed.

[0078] When the reference change capacitor Ctr1 is selected, the full-scale voltage of AD converter 1A is [Cdac / (Cdac+Ca1)]·VD1 from the ground voltage GND. Similarly, when the reference change capacitor Ctr2 is selected, the full-scale voltage of AD converter 1A is [Cdac / (Cdac+Ca2)]·VD1 from the ground voltage GND. When the reference change capacitor Ctr3 is selected, the full-scale voltage of AD converter 1A is [Cdac / (Cdac+Ca3)]·VD1 from the ground voltage GND.

[0079] The control circuit 30 determines an appropriate capacitor from among the reference changing capacitors Ctr1, Ctr2, and Ctr3 according to the amplitude of the analog input signal Ain, and switches the selection switch Sct using the control signal CNT B Outputs.

[0080] For example, when the amplitude of the analog input signal Ain is small, a higher compression ratio of the full-scale voltage allows for more efficient use of the resolution of the AD converter 1A. Therefore, the AD converter 1A may, for example, use two thresholds Th1 and Th2 to select the reference changing capacitor Ctr1 when the amplitude of the analog input signal Ain is smaller than threshold Th1, Ctr2 when it is greater than or equal to threshold Th1 and less than threshold Th2, and Ctr3 when it is greater than or equal to threshold Th2. Note that the above-described method of selecting the reference changing capacitors Ctr1, Ctr2, and Ctr3 is just one example, and other methods may be adopted. Regardless of the method of selecting the reference changing capacitors, the control circuit 30 is configured to select a reference changing capacitor with a large capacitance when the amplitude of the analog input signal Ain becomes small.

[0081] Furthermore, in the AD converter 1A, a variable capacitance capacitor may be used instead of the combination of reference changing capacitors Ctr1, Ctr2, and Ctr3 and the selection switch Sct. Even when a variable capacitance capacitor is used, the control circuit 30 may be configured to control the variable capacitance capacitor so that its capacitance increases when the amplitude of the analog input signal Ain decreases.

[0082] <Second Embodiment> A second embodiment will be described with reference to the drawings. Figure 16 is a configuration diagram of the AD converter 1B of the second embodiment. The AD converter 1B shown in Figure 16 has a differential input configuration. The AD converter 1B is a successive approximation type AD conversion circuit, similar to the AD converter 1 described above. A first analog input signal AinP and a second analog input signal AinN are input to the AD converter 1B. The AD converter 1B performs AD conversion on the difference signal Adif between the first analog input signal AinP and the second analog input signal AinN. The difference signal Adif can be said to be an analog input signal having the potential of the first analog input signal AinP as seen from the potential of the second analog input signal AinN.

[0083] The AD converter 1B shown in Figure 16 includes a first conversion unit 100P, a second conversion unit 100N, a comparator 20B, and a control circuit 30B. The first conversion unit 100P and the second conversion unit 100N have the same configuration as the AD converter 1A shown in Figure 14, excluding the comparator 20 and the control circuit 30.

[0084] The first conversion unit 100P includes a DAC 10P, a first sampling switch 50P, a first reference changing capacitor Ct1P having a first reference changing capacitor CtrP, and a first reference changing switch StrP. These components correspond to the DAC 10, sampling switch 50, reference changing capacitor Ct1 having a reference changing capacitor Ctr, and reference changing switch Str of the AD converter 1, respectively. The first analog input signal AinP is input to the wiring WR_AinP of the first conversion unit 100P. The first sampling switch 50P is also provided to supply the second reference voltage VD2 to the first comparison wiring WR1.

[0085] Similarly, the second conversion unit 100N includes a DAC 10N, a second sampling switch 50N, a second reference change capacitance unit Ct1N having a second reference change capacitor CtrN, and a second reference change switch StrN. These components respectively correspond to the DAC 10, the sampling switch 50, the reference change capacitance unit Ct1 having a reference change capacitor Ctr, and the reference change switch Str of the AD converter 1. The second analog input signal AinN is input to the wiring WR_AinN of the first conversion unit 100P. The second conversion unit 100N also has a second comparison wiring WR2 corresponding to the first comparison wiring WR1 of the AD converter 1B. The second sampling switch 50N is provided so as to supply the second reference voltage VD2 to the second comparison wiring WR2. For example, in the AD converter 1B, the capacitance of the first reference change capacitance unit Ct1P and the capacitance of the second reference change capacitance unit Ct1N are substantially the same. By doing so, the first analog input signal AinP and the second analog input signal AinN are compared with data converted at the same full-scale voltage.

[0086] Comparator 20B is connected to the first comparison wiring WR1 and the second comparison wiring WR2. Similar to the comparator 20 of the AD converter 1, comparator 20B compares the first comparison voltage V1 and the second comparison voltage V2, and generates and outputs a comparison result signal S CMP indicating the comparison result (high / low relationship) between the first comparison voltage V1 and the second comparison voltage V2. However, in the AD converter 1B, the second comparison voltage V2 is output from the DAC 10N. The comparison result signal S CMP is a binary signal having a value of "0" or "1". Comparator 20B has a non-inverting input terminal, an inverting input terminal, and an output terminal. Here, the inverting input terminal is connected to the first comparison wiring WR1 and the non-inverting input terminal is connected to the second comparison wiring WR2. Comparator 20 outputs a comparison result signal S CMP with a value of "0" when "V1 > V2", and outputs a comparison result signal S CMP with a value of "1" when "V1 < V2". When "V1 = V2", the comparison result signal S CMP has a value of "0".

[0087] The control circuit 30B receives the comparison result signal S. CMP The control circuit 30B controls the AD conversion operation as a whole and outputs the digital output signal Dout obtained by the AD conversion operation. Similar to the control circuit 30 of the AD converter 1, the control circuit 30B is provided with a register 31, in which the value of the digital output signal Dout can be stored. The control circuit 3B receives the control signal CNT from the DACs 10P and 10N. DAC By supplying the (DAC input signal), the states of switches S[1] to S[N] in DAC10P and 10N are controlled individually.

[0088] The control circuit 30B controls the first reference change switch StrP and the second reference change switch StrN with a control signal CNT A By supplying this signal, the states of the first reference change switch StrP and the second reference change switch StrN are controlled. In addition, a control signal CNT is supplied to the first sampling switch 50P and the second sampling switch 50N. S The supply of this power controls the states of the first sampling switch 50P and the second sampling switch 50N.

[0089] In both DAC10P and 10N, the capacitances of capacitors C[1] to C[n] are set in the same way as in DAC10 of AD converter 1B.

[0090] The conversion operation in AD converter 1B is the same as that of AD converter 1. Therefore, details of the conversion operation are omitted. In the AD conversion operation for the difference signal Adif in AD converter 1B, the difference signal Adif is converted into a digital signal by binary search, and the resulting digital signal is output as the digital output signal Ddif. The digital output signal Ddif is an N-bit digital signal, similar to AD converter 1B.

[0091] <Second variation> Figure 17 is a configuration diagram of the second modified AD converter 1C. The AD converter 1C shown in Figure 17 differs from the AD converter 1B in that it has a first reference changing capacitance unit Ct2P, a second reference changing capacitance unit Ct2N, a first selection switch SctP, and a second selection switch SctN. The other parts of the AD converter 1C have substantially the same configuration as the AD converter 1B. Therefore, the same reference numerals are used for the parts of the AD converter 1C that are the same as those of the AD converter 1B, and detailed explanations of these parts are omitted.

[0092] Furthermore, both the first reference changing capacitance section Ct2P and the second reference changing capacitance section Ct2N have first reference changing capacitors Ctr1, Ctr2, and Ctr3 and second reference changing capacitors Ctr1, Ctr2, and Ctr3, each with different capacitances. The first reference changing capacitors Ctr1, Ctr2, and Ctr3 and the second reference changing capacitors Ctr1, Ctr2, and Ctr3 are configured to have the same capacitance, which is the same capacitance as the reference changing capacitors Ctr1, Ctr2, and Ctr3 of the reference changing capacitance section Ct2 of the AD converter 1A.

[0093] In the AD converter 1C, the capacitances of the first reference changing capacitance section Ct2P and the second reference changing capacitance section Ct2N are changed by controlling the first selection switch ScrtP and the second selection switch ScrtN. The control circuit 30B controls the first selection switch ScrtP and the second selection switch ScrtN so that the capacitance of the first reference changing capacitance section Ct2P and the capacitance of the second reference changing capacitance section Ct2N become the same.

[0094] In this way, by controlling the first selection switch ScotP and the second selection switch ScotN, the resolution can be effectively utilized regardless of the amplitude of the first analog input signal AinP and the second analog input signal AinN. Furthermore, since the first reference changing capacitance section Ct2P and the second reference changing capacitance section Ct2N are controlled to have the same capacitance, the first analog input signal AinP and the second analog input signal AinN are converted with the same full-scale voltage. As a result, the difference signal Adif can be accurately digitized and output as a digital output signal Ddif.

[0095] Even in the AD converter 1B, which has a differential input configuration, a high-resolution digital output signal Ddif can be output even when there is variation in the magnitude of the differential signal Adif.

[0096] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure is indicated by the claims rather than by the description of the embodiments, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0097] <Note> The various embodiments described above will be summarized below.

[0098] The successive approximation AD conversion circuit (1, 1A) described above is a successive approximation AD conversion circuit configured to convert an analog input signal (Ain) into a digital output signal, A capacitor-type DAC (10) has a capacitor array (11) and a switch array (12) connected to the capacitor array (11), and during the sampling period, a wire to which an analog input signal (Ain) is applied is connected to the capacitor array (11) via the switch array (12), thereby accumulating charge in each capacitor (C[1]~C[N]) in the capacitor array (11) according to the analog input signal (Ain), and during the successive comparison period after the sampling period, a first reference voltage (VD1) or ground voltage (GND) is supplied to each capacitor (C[1]~C[N]) in the capacitor array (11) via the switch array (12), and a first comparison voltage (V1) based on the accumulated charge in the capacitor array (11) is generated on the first comparison wire (WR1), and It is connected to the first comparison wire (WR1) and the second comparison wire (WR2) to which the second comparison voltage (V2) is applied, and during the sequential comparison period, the first comparison voltage (V1) and the second comparison voltage (V2) are compared to produce a comparison result signal (S CMP A comparator (20) configured to generate ) During the successive comparison period, the comparison result signal (S CMP A control circuit (30) is configured to determine the value of a digital output signal (Dout) while controlling the state of the switch array (11) based on the above, A sampling switch (50) is configured to be placed between the first reference wiring (WR1) and the second reference voltage (VD1), A reference change capacitance section (Ct1, Ct2) having a first terminal connected to the first comparison wiring (WR1), The configuration (first configuration) includes a reference changing switch (Str) configured to selectively supply an analog input signal (Ain) or a ground voltage (GND) to the second terminal of a reference changing capacitance unit (Ctr).

[0099] In the successive approximation AD conversion circuit (1, 1A) of the first configuration described above, the control circuit (30) applies a second reference voltage (VD2 = VD1 / 2) to the first comparison wire (WR1) by turning on the sampling switch (50) during the sampling period, and turns off the sampling switch (50) during the successive approximation period. The control circuit (30) is configured to apply an analog input signal (Ain) to the second terminal of the reference changing capacitor section (Ct1, Ct2) during the sampling period and a ground voltage (GND) during the successive comparison period, through the control of the reference changing switch (Str) (second configuration).

[0100] In the successive approximation AD conversion circuit (1, 1A) of the first or second configuration described above, the digital output signal (Dout) is an N-bit digital signal having the first to the Nth bit, The capacitor array (11) has first to N capacitors (C[1] to C[N]) corresponding to the first to Mth bits, each having a first end and a second end. The reference change capacitor section (Ct1, Ct2) has the same capacitance as the smallest capacitor (C[1]) (third configuration).

[0101] In the successive approximation AD conversion circuit (1A) of any of the first to third configurations described above, the reference changing capacitance section (Ct1, Ct2) has a configuration in which the capacitance can be changed as appropriate (fourth configuration).

[0102] In the fourth configuration of the successive approximation AD conversion circuit (1A) described above, the control circuit (30) is configured to increase the capacitance of the reference changing capacitance section (Ct1, Ct2) when the amplitude of the analog input signal (Ain) decreases (fifth configuration).

[0103] In the successive approximation AD conversion circuit (1A) of the fourth or fifth configuration described above, the reference changing capacitance section (Ct2) has a configuration comprising a plurality of reference changing capacitors (Ctr1, Ctr2, Ctr3) having different capacitances, and a selection switch (Sct) that selects one of the reference changing capacitors (Ctr1, Ctr2, Ctr3), The control circuit (30) has a configuration (sixth configuration) in which the capacitance of the reference changing capacitance section (Ct2) is changed by switching a selection switch (Sct).

[0104] The successive approximation AD conversion circuit (1B) described above is configured to convert the difference signal between a first analog input signal and a second analog input signal into a digital output signal, A first capacitor-type DAC (10P) has a first capacitor array (11) and a first switch array (12) connected to the first capacitor array (11), and during the sampling period, a wiring to which a first analog input signal (AinP) is applied is connected to the first capacitor array (11) via the first switch array (12) to accumulate charge in each capacitor (C[1]~C[N]) in the first capacitor array (11) corresponding to the first analog input signal (AinP), and during the successive comparison period after the sampling period, a first reference voltage (VD1) or ground voltage (GND) is supplied to each capacitor (C[1]~C[N]) in the first capacitor array (11) via the first switch array (12), and a first comparison voltage (V1) based on the accumulated charge in the first capacitor array (11) is generated on the first comparison wiring (WR1), A second capacitor type DAC (10N) having a second capacitor array (11) and a second switch array (12) connected to the second capacitor array (11), wherein during the sampling period, a wiring to which a second analog input signal (AinN) is applied is connected to the second capacitor array (11) via the second switch array (12) to accumulate charge in each capacitor (C[1]~C[N]) in the second capacitor array (11) corresponding to the second analog input signal (AinN), and during the successive comparison period after the sampling period, a first reference voltage (VD1) or ground voltage (GND) is supplied to each capacitor (C[1]~C[N]) in the second capacitor array (11) via the second switch array (12), and a second comparison voltage (V2) based on the accumulated charge in the second capacitor array (11) is generated on the second comparison wiring (WR2), It is connected to the first comparison wire (WR1) and the second comparison wire (WR2), and compares the first comparison voltage (V1) and the second comparison voltage (V2) during the sequential comparison period to produce a comparison result signal (S CMP A comparator (20B) configured to generate ) During the successive comparison period, the comparison result signal (SCMP A control circuit (30B) is configured to determine the value of the digital output signal (Dout) while controlling the state of the first switch array (12) and the state of the second switch array (12) based on the above, A first sampling switch (50P) is configured to be placed between the first comparison wiring (WR1) and the second reference voltage (VD2), A second sampling switch (50N) is configured to be placed between the second comparison wiring (WR2) and the second reference voltage (VD2), A first reference change capacitance unit (Ct1P) having a first terminal connected to the first comparison wiring (WR1), A first reference changing switch (StrP) is configured to selectively supply either a first analog input signal (AinP) or a ground voltage (GND) to the second terminal of the first reference changing capacitance unit (Ct1P), A second reference changing capacitance unit (Ct1N) having a first terminal connected to a second comparison wiring (WR2), The configuration (the seventh configuration) includes a second reference changing switch (StrN) configured to selectively supply either a second analog input signal (AinN) or a ground voltage (GND) to the second terminal of the second reference changing capacitance unit (Ct1N).

[0105] In the successive approximation AD conversion circuit (1B) of the seventh configuration described above, the control circuit (30B) is: The control circuit (30B) is During the sampling period, by turning on the first sampling switch (50P) and the second sampling switch (50N), a second reference voltage (VD2) is applied to the first connection wiring (WR1) and the second connection wiring (WR2), and a first analog input signal (AinP) is applied to the second terminal of the first reference changing capacitor (Ct1P) through the control of the first reference changing switch (StrP), and a second analog input signal (AinN) is applied to the second terminal of the second reference changing capacitor (Ct1N) during the sampling period through the control of the second reference changing switch (StrN). In the sequential comparison period, the first sampling switch (50P) and the second sampling switch (50N) are turned off, and a ground voltage (GND) is applied to the second terminal of the first reference changing capacitor (Ct1P) through the control of the first reference changing switch (StrP), and a ground voltage (GND) is applied to the second terminal of the second reference changing capacitor (Ct1N) through the control of the second reference changing switch (StrN) (the eighth configuration).

[0106] In the successive approximation AD conversion circuit (1B) of the seventh or eighth configuration described above, the digital output signal (Dout) is an N-bit digital signal having the first to the Nth bits, The first capacitor array (11) and the second capacitor array (11) each have first to Nth capacitors (C[1] to C[N]) corresponding to the first to Nth bits, each having a first terminal and a second terminal. The first reference-changing capacitance section (Ct1P) and the second reference-changing capacitance section (Ct1N) have the same capacitance as the smallest capacitor (C[1]) (the ninth configuration).

[0107] In the successive approximation AD conversion circuit (1B) of the seventh or eighth configuration described above, the first reference changing capacitor section (Ct2P) and the second reference changing capacitor section (Ct2N) are both configured to allow the capacitance to be changed as appropriate, and the capacitance of the first reference changing capacitor section (Ct2P) and the capacitance of the second reference changing capacitor section (Ct1N) are the same (the tenth configuration).

[0108] In a successive approximation AD conversion circuit (1B) having any of the above configurations 7, 8, and 10, The control circuit (30B) has a configuration (the 11th configuration) in which the capacitance of the first reference changing capacitor section (Ct2P) is increased when the amplitude of the first analog input signal (AinP) decreases, and the capacitance of the second reference changing capacitor section (Ct2N) is increased when the amplitude of the second analog input signal (AinN) decreases.

[0109] In a successive approximation AD conversion circuit (1C) having any of the above configurations 7, 8, 10, and 11, the first reference changing capacitor section (Ct2P) has a configuration comprising a plurality of first reference changing capacitors (Ctr1, Ctr2, Ctr3) having different capacitances and a first selection switch (SctP) configured to select one of the first reference changing capacitors (Ctr1, Ctr2, Ctr3), and the second reference changing capacitor section (Ct2N) has a configuration comprising a plurality of second reference changing capacitors (Crt1, Ctr2, Ctr3) having different capacitances and a second selection switch (SctN) configured to select one of the second reference changing capacitors (Ctr1, Ctr2, Ctr3). The control circuit (30B) has a configuration (the 12th configuration) in which the capacitance of the first reference changing capacitance section (Ct2P) is changed by switching the first selection switch (SctP), and the capacitance of the second reference changing capacitance section (Ct2N) is changed by switching the second selection switch (SctN). [Explanation of Symbols]

[0110] 1, 1A, 1B, 1C AD converters 11 Capacitor Array 12 Switch Array 20, 20B comparator 30 Control circuits 30B control circuit 30C control circuit 31 Registers 40 Voltage generation circuit 50 Sampling Switches 100P First Conversion Unit 100N Second Conversion Unit 50P First Sampling Switch 50N Second Sampling Switch 91 Reference AD ​​Converter 911 Capacitor Array 912 Switch Array 920 Comparator 930 Control circuit 931 Register 940 Voltage Generation Circuit 950 Sampling Switch ADIF difference signal Ct1 Capacity section for changing the standard Ct1P Capacity section for first standard change Ct1N Second Standard Change Capacity Section Ct2 Capacity section for changing the reference Ct2P Capacity section for first standard change Ct2N Second Standard Change Capacity Section Ctr, Ctr1, Ctr2, Ctr3 Capacitors for changing reference settings CtrP Capacitor for first-reference modification CtrN Second Reference Modification Capacitor GND Ground voltage S All Switches S Switch Sct selection switch SctP First Selection Switch SctN Second Selection Switch Str switch for changing the reference StrP 1st Standard Change Switch StrN 2nd Standard Change Switch

Claims

1. In a successive approximation AD conversion circuit configured to convert an analog input signal into a digital output signal, A capacitor-type DAC having a capacitor array and a switch array connected to the capacitor array, wherein during the sampling period, the wiring to which the analog input signal is applied is connected to the capacitor array via the switch array, thereby accumulating a charge corresponding to the analog input signal in each capacitor in the capacitor array, and during the successive comparison period after the sampling period, a first reference voltage or ground voltage is supplied to each capacitor in the capacitor array via the switch array, and a first comparison voltage based on the accumulated charge in the capacitor array is generated on the first comparison wiring, A comparator is connected to the first comparison wiring and the second comparison wiring to which the second comparison voltage is applied, and is configured to compare the first comparison voltage and the second comparison voltage during the sequential comparison period to generate a comparison result signal. A control circuit configured to determine the value of the digital output signal while controlling the state of the switch array based on the comparison result signal during the aforementioned sequential comparison period, A sampling switch configured to be positioned between the first comparison wiring and the second reference voltage, A reference changing capacitance unit having a first terminal connected to the first comparison wiring, A successive approximation AD conversion circuit having a reference changing switch configured to selectively supply the analog input signal or the ground voltage to the second terminal of the reference changing capacitance section.

2. The control circuit applies the second reference voltage to the first comparison wiring by turning on the sampling switch during the sampling period, and turns off the sampling switch during the sequential comparison period. The successive approximation AD conversion circuit according to claim 1, wherein the control circuit is configured to supply the analog input signal to the second terminal of the reference changing capacitor during the sampling period and the ground voltage during the successive approximation period, through the control of the reference changing switch.

3. The aforementioned digital output signal is an N-bit digital signal having bits 1 to N, The capacitor array has first to n capacitors, each corresponding to the first to nth bits and having a first end and a second end, The successive approximation AD conversion circuit according to claim 1, wherein the reference changing capacitance section has the same capacitance as the capacitor with the smallest capacitance.

4. The successive AD conversion circuit according to claim 1, wherein the capacitor section for changing the reference is configured to allow the capacitance to be changed as appropriate.

5. The successive AD conversion circuit according to claim 4, wherein the control circuit is configured to increase the capacitance of the reference changing capacitance section when the amplitude of the analog input signal decreases.

6. The reference change capacitor section has a configuration comprising a plurality of reference change capacitors having different capacitances, and a selection switch that selects one of the reference change capacitors. The successive AD conversion circuit according to claim 4 or 5, wherein the control circuit is configured to change the capacitance of the reference changing capacitance section by switching the selection switch.

7. In a successive approximation AD conversion circuit configured to convert the difference signal between a first analog input signal and a second analog input signal into a digital output signal, A first capacitor-type DAC having a first capacitor array and a first switch array connected to the first capacitor array, wherein during the sampling period, a wiring to which the first analog input signal is applied is connected to the first capacitor array via the first switch array, thereby accumulating a charge corresponding to the first analog input signal in each capacitor in the first capacitor array, and during the successive comparison period after the sampling period, a first reference voltage or ground voltage is supplied to each capacitor in the first capacitor array via the first switch array, and a first comparison voltage based on the accumulated charge in the first capacitor array is generated on the first comparison wiring, A second capacitor-type DAC having a second capacitor array and a second switch array connected to the second capacitor array, wherein during the sampling period, the wiring to which the second analog input signal is applied is connected to the second capacitor array via the second switch array, thereby accumulating charge in each capacitor in the second capacitor array corresponding to the second analog input signal, and during the successive comparison period after the sampling period, a first reference voltage or ground voltage is supplied to each capacitor in the second capacitor array via the second switch array, and a second comparison voltage based on the accumulated charge in the second capacitor array is generated on the second comparison wiring, A comparator connected to the first comparison wiring and the second comparison wiring, configured to compare the first comparison voltage and the second comparison voltage during the sequential comparison period to generate a comparison result signal, A control circuit configured to determine the value of the digital output signal while controlling the state of the first switch array and the state of the second switch array based on the comparison result signal during the aforementioned sequential comparison period, A first sampling switch is configured to be positioned between the first comparison wiring and the second reference voltage, A second sampling switch is configured to be positioned between the second comparison wiring and the second reference voltage, A first reference changing capacitance unit having a first terminal connected to the first comparison wiring, A first reference changing switch is configured to selectively supply the first analog input signal or the ground voltage to the second terminal of the first reference changing capacitance unit, A second reference changing capacitance unit having a first end connected to the second comparison wiring, A successive approximation AD conversion circuit having a second reference changing switch configured to selectively supply the second analog input signal or the ground voltage to the second terminal of the second reference changing capacitance unit.

8. The aforementioned control circuit is During the sampling period, the first sampling switch and the second sampling switch are turned on to provide the second reference voltage to the first comparison wiring and the second comparison wiring, respectively, and the first analog input signal is provided to the second terminal of the first reference changing capacitor through the control of the first reference changing switch, and the second analog input signal is provided to the second terminal of the second reference changing capacitor during the sampling period through the control of the second reference changing switch. The successive approximation AD conversion circuit according to claim 7, wherein during the successive approximation period, the first sampling switch and the second sampling switch are turned off, and the ground voltage is applied to the second terminal of the first reference changing capacitor through the control of the first reference changing switch, and the ground voltage is applied to the second terminal of the second reference changing capacitor through the control of the second reference changing switch.

9. The aforementioned digital output signal is an N-bit digital signal having bits 1 to N, The first capacitor array and the second capacitor array each have first to n capacitors corresponding to the first to nth bits, each having a first end and a second end. The successive approximation AD conversion circuit according to claim 7, wherein the first reference changing capacitance section and the second reference changing capacitance section are configured to have the same capacitance as the capacitor with the smallest capacitance.

10. The successive approximation AD conversion circuit according to claim 7, wherein both the first reference changing capacitance unit and the second reference changing capacitance unit are configured to appropriately change their capacitance, and the capacitance of the first reference changing capacitance unit and the capacitance of the second reference changing capacitance unit are the same.

11. The successive AD conversion circuit according to claim 7 or 8, wherein the control circuit is configured to increase the capacitance of the first reference changing capacitor when the amplitude of the first analog input signal decreases, and to increase the capacitance of the second reference changing capacitor when the amplitude of the second analog input signal decreases.

12. The first reference changing capacitance unit has a configuration comprising a plurality of first reference changing capacitors having different capacitances and a first selection switch configured to select one of the first reference changing capacitors, and the second reference changing capacitance unit has a configuration comprising a plurality of second reference changing capacitors having different capacitances and a second selection switch configured to select one of the first reference changing capacitors. The successive approximation AD conversion circuit according to claim 7 or claim 8, wherein the control circuit is configured to change the capacitance of the first reference changing capacitance section by switching the first selection switch, and to change the capacitance of the second reference changing capacitance section by switching the second selection switch.

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