Decimal frequency divider circuit based on digital-to-time converter

Abstract

The invention belongs to the field of integrated circuit design, particularly relates to a fractional frequency divider circuit based on a digital time converter, and aims to solve the performance bottleneck caused by quantization errors in a fractional frequency division phase-locked loop. The circuit comprises three core modules, namely a differential integral modulator, a pulse swallowing multi-modulus frequency divider and a constant-slope digital time converter, wherein the differential integral modulator generates a multi-modulus frequency divider control word and a digital time converter control word according to integer and fractional frequency control words; the pulse swallowing multimode frequency divider receives an output signal of the voltage-controlled oscillator, and outputs a signal D1 and a time sequence control signal after frequency division processing; the constant slope digital-to-time converter time-converts D1 based on a control word and a timing signal, and outputs a delayed clock signal to counteract a quantization error. The femtosecond-level time delay circuit adopts an optimized circuit architecture design, has the characteristics of simple structure and low power consumption, realizes femtosecond-level time delay precision and high linearity, effectively inhibits phase noise and stray, is adaptive to various analog fractional frequency division phase-locked loop structures, remarkably improves the frequency spectrum purity and the system suitability of a clock generator, and has a wide application prospect. And the application requirements of the high-performance fractional frequency division phase-locked loop in the fields of wireless communication, radar and the like are met.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to a fractional frequency divider circuit based on a digital time converter. Background Technology

[0002] In modern wireless communication, radar, and phased array systems, high-performance clock generators are core modules. Their phase noise, jitter characteristics, and spectral purity directly determine the system's communication quality and signal processing accuracy. Fractional-number frequency-locked loops (PLLs), as a key component of clock generators, achieve flexible frequency adjustment by implementing non-integer division ratios. Digital time converters (DTCs), as the core device for eliminating quantization errors in fractional-number frequency division, have linearity, delay accuracy, and noise suppression capabilities that are crucial to the overall performance of the PLL. Therefore, developing fractional-number frequency divider circuits that combine low jitter, low spurious emissions, and high linearity has become a key direction for improving the performance of high-end electronic systems.

[0003] To achieve high-resolution digital time conversion, existing technologies are mainly divided into two categories: variable slope and constant slope digital time converters. Variable slope schemes control delay by adjusting the clock signal slope through load capacitance, achieving resolutions of hundreds of femtoseconds. However, their linearity is limited by propagation delay and nonlinear slope relationships, requiring complex calibration processes when applied to high-performance phase-locked loops. Constant slope schemes, on the other hand, utilize a constant current source to charge a capacitor, generating a linear voltage ramp. Delay is controlled by adjusting the initial voltage, including capacitor array and delay chain structures. Their linearity is superior to variable slope schemes. However, in existing designs combining constant slope digital time converters with frequency dividers, it is often difficult to balance femtosecond-level delay accuracy with low noise and low spurious characteristics. Furthermore, the complex structure of the frequency divider leads to higher power consumption.

[0004] In practical applications of fractional-order frequency-locked loops (PLLs), since the division ratio is a time average, fractional-order frequency division needs to be approximated using an integer sequence. This leads to quantization errors between the feedback clock and the reference clock, affecting phase / frequency detection accuracy even after the loop is locked. In existing fractional-order frequency divider circuits, the collaborative working mechanism between the digital time converter and the multi-mode divider is not optimized. Either insufficient linearity leads to noise folding and spurious emissions, or the delay accuracy cannot reach the femtosecond level, making it difficult to effectively offset quantization errors. Therefore, there is an urgent need for a fractional-order frequency divider circuit that is simple in structure, has low power consumption, and can simultaneously meet the requirements of high linearity, femtosecond-level accuracy, and low spurious emissions to overcome the performance bottlenecks of existing technologies. Summary of the Invention

[0005] To address the problems existing in the background art, the present invention provides a fractional frequency divider circuit based on a digital time converter, comprising: a differential integral modulator, a pulse swallowing multimode frequency divider, and a constant slope digital time converter circuit.

[0006] The differential integral modulator is used to generate a multi-mode frequency divider control word and a digital time converter control word based on an integer frequency control word and a fractional frequency control word;

[0007] The pulse swallowing multimode frequency divider is used to receive the output signal of the voltage-controlled oscillator and the multimode frequency divider control word generated by the differential integral modulator, divide the output signal of the voltage-controlled oscillator to obtain the output signal D1 of the pulse swallowing multimode frequency divider, and output the timing control signal in conjunction with the timing control module.

[0008] The constant slope digital time converter is used to receive the digital time converter control word generated by the differential integral modulator and the timing control signal output by the timing control module, and to perform time conversion processing on the output signal D1 to obtain a delayed clock signal.

[0009] The present invention has at least the following beneficial effects

[0010] This invention organically combines a differential integral modulator, a pulse swallowing multimode divider, and a constant slope digital time converter circuit. This solves the problems of insufficient linearity and complex calibration required in existing variable slope digital time converters, while also overcoming the shortcomings of insufficient delay accuracy and significant spurious emissions when traditional constant slope schemes work in conjunction with dividers. Its frequency division architecture, combining TSPC and T flip-flops, precise control with an 8-bit digital control word, and optimized design of the I_DAC converter, not only achieves structural simplification and low power consumption but also femtosecond-level delay accuracy and high linearity. It effectively offsets quantization errors caused by fractional frequency division, suppresses phase noise and spurious emissions, and is compatible with various analog fractional frequency division phase-locked loop structures. This significantly improves the spectral purity of the clock generator and system adaptability, meeting the core requirements of modern wireless communication, radar, and other fields for high-performance fractional frequency division phase-locked loops. Attached Figure Description

[0011] Figure 1 A schematic diagram of the circuit structure of this invention;

[0012] Figure 2 A schematic diagram of the circuit structure of the pulse swallowing multimode frequency divider of the present invention;

[0013] Figure 3 This is a timing diagram of the timing control module of the present invention;

[0014] Figure 4 This is a schematic diagram of the circuit structure of the timing control module of the present invention;

[0015] Figure 5 This is a schematic diagram of the circuit structure of the I_DAC converter of the present invention;

[0016] Figure 6 This is a schematic diagram of the circuit structure of the DAC unit of the present invention;

[0017] Figure 7 This is a timing diagram of the digital time converter of the present invention;

[0018] Figure 8 This is a schematic diagram of the overall structure of the present invention applied to a dual-path fractional frequency division phase-locked loop. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] Please see Figure 1 The present invention provides a fractional frequency divider circuit based on a digital time converter, comprising: a differential integral modulator, a pulse swallowing multimode frequency divider, and a constant slope digital time converter circuit;

[0021] The differential integral modulator is used to generate the multimode divider control word DIV_CODE<9:0> and the digital time converter control word DTC_CODE<7:0> based on the integer frequency control word FCW_int and the fractional frequency control word FCW_frac.

[0022] The pulse swallowing multimode frequency divider is used to receive the output signal VCO OUT of the voltage-controlled oscillator and the multimode frequency divider control word DIV_CODE<9:0> generated by the differential integral modulator, divide the output signal VCO OUT of the voltage-controlled oscillator to obtain the output signal D1 of the pulse swallowing multimode frequency divider, and output the timing control signal in conjunction with the timing control module.

[0023] The constant slope digital time converter is used to receive the digital time converter control word DTC_CODE<7:0> generated by the differential integral modulator and the timing control signal output by the timing control module, and to perform time conversion processing on the output signal D1 to obtain the delayed clock signal DTC_OUT.

[0024] In this embodiment, an integrated architecture is constructed in which a differential integral modulator, a pulse swallowing multimode divider, and a constant slope digital time converter work together. The differential integral modulator, as the core of control signal generation, can accurately receive integer frequency control words (FCW_int) and fractional frequency control words (FCW_frac), and generate a 10-bit multimode divider control word (DIV_CODE<9:0>) and an 8-bit digital time converter control word (DTC_CODE<7:0>) through internal logic operations, providing a precise control basis for subsequent frequency division and time conversion. The pulse swallowing multimode divider is responsible for receiving the voltage-controlled oscillator output signal (VCOOUT). Under the control of the multi-mode divider control word, the high-frequency signal is divided, and the core signal D1 after division is finally output. At the same time, it works with the timing control module to generate timing control signals adapted to the operation of subsequent modules, ensuring circuit timing coordination. The constant slope digital time converter, based on the digital time converter control word output by the differential integral modulator and the timing signal of the timing control module, performs high-precision time conversion processing on the signal D1 output by the pulse swallowing multi-mode divider, and finally outputs a delayed clock signal (DTC_OUT). The three work closely together through signal interaction and functional cooperation to realize the core function of fractional frequency division, laying the foundation for subsequent compensation of quantization errors and optimization of phase-locked loop performance.

[0025] Please see Figure 8 Preferably, the delayed clock signal acts on the frequency and phase detector to offset quantization errors and optimize its phase / frequency detection accuracy.

[0026] In this embodiment, the delayed clock signal directly acts on the frequency and phase detector of the fractional-division phase-locked loop. Since the fractional division ratio needs to be approximated by an integer sequence, there will inevitably be a quantization error between the feedback clock and the reference clock. Even after the loop is locked, this error will still interfere with the accurate detection of the phase / frequency difference by the frequency and phase detector. Combining the high linearity and femtosecond-level delay accuracy of the constant-slope digital-time converter in this scheme, the delayed clock signal can accurately compensate for the timing deviation caused by the quantization error. By canceling the phase difference between the integer division sequence and the ideal fractional division, the feedback signal received by the frequency and phase detector is made closer to the timing characteristics of the ideal reference signal, thereby significantly optimizing the accuracy of its phase / frequency detection. This provides a more reliable error signal for the subsequent loop adjustment of the phase-locked loop, ultimately achieving a high-performance fractional-division phase-locked loop output with low jitter and low spurious emissions.

[0027] Please see Figure 1Preferably, the step of generating the multimode divider control word and the digital time converter control word based on the integer frequency control word FCW_int and the fractional frequency control word FCW_frac includes: the differential integral modulator quantizes the fractional frequency control word FCW_frac and outputs a quantized fractional component; the quantized fractional component is added to the integer frequency control word FCW_int through an adder to obtain the multimode divider control word DIV_CODE<9:0>; the quantized fractional component is added to the fractional frequency control word FCW_frac through an adder to obtain the digital time converter control word DTC_CODE<7:0>.

[0028] In this embodiment, the Differential Integral Modulator (DSM) quantizes the input fractional frequency control word (FCW_frac) and outputs a stable and reliable quantized fractional component. This step provides a standardized fractional signal basis for the subsequent generation of the control word. Subsequently, this quantized fractional component is added to the integer frequency control word (FCW_int) using an adder to obtain a 10-bit multimode divider control word (DIV_CODE<9:0>), ensuring that the pulse swallowing multimode divider can accurately adjust the division parameters according to the target division ratio. At the same time, the quantized fractional component is added to the original fractional frequency control word (FCW_frac) using an adder to generate an 8-bit digital time converter control word (DTC_CODE<7:0>), which precisely corresponds to the quantization error compensation requirement generated by fractional frequency division. The entire generation process achieves coordinated adaptation of integer and fractional frequency control, providing both a precise division ratio control basis for the divider and a targeted error compensation signal for the digital time converter, ensuring the synchronous operation and performance optimization of the two core modules.

[0029] Please see Figure 3 and Figure 4 Preferably, the pulse swallowing multimode frequency divider divides the voltage-controlled oscillator output signal (VCOOUT) and outputs signal D1; signal D1 is connected to the D input terminal of the D flip-flop; the clock terminal of the D flip-flop is connected to the voltage-controlled oscillator output signal (VCOOUT); the output terminal of the D flip-flop outputs the timing control signal ResetH; the timing control signal ResetH and signal D1 are logically operated through an AND gate to output the timing control signal ENN.

[0030] In this embodiment, after the pulse swallowing multimode frequency divider performs frequency division processing on the high-frequency signal (VCOOUT) output by the voltage-controlled oscillator, the output frequency division signal D1 serves as the basic signal for timing control. On the one hand, it provides the core input for subsequent time conversion, and on the other hand, it is connected to the D input terminal of the D flip-flop. The clock terminal of the D flip-flop is directly connected to the output signal (VCOOUT) of the voltage-controlled oscillator. Utilizing the timing delay characteristics of the flip-flop, the timing control signal ResetH generated at the output terminal is delayed by one VCO cycle relative to D1. This delay design ensures that the capacitor reset operation of the constant slope digital time converter is precisely matched with the frequency division rhythm. Subsequently, the timing control signal ResetH and the frequency division signal D1 are logically operated through an AND gate. Only when D1 is high (indicating that the frequency division is completed and the time conversion stage has begun) and ResetH is high (indicating that the reset operation is completed) is a high-level timing control signal ENN output, thereby achieving precise triggering of the secondary discharge stage of the constant slope digital time converter and avoiding timing conflicts. The entire timing control process constructs a stable and coordinated signal link through a simple combination of triggers and logic gates, providing reliable timing assurance for the subsequent constant slope digital time converter to achieve femtosecond-level precise time conversion.

[0031] Please see Figure 2 Preferably, the pulse swallowing multimode divider includes: two TSPC flip-flops, eight T flip-flops, transistor NM4, inverter 1 and inverter 2;

[0032] The input of the first TSPC flip-flop is connected to the multi-mode divider control word DIV_CODE. <0> The clock control terminal of the first TSPC flip-flop is connected to the output signal of the voltage-controlled oscillator; the output terminal of the first TSPC flip-flop is connected to the clock control terminal of the second TSPC flip-flop.

[0033] The input of the second TSPC flip-flop is connected to the multi-mode divider control word DIV_CODE. <1> The output of the second TSPC flip-flop is connected to the clock terminal CLK of the first T flip-flop and the gate of transistor NM4; the source of transistor NM4 is grounded.

[0034] The D inputs of the eight T flip-flops are respectively connected to the multi-mode divider control word DIV_CODE. <2> ~DIV_CODE <9> The S terminal of the eight T flip-flops is connected to the S signal; the SN terminal of the eight T flip-flops is connected to the SN signal; the eight T flip-flops... The output signal D1 of the pulse swallowing multimode divider is connected to the drain of transistor NM4 and the input of inverter 1; the output of inverter 1 is connected to the S signal and the input of inverter 2; the output of inverter 2 is connected to the SN signal.

[0035] Starting with the second T flip-flop, the clock input CLK of each T flip-flop is connected to the Q output of the previous T flip-flop.

[0036] In this embodiment, the frequency divider is composed of two TSPC flip-flops, eight T flip-flops, a transistor NM4, and two inverters. The first two stages use TSPC flip-flops to adapt to the processing requirements of high-frequency scenarios (voltage-controlled oscillator output signal VCOOUT). The first TSPC flip-flop receives the multi-mode frequency divider control word DIV_CODE. <0> Its output drives the clock control of the second TSPC flip-flop, which in turn receives the DIV_CODE. <1> The output terminal is simultaneously connected to the clock input of the first T flip-flop and the gate of transistor NM4; the eight T flip-flops form a multi-stage frequency divider link through a series architecture (starting from the second T flip-flop, the clock input is connected to the Q output of the previous T flip-flop), and their D input terminals receive DIV_CODE respectively. <2> ~DIV_CODE <9> The S and SN terminals are also controlled by the S and SN signals. The Q terminals of the eight T flip-flops are connected to the drain of transistor NM4, the output signal D1 of the frequency divider, and the input of inverter 1. The source of transistor NM4 is grounded to cooperate with the logic control to achieve signal discharge. Inverter 1 inverts the combined signal output by the T flip-flops to generate the S signal, which is simultaneously input to inverter 2. Inverter 2 further inverts the signal to generate the SN signal, forming a closed-loop set control. This ensures that the two TSPC flip-flops and the eight T flip-flops synchronously switch between the 2-division or 3-division modes under the action of the control word. Ultimately, this achieves accurate frequency division of the voltage-controlled oscillator output signal and outputs a stable signal D1, providing a reliable high-frequency division basis for subsequent timing control and time conversion.

[0037] Please see Figure 1 Preferably, the constant slope digital-to-time converter includes: transistors PM1, PM2, NM1, NM2, NM3, capacitor C0, inverter 3, inverter 4, and I_DAC converter;

[0038] The I_DAC converter receives signal D1, digital time converter control word (DTC_CODE<7:0>), and timing control signal ENN, and converts them into an output signal. ;

[0039] One end of capacitor C0 is connected to the power supply VDD; the other end of capacitor C0 is connected to the signal. The source of NM1 and the source of NM2; the gate of NM1 is connected to the bias voltage. The drain of NM1, the drain of PM1, and the gate of PM2 are connected; the gate of PM1 is connected to the timing control signal ResetH; the source of PM1, the source of PM2, and the drain of NM2 are connected to the power supply VDD; the drain of PM2, the gate of NM2, the input of inverter 3, and the drain of NM3 are connected; the output of inverter 3 outputs a delayed clock signal ((DTC_OUT)); the source of NM3 is grounded; the input of inverter 4 is connected to the timing control signal ResetH; the output of inverter 4 is connected to the gate of NM3.

[0040] In this embodiment, the entire circuit of the constant slope digital time converter is through The programmable precision current output controls the charging and discharging process of capacitor C0. Combined with the bias and switching control of transistors, a stable linear voltage ramp is formed across the capacitor. The voltage change is then converted into a timing delay signal by inverter 3, ultimately achieving high linearity and femtosecond-level precision time conversion of signal D1. This provides core hardware support for offsetting fractional frequency division quantization errors.

[0041] Please see Figure 5 Preferably, the I_DAC converter includes: a current source, a resistor R, transistors NM5~NM8, an amplifier AMP, eight DAC units, and transistors NM01~NM08;

[0042] The positive terminal of the current source is connected to the power supply VDD; the negative terminal of the current source is connected to one end of resistor R, the gate of NM5, the gate of NM7, and the non-inverting input of amplifier AMP; the other end of resistor R, the drain of NM5, the gate of NM6, the gate of NM8, and the gates of NM01~NM08 are connected; the source of NM5 and the drain of NM6 are connected; the sources of NM6, NM8, and NM01~NM08 are grounded; the drain of NM7 is connected to the reference current. The output terminal and the inverting input terminal of the amplifier AMP are connected to the VS signal terminal; the source of NM7 and the drain of NM8 are connected.

[0043] Each DAC unit outputs a sink current based on signal VS, signal D1, timing control signal ENN, and the digital time converter control word. and output current Sink current of 8 DAC units The drains of transistors NM01~NM08 are connected respectively; the current of the 8 DAC units... The output terminals are connected in parallel to output signals. .

[0044] In this embodiment, the I_DAC converter serves as a key signal conversion unit in the constant slope digital-time converter, aiming to output a precise and controllable current signal. To support the generation of a linear voltage ramp: the positive terminal of the current source is connected to the power supply VDD, and the negative terminal is simultaneously connected to one end of resistor R, the gate of NM5, the gate of NM7, and the non-inverting input of amplifier AMP, forming the basis of the reference bias; amplifier AMP forms a voltage follower by shorting its output terminal to its inverting input terminal, stabilizing the voltage at the VS signal terminal; the source of NM7 and the drain of NM8 are connected, together forming a low-voltage self-biased cascode current mirror structure, effectively suppressing the channel length modulation effect and ensuring the accuracy of current replication; the entire architecture achieves precise bias design and 8-bit weighted current control, enabling the generation of a linear voltage ramp. The high-precision, linear control of the signal provides core current support for the stable linear charging and discharging of capacitor C0 in the constant slope digital time converter, thereby ensuring the femtosecond-level delay accuracy and high linearity of the delayed clock signal (DTC_OUT), and laying a key foundation for offsetting fractional frequency division quantization errors.

[0045] Please see Figure 6 Preferably, the DAC unit includes: inverters 5 to 8, transistors NM11 to NM16, transistors PM3 and PM4;

[0046] For the nth DAC unit, where n is an integer between 1 and 8; the input of inverter 6 is connected to the digital time converter control word DTC_CODE. <n-1>The output of inverter 6 is connected to the gate of NM11; the gate of PM3, the input of inverter 5, and the gate of NM12 are connected to signal D1; the sources of PM3 and PM4, and the drain of NM14 are connected to power supply VDD; the drains of PM3, the gate of PM4, the drains of NM11 and NM16, and the input of inverter 7 are connected; the output of inverter 5 is connected to the gate of NM13; the drains of PM4 and NM13 are connected to the input of inverter 8; the source of NM11 and the drain of NM12 are connected; the sources of NM12, NM16, and NM13 are grounded; the gate of NM16 is connected to signal ENN; the output of inverter 8 is connected to the gate of NM14; the sources of NM14 and NM15 are connected to current sinks. Output terminal; the output terminal of inverter 7 is connected to the gate of NM15; the drain of NM15 is connected to the current... Output terminal; the power supply terminals of inverters 7 and 8 are connected to the VS signal terminal.

[0047] In this embodiment, the DAC unit serves as the basic functional unit of the I_DAC converter, aiming to achieve precise current selection and output based on control signals. Linear modulation of the signal is supported: the input of inverter 6 receives the digital time converter control word DTC_CODE. <n-1>(n corresponds to the unit number), the output terminal controls the gate of NM11 to realize the inversion and driving of the control word signal; the gate of PM3, the input terminal of inverter 5 and the gate of NM12 are connected to signal D1, the source of PM3, the source of PM4 and the drain of NM14 are connected to the power supply VDD, forming the basis for power supply and switching control; the drain of PM3, the gate of PM4, the drain of NM11, the drain of NM16 and the input terminal of inverter 7 are connected, the output terminal of inverter 5 controls the gate of NM13, the drain of PM4 and the drain of NM13 are connected to the input terminal of inverter 8 to form a logic control link; the source of NM11 is connected to the drain of NM12, the sources of NM12, NM16 and NM13 are all grounded, the gate of NM16 is connected to the timing control signal ENN to realize the timing synchronization of current on and off; the output terminal of inverter 8 controls the gate of NM14, and the source of NM14 and the source of NM15 together constitute the current sink. At the output terminal, the output of inverter 7 controls the gate of NM15, and the drain of NM15 serves as the output current. The output terminals of inverters 7 and 8 are connected to the VS signal terminal to ensure voltage stability. The entire unit achieves precise control through the gating of DTC_CODE and the timing coordination of D1 and ENN. and On / off and regulation, 8 units These correspond to transistors NM01~NM08 in the I_DAC converter, respectively. After connecting, it forms The signal provides a precise weighted current for the linear charging and discharging of capacitor C0 in the constant slope digital time converter, thereby ensuring the high linearity and femtosecond-level delay accuracy of the delayed clock signal.

[0048] like Figure 7 As shown, Figure 7 As a timing diagram of a digital time converter, it intuitively presents the working timing logic of the constant slope digital time converter under different combinations of control signals, clearly linking the correspondence between key signal states, capacitor charging and discharging processes, and the generation of delayed clock signals: When control signal D1 is low, the constant current source IOUT is in the off state, holding capacitor C0 charged to power supply VDD, completing the reset operation, and laying the initial voltage foundation for subsequent time conversion; when D1 becomes high and the timing control signal ResetH is low, the reset state is released, and the constant current source is controlled by the digital time converter control word DTC_CODE<7: 0> Precise control (constant current source is on when DTC_CODE is 0, and off when it is 1) performs the first programmable discharge on capacitor C0, stopping after discharging to the preset start voltage corresponding to the control word, thus achieving flexible setting of the delay start point; when D1 remains high, ResetH becomes high, and the timing control signal ENN is high, the constant current source is fully turned on, performing a second complete discharge on capacitor C0. The voltage across the capacitor decreases along a stable linear ramp. When the voltage drops to the threshold voltage of inverter 3, inverter 3 outputs the delayed clock signal DTC_OUT, completing the time conversion of the input signal D1. This timing design, through staged charging and discharging control and multi-signal coordination, intuitively demonstrates the core working mechanism of the constant slope digital time converter to achieve femtosecond-level delay accuracy and high linearity, providing stable and reliable timing support for offsetting fractional-number quantization errors.

[0049] Figure 8 As a schematic diagram of the overall structure of this invention applied to a dual-path fractional-frequency divider phase-locked loop, it clearly presents the integrated logic and signal link of the fractional-frequency divider circuit based on the digital time converter in the complete phase-locked loop system, intuitively demonstrating its practical application scenarios and core value: This schematic diagram is based on a dual-path architecture, using the three core modules of this invention—the differential integral modulator, the pulse swallowing multimode divider, and the constant slope digital time converter—as the key feedback frequency division units of the phase-locked loop. The high-frequency signal (VCO_OUT) output by the voltage-controlled oscillator is first input to the pulse swallowing multimode divider, and then... Under the control of the multi-mode frequency divider control word (DIV_CODE<9:0>) generated by the modulator, the frequency is divided and the output signal D1 is completed. Subsequently, after receiving the digital time converter control word (DTC_CODE<7:0>) and timing control signal from the constant slope digital time converter, the output delayed clock signal (DTC_OUT) is fed back to the frequency and phase detector. The frequency and phase detector compares the phase / frequency of this delayed clock signal with the external reference clock, generates an error signal to drive the charge pump and loop filter, and then adjusts the output frequency of the voltage-controlled oscillator to form a complete closed-loop control. This schematic diagram clarifies the collaborative working relationship between the circuit of this invention and other modules of the phase-locked loop. It specifically solves the quantization error problem caused by the approximate fractional frequency division of integer sequences in traditional dual-path fractional frequency division phase-locked loops. Through the precise delay compensation of the constant slope digital time converter, phase noise and spurious signals are effectively suppressed. This intuitively demonstrates the core role of the circuit of this invention in improving the spectral purity of the phase-locked loop and reducing jitter, while also showing its good adaptability to the dual-path phase-locked loop architecture.

[0050] In summary, this invention organically combines a differential integral modulator, a pulse swallowing multimode divider, and a constant slope digital time converter circuit. This solves the problems of insufficient linearity and complex calibration required by existing variable slope digital time converters, while also overcoming the shortcomings of insufficient delay accuracy and significant spurious emissions when traditional constant slope schemes and dividers work together. Its frequency division architecture, combining TSPC and T flip-flops, precise control with an 8-bit digital control word, and optimized design of the I_DAC converter, not only achieves structural simplification and low power consumption but also femtosecond-level delay accuracy and high linearity. It effectively offsets quantization errors caused by fractional frequency division, suppresses phase noise and spurious emissions, and is compatible with various analog fractional frequency division phase-locked loop structures. This significantly improves the spectral purity of the clock generator and system adaptability, meeting the core requirements of modern wireless communication, radar, and other fields for high-performance fractional frequency division phase-locked loops.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fractional frequency divider circuit based on a digital time converter, characterized in that, include: Differential integral modulator, pulse swallowing multimode frequency divider and constant slope digital time converter circuit; The differential integral modulator is used to generate a multi-mode frequency divider control word and a digital time converter control word based on an integer frequency control word and a fractional frequency control word; The pulse swallowing multimode frequency divider is used to receive the output signal of the voltage-controlled oscillator and the multimode frequency divider control word generated by the differential integral modulator, divide the output signal of the voltage-controlled oscillator to obtain the output signal D1 of the pulse swallowing multimode frequency divider, and output the timing control signal in conjunction with the timing control module. The constant slope digital time converter is used to receive the digital time converter control word generated by the differential integral modulator and the timing control signal output by the timing control module, and to perform time conversion processing on the output signal D1 to obtain a delayed clock signal.

2. The fractional frequency divider circuit based on a digital time converter according to claim 1, characterized in that, The delayed clock signal acts on the frequency and phase detector to offset quantization errors and optimize its phase / frequency detection accuracy.

3. The fractional frequency divider circuit based on a digital time converter according to claim 1, characterized in that, The process of generating a multi-mode divider control word and a digital time converter control word based on an integer frequency control word and a fractional frequency control word includes: a differential integral modulator quantizing the fractional frequency control word and outputting a quantized fractional component; adding the quantized fractional component and the integer frequency control word through an adder to obtain the multi-mode divider control word; and adding the quantized fractional component and the fractional frequency control word through an adder to obtain the digital time converter control word.

4. A fractional frequency divider circuit based on a digital time converter according to claim 1, characterized in that, The pulse swallowing multimode frequency divider divides the voltage-controlled oscillator output signal and outputs signal D1; signal D1 is connected to the D input terminal of the D flip-flop; the clock terminal of the D flip-flop is connected to the voltage-controlled oscillator output signal; the output terminal of the D flip-flop outputs timing control signal ResetH; timing control signal ResetH and signal D1 are logically operated through an AND gate to output timing control signal ENN.

5. A fractional frequency divider circuit based on a digital time converter according to claim 4, characterized in that, The pulse swallowing multimode divider includes: two TSPC flip-flops, eight T flip-flops, transistor NM4, inverter 1, and inverter 2; The input of the first TSPC flip-flop is connected to the multi-mode divider control word DIV_CODE. <0> The clock control terminal of the first TSPC flip-flop is connected to the output signal of the voltage-controlled oscillator; the output terminal of the first TSPC flip-flop is connected to the clock control terminal of the second TSPC flip-flop. The input of the second TSPC flip-flop is connected to the multi-mode divider control word DIV_CODE. <1> The output of the second TSPC flip-flop is connected to the clock input CLK of the first T flip-flop and the gate of transistor NM4; the source of transistor NM4 is grounded. The D inputs of the eight T flip-flops are respectively connected to the multi-mode divider control word DIV_CODE. <2> ~DIV_CODE <9> The S terminal of the eight T flip-flops is connected to the S signal; the SN terminal of the eight T flip-flops is connected to the SN signal; the eight T flip-flops... The output signal D1 of the pulse swallowing multimode divider is connected to the drain of transistor NM4 and the input of inverter 1; the output of inverter 1 is connected to the S signal and the input of inverter 2; the output of inverter 2 is connected to the SN signal. Starting with the second T flip-flop, the clock input CLK of each T flip-flop is connected to the Q output of the previous T flip-flop.

6. A fractional frequency divider circuit based on a digital time converter according to claim 5, characterized in that, The constant slope digital-time converter includes: transistors PM1, PM2, NM1, NM2, NM3, capacitor C0, inverter 3, inverter 4, and I_DAC converter; The I_DAC converter receives signal D1, digital time converter control word, and timing control signal ENN, and then converts them to output signal. ; One end of capacitor C0 is connected to the power supply VDD; the other end of capacitor C0 is connected to the signal. The source of NM1 and the source of NM2; the gate of NM1 is connected to the bias voltage. The drain of NM1, the drain of PM1, and the gate of PM2 are connected; the gate of PM1 is connected to the timing control signal ResetH; the source of PM1, the source of PM2, and the drain of NM2 are connected to the power supply VDD; the drain of PM2, the gate of NM2, the input of inverter 3, and the drain of NM3 are connected; the output of inverter 3 outputs a delayed clock signal; the source of NM3 is grounded; the input of inverter 4 is connected to the timing control signal ResetH; the output of inverter 4 is connected to the gate of NM3.

7. A fractional frequency divider circuit based on a digital time converter according to claim 6, characterized in that, The I_DAC converter includes: a current source, a resistor R, transistors NM5~NM8, an amplifier AMP, 8 DAC units, and transistors NM01~NM08; The positive terminal of the current source is connected to the power supply VDD; the negative terminal of the current source is connected to one end of resistor R, the gate of NM5, the gate of NM7, and the non-inverting input of amplifier AMP; the other end of resistor R, the drain of NM5, the gate of NM6, the gate of NM8, and the gates of NM01~NM08 are connected; the source of NM5 and the drain of NM6 are connected; the sources of NM6, NM8, and NM01~NM08 are grounded; the drain of NM7 is connected to the reference current. The output terminal and the inverting input terminal of the amplifier AMP are connected to the VS signal terminal; the source of NM7 and the drain of NM8 are connected. Each DAC unit outputs a sink current based on signal VS, signal D1, timing control signal ENN, and the digital time converter control word. and output current Sink current of 8 DAC units The drains of transistors NM01~NM08 are connected respectively; the current of the 8 DAC units... The output terminals are connected in parallel to output signals. .

8. A fractional frequency divider circuit based on a digital time converter according to claim 7, characterized in that, The DAC unit includes: inverters 5 to 8, transistors NM11 to NM16, transistors PM3 and PM4; For the nth DAC unit, where n is an integer between 1 and 8; the input of inverter 6 is connected to the digital time converter control word DTC_CODE. <n-1>The output of inverter 6 is connected to the gate of NM11; the gate of PM3, the input of inverter 5, and the gate of NM12 are connected to signal D1; the sources of PM3 and PM4, and the drain of NM14 are connected to power supply VDD; the drains of PM3, the gate of PM4, the drains of NM11 and NM16, and the input of inverter 7 are connected; the output of inverter 5 is connected to the gate of NM13; the drains of PM4 and NM13 are connected to the input of inverter 8; the source of NM11 and the drain of NM12 are connected; the sources of NM12, NM16, and NM13 are grounded; the gate of NM16 is connected to signal ENN; the output of inverter 8 is connected to the gate of NM14; the sources of NM14 and NM15 are connected to current sinks. Output terminal; the output terminal of inverter 7 is connected to the gate of NM15; the drain of NM15 is connected to the current... Output terminal; the power supply terminals of inverters 7 and 8 are connected to the VS signal terminal.

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