solar cells

Abstract

The present invention provides a solar cell.SOLUTION: A solar cell, comprising a semiconductor substrate, a first passivation layer on the front surface of the semiconductor substrate, and a second passivation layer on the back surface of the semiconductor substrate, wherein the semiconductor substrate comprises a front surface and a back surface opposite to each other, and the back surface of the semiconductor substrate is provided with a P-type conductive region and an N-type conductive region arranged alternately, a gap region is provided between the P-type conductive region and the N-type conductive region, and a first notch region recessed along a first direction is provided between the P-type conductive region and the gap region; A first texture structure is disposed in the first notch region, the first direction is parallel to a direction from the spacing region to the P-type conductive region, a second texture structure is disposed in the spacing region, a shape of the second texture structure is different from a shape of the first texture structure, and the second passivation layer covers the P-type conductive region, the first notch region, the spacing region and the N-type conductive region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to the field of photovoltaic power generation production technology, and more particularly to a solar cell and a manufacturing method thereof, and a photovoltaic power generation module. [Background technology]

[0002] A solar cell power generation system is a clean power generation system that generates electricity using sunlight, which is uniformly received anywhere in the world, and can achieve high power generation efficiency without using large, complex devices as a power source. Furthermore, solar cell power generation systems are expected to be able to meet the increasing demand for electricity in the future without causing environmental damage, so solar cell power generation systems have attracted public attention, and the core component of a solar cell power generation system is the solar cell.

[0003] IBC (Interdigital Back Contact) cells are a back-contact solar cell technology in which phosphorus and boron are diffused on the backside of a silicon wafer to form interdigitally arranged p+ and n+ regions, with positive and negative metal electrodes also arranged in an interdigitated pattern on the backside of the cell. By adopting a full backside contact design, IBC cells can achieve optimal passivation on the front side of the cell and an optimized light trapping structure on the front side, enhancing the cell's optical absorption and achieving high photoelectric conversion efficiency. However, the light absorption efficiency of conventional IBC cells is limited, making it difficult to improve the cell's conversion efficiency. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a solar cell, a manufacturing method thereof, and a photovoltaic module that can improve the absorption of sunlight on the back surface and provide the cell with a good passivation effect, thereby improving the cell's conversion efficiency. [Means for solving the problem]

[0005] In a first aspect, an embodiment of the present invention provides a solar cell, the solar cell including a semiconductor substrate, a first passivation layer, a second passivation layer, a first electrode, and a second electrode; the semiconductor substrate includes opposed front and rear surfaces; The rear surface of the semiconductor substrate is provided with P-type conductive regions and N-type conductive regions arranged alternately, a partition region is provided between the P-type conductive region and the N-type conductive region, a first cutout region recessed along a first direction is provided between the P-type conductive region and the partition region, a first texture structure is provided within the first cutout region, the first direction is parallel to a direction from the partition region toward the P-type conductive region, and a second texture structure is provided within the partition region, a shape of the second texture structure is different from a shape of the first texture structure, the first passivation layer is located on a front side of the semiconductor substrate; the second passivation layer is located on a rear surface of the semiconductor substrate and covers the P-type conductive region, the first cutout region, the partition region, and the N-type conductive region; the first electrode extends through the second passivation layer to form an ohmic contact with the P-type conductivity region; The second electrode extends through the second passivation layer to form an ohmic contact with the N-type conductivity region.

[0006] In a second aspect, an embodiment of the present invention provides a method for manufacturing a solar cell, the method comprising: providing a semiconductor substrate including opposed front and rear surfaces; forming a P-type conductive region, a partition region, and an N-type conductive region on the rear surface of the semiconductor substrate, the partition region being located between the P-type conductive region and the N-type conductive region, and having a first cutout region recessed along a first direction between the P-type conductive region and the partition region, a first texture structure being provided in the first cutout region, the first direction being parallel to a direction from the partition region toward the P-type conductive region, and a second texture structure being provided in the partition region, the shape of the second texture structure being different from the shape of the first texture structure; forming a first passivation layer on the front side of the semiconductor substrate; forming a second passivation layer on the rear surface of the semiconductor substrate, the second passivation layer covering the P-type conductive region, the first recessed region, the partition region, and the N-type conductive region; and forming a first electrode and a second electrode on the surface of the second passivation layer.

[0007] In a third aspect, an embodiment of the present invention provides a photovoltaic module, the photovoltaic module comprising a cover plate, a packaging material layer, and at least one group of solar cells, the group of solar cells comprising a plurality of solar cells according to the first aspect or fabricated by the method according to the second aspect. [Effects of the Invention]

[0008] The technical solution provided by the present invention can achieve the following beneficial effects:

[0009] The solar cell of the present invention can form a first cutout region recessed along a first direction in a region between the P-type conductive region and the partition region on the rear surface of the semiconductor substrate. The first cutout region recessed along the first direction can increase the effective light absorption area of ​​the solar cell and further improve the light utilization efficiency of the solar cell, thereby solving the problem of the region between the P-type conductive region and the partition region on the rear surface of conventional solar cells being "step-like" or "sloped," which fails to provide gain to the solar cell. The first texture structure in the first cutout region and the second texture structure in the partition region have different shapes. The first texture structure has excellent light trapping properties and can increase the surface area of ​​the rear surface of the semiconductor substrate, thereby increasing solar light absorption on the rear surface and reducing solar light reflection on the rear surface. In addition, long-wavelength light transmitted through the semiconductor substrate from the front surface of the cell is also absorbed by the first texture structure, further improving the overall light absorption efficiency of the cell and improving the photoelectric conversion efficiency of the solar cell without affecting the passivation effect of the region between the P-type conductive region and the partition region.

[0010] It is to be understood that the foregoing general description and the following detailed description are merely exemplary and are not restrictive of the present invention.

[0011] The drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present invention and, together with the description, serve to explain the principles of the invention. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a structural schematic diagram of a p+ doped layer, a gap region, and an n+ doped layer in Related Art 1. FIG. [Figure 2] 1 is a structural schematic diagram of a p+ doped layer, a gap region, and an n+ doped layer in Related Art 2. FIG. [Figure 3] 1 is a structural schematic diagram of a solar cell provided by an embodiment of the present invention; [Figure 4]1 is an electron microscope photograph of a structure between two adjacent P-type and N-type conductive regions provided by an embodiment of the present invention. [Figure 5] 1 is an electron microscope photograph showing a first texture structure provided in a first cutout region provided according to an embodiment of the present invention. [Figure 6] 2 is a partial structural schematic diagram of a P-type conductive region, a first notch region, a partition region, and an N-type conductive region on the back surface of a semiconductor substrate provided by an embodiment of the present invention; [Figure 7] 3 is a schematic diagram illustrating measurement of a projection length of a first sidewall on a semiconductor substrate provided by an embodiment of the present invention and a projection length of a second sidewall on a plane on which the semiconductor substrate is located; FIG. [Figure 8] 1 is a manufacturing flowchart of a solar cell provided by an embodiment of the present invention. [Figure 9] 1 is a structural schematic diagram of a semiconductor substrate provided by an embodiment of the present invention; [Figure 10] 2 is a structural schematic diagram of a semiconductor substrate provided according to an embodiment of the present invention after a first diffusion process is performed on the rear surface thereof; [Figure 11] 3 is a schematic diagram of a structure obtained by performing a first local laser treatment and a first etching treatment on a first pre-treatment region provided by an embodiment of the present invention; FIG. [Figure 12] 2 is a schematic diagram of a structure obtained by performing a second diffusion process on the rear surface of a semiconductor substrate provided according to an embodiment of the present invention; FIG. [Figure 13] FIG. 2 is a structural schematic diagram of the semiconductor device according to an embodiment of the present invention after the second local laser treatment is performed; [Figure 14] FIG. 2 is a structural schematic diagram of the semiconductor device provided by an embodiment of the present invention after a second etching process is performed. [Figure 15] 1 is a structural schematic diagram of a semiconductor substrate provided according to an embodiment of the present invention, in which a first passivation layer is formed on the front surface of the semiconductor substrate and a second passivation layer is formed on the rear surface of the semiconductor substrate. [Figure 16] 1 is a structural schematic diagram of a photovoltaic module provided by an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0013] In order to clarify the objectives, technical solutions and advantages of the present invention, the present invention will be described in more detail below with reference to the drawings and examples. It should be understood that the specific examples described herein are merely for the purpose of illustrating the present invention, and are not intended to limit the present invention.

[0014] In describing the present invention, unless expressly specified and limited otherwise, the term "first 1 " and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance; unless otherwise specified and explained, the term "plurality" refers to two or more than two; and the terms "connected," "fixed," etc. should all be understood broadly; for example, "connected" may mean fixed connection, detachable connection, integral connection, or electrical connection, and may also be direct connection or indirect connection via an intermediate connecting member. Those skilled in the art can understand the specific meanings of the above terms in the present invention according to specific circumstances.

[0015] In the description of this specification, it should be understood that terms of orientation such as "top" and "bottom" described in the embodiments of the present invention are described in the perspective of the drawings and should not be understood as limitations on the embodiments of the present invention. Furthermore, when referring to an element being connected "top" or "bottom" of another element, depending on the context, it should be understood that the element may not only be directly connected "top" or "bottom" of the other element, but may also be indirectly connected "top" or "bottom" of the other element via an intermediate element.

[0016] In the related art, the backside process in the manufacturing process of an IBC battery involves forming p+ and n+ regions arranged in an interdigitated pattern by phosphorus diffusion and boron diffusion. Specifically, boron diffusion is first performed on the backside of a silicon substrate to form an n+ doped layer, then a local laser is used to remove part of the n+ doped layer, and phosphorus diffusion is performed in the area where the n+ doped layer was removed to form a p+ doped layer. Then, etching and pickling are performed to form a pyramidal gap region (gap region) between the n+ and p+ doped layers. In conventional batteries, the region between the p+ and gap regions on the backside of the battery often fails to provide efficiency or gain. Figure 1 shows a structural diagram of the p+ doped layer 10, gap region 30, and n+ doped layer 20 in related art 1, with a "step-like" structure between the p+ doped layer 10 and gap region 30. FIG. 2 shows a schematic diagram of the structure of the p+ doped layer 10, the gap region 30, and the n+ doped layer 20 in Related Art 2. The area between the p+ doped layer 10 and the gap region 30 exhibits a "slope-like" shape. The above-mentioned shape between the p+ doped layer 10 and the gap region 30 does not allow for efficient utilization of sunlight, resulting in low photoelectric conversion efficiency of the solar cell.

[0017] In view of this, an embodiment of the present invention provides a solar cell 100. FIG. 3 is a structural schematic diagram of the solar cell 100 of the present invention, which includes a semiconductor substrate 1, a first passivation layer 6, a second passivation layer 7, a first electrode 8, and a second electrode 9. The semiconductor substrate 1 includes a front surface and a rear surface that are disposed opposite to each other, The rear surface of the semiconductor substrate 1 is provided with P-type conductive regions 2 and N-type conductive regions 4 arranged alternately, with a partition region 3 between the P-type conductive region 2 and the N-type conductive region 4, and a first cutout region 5 recessed along a first direction between the P-type conductive region 2 and the partition region 3, with a first texture structure 501 provided within the first cutout region 5, the first direction being parallel to the direction from the partition region 3 toward the P-type conductive region 2, and a second texture structure 31 provided within the partition region 3, with the shape of the second texture structure 31 being different from the shape of the first texture structure 501, a first passivation layer 6 located on the front side of the semiconductor substrate 1; The second passivation layer 7 is located on the rear surface of the semiconductor substrate 1, and covers the P-type conductive region 2, the first cutout region 5, the partition region 3, and the N-type conductive region 4; The first electrode 8 penetrates the second passivation layer 7 and forms an ohmic contact (i.e., electrical contact) with the P-type conductive region 2, The second electrode 9 penetrates the second passivation layer 7 to form an ohmic contact (ie, electrical contact) with the N-type conductive region 4 .

[0018] In the above technical solution, the solar cell of the present invention can form a first cutout region 5 recessed along a first direction in a region between the P-type conductive region 2 and the partition region 3 on the rear surface of the semiconductor substrate 1. The first cutout region 5 recessed along the first direction can increase the effective light absorption area of ​​the solar cell and further improve the light utilization efficiency of the solar cell, thereby solving the problem of the region between the P-type conductive region 2 and the partition region 3 on the rear surface of conventional solar cells being "step-like" or "sloped," which fails to provide gain to the solar cell. The first texture structure 501 in the first cutout region 5 and the second texture structure 31 in the partition region 3 have different shapes. FIG. 4 shows an electron microscope image of the structure between the two P-type conductive regions 2 and the N-type conductive region 4, and FIG. 5 shows an electron microscope image of the first texture structure 501 provided in the first cutout region 5. Referring to FIGS. 4 and 5, the first texture structure 501 has excellent light trapping properties and can increase the surface area of ​​the rear surface of the semiconductor substrate 1, thereby increasing solar light absorption at the rear surface and reducing solar light reflection at the rear surface. In addition, long-wavelength light that passes through the semiconductor substrate 1 from the front of the cell is also absorbed by the first texture structure 501, further improving the overall light absorption efficiency of the cell and improving the photoelectric conversion efficiency of the solar cell without affecting the passivation effect of the region between the P-type conductive region 2 and the partition region 3.

[0019] In addition, the semiconductor substrate 1 generally has a front surface and a rear surface, and the front surface of the semiconductor substrate 1 may refer to the light-receiving surface, i.e., the surface that is irradiated with sunlight, and the rear surface of the semiconductor substrate 1 refers to the surface opposite to the front surface.

[0020] In some embodiments of the present invention, the term "texture structure" refers to a micro-nano-sized structure that can scatter or reflect light rays to enhance light absorption.

[0021] In some embodiments, the second texture structure 31 in the partition region 3 is typically pyramidal, i.e., the first texture structure 501 of the present invention is non-pyramidal, and the shape of the first texture structure 501 includes at least one of a prism, a pyramid, and a brush. In the prior art, pyramidal structures are typically formed by texturing, and the pyramidal structure has a single shape with a large base and a pointed apex. The pyramidal structure is located on the rear surface of the semiconductor substrate 1, which generally causes a reflective effect on backside light and is detrimental to the deposition of subsequent film layers. Compared to pyramidal texture structures, the first texture structure 501 of the present invention has a larger surface area and can utilize more sunlight.

[0022] In some embodiments of the present invention, the P-type conductivity region 2 refers to a region formed of a highly doped P-type semiconductor material, and the N-type conductivity region 4 refers to a region formed of a highly doped N-type semiconductor material. The P-type conductivity region 2 and the N-type conductivity region 4 are interdigitated on the rear surface of the semiconductor substrate 1 and have the primary function of separating and collecting carriers. Here, the P-type conductivity region 2 is for collecting holes, and the N-type conductivity region 4 is for collecting electrons. Since the collected carriers are transferred to the rear electrode of the semiconductor substrate 1, respectively, to form a path to an external load, the P-type conductivity region 2 and the N-type conductivity region 4 must not be in direct contact with each other. Otherwise, the collected carriers will come into direct contact with the rear surface of the semiconductor substrate 1, forming a short circuit and preventing effective carrier collection. Therefore, a "groove-shaped" partition region 3 is usually formed between the P-type conductive region 2 and the N-type conductive region 4. There is a certain height difference between the partition region 3 and the P-type conductive region 2, which forms a notch region between the partition region 3 and the P-type conductive region 2. There is also a certain height difference between the partition region 3 and the N-type conductive region 4, which forms a notch region between the partition region 3 and the N-type conductive region 4. In the solar cell of the present invention, the shapes and structures of the notch regions at the two different positions are different. Specifically, there is a first notch region 5 between the P-type conductive region 2 and the partition region 3, which is recessed in the direction from the partition region 3 to the P-type conductive region 2, and there is a first textured structure 501 within the first notch region 5, which improves the light absorption ability of the solar cell and further improves the photoelectric conversion efficiency. A third cutout region (not shown in the drawings) is provided between the N-type conductive region 4 and the partition region 3, and the third cutout region typically has a "step-like" or "slope-like" shape. The third cutout region also has a textured structure, and the textured structure also has a "step-like" or "slope-like" shape.

[0023] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer) or may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and embodiments of the present invention are not limited to the specific type of semiconductor substrate 1. If the semiconductor substrate 1 is N-type based, the doping element may be a Group V element such as phosphorus (P), arsenic (As), or tellurium (Te). The N-type semiconductor substrate 1 and the P-type conductive region 2 form a PN junction, and the N-type semiconductor substrate 1 and the N-type conductive region 4 form an N-N+ high-low junction. If the semiconductor substrate 1 is P-type based, the doping element may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type semiconductor substrate 1 and the N-type conductive region 4 form a PN junction, and the P-type semiconductor substrate 1 and the P-type conductive region 2 form a P-P+ high-low junction.

[0024] In some embodiments, FIG. 6 is a partial structural schematic diagram of a P-type conductive region, a first cutout region, a partition region, and an N-type conductive region on the back surface of a semiconductor substrate. Referring to FIGS. 4 and 6, the first cutout region 5 has a first sidewall 51 and a second sidewall 52, the first sidewall 51 is farther from the semiconductor substrate 1 than the second sidewall 52, and an included angle θ is formed between the first sidewall 51 and the second sidewall 52, and the included angle θ is not a right angle. In some examples, the included angle θ is an acute angle. In some examples, the included angle θ may be an obtuse angle.

[0025] The first cutout region 5 of the present invention is composed of a first sidewall 51 and a second sidewall 52, the first sidewall 51 being adjacent to the P-type conductive region 2 and the second sidewall 52 being adjacent to the partition region 3. The angle θ between the first sidewall 51 and the second sidewall 52 may be an acute angle, which means that the first sidewall 51 and the second sidewall 52 both have appropriate lengths and therefore have large surface areas, which is advantageous for improving the light absorption efficiency of the first cutout region 5. The angle θ between the first sidewall 51 and the second sidewall 52 is measured using a scanning electron microscope (SEM) and / or a transmission electron microscope (TEM). The angle θ between the first sidewall 51 and the second sidewall 52 refers to the angle between the interface between the first sidewall 51 and the P-type conductive region 2 and the interface between the second sidewall 52 and the P-type conductive region.

[0026] In some examples, the included angle θ is between 30° and 75°, and may be specifically 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, or 75°. In other examples, the included angle θ is between 92° and 160°, and may be specifically 92°, 105°, 110°, 118°, 130°, 135°, 145°, 155°, or 160°. By setting the included angle θ within the above range, the first cutout region 5 simultaneously has long first and second side walls 51 and 52, and the first cutout region 5 has an excellent light trapping effect. Moreover, sunlight irradiated to the first side wall 51 can be reflected multiple times between the first and second side walls 51 and 52, and sunlight irradiated to the second side wall 52 can also be reflected multiple times between the first and second side walls 51 and 52, thereby further improving the light utilization efficiency of the sunlight by the first cutout region 5. It should be understood that the above ranges of the included angle θ are merely examples, and other ranges of the included angle may be used according to needs.

[0027] In some embodiments, the length of the first sidewall 51 is L1 and the length of the second sidewall 52 is L2, where L1:L2 = 1:(1 to 5), and L1:L2 may be specifically 1:1, 1:2, 1:3, 1:4, or 1:5. By setting the sidewall lengths as described above, the lengths of the first sidewall 51 and the second sidewall 52 have an appropriate ratio, allowing for more sunlight to be utilized. Furthermore, the sunlight can be reflected multiple times between the first sidewall 51 and the second sidewall 52 on the rear surface of the semiconductor substrate 1, significantly improving the effective utilization of sunlight. In some embodiments of the present invention, the length of the first sidewall 51 may be equal to the length of the second sidewall 52, or the length of the first sidewall 51 may be shorter than the length of the second sidewall 52. This is understandable. It should be understood that the above ratio of L1 to L2 is merely an example, and other ratios may be used according to needs.

[0028] 4 to 6, in some embodiments of the present invention, the length of the first sidewall 51 refers to the distance from the boundary between the second sidewall 52 and the first sidewall 51 to the boundary between the first sidewall 51 and the second passivation layer 7, and the length of the second sidewall 52 refers to the distance from the boundary between the second sidewall 52 and the semiconductor substrate 1 to the boundary between the first sidewall 51 and the second sidewall 52. The lengths of the first sidewall 51 and the second sidewall 52 are obtained by direct measurement using a measuring device (such as a scanning electron microscope or a transmission electron microscope).

[0029] 6 , in some embodiments, the first texture structure 501 includes a plurality of first sub-texture structures a5011 provided on the first sidewall 51 and a plurality of first sub-texture structures b5012 provided on the second sidewall 52, where the first sub-texture structures a5011 protrude from the surface on which the first sidewall 51 is located, and the first sub-texture structures b5012 protrude from the surface on which the second sidewall 52 is located. In some embodiments of the present invention, the surface on which the first sidewall 51 is located refers to the plane on which the interface between the first sidewall 51 and the P-type conductive region 2 is located, and the surface on which the second sidewall 52 is located refers to the plane on which the interface between the second sidewall 52 and the P-type conductive region 2 is located. When sunlight is irradiated onto the back surface of the battery, the protruding first sub-texture structure a5011 and first sub-texture structure b5012 can not only absorb the sunlight, but the sunlight irradiated onto first sub-texture structure a5011 is reflected off the surface of first sub-texture structure a5011 and then reflected onto first sub-texture structure b5012. The sunlight irradiated onto first sub-texture structure b5012 is reflected off the surface of first sub-texture structure b5012 and then reflected onto first sub-texture structure a5011, thereby improving the effective utilization of sunlight.

[0030] In some embodiments, the size of first sub-texture structure a5011 is equal to or smaller than the size of first sub-texture structure b5012. The above "dimension" may refer to length, width, height, projected area, volume, etc. First sub-texture structure a5011 and first sub-texture structure b5012 can be realized by setting them using at least one of the above length, width, height, projected area, and volume. The following description will use the representative length of the dimension as an example.

[0031] The length of first sub-texture structure a5011 is less than the length of first sub-texture structure b5012, and the second side wall 52 has a better light absorption effect on sunlight than the first side wall 51, which is advantageous for improving the photoelectric conversion efficiency of the solar cell. Preferably, the length of first sub-texture structure a5011 is shorter than the length of first sub-texture structure b5012. By designing first texture structures 501 of different sizes according to different regions within the first cutout region 5, the present invention can more intentionally improve the light absorption effect of the corresponding regions and achieve higher conversion efficiency in the manufactured solar cell.

[0032] In some embodiments, the height of the first sub-texture structure a5011 is 1 μm to 3 μm, and may be, for example, 1 μm, 1.5 μm, 2 μm, 2.3 μm, 2.8 μm, or 3 μm. Setting the height of the first sub-texture structure a5011 within the above range ensures that the height of the first sub-texture structure a5011 is appropriate, which is beneficial to improving the integrity and uniformity of the film layer on the surface of the first sidewall 51, reducing internal reflection of light, and increasing the carrier surface recombination rate, thereby further improving the photoelectric conversion efficiency and cell quality of the solar cell. The first sub-texture structure a5011 protrudes from the first sidewall 51, and the height of the first sub-texture structure a5011 refers to the distance between the top of the first sub-texture structure a5011 and the surface on which the first sidewall 51 is located. This is understandable.

[0033] In some embodiments, the height of the first sub-texture structure b5012 is 1 μm to 3 μm, and may be, for example, 1 μm, 1.5 μm, 2 μm, 2.3 μm, 2.8 μm, or 3 μm. Setting the height of the first sub-texture structure a5012 within the above range ensures that the first sub-texture structure b5012 has an appropriate height, which is beneficial for improving the integrity and uniformity of the film layer on the surface of the second sidewall 52, reducing internal reflection of light, improving the carrier surface recombination rate, and further improving the photoelectric conversion efficiency of the solar cell. The first sub-texture structure b5012 protrudes from the second sidewall 52, and the height of the first sub-texture structure b5012 refers to the distance between the top of the first sub-texture structure b5012 and the surface on which the first sidewall 51 is located. This is understandable.

[0034] In some embodiments, the ratio of the total surface area of ​​the first sub-texture structures a5011 in the first side wall 51 to the area of ​​the surface on which the first side wall 51 is located is (1.2 to 2):1, and specifically may be 1.2:1, 1.4:1, 1.6:1, 1.8:1, or 2:1. By setting the total surface area of ​​the first sub-texture structures a5011 within the above range, the first side wall 51 can have a large number of first sub-texture structures a5011, thereby improving the efficiency of sunlight absorption by the first side wall 51. It should be understood that the above surface area ratios are merely examples, and other ratios may be used according to needs.

[0035] In some embodiments, the ratio of the total surface area of ​​the first sub-texture structures b5012 in the second side wall 52 to the area of ​​the surface on which the second side wall 52 is located is (1.3 to 2):1, and specifically may be 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, or 2:1. It can be seen that by setting the total surface area of ​​the first sub-texture structures a5012 within the above range, the second side wall 52 has a large number of first sub-texture structures b5012, thereby improving the solar light absorption efficiency of the second side wall 52. It should be understood that the above surface area ratios are merely examples, and other ratios may be used according to needs.

[0036] In some embodiments, still referring to FIG. 5, the first sub-texture structure a5011 has a plurality of first undulating portions on the first side wall 51, the first undulating portions including first undulating peaks 511 and first undulating valleys 512, and the first sub-texture structure b5012 has a plurality of second undulating portions on the second side wall 52, the second undulating portions including second undulating peaks 521 and second undulating valleys 522, and at least a portion of the first sub-texture structure a5011 is located within the second undulating valleys 522, and at least a portion of the first sub-texture structure b5012 is located within the first undulating valleys 512. When installed in this manner, at least some of the first sub-texture structures a5011 and first sub-texture structures b5012 are positioned offset from each other in the first cutout region 5, and when sunlight is irradiated onto the first sub-texture structure a5011, the first sub-texture structure a5011 can absorb the sunlight and multiple reflections can occur between the first sub-texture structure a5011 and the first sub-texture structure b5012.Furthermore, when sunlight is irradiated onto the first sub-texture structure b5012, the first sub-texture structure b5012 can absorb the sunlight and multiple reflections can occur between the first sub-texture structure a5011 and the first sub-texture structure b5012, further improving the utilization rate of sunlight on the back surface of the battery.

[0037] In some embodiments, the length D1 of the projection of the first sidewall 51 onto the plane on which the semiconductor substrate 1 lies is between 1 μm and 4 μm, and may specifically be 1 μm, 2 μm, 3 μm, or 4 μm.

[0038] In some embodiments, the length D2 of the projection of the second sidewall 52 on the plane on which the semiconductor substrate 1 lies is 4 μm to 6 μm, and specifically may be 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm.

[0039] 7 is a schematic diagram showing the measurement of the projection length of the first side wall on the semiconductor substrate and the projection length of the second side wall on the plane on which the semiconductor substrate is located, and the projection length D1 of the first side wall 51 on the plane on which the semiconductor substrate 1 is located refers to the length of the orthogonal projection of the first side wall 51 on the semiconductor substrate 1 along the longitudinal direction of the semiconductor substrate 1. The projection length D2 of the second side wall 52 on the plane on which the semiconductor substrate 1 is located refers to the length of the orthogonal projection of the second side wall 52 on the semiconductor substrate 1 along the longitudinal direction of the semiconductor substrate 1.

[0040] In some embodiments, the distribution rate of the first cutout regions 5 on the rear surface of the semiconductor substrate 1 may be 0.5% to 1.5%, and specifically may be 0.5%, 0.8%, 1%, 1.2% or 1.5%.

[0041] By limiting the projection length of the first sidewall 51 and the second sidewall 52 of the first cutout region 5 on the plane on which the semiconductor substrate 1 is located and the distribution ratio of the first cutout region 5 on the rear surface of the semiconductor substrate 1, a PN junction with excellent conductivity can be formed in the semiconductor substrate 1 during the process of manufacturing the solar cell, thereby improving the photoelectric performance of the manufactured solar cell. This is understandable.

[0042] In some embodiments, still referring to FIG. 6 , the second passivation layer 7 has a second cutout region 701 recessed along the first direction, where the second cutout region 701 corresponds to the position of the first cutout region 5. The second passivation layer 7 is provided on the rear surface of the semiconductor substrate 1 and also on the surfaces of the P-type conductive region 2 and the partition region 3. Thus, the second passivation layer 7 also has a second cutout region 701 formed in a region corresponding to the first cutout region 5. The second cutout region 701 has a third sidewall 71 and a fourth sidewall 72, where the third sidewall 71 is farther from the semiconductor substrate 1 than the fourth sidewall 72. In some examples, the included angle between the third sidewall 71 and the fourth sidewall 72 may be an acute angle. This is understandable, as it allows for good passivation to be formed in the second cutout region 701. In other examples, the included angle may be an obtuse angle.

[0043] Hereinafter, the manufacturing method of the solar cell 100 of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention, and the described embodiments are only some of the embodiments of the present invention, and are not all of the embodiments.

[0044] FIG. 8 shows a manufacturing flow chart of a solar cell provided by an embodiment of the present invention. As shown in FIG. 8, the manufacturing method of a solar cell includes the following steps: providing a semiconductor substrate 1 including opposed front and rear surfaces; a P-type conductive region 2, a partition region 3, and an N-type conductive region 4 are formed on a rear surface of a semiconductor substrate 1, the partition region 3 is located between the P-type conductive region 2 and the N-type conductive region 4, a first cutout region 5 recessed along a first direction is formed between the P-type conductive region 2 and the partition region 3, a first texture structure 501 is formed in the first cutout region 5, the first direction is parallel to the direction from the partition region 3 toward the P-type conductive region 2, a second texture structure 31 is formed in the partition region 3, and the shape of the second texture structure 31 is different from the shape of the first texture structure 501; forming a first passivation layer 6 on the front side of the semiconductor substrate 1; forming a second passivation layer 7 on the rear surface of the semiconductor substrate 1, the second passivation layer 7 covering the P-type conductive region 2, the first cutout region 5, the partition region 3 and the N-type conductive region 4; forming a first electrode 8 on the surface of the second passivation layer 7; forming a second electrode 9 on the surface of the second passivation layer 7.

[0045] In the above technical solution, the embodiment of the present invention forms a first cutout region 5 recessed along a first direction in the region between the P-type conductive region 2 and the partition region 3 on the rear surface of the semiconductor substrate 1. The first cutout region 5 recessed along the first direction can improve the effective light absorption area of ​​the solar cell, solving the problem that the region between the P-type conductive region 2 and the partition region 3 on the rear surface of a conventional solar cell has a "step-like" or "slope-like" shape, which fails to provide gain to the solar cell. The first texture structure 501 in the first cutout region 5 and the second texture structure 31 in the partition region 3 have different shapes, and the second texture structure 31 is usually pyramidal. That is, the first texture structure 501 of the present invention has a non-pyramidal shape. The first texture structure 501 in the first cutout region 5 has a light trapping effect and can increase the surface area of ​​the rear surface of the semiconductor substrate 1, thereby increasing the solar light absorption on the rear surface and reducing solar reflection on the rear surface. In addition, long-wavelength light that passes through the semiconductor substrate 1 from the front of the cell is also absorbed by the first texture structure 501, further improving the overall light absorption efficiency of the cell and improving the photoelectric conversion efficiency of the solar cell without affecting the passivation effect of the region between the P-type conductive region 2 and the partition region 3.

[0046] Step 100: Provide a semiconductor substrate 1, which includes a front surface and a rear surface facing each other. The structure of the semiconductor substrate 1 is as shown in FIG.

[0047] In some embodiments, the front surface of the semiconductor substrate 1 corresponds to the front surface of the cell, which is the surface facing the sun (i.e., the light-receiving surface), and the rear surface of the semiconductor substrate 1 corresponds to the back surface of the cell, which is the surface facing away from the sun (i.e., the light-non-receiving surface).

[0048] In some embodiments, the semiconductor substrate 1 is an N-type crystalline silicon substrate (or silicon wafer), and may be a P-type crystalline silicon substrate (silicon wafer). The crystalline silicon substrate (silicon substrate) may be, for example, a polycrystalline silicon substrate, a single-crystal silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and the embodiments of the present invention are not limited to a specific type of the semiconductor substrate 1.

[0049] In some embodiments, the thickness of the semiconductor substrate 11 is 60 μm to 240 μm, and specifically may be 60 μm, 80 μm, 90 μm, 100 μm, 120 μm, 150 μm, 200 μm, or 240 μm, etc., but is not limited thereto.

[0050] Step S200: A P-type conductive region 2, a partition region 3, and an N-type conductive region 4 are formed on the rear surface of the semiconductor substrate 1, the partition region 3 is located between the P-type conductive region 2 and the N-type conductive region 4, a first notch region 5 is formed between the P-type conductive region 2 and the partition region 3 and is recessed along a first direction, a first texture structure 501 is formed in the first notch region 5, the first direction is parallel to the direction from the partition region 3 to the P-type conductive region 2, and a second texture structure 31 is formed in the partition region 3, and the shape of the second texture structure 31 is different from the shape of the first texture structure 501.

[0051] S201: A first diffusion process is performed on the rear surface of the semiconductor substrate 1 to obtain a first pre-processed region, and the resulting structure is as shown in FIG.

[0052] In this step, the first diffusion process is a diffusion process performed on the entire back surface of the semiconductor substrate 1. The doping source of the first diffusion process includes a P-type conductive doping source. In a specific embodiment, the doping source of the first diffusion process may be, for example, a boron source. The first diffusion process may diffuse boron atoms from the boron source to form a boron diffusion layer (i.e., the P-type conductive region 2). The boron source may be, for example, boron tribromide. Due to the high concentration of boron on the surface of the semiconductor substrate 1, a borosilicate glass (BSG) layer 21 is usually formed. This borosilicate glass layer 21 has a metal gettering effect and affects the normal operation of the solar cell, so it must be removed later.

[0053] In some embodiments, the first diffusion treatment may be performed by one or more of high-temperature diffusion, slurry doping, or ion implantation. The process of the first diffusion treatment will be specifically described below using high-temperature diffusion as an example.

[0054] In some embodiments, the temperature of the first diffusion treatment is 800°C to 1200°C, and specifically may be 800°C, 850°C, 900°C, 950°C, 1000°C, 1100°C, or 1200°C.

[0055] In some embodiments, the duration of the first diffusion treatment may be 2 hours to 5 hours, specifically 2 hours, 3 hours, 4 hours, or 5 hours.

[0056] In some embodiments, the first diffusion treatment forms a borosilicate glass layer 21 on the surface of the first pre-treatment region, and the thickness of the borosilicate glass layer 21 is 100 nm to 200 nm, and specifically may be 100 nm, 110 nm, 130 nm, 150 nm, 180 nm, or 200 nm.

[0057] S202: The first pre-processed region is subjected to a first local laser processing and a first etching processing, and the resulting structure is as shown in FIG.

[0058] In this step, by performing local laser treatment on the first pre-treatment region, part of the boron diffusion layer and the borosilicate glass layer 21 in step S201 are etched, exposing the semiconductor substrate 1, while the region not treated with the laser remains the P-type conductive region 2 and the borosilicate glass layer 21. During the laser treatment, the semiconductor material is susceptible to laser-induced thermal melting damage and thermal stress damage, so the first etching treatment removes the thermal damage caused by the first local laser treatment, which is understandable.

[0059] In some embodiments, the laser power of the first localized laser treatment is between 20W and 30W, and may specifically be 20W, 22W, 25W, 28W, or 30W.

[0060] In some embodiments, the etching width of the first localized laser treatment is between 300 μm and 600 μm, and may be specifically 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 560 μm, or 600 μm.

[0061] In some embodiments, the etching agent for the first etching process includes an alkaline substance and a treatment agent, and the treatment agent includes at least one of a texturing additive and an alkaline polishing additive. The alkaline substance may be, for example, sodium hydroxide. The texturing additive and / or alkaline polishing additive are typically isopropanol, a surfactant, an antifoaming agent, sodium acetate, potassium sorbate, and deionized water. The texturing additive and / or alkaline polishing additive used in the present invention are commonly used reagents for etching in this field, and the specific components are not limited thereto. The texturing additive can improve the hydrophilicity of the texturing solution and the semiconductor substrate 1 surface, accelerate bubble removal from the semiconductor substrate 1 surface, remove oil stains from the semiconductor substrate 1 surface, and control the corrosion rate of the semiconductor substrate 1 in the alkaline solution. Based on a similar principle, alkaline polishing additives can also control the corrosion rate of semiconductor substrate 1 in alkaline solution, and embodiments of the present invention add texturing additives and / or alkaline polishing additives to alkaline materials to control the anisotropy of material etching in P-type conductive region 2, thereby obtaining first recessed regions 5 recessed along a first direction and improving the light utilization efficiency of the cell.

[0062] In some embodiments, the mass ratio of the alkaline substance to the treatment agent is (2 to 6):1. Specifically, it may be 2:1, 3:1, 4:1, 5:1, or 6:1. By setting the mass ratio of the alkaline substance to the treatment agent within the above range, the direction and speed of the first etching process can be controlled, reducing etching along the thickness direction of the semiconductor substrate 1 and increasing etching along the length or width direction of the semiconductor substrate 1. As a result, a first cutout region 5 is formed at the edge of the P-type conductive region 2, and the first cutout region 5 has a first sidewall 51 and a second sidewall 52, the first sidewall 51 being farther from the semiconductor substrate 1 than the second sidewall 52, and a first textured structure 501 is provided within the first cutout region 5.

[0063] In a specific embodiment, the mass ratio of the alkaline substance to the treatment agent is controlled to control the size of the first side wall 51 and the second side wall 52. It should be understood that the above mass ratios are only examples, and other mass ratios may be used according to needs.

[0064] In a specific embodiment, the mass ratio of the alkaline substance to the treatment agent is controlled to control the size of the first texture structure 501 in the first side wall 51 and the second side wall 52, such that the first side wall 51 has a first sub-texture structure a5011 and the second side wall 52 has a first sub-texture structure b5012. As the amount of treatment agent added increases, the sizes of the first sub-texture structure a5011 and the first sub-texture structure b5012 gradually increase. However, if the sizes of the first sub-texture structure a5011 and the first sub-texture structure b5012 are too large, the number of first texture structures 501 arranged on the first side wall 51 and the second side wall 52 will be reduced. Therefore, the present invention controls the mass ratio of the alkaline substance to the treatment agent to (2~6):1, thereby achieving a balance between the sizes of the first side wall 51 and the second side wall 52 and the first texture structures 501 in the first side wall 51 and the second side wall 52, and effectively improving the solar light utilization efficiency of the P-type conductive region 2.

[0065] In some embodiments, the time for the first etching process is 500 seconds to 1000 seconds, and specifically may be 500 seconds, 600 seconds, 700 seconds, 800 seconds, 900 seconds, or 1000 seconds. Setting the time for the first etching process within the above range is advantageous for forming first sidewall 51 and second sidewall 52 of appropriate sizes and first texture structure 501 on first sidewall 51 and second sidewall 52, and is advantageous for improving the solar utilization efficiency on the back surface of the cell.

[0066] In an embodiment of the present invention, by controlling the etching agent and etching process of the first etching process, the first sidewalls 51 and second sidewalls 52 in the first cutout region 5 have a specific structure, and the first sidewalls 51 and second sidewalls 52 have a specific shape of the first texture structure 501, which can reduce the utilization rate of incident light on the back surface of the semiconductor substrate 1, increase the light absorption of long-wavelength light on the front surface of the semiconductor substrate 1, improve the light utilization rate of the solar cell, and improve the photoelectric conversion efficiency of the solar cell without affecting the passivation effect of the region between the P-type conductive region 2 and the partition region 3.

[0067] S203: A second diffusion process is performed on the rear surface of the semiconductor substrate 1 to obtain a second pre-processed region, and the resulting structure is as shown in FIG.

[0068] In some embodiments, the doping source for the second diffusion process includes an N-type conductive doping source. In a specific example, the doping source for the second diffusion process may be, for example, a phosphorus source. The first diffusion process may diffuse phosphorus atoms using the phosphorus source to form a phosphorus diffusion layer (i.e., N-type conductive region 4), and the phosphorus source may be, for example, POCl3. Due to the high concentration of phosphorus on the surface of semiconductor substrate 1, a phosphosilicate glass (PSG) layer 41 is usually formed. This phosphosilicate glass layer 41 has a metal gettering effect and affects the normal operation of the solar cell, so it needs to be removed later.

[0069] In this step, by performing the second diffusion treatment on the rear surface of the semiconductor substrate 1, a P-type conductive region 2, a borosilicate glass layer 21, an N-type conductive region 4, and a phosphosilicate glass layer 41 are sequentially provided on the rear surface of the semiconductor substrate 1 in an area on the rear surface of the semiconductor substrate 1 that has not been subjected to the first local laser treatment. An N-type conductive region 4 and a phosphosilicate glass layer 41 are sequentially provided on the rear surface of the semiconductor substrate in an area on the rear surface of the semiconductor substrate 1 that has been subjected to the first local laser treatment.

[0070] In some embodiments, the second diffusion process may employ any one or more of the following methods: high temperature diffusion, slurry doping, or ion implantation.

[0071] The process of the second diffusion treatment will be specifically described below using high-temperature diffusion as an example.

[0072] The temperature of the second diffusion treatment is 700°C to 1000°C, and specifically may be 700°C, 750°C, 800°C, 830°C, 890°C, 950°C, or 1000°C.

[0073] In some embodiments, the duration of the second diffusion treatment is 1 hour to 3 hours, and specifically may be 1 hour, 1.5 hours, 2 hours, 2.5 hours, or 3 hours.

[0074] In some embodiments, the thickness of the phosphosilicate glass layer 41 is 100 nm to 200 nm, and specifically may be 100 nm, 110 nm, 130 nm, 150 nm, 180 nm, or 200 nm.

[0075] S204: A second localized laser treatment and a second etching treatment are performed on the second pre-treatment region, thereby converting the second pre-treatment region into a P-type conductive region 2, a partition region 3, and an N-type conductive region 4, the partition region 3 being located between the P-type conductive region 2 and the N-type conductive region 4, and having a first cutout region 5 recessed along a first direction between the partition region 3 and the P-type conductive region 2, and a first texture structure 501 being provided in the first cutout region 5, and the resulting structure is as shown in FIG. 14.

[0076] In this step, the second local laser treatment region is the region where the first local laser treatment was performed in step 202 and a portion of the region where the first local laser treatment was not performed, and the second local laser treatment removes the phosphosilicate glass layer 41 in the region where the first local laser treatment was performed and the phosphosilicate glass layer 41 in the portion of the region where the first local laser treatment was not performed, resulting in a structure as shown in Fig. 13. Next, a second etching process is performed to etch the borosilicate glass layer 21 and the N-type conductive region 4 in the region where the first local laser treatment was performed, and to etch the phosphosilicate glass layer 41 and a portion of the N-type conductive region 4 in the portion of the region where the first local laser treatment was not performed, thereby forming the P-type conductive region 2, the partition region 3, and the N-type conductive region 4 on the rear surface of the semiconductor substrate 1, providing the partition region 3 between the P-type conductive region 2 and the N-type conductive region 4, and exposing the first cutout region 5 between the P-type conductive region 2 and the partition region 3.

[0077] In some embodiments, the laser power of the second localized laser treatment is between 20W and 30W, and may be specifically 20W, 22W, 25W, 28W, or 30W.

[0078] In some embodiments, the etching width of the second local laser treatment is between 400 μm and 700 μm, and may be 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, or 700 μm. The etching width of the second local laser treatment is understandably larger than the etching width of the first local laser treatment.

[0079] In some embodiments, the etchant for the second etching process comprises an alkaline solution, and illustratively the alkaline solution may be, for example, a sodium hydroxide solution.

[0080] In some embodiments, the concentration of the alkaline solution is 0.5% to 5%, and may specifically be 0.5%, 1%, 1.8%, 2.5%, 3.2%, 3.5%, 4%, 4.5%, or 5%.

[0081] In some embodiments, the temperature of the second etching treatment is 60°C to 80°C, and specifically may be 60°C, 63°C, 68°C, 73°C, 77°C, or 80°C.

[0082] In some embodiments, the duration of the second etching process is 300 to 800 seconds, and may specifically be 300, 400, 500, 600, 700, or 800 seconds.

[0083] In an embodiment of the present invention, after the first localized laser treatment, a first etching treatment is performed using a specific etching agent to pre-form a first cutout region 5 with a specific shape and structure in a region of the P-type conductive region 2 close to the partition region 3, and a first texture structure 501 is formed within the first cutout region 5. This reduces the reflection of incident light on the back surface of the semiconductor substrate 1 and increases the reflection of long-wavelength light on the front surface of the semiconductor substrate 1, thereby improving the light utilization rate of the solar cell and improving the photoelectric conversion efficiency of the solar cell without affecting the passivation effect of the region between the P-type conductive region 2 and the partition region 3.

[0084] Because the second etching process is performed after the second diffusion process, a third cutout region is formed in the region between the partition region 3 and the N-type conductive region 4, and the shape of the third cutout region is a typical shape, i.e., a "step-like" or "slope-like" shape, which makes it impossible to effectively utilize sunlight and therefore does not effectively improve the photoelectric conversion efficiency of the cell. This is understandable.

[0085] Step 300: Form a first passivation layer 6 on the front side of the semiconductor substrate 1.

[0086] In an embodiment of the present invention, a first passivation layer 6 is formed on the front surface of the semiconductor substrate 1. The first passivation layer 6 can utilize the passivation effect to reduce the minority carrier concentration on the surface of the semiconductor substrate 1, suppressing carrier recombination on the cell surface, thereby slowing down the surface recombination rate, and also reducing the series resistance and improving the electron transport capacity.

[0087] In some embodiments, the first passivation layer 6 may include, but is not limited to, a single oxide layer or a multi-layer structure, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may also be used, and the present invention is not limited to the specific material of the first passivation layer 6. The first passivation layer 6 can provide good passivation and anti-reflection effects for the semiconductor substrate 1, thereby improving the conversion efficiency of the cell.

[0088] In some embodiments, the thickness of the first passivation layer 6 ranges from 10 nm to 100 nm, and may be, for example, 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and of course may be other values ​​within the above range, and is not limited thereto.

[0089] In some embodiments, the manufacturing method of the present invention further comprises forming a reflection-reducing layer on the surface of the first passivation layer 6 to reduce light reflection on the front surface of the cell.

[0090] In some embodiments, the reflection-reducing layer may be, for example, a silicon oxynitride layer or an aluminum oxide / silicon nitride stacked structure, but the present invention is not limited thereto. Taking a silicon oxynitride layer as an example, the presence of silicon oxynitride can effectively reduce light reflection and improve light transmittance. By controlling the film thickness, the reflectance can be adjusted to achieve the desired reflection-reducing effect. Furthermore, NH4, the raw material for silicon oxynitride, decomposes into H atoms during the reaction process. The H atoms penetrate into the semiconductor substrate 1 at high temperatures and bond with dangling bonds on the surface, providing passivation.

[0091] In some embodiments, the thickness of the first passivation layer 6 ranges from 40 nm to 100 nm, and may be, for example, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and of course may be other values ​​within the above range, and is not limited thereto.

[0092] In some embodiments, the first passivation layer 6 and / or the reflection-reducing layer may be deposited using plasma-assisted chemical vapor deposition, although other methods, such as organic chemical vapor deposition, may also be used. The specific embodiment of the first passivation layer 6 is not limited in the embodiments of the present invention.

[0093] Step S400: Form a second passivation layer 7 on the rear surface of the semiconductor substrate 1, so that the second passivation layer 7 covers the P-type conductive region 2, the first cutout region 5, the partition region 3 and the N-type conductive region 4, and the resulting structure is as shown in FIG. 15.

[0094] 15 and 4, in this step, the formed second passivation layer 7 covers the first cutout region 5 between the P-type conductive region 2 and the partition region 3. Therefore, the second passivation layer 7 has a second cutout region 701 corresponding to the first cutout region 5. The second cutout region 701 includes a third sidewall 71 and a fourth sidewall 72, and an included angle is formed between the third sidewall 71 and the fourth sidewall 72. In some examples, the included angle may be acute. In other examples, the included angle may be obtuse. By setting the included angle within the above range, the second passivation layer 7 completely covers the first cutout region 5, thereby improving the passivation effect on the back surface of the battery. The surface of the second passivation layer 7 has a smooth structure and can fill the first undulating valleys 512 and second undulating valleys 522 of the first sub-texture structure. This is understandable.

[0095] In some embodiments, the second passivation layer 7 includes one or a combination of a silicon nitride layer, a silicon oxynitride layer, and an aluminum oxide / silicon nitride stack. Naturally, other types of passivation layers may be used for the second passivation layer 7, and the present invention does not limit the specific material of the second passivation layer 7. For example, in another embodiment, the second passivation layer 7 may be a stack of silicon dioxide and silicon nitride. The second passivation layer 7 can provide good passivation for the silicon substrate, contributing to improving the conversion efficiency of the battery.

[0096] In some embodiments, the second passivation layer 7 may be deposited using plasma-enhanced chemical vapor deposition, although of course other methods such as organic chemical vapor deposition may also be used.

[0097] In some embodiments, the thickness of the second passivation layer 7 ranges from 10 nm to 100 nm, and may be, for example, 10 nm, 20 nm, 30 nm, 42 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm, and of course may be other values ​​within the above range and is not limited thereto.

[0098] Step S500: Form a first electrode 8 and a second electrode 9 on the surface of the second passivation layer 7 to obtain a solar cell 100, the structural schematic diagram of which is shown in FIG.

[0099] Specifically, in this step, a metallization process is performed on the surface of the second passivation layer 7 to obtain a first electrode 8 and a second electrode 9 corresponding to the P-type conductive region 2 and the N-type conductive region 4, respectively. The first electrode 8 and the second electrode 9 are fabricated using a screen printing method and then sintered, so that the first electrode 8 penetrates the second passivation layer 7 to form an ohmic contact with the N-type conductive region 4, and the second electrode 9 penetrates the second passivation layer 7 to form an ohmic contact with the P-type conductive region 2, or the first electrode 8 penetrates the second passivation layer 7 to form an ohmic contact with the P-type conductive region 2, and the second electrode 9 penetrates the second passivation layer 7 to form an ohmic contact with the N-type conductive region 4. Of course, the first electrode 8 and the second electrode 9 may also be formed on the rear surface of the battery using at least one of a metal evaporation method and an electroplating method.

[0100] In the embodiments of the present invention, the specific materials of the first electrode 8 and the second electrode 9 are not limited. For example, when the first electrode 8 forms an ohmic contact with the P-type conductive region 2 and the second electrode 9 forms an ohmic contact with the N-type conductive region 4, the first electrode 8 is a silver electrode or a silver / aluminum electrode, and the second electrode 9 is a silver electrode. For example, a silver paste may be printed on the lower surface of the second passivation layer 7 corresponding to the N-type conductive region 4, and a silver paste or a silver / aluminum paste doped with a small amount of aluminum may be printed on the lower surface of the second passivation layer 7 corresponding to the P-type conductive region 2, followed by sintering. Each paste may be fired through the second passivation layer 7, and the formed silver electrode or silver / aluminum electrode may form an ohmic contact with the P-type conductive region 2, and the formed silver electrode may form an ohmic contact with the N-type conductive region 4.

[0101] In the present invention, unless otherwise specified, the processing steps may be performed in the order described or in a different order from the order described. In the embodiments of the present invention, the order of steps for manufacturing a solar cell is not limited and may be adjusted according to the actual production process.

[0102] The solar cell of the present invention may be an N-type IBC cell or a P-type IBC cell.

[0103] In a third aspect, an embodiment of the present invention provides a photovoltaic module 1000 including a group of cells formed by electrically connecting the solar cells described above.

[0104] Specifically, referring to FIG. 16, a photovoltaic module 1000 includes a first cover plate 200, a first package adhesive layer 300, a group of solar cells, a second package adhesive layer 400, and a second cover plate 500.

[0105] In some embodiments, the solar cell group includes a plurality of the aforementioned solar cells 100 connected via conductive bands, and the solar cells 100 may be connected by partial stacking or splicing.

[0106] In some embodiments, the first cover plate 200, the second cover plate 500 may be a transparent or opaque cover plate, for example, a glass cover plate, a plastic cover plate.

[0107] Both sides of the first package adhesive layer 300 are in contact with and bonded to the first cover 200 and the battery group, respectively, and both sides of the second package adhesive layer 400 are in contact with and bonded to the second cover 500 and the battery group, respectively. The first package adhesive layer 300 and the second package adhesive layer 400 may each be an ethylene-vinyl acetate copolymer (EVA) adhesive film, a polyethylene-octene copolymer (POE) adhesive film, or a polyethylene terephthalate (PET) adhesive film.

[0108] In order to prevent the occurrence of lamination misalignment in the solar photovoltaic module 1000 during the lamination process, the solar photovoltaic module 1000 may adopt a fully enclosed side sealing, that is, a sealing tape is used to completely cover and seal the sides of the solar photovoltaic module 1000.

[0109] The photovoltaic module 1000 further includes an edge sealing member, which is fixed to and seals a portion of the edge of the photovoltaic module 1000. The edge sealing member may be fixed to and seal an edge near a corner of the photovoltaic module 1000. The edge sealing member may be high-temperature resistant tape. The high-temperature resistant tape has relatively good high-temperature resistance and will not decompose or fall off during the lamination process, ensuring reliable sealing of the photovoltaic module 1000. Both ends of the high-temperature resistant tape are fixed to the second cover plate 500 and the first cover plate 200, respectively. Both ends of the high-temperature resistant tape may be adhered to the second cover plate 500 and the first cover plate 200, respectively, and the center of the high-temperature resistant tape can achieve positional regulation with respect to the side edges of the photovoltaic module 1000, preventing the photovoltaic module 1000 from being misaligned during the lamination process.

[0110] The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention. Those skilled in the art can make various modifications and changes to the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention. [Explanation of symbols]

[0111] 1000...Photovoltaic modules, 100...solar cells, 200...First cover plate, 300...first package adhesive layer, 400...second package adhesive layer, 500...Second cover plate, 10...p+ doped layer, 20...n+ doped layer, 30...gap region, 1...Semiconductor substrate, 2...P-type conductive region, 21...borosilicate glass layer, 3...Partition area, 31...second texture structure, 4...N-type conductive region, 41...phosphosilicate glass layer, 5...first notch area, 501...first texture structure, 5011...first sub-texture structure a, 5012...first sub-texture structure b, 51...first side wall, 511...First hill, 512...1st relief valley, 52...second side wall, 521…Second undulating mountain, 522…Second undulating valley, 6...first passivation layer, 7...second passivation layer, 701...second notch area, 71...Third side wall, 72...Fourth side wall, 8...first electrode, 9...Second electrode.

Claims

1. A solar cell, the solar cell including a semiconductor substrate, a first passivation layer, and a second passivation layer; the semiconductor substrate includes opposed front and rear surfaces; a P-type conductive region, an N-type conductive region, and a partition region are provided on a rear surface of the semiconductor substrate, the P-type conductive region has a first notch recessed toward the partition region along a first direction, a first texture structure is provided within the first notch, the first direction is parallel to a direction from the partition region toward the P-type conductive region, a second texture structure is provided within the partition region, and a shape of the second texture structure is different from a shape of the first texture structure; the first passivation layer is located on a front side of the semiconductor substrate; The solar cell, wherein the second passivation layer is located on a rear surface of the semiconductor substrate.

2. 2. The solar cell of claim 1, wherein the first notch has a first sidewall and a second sidewall, the first sidewall being farther from the semiconductor substrate than the second sidewall, and an included angle formed between the first sidewall and the second sidewall, the included angle being a non-right angle.

3. 2. The solar cell of claim 1, wherein the second passivation layer has a second notch recessed along the first direction, the second notch corresponding to the position of the first notch, the second notch having a third sidewall and a fourth sidewall, the third sidewall being farther from the semiconductor substrate than the fourth sidewall, and an included angle between the third sidewall and the fourth sidewall being a non-right angle.

4. 2. The solar cell according to claim 1, wherein the N-type conductive region has a third cutout facing the partition region, the third cutout having a "step-like" or "slope-like" shape, and the third cutout has a third texture structure.

5. The solar cell according to claim 2 , wherein the length of the first sidewall is smaller than the length of the second sidewall.

6. 3. The solar cell of claim 2, wherein the first texture structure includes a plurality of first sub-texture structures a provided on the first side wall and a plurality of first sub-texture structures b provided on the second side wall, the first sub-texture structures a protruding from a surface on which the first side wall is located, and the first sub-texture structures b protruding from a surface on which the second side wall is located.

7. The solar cell according to claim 6 , wherein the size of the first sub-texture structure a is equal to or smaller than the size of the first sub-texture structure b.

8. a ratio of a total surface area of ​​the first sub-texture structure a on the first sidewall to an area of ​​the surface on which the first sidewall is located is (1.2 to 2):1; The solar cell of claim 6, wherein the ratio of the total surface area of ​​the first sub-texture structure b on the second side wall to the area of ​​the surface on which the second side wall is located is (1.3 to 2):

1.

9. The solar cell according to claim 6 , wherein the shape of the first texture structure includes at least one of a prism shape and a pyramid shape.

10. the first sub-texture structure a has a plurality of first undulating portions on the first sidewall, the first undulating portions including first undulating peaks and first undulating valleys; the first sub-texture structure b has a plurality of second undulating portions on the second sidewall, the second undulating portions including second undulating peaks and second undulating valleys; 7. The solar cell of claim 6, wherein at least a portion of the first sub-texture structure a is located within the second undulating valley, and at least a portion of the first sub-texture structure b is located within the first undulating valley.

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