Filter stage system, method for quantum computing, computer program (current-mode transconductance-capacitance filter in radio frequency digital-to-analog converter)

Abstract

To provide a filter stage system.SOLUTION: A filter stage system includes a continuous time baseband filter comprising a feedback loop that employs at least one first impedance node and at least one second impedance node. The at least one first impedance node has a higher impedance than the at least one second impedance node. The at least one first impedance node provides a dominant pole, and the at least one second impedance node provides a non-dominant pole. The continuous time baseband filter generates a filtered current. The filter stage system also includes a mirroring component that mirrors the filtered current to an output.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to integrated radio frequency digital-to-analog converters (RF DACs), and more particularly to utilizing current-mode transconductance-capacitance filters to generate filtered current and provide a path for current reuse between the filter and adjacent stages in the signal chain. [Background technology]

[0002] Quantum computing is generally the use of quantum mechanical phenomena to perform computing and information processing functions. Quantum computing contrasts with classical computing, which generally operates on the binary values ​​of transistors. That is, while classical computers operate on two basis states, either 0 or 1, quantum computers operate on qubits, which have a probabilistic superposition of both 0 and 1, and can entangle multiple qubits and use interference. Quantum computing is emerging as a new paradigm that solves a wide variety of problems that represent undesirable expansion for traditional classical high-performance computers. The ability to generate arbitrary waveforms with variable amplitude and low distortion is desirable in multiple contexts, including the control of qubits in the field of quantum computing. In particular, radio frequency digital-to-analog converters (RFDACs) are useful in various applications, including wireless transmitters and implementing control pulses for qubits. Filter implementation and the interface between filters and other elements of the signal chain are valuable in such designs. Continuous-time filters are well suited for high dynamic range and low-power active filter implementations. Current-mode signal processing is well suited for low-distortion applications because it reduces the voltage swings at various nodes of interest. However, conventional current-mode input filters using operational amplifiers consume a significant amount of power and are limited to high-frequency applications. Summary of the Invention [Problem to be solved by the invention]

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, or computer program product, or combination thereof, facilitates an integrated radio frequency digital-to-analog converter (RF DAC), and more specifically, utilizes a current-mode transconductance-capacitance filter to generate and provide a path for filtered current for current reuse between the filter and adjacent stages in the signal chain. [Means for solving the problem]

[0004] According to one embodiment, a system includes a processor capable of executing components stored in a memory to implement the following system: a radio frequency digital-to-analog converter (RFDAC) operating in current mode; and a continuous-time baseband filter including a feedback loop utilizing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole and the at least one second impedance node providing a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current.

[0005] In any embodiment, a mirroring component operating in current mode mirrors the filtered current to the output.

[0006] According to one embodiment, a system in which the method is implemented comprises a radio frequency digital-to-analog converter executing system executable components to perform the following operations: operating in current mode with a baseband filter in which the input and output of the system block are represented as currents.

[0007] In any aspect, the system-implemented method further comprises mapping a mirroring component through the system and operating in current mode to mirror the filtered current to the output, which selectively varies the mirroring ratio to achieve variable gain for fine baseline steps. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows a block diagram of an example system implementation that implements an integrated digital-to-analog converter (DAC) that utilizes a current-mode signal path.

[0009] [Figure 2] 1 illustrates an exemplary flow chart for an integrated radio frequency digital-to-analog converter utilizing a current-mode transconductance-capacitance filter.

[0010] [Figure 3] 1 illustrates an example architecture of a radio frequency digital-to-analog converter (RF DAC) signal chain.

[0011] [Figure 4] 1 illustrates an exemplary block-level diagram architecture of a feedback-based transconductance-capacitor baseband filter.

[0012] [Figure 5] 1 shows an exemplary schematic transistor-level diagram of a single-ended implementation of a filter.

[0013] [Figure 6] 1 shows an exemplary schematic transistor-level implementation of a baseband filter.

[0014] [Figure 7] 10 illustrates another exemplary transistor-level diagram of an embodiment of an alternating filter arrangement.

[0015] [Figure 8] 10 illustrates another exemplary transistor-level diagram of an embodiment of an alternating filter arrangement.

[0016] [Figure 9] 10 illustrates another exemplary transistor-level diagram of an embodiment of an alternating filter arrangement.

[0017] [Figure 10] 1 illustrates an exemplary transistor-level diagram of one embodiment of a differential filter transfer function.

[0018] [Figure 11] An example of simulation results for a current-mode transconductance-capacitance filter is shown.

[0019] [Figure 12] 1 shows an example of a schematic expansion of an array-based system.

[0020] [Figure 13] 1 shows a schematic example of a cascaded extension of the complement stage.

[0021] [Figure 14] 1 illustrates a block diagram of an example non-limiting operating environment in which one or more embodiments described herein can be facilitated.

[0022] [Figure 15] 1 illustrates a block diagram of an example non-limiting cloud computing environment in accordance with one or more embodiments of the present disclosure.

[0023] [Figure 16] FIG. 1 illustrates a block diagram of an example of non-limiting abstraction model layers in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following detailed description is merely exemplary and is not intended to limit the embodiments or the application or uses of the embodiments, or combinations thereof. Furthermore, there is no intention to be bound by any express or implied information presented in the preceding Summary section or the Detailed Description section. One or more embodiments will now be described with reference to the drawings. Like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that in various instances one or more embodiments may be practiced without these specific details.

[0025] The present disclosure generally relates to systems and methods for implementing a current-mode end-to-end path from a radio frequency digital-to-analog converter (RF DAC) through an output that allows for the realization of a preferred set of tradeoffs in terms of power consumption and distortion. The elements of the signal path are the RF DAC, baseband filter, mirroring, and output stage. Benefits can be realized by implementing the entire chain in current mode or by implementing sub-elements of the chain in current mode.

[0026] Embodiments integrate a radio frequency digital-to-analog converter using a current-mode transconductance-capacitance filter to generate a filtered current and provide a path for current reuse between the filter and adjacent stages in the signal chain. Current-mode signal processing is well suited for low-distortion applications because it reduces voltage swings at various nodes of interest. However, conventional current-mode input filters using operational amplifiers consume a significant amount of power and are limited to high-frequency applications. The embodiments disclosed and claimed herein offer a promising solution to this problem by providing a current-mode signal path design in an integrated digital-to-analog converter implementation. The efficient current-mode filter stage implementation offers multiple advantages in the context of a proposed end-to-end current-mode analog signal path RF DAC architecture developed for low-power and low-distortion random waveform generation applications. It provides a path for current reuse between the filter and adjacent stages in the signal chain. It also avoids introducing additional current-to-voltage conversion in the signal path (such conversion may be included in the feedback path), helps limit the generation of undesired distortion, and is well tuned for low output swing requirements.

[0027] Quantum computing uses qubits as its essential units, instead of bits in classical computing. A qubit (e.g., a quantum binary digit) is the quantum mechanical equivalent of a classical bit. While a classical bit can only utilize one of two basis states (e.g., 0 or 1), a qubit can utilize a superposition of its basis states (e.g., α|0>+β|1>, where α and β are |α| 2 +|β| 2Quantum computers (e.g., computers that use qubits instead of just classical bits) can theoretically hold exponentially more information than the same number of classical bits. Thus, quantum computers (e.g., computers that use qubits instead of just classical bits) could theoretically quickly solve problems that would be extremely difficult for classical computers. A classical computer bit is a simple binary digit, either 0 or 1. Almost any device with two distinct states, such as a switch, valve, magnet, coin, or similar binary-type state measurement, can function to represent a classical bit. Qubits, with their quantum mystique, can occupy a superposition of 0 and 1 states. Qubits cannot have intermediate values ​​such as 0.63; when a qubit's state is measured, the result is either 0 or 1. However, in the course of a computation, a qubit can behave as if it were a mixture of, for example, 63 percent 0 and 37 percent 1 states. A typical quantum program requires coordination of the quantum and classical parts of the computation. One way to think about a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, translating the algorithm into an executable form, running an experiment or simulation, and analyzing the results. A concept that spans these processes is that of an intermediate representation. An intermediate representation (IR) of an operation is neither its source language description nor its target machine instructions, but something in between. A compiler may use several IRs during the process of translating and optimizing a program. The input is source code describing the quantum algorithm and compile time parameters. The output is a combined quantum / classical program represented using high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic; therefore, measurements of algorithm outputs provide a correct solution within an algorithm-specific confidence interval. The operation is then repeated until a solution with satisfactory probability can be achieved.

[0028] By processing information using the laws of quantum mechanics, quantum computers offer new means of performing computational tasks such as molecular computation, optical photonics, optimization, and many more. Many algorithms have been developed to efficiently perform such computational tasks. In particular, radio frequency digital-to-analog converters are useful in a variety of applications, including implementing control pulses for wireless transmitters and qubits. Designs using voltage-mode representations of signal paths present few challenges, including nonlinear behavior and high dynamic range requirements at block interfaces, which leads to the production of higher amplitude distortion and independent power for each block without any power efficiency advantages resulting from current reuse. Accordingly, embodiments herein propose an efficient current-mode filter design for implementing distortion-integrated RF DAC solutions to develop low-power random waveform generation applications. This provides a path for current reuse between the filter and adjacent stages in the signal chain, avoiding additional current-to-voltage conversion in the signal path (e.g., such conversion may be included in the feedback path), helping to limit the generation of undesired distortion, and it also scales well with low output amplitude requirements.

[0029] FIG. 1 shows a block diagram of an example system 100 capable of accessing and processing data using the illustrated variable computation component according to one or more embodiments described herein. System 100 may use machine learning and training of neural networks or other types of models to facilitate the evaluation and identification of large amounts of various types of data. System 100 may also generate predictive recommendations at an individual level in the context of one or more embodiments described herein. Aspects of a system (e.g., system 100, etc.), apparatus, or process described in this disclosure may constitute machine-executable components embodied within a machine, e.g., embodied in one or more computer-readable medium(s) associated with one or more machines. Such components, when executed by one or more machines, e.g., computers, computing devices, virtual machines, etc., may cause the machine to perform the operations described herein. Repeated descriptions of similar elements utilized in one or more embodiments described herein are omitted for brevity.

[0030] System 100 utilizes a current-mode signal path to facilitate an integrated radio frequency digital-to-analog converter (RFDAC). Embodiments relate to maintaining elements of the signal path, RFDAC, baseband filters, mirroring, and output stage. Benefits can be realized by implementing the entire chain in current mode or by implementing sub-elements of the chain in current mode.

[0031] System 100 may optionally include a server device, one or more networks, and one or more devices (not shown). System 100 may also include or be otherwise associated with a radio frequency digital-to-analog converter 102 operating in current mode, comprising a continuous-time baseband filter 104 operating in current mode, in which the input and output of the system block are represented as currents. A mirroring component 106 mirrors the filtered current to an output 108 operating in current mode.

[0032] In an implementation, a current-mode end-to-end path from the radio frequency digital-to-analog converter via output 108 enables the feasibility of low-power, low-distortion random waveform generation applications. Continuous-time baseband filter 104 includes a feedback loop utilizing at least one first impedance node and at least one second impedance node, where the at least one first impedance node has a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole, and the at least one second impedance node providing a non-dominant pole, and the continuous-time baseband filter generates a filtered current. Mirroring component 106 mirrors the filtered current to output 108, selectively varying the mirroring ratio to achieve variable gain for fine baseline steps.

[0033] System 100 may be any suitable computing device or set of computing devices that may be communicatively coupled to devices, non-limiting examples of which include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated test system, a network storage device, a communications device, a web server device, a network switch device, a network routing device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device may be any device that may utilize information provided by system 100 and that may communicate information with system 100 or any other suitable device or combination thereof. It should be appreciated that system 100, components, models, or devices may be deployed with communications components (not shown) that enable communication between systems, components, models, devices, etc. in one or more networks.

[0034] The components of system 100 may be connected either directly or through one or more networks. Such networks may include a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), and may include wired and wireless networks, including, by way of non-limiting example, cellular, WAN, wireless fidelity (Wi-Fi), WLAN, wireless communications, microwave communications, satellite communications, optical communications, acoustic communications, or any other suitable communications technology. Also, the above-referenced systems or devices or combinations thereof have been described in terms of interactions between several components. It may be recognized that such systems and components may include those components or subcomponents designated therein, some of the designated components or subcomponents, or additional components, or combinations thereof. Subcomponents may also be implemented as components communicatively coupled to other components rather than comprising a parent component. Furthermore, one or more components or subcomponents, or combinations thereof, may be combined into a single component providing aggregate functionality. A component may also interact with one or more other components not specifically described herein for the sake of brevity, but known to those skilled in the art.

[0035] The computer processing system, method, apparatus, or computer program product, or combination thereof, of the present application may be utilized to solve new problems that arise through the evolution of technology, computers, networks, the Internet, and the like.

[0036] In today's digital world, one of the largest growth areas in electronics continues to be wireless communication applications. Modern radio frequency systems, such as superconducting qubit controllers, are based on wideband multi-channel architectures. The use of vector signal generation means, such as IQ modulators and analog synthesizers for RF signals, is limited due to the complexity and cost of their calibration. Therefore, digital-to-analog conversion is useful for performing signal processing, modulation, and signal generation. Wireless digital-to-analog converters (RF DACs) are also useful in various applications, including implementing control pulses for wireless transmitters and qubits, addressing signal-to-noise ratios. In particular, RFDAC implementations may ideally aim for minimal power consumption while maintaining low distortion. Generally, these objectives form a trade-off space that can be guided in design progression. RFDAC signal path implementations can include voltage-mode signals, current-mode signals, or a combination of both. Therefore, embodiments propose a promising solution that results in a current-mode signal path design in an integrated digital-to-analog converter. An efficient current-mode filter offers several advantages in the context of end-to-end current-mode analog signal path RFDAC architectures developed for low-power and low-distortion random waveform generation applications. It provides a path for current reuse between the filter and adjacent stages in the signal chain. It also avoids introducing additional current-to-voltage conversions in the signal path (e.g., such conversions may be included in the feedback path), mitigates the generation of undesired distortion, and is well-tuned for low output swing requirements.

[0037] FIG. 2 shows an example flowchart of an integrated radio frequency digital-to-analog converter using a current-mode transconductance-capacitance filter. As illustrated in flowchart 200, the system includes a radio frequency digital-to-analog converter (RFDAC) in which a current-mode baseband filter is used. At 202, the continuous-time baseband filter includes a feedback loop utilizing at least one first impedance node and at least one second impedance node, where the at least one first impedance node has a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole, and the at least one second impedance node providing a non-dominant pole. At 204, the continuous-time baseband filter generates a filtered current. At 206, the mirroring component selectively changes a mirroring ratio to achieve a variable gain for fine baseline steps. At 208, the scaling component scales the input current of the feedback loop to facilitate coarse gain control. At 210, the monitoring component monitors a scaled version of the input current to mitigate distortion interference through the monitoring. An additional set of poles is placed between the continuous-time baseband filter and the mirroring component to facilitate higher-order filtering and mitigate loss of stability in the continuous-time baseband filter. At 212, a subset of the multiple cascaded continuous-time baseband filters provides low-pass, band-pass, or high-pass characteristics with corner frequencies, quality factors, or gain control set by digital control. The output from this continuous-time filter is a current, and multiple such filters can be easily cascaded to achieve higher-order current-mode filters. The filters can provide low-pass, band-pass, or high-pass characteristics with corner frequencies, quality factors, and gain steps set by digital control.

[0038] Wireless communication applications present challenges due to the speed and frequency domain performance requirements of modern data converters. High-speed digital-to-analog converters require fewer mixing and filtering stages to create an effective output. Today's technological advances face many challenges to meet increasing bandwidth demands in a congested frequency spectrum. This increases signal chain complexity as frequency planning compromises size, power, and performance requirements. The ability to utilize the frequency spectrum creates enhanced user experiences and enables new system capabilities. Radio frequency converters are used to convert microwave signals to lower or higher frequency ranges for a wide range of processing options. Reducing the size and cost of telecommunications and military systems is driving the evolution of modern digital-to-analog converters, integrating more functionality onto a single chip. Some high-speed digital-to-analog converters incorporate digital signal processing and conditioning functions such as filtering, complex modulation, and numerically controlled oscillators. This allows for efficient and compact direct generation of complex RF signals. In traditional RFDAC architectures, information is processed from one frequency and converted to another. The embodiments disclosed herein perform general-purpose signal processing at lower frequencies, reducing power consumption.

[0039] FIG. 3 shows an example architecture of a radio frequency digital-to-analog converter (RFDAC) signal chain. One way to generate a complex signal is to modulate a carrier signal frequency with a local oscillator using a vector modulator. In RF applications, baseband digital I and Q signals are generated using an arbitrary waveform generator (AWG) that includes two or more synchronized digital-to-analog converters. The RFDAC chain architecture 300 includes baseband digital BBI 302 and BBQ 304 signals. Multi-bit baseband digital-to-analog converters (DACs) 306 and 308 take the digital bits and convert them to analog signals depending on the signal bandwidth and sampling clock frequency. This allows for the output of a current, which is then filtered and amplified and provided to a mixer. The signal is processed through low-pass filters 306 and 308 to reject out-band noise components resulting from the digital-to-analog converter 300. The filtered signals are mixed and thus upconverted by mixers 310 and 312 using two carriers (LO-Q and LO-I) with quadrature phases of 0 and 90 degrees relative to I and Q. The resulting signals are combined using signal combiner 311 to create a single-sideband signal representation. For example, if an (x*y) function needs to be performed in single-sideband representation, then variable x can be expressed as a combination of 0 and 90 degrees, and variable y can be expressed as a combination of 0 and 90 degrees. These two variables can then be multiplied and added, similar to the scalar product of two vectors. The output of this function is processed through driver DRV 314. Matching network MN 316 is typically a component comprising passive elements that do not provide distortion. Matching network 316 transforms resistor 318 (e.g., 50 ohms) to the impedance required by the driver, maximizing power transfer. The outputs 320 of these DACs are filtered and upconverted using I and Q channel mixers, and the resulting signals are combined and fed through a driver and matching network to a nominal load (e.g., 50 ohms) at output 320.The filter implementation and the interface between the filter and other elements of the signal chain are significant in such designs. Continuous-time filters are well suited for high dynamic range and low-power active filter implementations. Current-mode signal processing is well suited for low-distortion applications because it reduces the voltage swings at various nodes of interest. However, traditional current-mode input filters using operational amplifiers consume a significant amount of power and are limited in high-frequency applications. Continuous-time gm-C filters typically provide a high input impedance, which results in the production of higher distortion. While gm-C type filters are well suited for high-frequency applications, they are quite limited in terms of the dynamic range they support because the input is typically a voltage.

[0040] 4 shows an exemplary block-level diagram architecture of a feedback-based transconductance-capacitor baseband filter. The circuit architecture 400 is connected to a DC power supply V DD The circuit 400 includes a buffer BUF 403 and a high impedance Z 404 that provides the output impedance from the load transistor. Two transconductance blocks, g m1 410 and g m2 412. The two capacitances C1 406 and C2 408 with arrows indicate that C1 and C2 can be controlled together or independently. The transconductance and the ratio of the capacitors determine the quality factor of the filter. The current bleeder IBLD 416 is m1 410 and buffer BUF403 can be different. m2 ,Z,BUF,g m1 The route is via the following formula:

number

number

[0041] 5 shows an exemplary transistor-level diagram of a single-ended implementation of filter 500. The exemplary embodiment is one way of constructing a filter. Transistor M PB 502 or M N1 504 may implement a DC offset compensation DAC. The filter 500 has a current mode input / output gm-C filter. The common mode of the input current 506 is set, and the output current 508 is switched using drain / gate / source switching elements. NMX This is programmed via M NC1 510 and M N2 512, then M N1 504, and three transistors are inside the loop. The other two transistors M PB 502 and M NB 514 are PMOS and NMOS bias transistors, respectively. The baseband filter has a current-mode input with a negative feedback loop. The feedback loop comprises two capacitors, C1 516 and C2 518. C1 516 is associated with the dominant pole, where node C1 is connected, and C2 518 is associated with the non-dominant pole. The feedback loop is connected to one dominant pole and one non-dominant pole. In this way, it provides an optimization margin for phase margin and stability purposes. The dominant pole is formed by the output conductance of the transistor, and the non-dominant pole is formed by the transconductance of the transistor. The third pole is formed by resistor R520 and device M NMX Together with an input capacitance of 522, this provides three poles, and the third pole can be realized without any additional consumption of current. The output also has a current i out 508, which provides the filtering and gain functions, the gain being i out / i in The filter 500 simultaneously offers the possibility of low-pass or band-pass transfer functions. out / i in By using the current waveform associated with i(MNC1 ) / i in which would be a bandpass response. Thus, this filter 500 provides both responses simultaneously; it has two poles that are complex conjugates of each other, and the real pole formed on the outside of the loop is M NMX is given by the resistance and input capacitance of V P 530 and V N2 The network is comprised of I1524 and I2526, which are digitally programmable using current mirroring via 532. NC2 528 is used as an attenuator to handle the input dynamic range. This is one representation of an example configuration. If the NMOS is changed to PMOS, then it can be another example representation.

[0042] Figure 6 shows the DC power supply V DD 6 shows another exemplary transistor-level diagram of a single-ended implementation of a filter architecture 600 having two transistors M P1 604 and M P2 608. Z1 606 and Z2 610 represent capacitors associated with the dominant and non-dominant poles. Z1 606 and Z2 610 may be represented using series and parallel combinations of at least one reactive element (e.g., capacitance, inductance). This feedback loop includes a transistor M that provides negative feedback using current-mode signaling. PC1 612, M P2 604, M P1 608. Low-pass and high-pass filters H LP and H HP The transfer function of the variables is

number

[0043] 7 shows another exemplary transistor-level diagram of an alternate filter arrangement of the embodiment. There are many implementation combinations of baseband filters, and these embodiments suggest one such implementation method. As shown in diagram 700A, m represents the transconductance of the transistor, and C represents the capacitor. The architecture 700A is driven by a DC power supply V DD 702. In this configuration, impedance Z2 706 is associated with the dominant pole and Z1 704 is associated with the non-dominant pole. This configuration also uses positive feedback using current mode signaling. Another example of an embodiment is shown in diagram 700B. In this configuration, impedance Z2 708 is associated with M P1 710. This results in a smaller size pole, with Z1 712 associated with the non-dominant pole. This configuration also uses positive feedback using current-mode signaling.

[0044] FIG. 8 shows another exemplary transistor-level diagram of an alternating filter arrangement of a sample embodiment. There are many implementation combinations for baseband filters, and these embodiments suggest one such implementation method. As shown in diagram 800A, impedance Z2 804 is associated with the dominant pole, and Z1 802 is associated with the non-dominant pole. This configuration uses negative feedback using current-mode signaling. Similarly, the architecture shown in 800B adds an additional current-mode signaling leg to the feedback loop (M N1 806" and Z3808). Depending on the signal magnification and polarity, the order of the filter can be increased.

[0045] FIG. 9 illustrates another exemplary transistor-level diagram of an alternate filter arrangement of an embodiment. There are many implementation combinations for a baseband filter, and these embodiments propose one such implementation method. As shown in diagram 900A, this configuration has an impedance Z2 902 associated with the dominant pole, and Z1 904 associated with the non-dominant pole. This configuration uses negative feedback using current-mode signaling. Impedance Z3 906 is inserted in the loop to achieve high-order filtering and includes at least one passive element, and Z3 906 is connected to the M N2 904. Similarly, the diagram shown in 900B has additional impedances, impedance Z2 908 associated with the dominant pole and Z1 910 associated with the non-dominant pole. This configuration uses positive feedback using current-mode signaling.

[0046] FIG. 10 shows an exemplary transistor-level diagram of a differential filter transfer function of a sample embodiment. There are many implementation combinations for baseband filters, and these embodiments suggest one such implementation method. As shown in diagram 1000A, this configuration has impedance Z2 1002 associated with the dominant pole, and Z1 1004 associated with the non-dominant pole. This schematic diagram is a differential filter in which transistors are transferred to the differential side 1006. Additionally, the diagram shown in 1000B is configured so that impedance Z2 1008 is associated with the dominant pole and Z1 1010 is associated with the non-dominant pole. Additional series impedance at the input terminals can provide neutralization and reduce the load on the driver circuit. The neutralization network comprises at least one passive element.

[0047] The novelty of these embodiments is the use of a current-mode gm-C continuous-time filter. This methodology can realize two poles within the feedback loop. The feedback loop can realize a complex pair of poles. Feedback provides linearization leading to low distortion. A real pole is realized outside the loop. Variable gain is also implemented by using multiple current mirroring elements, allowing M out of N elements to implement the desired output current. Current can be shared between the mixer and the baseband filter output stage to reduce power. Three poles can be realized while incurring the distortion of only one transconductor stage. This concept can be extended by seamless cascading of multiple current-mode filters with common-mode compatibility. The input stage can be shared with the previous stage output to further reduce power consumption. The output stage can be shared with the next stage output to further reduce power consumption. Complex filter implementations can be realized using delayed signals from I and Q.

[0048] Figure 11 shows example simulation results for a current-mode transconductance-capacitance filter. The simulation shows the frequency response 1102 at a 3 dB cutoff frequency. The intermodulation results 1104 show the results varying based on the frequency spectrum on the x-axis. The loop stability and output noise obtained with this baseband filter 1108 are based on the varying frequency spectrum 1106. These simulations determine that this type of current-mode baseband filter is necessary for the overall requirements of the correct controller block for quantum applications. It can also be used in a global sense for any transmitter, such as a wireless transmitter. The output and intermodulation results show that this filter provides a path for current reuse between the filter and any adjacent stages in the signal chain. This helps limit the generation of undesired distortion and avoids introducing additional current-to-voltage conversion in the signal path. It is also well-tuned for low output amplitude requirements.

[0049] Figure 12 shows an example of a schematic extension of an array-based system. As shown in diagram 1200, the input is provided by baseband signals I and Q, represented as BBI 11202 and BBQ 11204. This also provides n signals BBI N 1206 and BBQ N1208. In this flow, filter elements are shared among multiple channels. With input and output as currents, current is taken from one filter to another filter 1210 and 1212. Addition or subtraction 1214 can also be performed by any of these interfaces, most simply by creating an output 1216 with a 50 ohm resistance. Another set of applications can also be performed, using one filter for an array, one filter for a low-pass configuration, and another filter for a band-pass response. Through this means, different types of signals are provided to different sensors or qubits. Higher-order filtering can be achieved by cascading multiple filters with common mode compatibility. Low-distortion polyphase filtering is also implemented by cross-coupling with quadrature filters.

[0050] FIG. 13 shows a schematic example of a cascaded extension of complementary stages. The block diagram 1300 shows how cascading can be done, where filter 1302 is a third-order filter but can consume only the current of a second-order filter. This allows it to be in a loop. The output of the NMOS stage is directly coupled 1304 to the input of PMOS stage 1306. The filter shown in this diagram is a third-order filter, and the cascade is sixth-order, resulting in minimal power consumption and low distortion. While this diagram is shown in a single-phase system, a differential loop configuration can also be used. Filter 1306 is also a third-order filter, and two similar filters can be used to form a higher-order filter without loss of dynamic range, thus simplifying the cascading of these two filters. In prior art implementations, OTA-based transimpedance filters have been commonly used in wireless systems. These filters typically use shunt-shunt feedback; however, the gain-bandwidth requirements lead to high power consumption. Both low- and band-pass transfer functions can be realized. These proposed configurations can operate with only one high-impedance node in the feedback loop for a quartic function. This is compact due to the lack of resistors. An open-loop cascade structure with a common gate input is used in some cases, typically by current-to-voltage converters. This proposed structure uses feedback to realize two complex poles leading to two real poles. This limits the reliability of the filter transfer function.

[0051] The current-mode solution offers a path for current reuse and low distortion well suited to the requirements of cryogenic waveform generation. The novelty of these embodiments lies in the use of transconductance-capacitor filters (gm-C). Its primary contribution is the feasibility of gm-C filters to provide low input impedance. Conventional gm-C filters have high input impedance and typically provide an input voltage to output voltage transfer function. Implementation in commercial CMOS technology is entirely feasible. This circuit approach is useful for implementing CMOS-controlled pulse generation analog circuits to enable enhanced scalability of future quantum computing systems.

[0052] To provide a context for various aspects of the disclosed subject matter, Figure 14 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter may be implemented. Figure 14 illustrates a block diagram of an example non-limiting operating environment that may facilitate one or more embodiments described herein. For the sake of brevity, repeated descriptions of similar elements utilized in other embodiments described herein are omitted.

[0053] 14, a suitable operating environment 1400 for implementing various aspects of the disclosure may also include a computer 1412. The computer 1412 may also include a processing unit 1414, a system memory 1416, and a system bus 1418. The system bus 1418 couples system components including, but not limited to, the system memory 1416 to the processing unit 1414. The processing unit 1414 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be utilized as the processing unit 1414. The system bus 1418 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, or a local bus, or combinations thereof, using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (registered trademark) (IEEE 1394), Small Computer System Interface (SCSI).

[0054] The system memory 1416 may also include volatile memory 1420 and nonvolatile memory 1422. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 1412, such as during start-up, is stored in the nonvolatile memory 1422. The computer 1412 may also include removable and non-removable, volatile and non-volatile computer storage media. FIG. 14 illustrates, for example, disk storage 1424. The disk storage 1424 may also include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 1424 may also include a storage medium separate from or in combination with other storage media. A removable or non-removable interface, such as interface 1426, is typically used to facilitate connection of the disk storage 1424 to the system bus 1418. FIG. 14 also illustrates software that acts as an intermediary between users and the basic computer resources described in the preferred operating environment 1400. Such software may also include, for example, operating system 1428. Operating system 1428, which may be stored on disk storage 1424, acts to control and allocate resources of the computer 1412.

[0055] System applications 1430 leverage the management of resources by operating system 1428 through program modules 1432 and program data 1434, stored, for example, either in system memory 1416 or on disk storage 1424. It should be appreciated that the present disclosure may be implemented with various operating systems or combinations of operating systems. Users enter commands or information into computer 1412 through input devices 1436. Input devices 1436 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, and webcam. These and other input devices connect to processing unit 1414 through system bus 1418 via interface ports 1438. Interface ports 1438 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 1440 use several of the same types of ports as input devices 1436. Thus, for example, a USB port may be used to provide input to computer 1412 and to output information from computer 1412 to output device 1440. Output adapter 1442 is provided to illustrate that there are some output devices 1440, such as monitors, speakers, and printers, among other output devices 1440, that require special adapters. Output adapters 1442 include, by way of example and not limitation, video and sound cards that provide a means of connection between output device 1440 and system bus 1418. It should be noted that other devices or systems of devices, or combinations thereof, provide both input and output capabilities, such as remote computer 1444.

[0056] The computer 1412 may operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1444. The remote computer 1444 may be a computer, a server, a router, a network PC, a workstation, a microprocessor-based device, a peer device or other common network node, and may typically include many or all of the elements described relative to the computer 1412. For purposes of simplicity, only a memory storage device 1446 is shown with the remote computer 1444. The remote computer 1444 is logically connected to the computer 1412 through a network interface 1448 and is then physically connected via a communication connection 1450. The network interface 1448 encompasses wired or wireless networks or a combination thereof, such as a local area network (LAN), a wide area network (WAN), a cellular network, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereon, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 1450 refer to the hardware / software utilized to connect network interface 1448 to system bus 1418. For clarity of illustration, communications connection(s) 1450 are shown internal to computer 1412, but may also be external to computer 1412. The hardware / software for connecting to network interface 1448 may also include, by way of example only, internal and external technologies such as ordinary telephone-grade modems, cable modems, modems including DSL modems, ISDN adapters, Ethernet cards, etc.

[0057] Referring now to FIG. 15 , an exemplary cloud computing environment 1550 is illustrated. As shown, the cloud computing environment 1550 includes one or more cloud computing nodes 1510, with which local computing devices used by cloud consumers, such as, for example, a personal digital assistant (PDA) or cellular phone 1554A, a desktop computer 1554B, a laptop computer 1554C, or a vehicle computer system 1554N, or combinations thereof, may communicate. Although not shown in FIG. 15 , the cloud computing nodes 1510 may further include a quantum platform (e.g., a quantum computer, quantum hardware, quantum software, etc.) with which local computing devices used by cloud consumers may communicate. The nodes 1510 may communicate with each other. The nodes may be physically or virtually grouped (not shown) in one or more networks, such as a private cloud, community cloud, public cloud, or hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 1550 to provide infrastructure, platform, or software, or combinations thereof, as a service without the cloud consumer having to maintain resources on their local computing devices. It will be understood that the types of computing devices 1554A-N shown in FIG. 15 are intended to be illustrative only, and that the computing node 1510 and cloud computing environment 1550 may communicate with any type of computerized device via any type of network, or network-addressable connection, or combination thereof (e.g., using a web browser).

[0058] Referring now to Figure 16, a set of functional abstraction layers provided by cloud computing environment 1550 (Figure 15) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 16 are intended to be illustrative only, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0059] Hardware and software layer 1660 includes hardware and software components. Examples of hardware components include mainframe 1661, RISC (Reduced Instruction Set Computer) architecture-based servers 1662, servers 1663, blade servers 1664, storage devices 1665, and network and networking components 1666. In some embodiments, software components include network application server software 1667, Quantum platform routing software 1668, or Quantum software (not shown in FIG. 16), or a combination thereof.

[0060] The virtualization layer 1670 provides an abstraction layer from which the following example virtual entities can be provided: virtual servers 1671, virtual storage 1672, virtual networks including virtual private networks 1673, virtual applications and operating systems 1674, and virtual clients 1675.

[0061] In one example, management layer 1680 may provide the functions described below. Resource provisioning 1681 provides dynamic procurement of computing resources and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 1682 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of those resources. In one example, these resources may include application software licenses. Security provides identity authentication for cloud consumers and tasks, as well as protection for data and other resources. User portal 1683 provides consumers and system administrators with access to the cloud computing environment. Service level management 1684 provides cloud computing resource allocation and management so that required service levels are met. Service level agreement (SLA) planning and fulfillment 1685 provides pre-configuration and procurement for cloud computing resources where future demand is predicted according to SLAs.

[0062] Workload layer 1690 provides examples of functionality for which a cloud computing environment may be utilized. Non-limiting examples of workloads and functions that may be provided from this layer include mapping and navigation 1691, software development and lifecycle management 1692, virtual classroom instruction delivery 1693, data analytics processing 1694, transaction processing 1695, and quantum state preparation software 1696.

[0063] The present invention may be a system, method, apparatus, or computer program product, or combinations thereof, at any possible level of technical detail of integration. A computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media may also include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical coding devices such as punch cards or raised structures in grooves with instructions recorded on them, and any suitable combination of the above. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagated through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over a wire.

[0064] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing / processing device, or may be downloaded to an external computer or external storage device, via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in the computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device. The computer-readable program instructions for carrying out operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, or the like, or conventional procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server.In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, to carry out aspects of the invention, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry.

[0065] Aspects of the present invention are described herein with reference to flowchart illustrations or block diagrams, or combinations thereof, of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations or block diagrams, or combinations thereof, and combinations of blocks in the flowchart illustrations or block diagrams, or combinations thereof, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine. The instructions, executed by the processor of the computer or other programmable data processing apparatus, thereby create means for implementing the function / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or combinations thereof. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combinations thereof, to function in a particular manner. A computer-readable storage medium having instructions stored thereon thereby comprises a product including instructions that implement aspects of the functions / acts specified in a block or blocks of the flowchart illustrations or block diagrams, or combinations thereof. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus, or other device to create a computer-implemented process whereby the instructions executing on the computer, other programmable apparatus, or other device implement the function / acts specified in a block or blocks of the flowchart or block diagram, or a combination thereof.

[0066] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in the blocks may occur out of the order depicted in the figures. For example, two blocks shown in succession may be executed substantially simultaneously, depending on the functionality involved, or the blocks may be executed in reverse order in some cases. It may also be noted that each block of a block diagram or flowchart diagram, or a combination thereof, and combinations of blocks in block diagrams or flowchart diagrams, or a combination thereof, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations, or may execute a combination of special-purpose hardware and computer instructions.

[0067] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on a computer or multiple computers, or combinations thereof, those skilled in the art will recognize that the present disclosure may also be implemented or implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks or implement particular abstract data types, or combinations thereof. Furthermore, those skilled in the art will recognize that the computer-implemented methods of the present invention may be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0068] As used herein, terms such as “component,” “system,” “platform,” and “interface” may refer to, include, or be a combination of computer-related entities or entities associated with an operating machine having one or more specific functionalities. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or any combination thereof. By way of example, both an application running on a server and the server may be a component. One or more components may reside within a process or thread of execution, or any combination thereof, and a component may be localized on one computer, distributed between two or more computers, or any combination thereof. In another example, each component may execute from various computer-readable media having various data structures stored thereon. Components may communicate via local or remote processes or a combination thereof, such as according to signals having one or more data packets (e.g., data from one component interacting with another component in a local system, a distributed system, or a network such as the Internet with other systems or a combination thereof via signals). As another example, a component may be a device having inherent functionality provided by mechanical parts operated by electrical or electronic circuits operated by software or firmware applications executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application.As yet another example, a component may be a device that provides its inherent functionality without mechanical parts but through electronic components that may include a processor or other means for executing software or firmware that provides at least a portion of the functionality of the electronic component. In an aspect, a component may emulate the electronic component via a virtual machine, for example, in a cloud computing system.

[0069] Additionally, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X utilizes A or B" is intended to mean any of the natural inclusive permutations. That is, if X utilizes A, X utilizes B, or X utilizes both A and B, then "X utilizes A or B" is satisfied under any of the foregoing examples. Furthermore, the articles "a" and "an," as used in this specification and the appended claims, should generally be construed to mean "one or more" unless otherwise specified or clear from context that the singular is intended. As used herein, the terms "example" or "exemplary," or combinations thereof, are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. Additionally, any aspect or design described herein as an "example" or "exemplary" or combination thereof is not necessarily to be construed as preferred or superior over other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0070] The term "processor" as used herein may refer to, but is not limited to, a single-core processor, a single processor with software multithreading execution capability, a multi-core processor, a multi-core processor with software multithreading execution capability, a multi-core processor with hardware multithreading technology, a parallel platform, and a parallel platform with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization or enhance the performance of user equipment. A processor may also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component associated with the operation and functionality of a component are utilized to refer to a "memory" or a "memory component" entity embodied in a component comprising memory. It should be recognized that memory or memory components or combinations thereof described herein can be either volatile memory or non-volatile memory, or can include both volatile and non-volatile memory.By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which may act as external cache memory, for example. By way of example, and not limitation, RAM is available in many forms, including synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0071] What has been described above includes only example systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, when terms such as "including," "having," and "comprising" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional phrase in the claims.

[0072] The descriptions of various embodiments are presented for illustrative purposes and are not intended to be exhaustive or limiting to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over techniques found in the industry, or to enable those skilled in the art to understand the embodiments disclosed herein. According to the present disclosure, the following items are also disclosed: (Item 1) a continuous-time baseband filter comprising a feedback loop utilizing at least one first impedance node and at least one second impedance node, the at least one first impedance node having a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole and the at least one second impedance node providing a non-dominant pole, the continuous-time baseband filter generating a filtered current; and a mirroring component that mirrors the filtered current to an output. Filter stage system. (Item 2) Item 1. The filter stage system of item 1, wherein the mirroring component selectively varies a mirroring ratio to achieve variable gain. (Item 3) 3. The filter stage system of claim 1 or 2, further comprising a scaling component that scales an input current of the feedback loop to facilitate coarse gain control. (Item 4) Item 4. The filter stage system of item 3, further comprising a monitoring component that monitors a scaled version of the input current to mitigate distorting interference. (Item 5) 5. The filter stage system of claim 1, further comprising a set of poles positioned between the continuous-time baseband filter and the mirroring component to facilitate high-order filtering and mitigate loss of stability of the continuous-time baseband filter. (Item 6) 6. The filter stage system of any one of items 1 to 5, further comprising a plurality of cascaded continuous-time baseband filters. (Item 7) 7. The filter stage system of claim 6, wherein a subset of the plurality of cascaded continuous-time baseband filters provides low-pass, band-pass, or high-pass characteristics, a quality factor, or gain control set by digital control of corner frequency. (Item 8) The feedback loop is:

number

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Claims

1. a continuous-time baseband filter comprising a feedback loop utilizing at least one first impedance node and at least one second impedance node, the at least one first impedance node having a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole and the at least one second impedance node providing a non-dominant pole, the continuous-time baseband filter generating a filtered current; and a mirroring component that mirrors the filtered current to an output; the feedback loop includes the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductor, and a second transconductor; Filter stage system.

2. 10. The filter stage system of claim 1, wherein the mirroring component selectively varies a mirroring ratio to achieve variable gain.

3. 3. A filter stage system as claimed in claim 1 or 2, further comprising a scaling component that scales an input current of the feedback loop to facilitate coarse gain control.

4. 4. The filter stage system of claim 3, further comprising a monitoring component that monitors a scaled version of the input current to mitigate distorting interference.

5. 5. The filter stage system of claim 1, further comprising a pole provided by a resistor and a capacitor located between the continuous-time baseband filter and the mirroring component to facilitate high-order filtering and mitigate loss of stability of the continuous-time baseband filter.

6. 6. A filter stage system according to claim 1, further comprising a plurality of cascaded continuous-time baseband filters.

7. 7. The filter stage system of claim 6, wherein a subset of the plurality of cascaded continuous-time baseband filters provides low-pass, band-pass, or high-pass characteristics, a quality factor, or gain control set by digital control of corner frequency.

8. The feedback loop has the following formula: [Equation 4] where C １，２ is the capacitor, and g ｍ１，２ 8. A filter stage system according to claim 3, wherein: ∑ is the transconductor, Q is the quality factor, and BW is the bandwidth.

9. 9. A filter stage system according to any one of claims 1 to 8, wherein the continuous-time baseband filter is single-ended.

10. 10. A filter stage system according to any one of claims 1 to 9, wherein the continuous-time baseband filter is differential.

11. The filter stage system of claim 4 , wherein at least one of the continuous-time baseband filter, the mirroring component, the scaling component, or the monitoring component is a cryogenic electronic component.

12. using a continuous-time baseband filter comprising a feedback loop utilizing at least one first impedance node and at least one second impedance node, the at least one first impedance node having a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole and the at least one second impedance node providing a non-dominant pole, the continuous-time baseband filter generating a filtered current; using a mirroring component to mirror the filtered current to an output; Equipped with 1. A method for quantum computing, wherein the feedback loop comprises the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductor, and a second transconductor.

13. The method of claim 12 further comprising using the mirroring component to selectively vary a mirroring ratio to achieve a variable gain.

14. 14. The method of claim 12 or 13, further comprising using a scaling component to scale the input current of the feedback loop to facilitate coarse gain control.

15. 15. The method of claim 13 or 14, further comprising using a monitoring component to monitor a scaled version of the input current so as to mitigate distorting interference.

16. 16. The method of claim 12, further comprising using a pole provided by a resistor and a capacitor located between the continuous-time baseband filter and the mirroring component to facilitate high-order filtering and mitigate loss of stability of the continuous-time baseband filter.

17. 17. The method of any one of claims 12 to 16, further comprising using a plurality of cascaded continuous-time baseband filters.

18. 20. The method of claim 17, further comprising using a subset of the plurality of cascaded continuous-time baseband filters to provide low-pass, band-pass, or high-pass characteristics, a quality factor, or gain control set by digital control of a corner frequency.

19. The feedback loop has the following formula: [Equation 5] where C １，２ is the capacitor, and g ｍ１，２ 19. The method of any one of claims 12 to 18, wherein ∑ is the transconductor, Q is the quality factor, and BW is the bandwidth.

20. A computer program having program instructions for execution by said program instructions causing a processor to: using a continuous-time baseband filter comprising a feedback loop utilizing at least one first impedance node and at least one second impedance node, the at least one first impedance node having a higher impedance than the at least one second impedance node, the at least one first impedance node providing a dominant pole and the at least one second impedance node providing a non-dominant pole, the continuous-time baseband filter generating a filtered current; using a mirroring component to mirror the filtered current to an output; executable by the processor to cause The feedback loop includes the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductor, and a second transconductor.

21. The program instructions may cause the processor to: and using said mirroring component to selectively vary the mirroring ratio to achieve variable gain.

21. The computer program of claim 20, executable by the processor to further cause:

22. 22. A computer program product as claimed in claim 20 or 21, wherein the program instructions are executable by the processor to use a scaling component to scale an input current of a feedback loop to facilitate coarse gain control.

23. The program instructions may cause the processor to: A procedure using a monitoring component that monitors a scaled version of the input current to mitigate distorting interference.

23. A computer program according to any one of claims 20 to 22, executable by the processor to further cause:

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