Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a semiconductor device.SOLUTION: A semiconductor device comprises a field plate electrode FP that is formed in a lower part of a trench TR, and a gate electrode GE that is formed in an upper part of the trench TR. A part of the field plate electrode FP constitutes a contact part FPa. The contact part FPa is formed not only in the lower part of the trench TR but also in the upper part of the trench TR, within the trench TR positioned between the gate electrode GE on the side of a region 2A and the gate electrode GE on the side of a region 2A'. The gate electrode GE includes a connection part GEa for connecting the gate electrode GE on the side of the region 2A and the gate electrode GE on the side of the region 2A', within the trench TR in which the contact part FPa is formed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode and a field plate electrode inside a trench and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices equipped with semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) employ a trench gate structure in which a gate electrode is embedded inside a trench. One type of trench gate structure is a split gate structure in which a field plate electrode is formed at the bottom of the trench and a gate electrode is formed at the top of the trench. The field plate electrode is electrically connected to the source electrode. This allows the depletion layer to expand from the field plate electrode when the device is turned off, improving the breakdown voltage of the semiconductor device.

[0003] For example, Patent Document 1 discloses a semiconductor device employing a double gate structure. In Patent Document 1, a source wiring is disposed in the center of the semiconductor device, a gate wiring is disposed around the source wiring, and a wiring for a field plate electrode (control electrode wiring) is disposed around the gate wiring. The control electrode wiring is physically and electrically separated from the source wiring and the gate wiring. Therefore, by connecting an external connection member such as a wire bonding for supplying a desired potential to the control electrode wiring, it is possible to supply not only the source potential but also a desired potential to the control electrode wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-82202 Summary of the Invention [Problem to be solved by the invention]

[0005] When the control electrode is used as a field plate electrode fixed to the source potential, in Patent Document 1, the wiring for the field plate electrode is independent from the wiring for the source, and therefore separate external connection members must be connected to these wirings, which results in an inefficient layout of the semiconductor device and increases the manufacturing process and manufacturing costs for connecting the external connection members.

[0006] Considering these factors, it is efficient to connect the field plate electrode below the source electrode. However, in this case, the field plate electrode must be exposed on the upper surface of the semiconductor substrate, which means that a region where the field plate electrode is formed is provided throughout the entire interior of the trench. This region then divides the gate electrode. Therefore, it is necessary to connect gate wiring individually to each of the divided gate electrodes in the peripheral region of the semiconductor device.

[0007] Here, the gate electrode and the gate wiring are connected via a hole formed in the interlayer insulating film, but there is a risk of the hole not completely reaching the gate electrode due to, for example, an insufficient amount of etching when forming the hole.Even if a hole is formed properly on one side of the divided gate electrode, if the hole on the other side of the divided gate electrode is not opened, the MOSFET using the other gate electrode will not function.

[0008] The main purpose of this application is to provide a technology that allows a MOSFET using a divided gate electrode to function normally even if the hole to the other side of the divided gate electrode is not opened, thereby improving the reliability of the semiconductor device.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A brief summary of a representative embodiment of the present invention will be given below.

[0011] In one embodiment, the semiconductor device comprises a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, a trench formed in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate and extending in a first direction in a planar view, a field plate electrode formed inside the trench at the bottom of the trench, a gate electrode formed inside the trench at the top of the trench and electrically insulated from the field plate electrode, an interlayer insulating film formed on the upper surface of the semiconductor substrate to cover the trench, a source electrode formed on the interlayer insulating film, a gate wiring formed on the interlayer insulating film to surround the source electrode in a planar view, and a first hole, a second hole, and a third hole formed in the interlayer insulating film, respectively. Here, the gate electrode includes a first end in a first direction and a second end located opposite the first end in the first direction. A portion of the field plate electrode is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, not only in the lower part of the trench but also in the upper part of the trench, and forms a contact portion of the field plate electrode. The first hole is formed to overlap the first end in a planar view, the second hole is formed to overlap the second end in a planar view, and the third hole is formed to overlap the contact portion in a planar view. The gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode, and the source electrode is embedded in the third hole and is electrically connected to the field plate electrode. The gate electrode includes a connecting portion connecting the gate electrode on the first end side and the gate electrode on the second end side inside the trench in which the contact portion is formed.

[0012] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate and extend in a first direction in a plan view; (c) after the step (b), forming a first insulating film inside the trench; (d) after the step (c), forming a field plate electrode so as to fill the inside of the trench via the first insulating film; (e) after the step (d), recessing another portion of the field plate electrode so that a portion of the field plate electrode remains as a contact portion; and (f) after the step (e), forming a trench such that the position of the upper surface of the trench is lower than the position of the upper surface of the field plate electrode. (g) after step (f), forming a gate insulating film on the semiconductor substrate inside the trench and forming a second insulating film on the upper surface and side surfaces of the field plate electrode exposed from the first insulating film; (h) after step (g), forming a gate electrode on the field plate electrode set back in step (e) so as to fill the inside of the trench; (i) after step (h), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench; (j) after step (i), forming a first hole, a second hole, and a third hole in the interlayer insulating film; and (k) after step (j), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film. Here, the gate electrode includes a first end in a first direction and a second end located opposite the first end in the first direction, and the contact portion is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side. Also, the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end in a plan view, and the third hole is formed to overlap the contact portion in a plan view.The gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode, and the source electrode is embedded in the third hole and is electrically connected to the field plate electrode. In addition, in the step (h), a coupling portion that connects the gate electrode on the first end side and the gate electrode on the second end side is formed as a part of the gate electrode inside the trench in which the contact portion is formed. [Effects of the Invention]

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is an enlarged plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 3] 1 is an enlarged plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 6] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a manufacturing process following FIG. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13]13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing the manufacturing process at the same timing as in FIG. 13. [Figure 15] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process following FIG. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 21 is a cross-sectional view showing a manufacturing process following FIG. 20. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) <Structure of semiconductor device> 1 to 5, a semiconductor device 100 according to a first embodiment will be described below. The semiconductor device 100 includes a MOSFET with a trench gate structure as a semiconductor element. In particular, the MOSFET according to the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode FP.

[0018] Fig. 1 is a plan view of a semiconductor chip that is a semiconductor device 100. Fig. 1 mainly shows a wiring pattern formed above a semiconductor substrate SUB. Fig. 2 is a plan view of a main part, enlarging a part of Fig. 1. Fig. 3 shows the structure below Fig. 2, and illustrates the structure of a trench gate formed in the semiconductor substrate SUB.

[0019] As shown in FIG. 1, most of the semiconductor device 100 is covered with a source electrode (fixed potential supply wiring) SE. A gate wiring GW is provided along the periphery of the semiconductor device 100 and surrounds the source electrode SE in a plan view. Although not shown here, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and gate wiring GW exposed in the opening become a source pad SP and a gate pad GP. External connection members such as wire bonding or clips (copper plates) are connected to the source pad SP and the gate pad GP, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0020] The semiconductor device 100 also includes a region 1A and regions 2A and 2A' surrounding the region 1A in a plan view. The region 1A is a cell region where main semiconductor elements such as multiple MOSFETs are formed. The regions 2A and 2A' are peripheral regions used for connecting the gate electrode GE to the gate wiring GW, etc.

[0021] The positional relationship of the holes CH1 to CH3 shown in Fig. 3 is the same as the positional relationship of the holes CH1 to CH3 shown in Fig. 2. The structure of region 2A' is obtained by inverting the structure of region 2A on the drawing. Therefore, like the CC cross section in Fig. 5, the cross-sectional structure of region 2A' is similar to the cross-sectional structure of region 2A.

[0022] 3, a plurality of trenches TR extend in the Y direction and are adjacent to each other in the X direction. The width of each trench TR in the X direction is, for example, not less than 1.5 μm and not more than 1.8 μm.

[0023] Inside the trench TR, a field plate (fixed potential electrode) electrode FP is formed at the bottom of the trench TR, and a gate electrode GE is formed at the top of the trench TR. Therefore, the gate electrode GE is exposed in Fig. 3. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0024] A part of the field plate electrode FP forms a contact portion FPa. The field plate electrode FP constituting the contact portion FPa is formed inside the trench TR in region 1A not only in the lower portion of the trench TR but also in the upper portion of the trench TR. Therefore, in FIG. 3, the contact portion FPa is exposed.

[0025] The gate electrode GE is divided into the region 2A side and the region 2A' side by the contact portion FPa. However, the gate electrode GE includes a connecting portion GEa. The connecting portion GEa connects the gate electrode GE on the region 2A side to the gate electrode GE on the region 2A' side inside the trench TR in which the contact portion FPa is formed. The connecting portion GEa is also formed on both side surfaces of the contact portion FPa in the X direction via the insulating film IF2.

[0026] The cross-sectional structure of the semiconductor device 100 will be described below with reference to Figures 4 and 5. Figure 4 is a cross-sectional view taken along lines AA and BB shown in Figure 3. Figure 5 is a cross-sectional view taken along lines CC and DD shown in Figure 3.

[0027] First, the basic structure of a MOSFET will be described using the AA cross section in FIG. 4. The semiconductor device 100 includes a semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked body consisting of an n-type silicon substrate and an n-type semiconductor layer will also be described as the semiconductor substrate SUB.

[0028] A plurality of trenches TR1 are formed in the semiconductor substrate SUB, each extending from the upper surface of the semiconductor substrate SUB to a predetermined depth. The depth of each trench is, for example, 5 μm or more and 7 μm or less. Inside the trenches TR, a field plate electrode FP is formed at the bottom of the trenches TR via an insulating film IF1. The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. An insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1. Furthermore, a gate insulating film GI is formed on the semiconductor substrate SUB inside the trenches TR.

[0029] A gate electrode GE is formed inside the trench TR above the trench TR. The gate electrode GE is electrically insulated from the field plate electrode FP by an insulating film IF2 and from the semiconductor substrate SUB by a gate insulating film GI. The gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB, with the gate insulating film GI and insulating film IF2 interposed therebetween.

[0030] The upper surface of the gate electrode GE is slightly recessed from the upper surface of the semiconductor substrate SUB. An insulating film IF3 is formed on part of the upper surface of the gate electrode GE so as to be in contact with the gate insulating film GI.

[0031] The gate electrode GE and the field plate electrode FP are made of, for example, a polycrystalline silicon film doped with n-type impurities. The insulating films IF1, IF2, IF3 and gate insulating film GI are made of, for example, a silicon oxide film.

[0032] The thickness of the insulating film IF1 is greater than the thicknesses of the insulating films IF2, IF3, and gate insulating film GI. The thickness of the insulating film IF1 is, for example, 400 nm or more and 600 nm or less. The thickness of each of the insulating film IF2 and the gate insulating film is, for example, 50 nm or more and 80 nm or less. The thickness of the insulating film IF3 is, for example, 30 nm or more and 80 nm or less.

[0033] A p-type body region PB is formed in the semiconductor substrate SUB on the upper surface side thereof so as to be shallower than the trench TR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0034] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film made by appropriately stacking these metal films.

[0035] An interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL may be a stacked film of a thin silicon oxide film and a thick silicon oxide film containing phosphorus (PSG: Phospho Silicate Glass film).

[0036] A hole CH1 is formed in the interlayer insulating film IL, the source region NS, and the body region PB. A high-concentration region PR is formed in the body region PB at the bottom of the hole CH1. The high-concentration region PR has a higher impurity concentration than the body region PB.

[0037] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is embedded in the hole CH1. The source electrode SE is electrically connected to the source region NS, the body region PB, and the heavily doped region PR, and supplies a source potential (fixed potential) to these regions.

[0038] 3 and the CC cross section in FIG. 5, the gate electrode GE includes a first end portion on the region 2A side and a second end portion on the region 2A' side in the Y direction. A hole CH2 is formed in the interlayer insulating film IL. The hole CH2 on the region 2A side is formed so as to overlap the first end portion of the gate electrode GE in a plan view, and the hole CH2 on the region 2A' side is formed so as to overlap the second end portion of the gate electrode GE in a plan view.

[0039] Note that the "first end of the gate electrode GE" described in this specification refers to a portion of the gate electrode GE where the hole CH2 in the region 2A is provided, and is a portion adjacent to the body region PB where the source region NS is not formed, as in the CC cross section of Fig. 5. Similarly, the "second end of the gate electrode GE" described in this specification refers to a portion of the gate electrode GE where the hole CH2 in the region 2A' is provided, and is a portion adjacent to the body region PB where the source region NS is not formed, as in the CC cross section of Fig. 5.

[0040] A gate wiring GW is formed on the interlayer insulating film IL. The gate wiring GW is buried inside the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE and supplies a gate potential to the gate electrode GE.

[0041] 3 and the BB cross section in Fig. 4 and the DD cross section in Fig. 5, a part of the field plate electrode FP forms a contact portion FPa of the field plate electrode FP. The contact portion FPa is formed not only in the lower portion of the trench TR but also in the upper portion of the trench TR, inside the trench TR located between the gate electrode GE on the region 2A side (first end side) and the gate electrode GE on the region 2A' side (second end side).

[0042] The position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. That is, the position of the upper surface of the insulating film IF1 in the AA cross section is located at a depth of 700 nm or more and 900 nm or less from the upper surface of the semiconductor substrate SUB. The position of the upper surface of the insulating film IF1 in the BB cross section is located at a depth of 600 nm or more and 800 nm or less from the upper surface of the semiconductor substrate SUB.

[0043] The position of the upper surface of the contact portion FPa is higher than the position of the upper surface of the semiconductor substrate SUB, and is located at a height of 200 nm or more and 400 nm or less from the upper surface of the semiconductor substrate SUB.

[0044] The coupling portion GEa is formed on both side surfaces of the contact portion FPa in the X direction via an insulating film IF2. The coupling portion GEa also extends in the Y direction and connects the gate electrode GE on the region 2A side (first end side) to the gate electrode GE on the region 2A' side (second end side). The gate electrode GE and the coupling portion GEa are made of an integrated n-type polycrystalline silicon film. Therefore, the gate potential is also supplied to the coupling portion GEa from the gate wiring GW. The coupling portion GEa is also covered with an insulating film IF3.

[0045] A hole CH3 is formed in the interlayer insulating film IL. The hole CH3 is formed so as to overlap the contact portion FPa in a plan view. A source electrode SE is buried inside the hole CH3. The source electrode SE is electrically connected to the field plate electrode FP and supplies a source potential to the field plate electrode FP.

[0046] The source electrode SE and the gate wiring GW are each made of, for example, a barrier metal film and a conductive film formed on the barrier metal film, where the barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0047] The source electrode SE and the gate wiring GW may be composed of a plug layer filling the holes CH1 to CH3 and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is composed of the barrier metal film and the conductive film. The plug layer is composed of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0048] <Main features of the first embodiment> In the first embodiment, the contact portion FPa of the field plate electrode FP is exposed from the semiconductor substrate SUB below the source electrode SE, and the source electrode SE and the contact portion FPa are connected via the hole CH3. Therefore, as shown in Fig. 3, the gate electrode GE is divided by the contact portion FPa, and therefore, in the region 2A and the region 2A', it is necessary to connect the divided gate electrode GE and the gate wiring GW via the hole CH2.

[0049] Here, if the amount of etching when forming the hole CH2 is insufficient, for example, the hole CH2 in either the region 2A or the region 2A' may become closed, which may cause a problem that the MOSFET using the gate electrode GE in either the region 2A or the region 2A' will no longer function.

[0050] To address this problem, in the first embodiment, a connecting portion GEa is provided on a side surface of the contact portion FPa. The connecting portion GEa connects the gate electrode GE on the region 2A side (first end side) to the gate electrode GE on the region 2A' side (second end side). Therefore, even if, for example, the hole CH2 in the region 2A is not opened and a gate potential is not directly supplied to the gate electrode GE on the region 2A side, the gate potential is supplied to the gate electrode GE on the region 2A side from the gate electrode GE on the region 2A' side via the connecting portion GEa. That is, the gate wiring GW in the first embodiment is in direct contact with at least one of the first end of the gate electrode GE on the region 2A side or the second end of the gate electrode GE on the region 2A' side.

[0051] As described above, according to the first embodiment, the MOSFET using the gate electrode GE can be made to function normally, and therefore the reliability of the semiconductor device 100 can be improved.

[0052] As another layout example of the gate wiring GW and source electrode SE, it is possible to make the gate wiring GW cross in the X direction from the gate pad GP and connect the gate electrode GE and the gate wiring GW at the position of the hole CH3. In this case, the source electrode SE is divided, and the contact portion FPa of the field plate electrode FP is connected to the source electrode SE at the position of the hole CH2 in each of the regions 2A and 2A'. This prevents the gate electrode GE from being divided.

[0053] However, in this example, it is necessary to connect separate external connection members to the divided source electrodes SE. This makes the layout of the semiconductor device inefficient, and increases the manufacturing process and manufacturing costs for connecting the external connection members. Therefore, it is more efficient to arrange the gate wiring GW around the outer periphery of the source electrode SE, as in the first embodiment.

[0054] <Method of manufacturing a semiconductor device> 6 to 21, a method for manufacturing the semiconductor device 100 will be described below. In the following description, cross sections AA and BB in Fig. 4 will be mainly used, but cross sections CC and DD in Fig. 5 will also be used as necessary.

[0055] 6, a semiconductor substrate SUB is prepared, which has an upper surface and a lower surface and an n-type drift region NV. As described above, the n-type semiconductor substrate SUB itself constitutes the drift region NV, but the drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P).

[0056] Next, a trench TR is formed in the semiconductor substrate SUB. To form the trench TR, first, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. Next, a resist pattern having an opening is formed on the silicon oxide film by photolithography. Next, the silicon oxide film is patterned by performing a dry etching process using the resist pattern as a mask. Next, the resist pattern is removed by ashing. Next, a dry etching process is performed using the silicon oxide film as a mask to form a trench TR in the semiconductor substrate SUB. Thereafter, the silicon oxide film is removed by, for example, a wet etching process using a solution containing hydrofluoric acid.

[0057] As shown in FIG. 7, first, a thermal oxidation process is performed to form an insulating film IF1 made of, for example, a silicon oxide film on the semiconductor substrate SUB, including the inside of the trench TR. The insulating film IF1 may be a stacked film of a thin silicon oxide film formed by the thermal oxidation process and a thick silicon oxide film formed by the CVD method. Next, a conductive film CF1 is formed on the semiconductor substrate SUB by, for example, the CVD method so as to fill the inside of the trench TR via the insulating film IF1. The conductive film CF1 is made of, for example, an n-type polycrystalline silicon film.

[0058] 8, the conductive film CF1 formed outside the trench TR is removed by polishing using a CMP (Chemical Mechanical Polishing) method. In this way, the field plate electrode FP is formed so as to fill the inside of the trench TR via the insulating film IF1.

[0059] As shown in Figure 9, a portion of the field plate electrode FP is selectively recessed (cross section AA) so that a portion of the field plate electrode FP remains as the contact portion FPa (cross section BB). First, a resist pattern RP1 is formed to selectively cover the region that will become the contact portion FPa. Next, dry etching is performed using the resist pattern RP1 as a mask. This selectively recesses the field plate electrode FP other than the contact portion FPa.

[0060] 10 and 11, the insulating film IF1 is recessed inside the trench TR so that the position of its upper surface is lower than the position of the upper surface of the field plate electrode FP. First, as shown in FIG. 10, using the resist pattern RP1 as a mask, a wet etching process is performed using, for example, a solution containing hydrofluoric acid. As a result, the insulating film IF1 on the semiconductor substrate SUB is removed except for the periphery of the contact portion FPa, and the insulating film IF1 inside the trench TR is recessed. Next, the resist pattern RP1 is removed by ashing.

[0061] 11, the entire semiconductor substrate SUB is subjected to a wet etching process using, for example, a solution containing hydrofluoric acid. As a result, the insulating film IF1 on the semiconductor substrate SUB is removed around the contact portion FPa, the insulating film IF1 formed on the side surface of the field plate electrode FP is receded, and the upper portion of the field plate electrode FP is exposed.

[0062] At this point, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. Moreover, by removing the insulating film IF1 on the semiconductor substrate SUB, the position of the upper surface of the contact portion FPa is higher than the position of the upper surface of the semiconductor substrate SUB.

[0063] By creating a step between the upper surface of the contact portion FPa and the upper surface of the insulating film IF1, the connecting portion GEa described below can be easily processed into a sidewall shape, and the connecting portion GEa can be easily left on both side surfaces of the contact portion FPa.

[0064] 12, a gate insulating film GI made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the trench TR by performing a thermal oxidation process. By this thermal oxidation process, an insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1.

[0065] Next, on the field plate electrode FP that was set back in the process of Fig. 9, a conductive film CF2 is formed on the semiconductor substrate SUB, including the inside of the trench TR, by, for example, a CVD method so as to fill the inside of the trench TR (cross section AA). Here, the conductive film CF2 is also formed inside the trench TR in which the contact portion FPa is formed (cross section BB). The conductive film CF2 is made of, for example, an n-type polycrystalline silicon film.

[0066] 13 and 14, an anisotropic dry etching process is performed on the conductive film CF2 to remove the conductive film CF2 formed outside the trench TR and to form a gate electrode GE inside the trench TR (cross sections AA, CC, and DD). By this anisotropic dry etching process, inside the trench TR in which the contact portion FPa is formed, the conductive film CF2 is processed into a sidewall shape as a connecting portion GEa, and the connecting portion GEa is formed as part of the gate electrode GE on both side surfaces of the contact portion FPa via the insulating film IF2 (cross section BB).

[0067] In addition, in order to completely remove the conductive film CF2 outside the trench TR, the anisotropic dry etching process is performed by over-etching, so the position of the upper surface of the gate electrode GE is slightly lower than the position of the upper surface of the semiconductor substrate SUB (cross section AA, cross section CC, cross section DD).

[0068] 15, an insulating film IF3 is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR. The insulating film IF3 is made of, for example, a silicon oxide film or a silicon nitride film.

[0069] 16, an anisotropic dry etching process is performed on the insulating film IF3. As a result, the insulating film IF3 remains on the upper surface of part of the gate electrode GE so as to be in contact with the gate insulating film GI (AA cross section), and the coupling portion GEa is covered with the insulating film IF3 (BB cross section).

[0070] As shown in FIG. 17, first, a p-type body region PB is formed in the semiconductor substrate SUB by introducing, for example, boron (B) into the upper surface side of the semiconductor substrate SUB by ion implantation. The body region PB is formed to be shallower than the trench TR. Next, after covering the periphery of the contact portion FPa with a resist pattern, an n-type source region NS is formed in the body region PB by introducing, for example, arsenic (As) into the body region PB by ion implantation. Next, the resist pattern is removed by ashing. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0071] Before the ion implantation of the source region NS and the body region PB, a thin silicon oxide film may be formed as a through film on the semiconductor substrate SUB. This through film may be removed after the ion implantation, or may be left as a part of the interlayer insulating film IL.

[0072] 18, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The interlayer insulating film IL may be a laminated film of a thin silicon oxide film formed by a CVD method and a PSG film formed by a coating method.

[0073] 19 and 20, holes CH1, CH2, and CH3 are formed in the interlayer insulating film IL. Although hole CH2 is not shown here, hole CH2 is formed in the same step as the step of forming hole CH3.

[0074] 19, a resist pattern RP2 having a pattern that opens the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, a dry etching process is performed using the resist pattern RP2 as a mask to form a hole CH1 in the interlayer insulating film IL, the source region NS, and the body region PB. The bottom of the hole CH1 is located in the body region PB.

[0075] Next, for example, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by ion implantation to form a p-type high concentration region PR. Thereafter, the resist pattern RP2 is removed by ashing.

[0076] 20, a resist pattern RP3 is formed on the interlayer insulating film IL, the resist pattern RP3 having a pattern that opens over the contact portion FPa, a first end portion of the gate electrode GE on the region 2A side, and a second end portion of the gate electrode GE on the region 2A' side. Next, a dry etching process is performed using the resist pattern RP3 as a mask, thereby forming holes CH3 and CH2 in the interlayer insulating film IL. The hole CH3 is formed so as to overlap the contact portion FPa in a planar view. The hole CH2 is formed so as to overlap the first end portion and the second end portion in a planar view. The resist pattern RP3 is then removed by ashing.

[0077] The order of the step of forming the hole CH1 and the step of forming the hole CH2 and the hole CH3 does not matter.

[0078] 21, a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL. First, a laminated film of a barrier metal film made of, for example, a titanium nitride film and a conductive film made of, for example, an aluminum film is formed on the interlayer insulating film IL by sputtering or CVD. Next, the laminated film is patterned to form the source electrode SE and the gate wiring GW.

[0079] The gate wiring GW is buried in the hole CH2 and electrically connected to the gate electrode GE. The source electrode SE is buried in the hole CH1 and the hole CH3 and electrically connected to the source region NS, the body region PB, the heavily doped region PR, and the field plate electrode FP.

[0080] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Parts of the protective film are opened to expose the regions of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0081] 4 and 5 is manufactured through the following steps. First, the lower surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface of the semiconductor substrate SUB by sputtering.

[0082] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0083] For example, in the above embodiment, a MOSFET with a trench gate structure is exemplified as the semiconductor element included in the semiconductor device 100, but the semiconductor element may be an IGBT. In that case, the n-type source region NS functions as an emitter region, the source electrode SE functions as an emitter electrode, the p-type body region PB functions as a base region, the n-type drain region ND functions as a collector region, and the drain electrode DE functions as a collector electrode. [Explanation of symbols]

[0084] 100 Semiconductor device 1A Area (Cell Area) 2A, 2A' area (outer area) CF1, CF2 conductive film CH1~CH3 hole DE drain electrode FP field plate electrode (fixed potential electrode) FPa contact part GE gate electrode GEa connection part GI gate insulating film GP Gate Pad GW Gate wiring IF1~IF3 insulating film IL Interlayer insulating film ND drain region NS Source Region NV drift region PB body region PR high concentration area SP sauce pad SUB Semiconductor substrate SW source wiring (fixed potential supply wiring) TR Trench

Claims

1. a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a trench formed in the semiconductor substrate to reach a predetermined depth from an upper surface of the semiconductor substrate and to extend in a first direction in a plan view; a field plate electrode formed inside the trench at a lower portion of the trench; a gate electrode formed inside the trench on an upper portion of the trench and electrically insulated from the field plate electrode; an interlayer insulating film formed on the upper surface of the semiconductor substrate so as to cover the trench; a source electrode formed on the interlayer insulating film; a gate wiring formed on the interlayer insulating film so as to surround the source electrode in a plan view; a first hole, a second hole, and a third hole formed in the interlayer insulating film; Equipped with the gate electrode includes a first end in a first direction and a second end located on the opposite side to the first end in the first direction; a portion of the field plate electrode is formed not only in the lower part of the trench but also in the upper part of the trench, inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, and forms a contact part of the field plate electrode; the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end in a plan view, the third hole is formed to overlap the contact portion in a plan view, the gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode; the source electrode is embedded in the third hole and is electrically connected to the field plate electrode; the gate electrode includes a coupling portion that connects the gate electrode on the first end side and the gate electrode on the second end side inside the trench in which the contact portion is formed, The semiconductor device, wherein the gate electrode including the coupling portion is made of an integrated polycrystalline silicon film.

2. 2. The semiconductor device according to claim 1, the contact portion and the coupling portion each extend in the first direction; The semiconductor device, wherein the coupling portion is formed on a side surface of the contact portion via an insulating film in a second direction that intersects with the first direction in a plan view.

3. 2. The semiconductor device according to claim 1, a body region formed in the semiconductor substrate on an upper surface side thereof so as to be shallower than the trench, and having a second conductivity type opposite to the first conductivity type; a source region of the first conductivity type formed in the body region; a drain electrode formed below the lower surface of the semiconductor substrate; a fourth hole formed in the interlayer insulating film, the source region, and the body region; Further provided with the source electrode is embedded in the fourth hole and is electrically connected to the source region and the body region.

4. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the gate wiring is in direct contact with at least one of the first end and the second end.

5. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate and to extend in a first direction in a plan view; (c) after the step (b), forming a first insulating film inside the trench; (d) after the step (c), forming a field plate electrode so as to fill the trench with the first insulating film therebetween; (e) after the step (d), selectively recessing a portion of the field plate electrode so that another portion of the field plate electrode is left as a contact portion; (f) after the step (e), recessing the first insulating film so that the position of the upper surface of the first insulating film inside the trench is lower than the position of the upper surface of the field plate electrode; (g) after the step (f), forming a gate insulating film on the semiconductor substrate inside the trench and forming a second insulating film on the upper surface and side surfaces of the field plate electrode exposed from the first insulating film; (h) after the step (g), forming a gate electrode on the field plate electrode recessed in the step (e) so as to fill the inside of the trench; (i) after the step (h), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the trench; (j) forming a first hole, a second hole, and a third hole in the interlayer insulating film after the step (i); (k) after the step (j), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film; Equipped with the gate electrode includes a first end in a first direction and a second end located on the opposite side to the first end in the first direction; the contact portion is formed inside the trench located between the gate electrode on the first end side and the gate electrode on the second end side, the first hole is formed to overlap the first end in a plan view, the second hole is formed to overlap the second end in a plan view, the third hole is formed to overlap the contact portion in a plan view, the gate wiring is embedded in the first hole and the second hole and is electrically connected to the gate electrode; the source electrode is embedded in the third hole and is electrically connected to the field plate electrode; A method for manufacturing a semiconductor device, wherein in the step (h), a connecting portion connecting the gate electrode on the first end side and the gate electrode on the second end side is formed as part of the gate electrode inside the trench in which the contact portion is formed.

6. 6. The method for manufacturing a semiconductor device according to claim 5, the contact portion and the coupling portion each extend in the first direction; The method for manufacturing a semiconductor device, wherein the coupling portion is formed on a side surface of the contact portion via the second insulating film in a second direction intersecting the first direction in a plan view.

7. 7. The method for manufacturing a semiconductor device according to claim 6, The step (h) (h1) forming a conductive film on the semiconductor substrate including the inside of the trench; (h2) performing an anisotropic etching process on the conductive film to form the gate electrode on the field plate electrode recessed in the step (e), and to form the coupling portion on a side surface of the contact portion via the second insulating film; The method for manufacturing a semiconductor device includes the steps of:

8. 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the conductive film is made of a polycrystalline silicon film.

9. 6. The method for manufacturing a semiconductor device according to claim 5, (l) after the step (h) and before the step (i), forming a body region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate so as to be shallower than the trench; (m) forming a source region of the first conductivity type in the body region after the step (l) and before the step (i); (n) forming fourth holes in the interlayer insulating film, the source region, and the body region after the step (i) and before the step (k); (o) after step (k), forming a drain electrode below the lower surface of the semiconductor substrate; Further provided with the source electrode is embedded in the fourth hole and is electrically connected to the source region and the body region.

10. 6. The method for manufacturing a semiconductor device according to claim 5, The method for manufacturing a semiconductor device, wherein the gate wiring is in direct contact with at least one of the first end portion and the second end portion.

11. 6. The method for manufacturing a semiconductor device according to claim 5, the gate electrode is electrically insulated from the field plate electrode by the second insulating film, and is also electrically insulated from the semiconductor substrate by the gate insulating film.

Images