Semiconductor device and manufacturing method thereof

Abstract

To improve the reliability of a semiconductor device and prevent a reduction in yield.SOLUTION: A hard mask (HM1) is formed on a top face of a semiconductor substrate SUB. A trench TR is formed in a semiconductor substrate SUB exposed from the hard mask (HM1). A gate insulating film GI1 is formed inside the trench TR. A conductive film (CF1) is formed on the gate insulating film GI1 and on the hard mask (HM1). The conductive film (CF1) on the hard mask (HM1) is removed, and a gate electrode GE1 is formed inside the trench TR. A cap film CP1 is formed on a top face of the gate electrode GE1. The hard mask (HM1) is removed. A gate insulating film GI2 is formed on the top face of the semiconductor substrate SUB. A conductive film CF2 is formed on the gate insulating film GI2 and on the cap film CP1. The conductive film CF2 on the cap film CP1 is removed, and a gate electrode GE2 is formed on the gate insulating film GI2.SELECTED DRAWING: Figure 62

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a trench gate MOSFET and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices that require high breakdown voltages use semiconductor elements such as trench-gate MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which have gate electrodes embedded inside trenches. Semiconductor devices have also been developed that use trench-gate MOSFETs as output circuits and planar MOSFETs as control circuits that control the gate potential of the output circuits. These semiconductor devices are called intelligent power devices (IPDs).

[0003] One form of semiconductor device that makes up an IPD is a semiconductor module in which a semiconductor chip for an output circuit and a semiconductor chip for controlling a control circuit are mounted in a single package. Another form is where the MOSFETs that make up the output circuit and the control circuit are formed on the same semiconductor substrate and mounted together on a single semiconductor chip.

[0004] For example, Patent Documents 1 to 3 disclose semiconductor devices as IPDs in which MOSFETs constituting an output circuit and a control circuit are formed on the same semiconductor substrate. The IPD in Patent Document 1 also discloses a technique for forming the gate electrode of a trench-gate MOSFET and the gate electrode of a planar MOSFET in separate manufacturing processes. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-87133 [Patent Document 2] Japanese Patent Application Publication No. 2019-145537 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-207787 Summary of the Invention [Problem to be solved by the invention]

[0006] Forming the MOSFETs constituting the output circuit and the control circuit on the same semiconductor substrate is advantageous in terms of reducing packaging costs and miniaturizing the semiconductor device. However, the trench-gate MOSFET for the output circuit and the planar-type MOSFET for the control circuit have different device structures and different required characteristics, which tends to complicate the manufacturing process. Therefore, defects that do not occur separately may occur in the manufacturing process for the trench-gate MOSFET and the manufacturing process for the planar-type MOSFET, resulting in problems such as reduced reliability and reduced yield of the semiconductor device.

[0007] The main object of the present application is to provide a technology that can improve the reliability of semiconductor devices and suppress a decrease in yield when trench-gate MOSFETs and planar MOSFETs are formed on the same semiconductor substrate. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief summary of a representative embodiment of the present invention will be given below.

[0009] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a first hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate; (c) after the step (b), forming a trench in the semiconductor substrate exposed from the first hard mask; (d) after the step (c), forming a first gate insulating film inside the trench; (e) after the step (d), forming a first conductive film on the first gate insulating film and on the first hard mask; and (f) after the step (e), performing an anisotropic etching process on the first conductive film to remove the first conductive film on the first hard mask and to remove the first conductive film from the first hard mask. (g) after step (f), forming a first gate electrode inside the trench so as to fill the inside of the trench with a gate insulating film therebetween; (h) after step (g), removing the first hard mask; (i) after step (h), forming a second gate insulating film on the upper surface of the semiconductor substrate; (j) after step (i), forming a second conductive film on the second gate insulating film and the first cap film; and (k) after step (j), patterning the second conductive film to remove the second conductive film on the first cap film and form a second gate electrode on the upper surface of the semiconductor substrate with the second gate insulating film therebetween.

[0010] A semiconductor device according to one embodiment has a first region in which a first MOSFET for an output circuit is formed and a second region in which a second MOSFET for a control circuit that controls a gate potential of the first MOSFET is formed. The semiconductor device includes: a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; a trench formed in the semiconductor substrate in the first region from the upper surface of the semiconductor substrate to a predetermined depth; a first gate insulating film formed on side and bottom surfaces of the trench; a first gate electrode formed inside the trench to fill the trench with the first gate insulating film interposed therebetween; a first insulating film formed so as to cover an upper surface of the first gate electrode; a second gate insulating film formed on the upper surface of the semiconductor substrate in the second region; and a second gate electrode formed on the second gate insulating film. The first MOSFET has the first gate insulating film, the first gate electrode, and the first insulating film, the second MOSFET has the second gate insulating film and the second gate electrode, the first gate electrode is formed of a first polycrystalline silicon film into which an impurity has been introduced, the first insulating film is a silicon oxide film formed by thermally oxidizing an upper surface of the first polycrystalline silicon film, the thickness of the first insulating film is thicker than the thicknesses of the first gate insulating film and the second gate insulating film, and the upper surface of the semiconductor substrate is located within the thickness range of the first insulating film. [Effects of the Invention]

[0011] According to one embodiment, the reliability of the semiconductor device can be improved and a decrease in yield can be suppressed. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 3] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 6] 1 is an enlarged plan view of a part of a semiconductor device according to a first embodiment. [Figure 7] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 8] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 9] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 10] 9 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 8. [Figure 11] 10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 12] 11A to 11C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 13] 12 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 14] 13 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 15] 14 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 13. [Figure 16] 15 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 14. [Figure 17] 16 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 15. [Figure 18] 17A to 17C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 16. [Figure 19] 18 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 17. [Figure 20] 19 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 18. [Figure 21] 19A to 19C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. [Figure 22] 21 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 20. [Figure 23] 22 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 21. [Figure 24] 23 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 22. [Figure 25] 24 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 23. [Figure 26] 25 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 24. [Figure 27] 26 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 25. [Figure 28] 27 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 26. [Figure 29] 28 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 27. [Figure 30] 29 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 28. [Figure 31] 30 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 29. [Figure 32] 31 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 30. [Figure 33] 32 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 31. [Figure 34] 33 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 32. [Figure 35] 34 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 33. [Figure 36] 35 is a cross-sectional view showing a manufacturing process of the semiconductor device following FIG. 34. [Figure 37] 36 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 35. [Figure 38] 37 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 36. [Figure 39] 38 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 37. [Figure 40] 39 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 38. [Figure 41] 39. FIG. 40 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. [Figure 42] 41 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 40. [Figure 43]42 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 41. [Figure 44] 43 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 42. [Figure 45] 44 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 43. [Figure 46] 45 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 44. [Figure 47] 46 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 45. [Figure 48] 47 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 46. [Figure 49] 48 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 47. [Figure 50] 49 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 48. [Figure 51] 49. FIG. 50 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. [Figure 52] 51 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 50. [Figure 53] 52 is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 51. [Figure 54] 2 is a cross-sectional view of a main part illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. [Figure 55] 1A to 1C are cross-sectional views of a main part illustrating a manufacturing process of a semiconductor device in Study Example 1. [Figure 56] FIG. 55 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 54. [Figure 57] 56 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 55. [Figure 58] FIG. 57 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 56. [Figure 59] FIG. 58 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 57. [Figure 60] FIG. 59 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 58. [Figure 61] FIG. 60 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 59. [Figure 62] 61 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device following FIG. 60. [Figure 63] 62 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device following FIG. 61. [Figure 64] 10A to 10C are cross-sectional views of a main part illustrating a manufacturing process of a semiconductor device in Study Example 2. [Figure 65] 10A to 10C are cross-sectional views of a main part illustrating a manufacturing process of a semiconductor device in Study Example 3. [Figure 66] 1 is an enlarged plan view of a part of a semiconductor device according to a first embodiment. [Figure 67] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 68] 1 is a graph showing experimental data obtained by the inventors of the present application. [Figure 69] 1 is an enlarged plan view of a part of a semiconductor device according to a first embodiment. [Figure 70] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 71] 10A to 10C are cross-sectional views of a main part illustrating a manufacturing process of a semiconductor device according to a second embodiment. [Figure 72] 10A to 10C are cross-sectional views of a main part illustrating a manufacturing process of a semiconductor device in Study Example 4. [Figure 73] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device in accordance with a second embodiment. [Figure 74] FIG. 74 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 73. [Figure 75] FIG. 75 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 74. [Figure 76] FIG. 76 is a cross-sectional view of a main part showing a manufacturing process of the semiconductor device subsequent to FIG. 75. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] Furthermore, the X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the up-down direction, height direction, or thickness direction of a structure. Furthermore, expressions such as "plan view" or "plan view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0015] (Embodiment 1) <Structure of semiconductor device> 1 to 7, a semiconductor device 100 according to a first embodiment will be described below. The semiconductor device 100 is a semiconductor chip in which an output circuit for driving a load external to the semiconductor device 100 and a control circuit for controlling the gate potential of the output circuit are formed on the same semiconductor substrate SUB, and is an IPD. The load is, for example, various electronic components mounted on a vehicle.

[0016] Fig. 1 is a plan view of a semiconductor chip that is a semiconductor device 100. As shown in Fig. 1, the semiconductor device 100 has a region 1A where MOSFETs for an output circuit are formed, and regions 2A to 4A where semiconductor elements such as MOSFETs and resistor elements for a control circuit are formed. The layout of regions 2A to 4A is not limited to the example in Fig. 1 and can be freely designed as appropriate.

[0017] 1 also shows a plurality of pads PADs and source pads PADs that are part of the wiring M3 on the top layer. The source pads PADs are provided above the region 1A and serve as output terminals of the output circuit. The plurality of pads PADs are provided around the regions 2A to 4A. Various signals and ground potentials from outside the semiconductor device 100 are transmitted to the control circuit via the plurality of pads PADs.

[0018] Fig. 2 shows an n-type MOSFET 1Qn formed in region 1A, and an n-type MOSFET 2Qn and a p-type MOSFET 2Qp formed in region 2A. MOSFET 1Qn is a trench-gate MOSFET, and MOSFETs 2Qn and 2Qp are planar MOSFETs. Fig. 4 also shows the wiring structure formed above MOSFETs 1Qn, 2Qn, and 2Qp.

[0019] 3 shows an n-type MOSFET 3Qn and a p-type MOSFET 3Qp formed in region 3A, and a resistor element RS formed in region 4A. MOSFETs 3Qn and 3Qp are planar MOSFETs. Fig. 5 shows a wiring structure formed above MOSFETs 3Qn, 3Qp, and resistor element RS.

[0020] 2 representatively shows only a portion of the structure of region 1A, and Fig. 6 and Fig. 7 show the specific structure of region 1A. Fig. 6 is a plan view showing multiple MOSFETs 1Qn. Fig. 7 is a cross-sectional view taken along lines AA and BB shown in Fig. 6.

[0021] <MOSFET1Qn in area 1A> First, the structure of the MOSFET 1Qn in the region 1A will be described with reference to FIGS.

[0022] As will be described below, the MOSFET 1Qn includes a gate insulating film GI1, a gate electrode GE1, a body region PB, a source region NS, a heavily doped diffusion region PR, a column region PC, and a cap film CP1. The MOSFET 1Qn also includes, as a drain, a drain region ND and a drift region NV (a semiconductor substrate SUB in the region 1A).

[0023] As shown in FIG. 6, a plurality of trenches TR are formed in the semiconductor substrate SUB. The plurality of trenches TR are formed in a stripe shape, each extending in the Y direction and adjacent to one another in the X direction. A gate electrode GE1 is formed inside the trench TR. A plurality of holes CH1 are arranged along the extension direction of the trench TR while being spaced apart from one another. The source electrode SE is electrically connected to the source region NS and the body region PB via the hole CH1. The hole CH2 is arranged on the gate electrode GE1 near the end of the trench TR. The gate wiring GW is electrically connected to the gate electrode GE1 via the hole CH2.

[0024] As shown in FIGS. 2 and 7, semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB is made of silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked body consisting of an n-type silicon substrate and an n-type semiconductor layer will also be described as the semiconductor substrate SUB.

[0025] A trench TR is formed in the semiconductor substrate SUB on the upper surface side thereof, reaching a predetermined depth from the upper surface of the semiconductor substrate SUB. The depth of the trench TR is, for example, 0.5 μm or more and 2 μm or less. A gate insulating film GI1 is formed inside the trench TR (on the side and bottom surfaces of the trench TR). The gate insulating film GI1 is, for example, a silicon oxide film, and has a thickness of, for example, 10 nm or more and 20 nm or less.

[0026] A gate electrode GE1 is formed inside the trench TR so as to fill the inside of the trench TR via the gate insulating film GI1. The gate electrode GE1 is, for example, a polycrystalline silicon film doped with n-type impurities. A cap film CP1 is formed on the upper surface of the gate electrode GE1 so as to cover the upper surface of the gate electrode GE1. The cap film CP1 is an insulating film, and is a silicon oxide film formed by thermally oxidizing the upper surface of the gate electrode GE1 (polycrystalline silicon film). The thickness of the cap film CP1 is thicker than the thickness of the gate insulating film GI1 and the thickness of gate insulating films GI2 and GI3 described below, and is, for example, 40 nm or more and 60 nm or less.

[0027] A p-type body region PB is formed in the semiconductor substrate SUB on the upper surface side thereof so as to be shallower than the depth of the trench TR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0028] A p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB. As shown in FIG. 6, the plurality of column regions PC are provided at equal intervals in the extension direction (Y direction) of the trench TR. The plurality of column regions PC are also arranged in a staggered pattern. By two-dimensionally arranging the p-type column regions PC in the n-type drift region NV, the periphery of the column region PC can be depleted, thereby improving the breakdown voltage. Furthermore, as in the column regions PC1 to PC3, an equilateral triangle is formed by lines connecting the centers of the plurality of column regions PC. This makes it easier to uniformize the depletion layer extending from each column region PC, and makes it easier to achieve sufficient depletion between each column region PC.

[0029] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film in which these metal films are appropriately laminated. The drain region ND and the drain electrode DE are formed across regions 1A to 4A.

[0030] The drain region ND and the semiconductor substrate SUB (drift region NV) form the drain of the MOSFET 1Qn. A power supply potential is supplied as a drain potential to the drain region ND and the semiconductor substrate SUB from outside the semiconductor device 100 via the drain electrode DE.

[0031] When the semiconductor substrate SUB is a laminate of an n-type silicon substrate and an n-type semiconductor layer, the n-type silicon substrate may function as the drain region ND. In this case, the drain region ND does not have to be formed. That is, the formation of the drain region ND is not essential.

[0032] A silicon nitride film SN1 and an interlayer insulating film IL1 are formed on the upper surface of the semiconductor substrate SUB so as to cover the gate electrode GE1. The interlayer insulating film IL1 is formed on the silicon nitride film SN1. The silicon nitride film SN1 has a thickness of, for example, 10 nm or more and 20 nm or less. The interlayer insulating film IL1 has a thickness of, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL1 is, for example, a stacked film of a thin silicon oxide film and a thick silicon oxide film containing boron and phosphorus (BPSG: Boro Phospho Silicate Glass film).

[0033] A hole CH1 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB. The bottom of the hole CH1 is located inside the body region PB. A high-concentration diffusion region PR is formed in the body region PB near the bottom of the hole CH1. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. Furthermore, a hole CH2 is formed in the interlayer insulating film IL1 and the silicon nitride film SN1 so as to penetrate the cap film CP1 and reach the gate electrode GE1.

[0034] A plug PG is formed inside each of the holes CH1 and CH2. A plurality of wirings M1 is formed on the interlayer insulating film IL1. In the region 1A, some of the plurality of wirings M1 function as a source electrode SE and a gate wiring GW. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via the plug PG inside the hole CH1. The gate wiring GW is electrically connected to the gate electrode GE1 via the plug PG inside the hole CH2.

[0035] The gate wiring GW is electrically connected to semiconductor elements such as MOSFETs 2Qn, 2Qp, 3Qn, and 3Qp and resistor element RS via other wirings such as wiring M1 in regions 2A to 4A. Therefore, the potential supplied to gate electrode GE1 is controlled by control circuits in regions 2A to 4A including the semiconductor elements.

[0036] The plug PG is composed of a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0037] The wiring M1 is composed of a stacked film of a first barrier metal film, a conductive film formed on the first barrier metal film, and a second barrier metal film formed on the conductive film. The first barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum film or an aluminum alloy film doped with copper or silicon. The second barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film.

[0038] <MOSFETs 2Qn and 2Qp in area 2A> The structure of the MOSFETs 2Qn and 2Qp in the region 2A will be described below with reference to FIG.

[0039] As will be described below, the MOSFET 2Qn includes a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, and a well region PW1. The source and drain regions of the MOSFET 2Qn are formed by impurity regions N1 and N2.

[0040] The MOSFET 2Qp also includes a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, and a well region NW1. The source and drain regions of the MOSFET 2Qp are formed of impurity regions P1 and P2.

[0041] A p-type well region HPW is formed in the semiconductor substrate SUB in the region 2 A and the region 3 A. The well region HPW is provided mainly to separate the well region NW1 in the region 2 A and the well region NW2 in the region 3 A from the n-type semiconductor substrate SUB.

[0042] A p-type well region PW1 and an n-type well region NW1 are formed in the well region HPW of the region 2A. A gate insulating film GI2 is formed on each of the well regions PW1 and NW1. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness of, for example, 10 nm or more and 20 nm or less. A gate electrode GE2 is formed on the gate insulating film GI2.

[0043] The MOSFETs 2Qn and 2Qp in region 2A are provided for high-speed operation and operate at a lower operating voltage than the MOSFET 1Qn in region 1A. Therefore, the material contained in gate electrode GE2 is different from the material contained in gate electrode GE1, and has a lower sheet resistance than the material contained in gate electrode GE1. Furthermore, gate electrode GE2 is formed by a different manufacturing process than gate electrode GE1. Gate electrode GE2 is made of, for example, a stacked film of a polycrystalline silicon film doped with n-type impurities and a tungsten silicide film formed on the polycrystalline silicon film.

[0044] The thickness of the polycrystalline silicon film is 60 nm or more and 100 nm or less, and the thickness of the tungsten silicide film is 80 nm or more and 120 nm or less. The impurity concentration of the polycrystalline silicon film included in the gate electrode GE2 is the same as or higher than the impurity concentration of the polycrystalline silicon film included in the gate electrode GE1.

[0045] A cap film CP2 is formed on the upper surface of the gate electrode GE2. The cap film CP2 is an insulating film, such as a silicon oxide film. The thickness of the cap film CP2 is, for example, 100 nm or more and 150 nm or less. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE2. The sidewall spacers SW are, for example, silicon oxide films.

[0046] In the well region PW1, an n-type impurity region N1 and an n-type impurity region N2 are formed. The well region PW1, sandwiched between the pair of impurity regions N1 and located below the gate electrode GE2, serves as the channel region of the MOSFET 2Qn. The impurity region N2 is formed to a deeper position than the impurity region N1 and has a higher impurity concentration than the impurity region N1.

[0047] In the well region NW1, a p-type impurity region P1 and a p-type impurity region P2 are formed. The well region NW1, sandwiched between the pair of impurity regions P1 and located below the gate electrode GE2, serves as the channel region of the MOSFET 2Qp. The impurity region P2 is formed to a deeper position than the impurity region P1 and has a higher impurity concentration than the impurity region P1.

[0048] Each of the regions 1A to 4A is partitioned by an element isolation portion LOC formed in the semiconductor substrate SUB. The element isolation portion LOC is, for example, a silicon oxide film having a thickness of, for example, 300 nm or more and 600 nm or less. The element isolation portion LOC is also formed at the boundary between MOSFET 2Qn and MOSFET 2Qp in region 2A, and at the boundary between MOSFET 3Qn and MOSFET 3Qp in region 3A.

[0049] <MOSFETs 3Qn and 3Qp in area 3A> The structure of the MOSFETs 3Qn and 3Qp in the region 3A will be described below with reference to FIG.

[0050] As described below, MOSFET 3Qn includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region PW2, and an element isolation portion LOC. The source region of MOSFET 3Qn is formed by impurity regions N1 and N2. The drain region of MOSFET 3Qn is formed by well region NW2 and impurity region N2.

[0051] The MOSFET 3Qp also includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region NW3, and an element isolation portion LOC. The source region of the MOSFET 3Qp is formed by impurity regions P1 and P2. The drain region of the MOSFET 3Qp is formed by well region PW3 and impurity region P2.

[0052] A p-type well region PW2 and an n-type well region NW2 are formed in the well region HPW of the region 3A. A gate insulating film GI3 is formed on the well region PW2 and the well region NW2. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE3.

[0053] Furthermore, an element isolation portion LOC is formed in a part of the well region NW2. A part of the gate electrode GE3 is formed on the element isolation portion LOC, and an end of the gate electrode GE3 on the drain region side is located on the element isolation portion LOC.

[0054] The MOSFETs 3Qn and 3Qp in region 3A are driven at a higher operating voltage than the MOSFETs 2Qn and 2Qp in region 2A. For example, a potential of about 5 V is applied to the drain region of MOSFET 2Qn in region 2A, while a potential of 10 V or more is applied to the drain region of MOSFET 3Qn in region 3A. Therefore, in order to alleviate electric field concentration in the drain region, an element isolation portion LOC is provided under the gate electrode GE3 on the drain region side of MOSFET 3Qn.

[0055] An n-type impurity region N1 and an n-type impurity region N2 are formed in the well region PW2. An n-type impurity region N2 is formed in the well region NW2. The well region PW2, which is sandwiched between the impurity region N1 and the well region NW2 in the well region PW2 and is located below the gate electrode GE3, becomes the channel region of the MOSFET 3Qn.

[0056] An n-type well region NW3 and a p-type well region PW3 are formed in the semiconductor substrate SUB in region 3A. A gate insulating film GI3 is formed on the well region NW3 and the well region PW3. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE3.

[0057] In addition, in the MOSFET 3Qp, an element isolation portion LOC is formed in a part of the well region NW3 in order to reduce electric field concentration in the drain region. A part of the gate electrode GE3 is formed on the element isolation portion LOC, and the end of the gate electrode GE3 on the drain region side is located on the element isolation portion LOC.

[0058] A p-type impurity region P1 and a p-type impurity region P2 are formed in the well region NW3. A p-type impurity region P2 is formed in the well region PW3. The well region NW3, which is sandwiched between the impurity region P1 and the well region PW3 in the well region NW3 and is located below the gate electrode GE3, becomes the channel region of the MOSFET 3Qp.

[0059] The gate insulating film GI3, gate electrode GE3, cap film CP3, and sidewall spacers SW in region 3A are formed in the same manufacturing steps as the gate insulating film GI2, gate electrode GE2, cap film CP2, and sidewall spacers SW in region 2A, respectively, and therefore their materials and thicknesses are the same as those described for the MOSFETs 2Qn and 2Qp in region 2A.

[0060] <Resistance element RS in region 4A> The structure of the resistor element RS in the region 4A will be described below with reference to FIG.

[0061] An element isolation portion LOC is formed in the semiconductor substrate SUB in the region 4A. An insulating film IF4 is formed on the element isolation portion LOC. The insulating film IF4 is, for example, a silicon oxide film and has a thickness of, for example, 50 nm or more and 70 nm or less.

[0062] A resistor element RS is formed on the insulating film IF4. The resistor element RS needs to be designed to obtain a high resistance value. Therefore, the material contained in the resistor element RS has a sheet resistance higher than that of the material contained in the gate electrodes GE1 to GE3. The resistor element RS is formed in a manufacturing process different from that of the gate electrodes GE1 to GE3. The resistor element RS is, for example, a polycrystalline silicon film doped with p-type impurities, and has a thickness of, for example, 120 nm or more and 180 nm or less.

[0063] <Wiring structure> The wiring structure formed above the MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, 3Qp and resistor RS will be described below with reference to FIGS.

[0064] In regions 2A to 4A, a silicon nitride film SN1 and an interlayer insulating film IL1 are formed on the upper surface of the semiconductor substrate SUB so as to cover the gate electrodes GE2 and GE3 and the resistor element RS. The material contained in the interlayer insulating film IL1 is the same as that described for region 1A.

[0065] Here, in the MOSFETs 2Qp and 3Qp, positive charges may be trapped in the gate insulating films GI2 and GI3, which may cause NBTI degradation. Covering the MOSFETs 2Qp and 3Qp with the silicon nitride film SN1 can suppress the intrusion of positive charges into the gate insulating films GI2 and GI3, thereby improving the reliability of the semiconductor device 100.

[0066] In regions 2A to 4A, a plurality of holes CH3 are formed in the interlayer insulating film IL1 and the silicon nitride film SN1. A plug PG is formed inside each of the plurality of holes CH3. A plurality of wirings M1 are formed on the interlayer insulating film IL1. The materials contained in the plugs PG and the wirings M1 are the same as those described for region 1A.

[0067] The impurity regions N2, P2 and the resistor element RS are electrically connected to a plurality of wirings M1 via plugs PG inside the holes CH3. Although not shown, the gate electrodes GE2, GE3 are also electrically connected to the wirings M1 via plugs PG inside the holes CH3.

[0068] In the regions 1A to 4A, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the multiple wirings M1. The interlayer insulating film IL2 is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL2 is, for example, not less than 650 nm and not more than 850 nm.

[0069] A plurality of vias V1 connected to a plurality of wirings M1 are formed in the interlayer insulating film IL2. The vias V1 are formed by filling contact holes formed in the interlayer insulating film IL2 with a laminated film of a barrier metal film and a conductive film. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0070] A plurality of wirings M2 connected to a plurality of vias V1 are formed on the interlayer insulating film IL2. The material contained in the wirings M2 is the same as that of the wirings M1. An interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the plurality of wirings M2. The material contained in the interlayer insulating film IL3 is the same as that of the interlayer insulating film IL2. The thickness of the interlayer insulating film IL3 is, for example, not less than 650 nm and not more than 850 nm. A plurality of vias V2 connected to the plurality of wirings M2 are formed in the interlayer insulating film IL3. The configuration of the vias V2 is the same as that of the vias V1.

[0071] A plurality of wirings M3 connected to the plurality of vias V2 are formed on the interlayer insulating film IL3. The wirings M3 are composed of a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film. The conductive film is, for example, an aluminum film or an aluminum alloy film with copper or silicon added. The thickness of the wirings M1 and M2 is, for example, 300 nm to 600 nm, but the thickness of the wiring M3 is sufficiently thicker than the thickness of the wirings M1 and M2, for example, 3 μm to 5 μm.

[0072] A protective film PVF is formed on the interlayer insulating film IL3 so as to cover the wirings M3. The protective film PVF is, for example, a polyimide film. The thickness of the protective film PVF is, for example, 4 μm or more and 7 μm or less.

[0073] An opening OP1 and a plurality of openings OP2 are formed in the protective film PVF on the wiring M3 so that portions of the plurality of wirings M3 are exposed (see FIGS. 67 and 70). The portions of the wirings M3 exposed in the opening OP1 form source pads PADs for connection to external connection members BW. Furthermore, the portions of the wirings M3 exposed in the plurality of openings OP2 form a plurality of pads PAD for connection to external connection members BW.

[0074] The external connection members BW are, for example, bonding wires made of gold or copper, or clips made of copper plate, etc. By connecting the external connection members BW to the source pads PADs and the multiple pads PADs, the semiconductor device 100 is electrically connected to another semiconductor chip or a wiring board, etc.

[0075] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device 100 will be described below mainly with reference to FIGS.

[0076] 8 and 9, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. As described above, the n-type semiconductor substrate SUB itself constitutes the drift region NV, but the drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P).

[0077] Next, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB, for example, by thermal oxidation. Next, a silicon nitride film is formed on the silicon oxide film, for example, by CVD (Chemical Vapor Deposition). Next, the silicon oxide film and the silicon nitride film are patterned to form a hard mask HM1 that selectively covers the upper surface of the semiconductor substrate SUB. Next, a thermal oxidation process is performed on the semiconductor substrate SUB, thereby forming an element isolation portion LOC made of a silicon oxide film in the semiconductor substrate SUB that is exposed from the hard mask HM1. Thereafter, the hard mask HM1 is removed by isotropic etching.

[0078] 10 and 11, first, a through film TH1 made of a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB by thermal oxidation. Next, ions are selectively implanted from the upper surface side of the semiconductor substrate SUB so as to pass through the through film TH1, thereby forming p-type well regions HPW in the semiconductor substrate SUB in regions 2A and 3A. In this ion implantation, boron (B), for example, is used as an impurity.

[0079] Next, the well region HPW is subjected to a heat treatment. This heat treatment is performed in a nitrogen atmosphere under conditions such as 1150°C and 90 minutes. This heat treatment causes the impurities contained in the well region HPW to diffuse into the semiconductor substrate SUB and become activated.

[0080] Because the heat treatment takes a relatively long time, if the heat treatment is performed after the formation of the gate insulating film GI1, stress will be generated from the gate insulating film GI1 into the semiconductor substrate SUB, and this stress may cause crystal defects in the semiconductor substrate SUB. Furthermore, the hard mask HM1 and a hard mask HM2 described below contain a silicon nitride film, and if the heat treatment is performed with the silicon nitride film formed on the upper surface of the semiconductor substrate SUB, the stress of the silicon nitride film may also cause crystal defects in the semiconductor substrate SUB.

[0081] That is, the heat treatment is preferably performed before the trench TR is formed and before the gate insulating film GI1 is formed, and is preferably performed in a state where the silicon nitride film is not formed on the upper surface of the semiconductor substrate SUB.

[0082] 12 and 13, first, an insulating film IF1 made of a silicon nitride film is formed on the through film TH1 by, for example, a CVD method. Next, an insulating film IF2 made of a silicon oxide film is formed on the insulating film IF1 by, for example, a CVD method. Next, a part of the region 1A is selectively opened, and a resist pattern RP1 is formed on the insulating film IF2 so as to cover the regions 2A to 4A.

[0083] As shown in FIGS. 14 and 15, first, an anisotropic etching process is performed using the resist pattern RP1 as a mask to pattern the through film TH1, the insulating film IF1, and the insulating film IF2. This forms a hard mask HM2. Next, the resist pattern RP1 is removed by ashing. Next, an anisotropic etching process is performed using the hard mask HM2 as a mask to form trenches TR in the semiconductor substrate SUB exposed from the hard mask HM2. Thereafter, the semiconductor substrate SUB is cleaned. At this time, the insulating film IF2 is removed, but the through film TH1 and the insulating film IF1 remain as the hard mask HM2.

[0084] As shown in FIGS. 16 and 17, first, a gate insulating film GI1 is formed inside the trench TR by thermal oxidation. Next, a conductive film CF1 is formed on the gate insulating film GI1 and the hard mask HM2 by, for example, CVD. The conductive film CF1 is a polycrystalline silicon film. Next, impurities such as phosphorus (P) are ion-implanted into the conductive film CF1 to convert the conductive film CF1 into an n-type polycrystalline silicon film.

[0085] 18 and 19, an anisotropic etching process is performed on the conductive film CF1. As a result, the conductive film CF1 on the hard mask HM2 is removed, and a gate electrode GE1 is formed inside the trench TR so as to fill the inside of the trench TR via the gate insulating film GI1.

[0086] 20 and 21, a portion of the gate electrode GE1 is oxidized by thermal oxidation. As a result, a cap film CP1 made of an insulating film is formed on the upper surface of the gate electrode GE1. That is, the cap film CP1 is a silicon oxide film formed by thermally oxidizing the upper surface of a polycrystalline silicon film.

[0087] 22 and 23, the hard mask HM2 is removed. First, the insulating film IF1 is removed by isotropic etching using an aqueous solution containing phosphoric acid. Next, a cleaning process is performed using an aqueous solution containing hydrofluoric acid to remove the through film TH1.

[0088] As shown in FIGS. 24 and 25, impurity regions are selectively formed in the semiconductor substrate SUB in the regions 1A to 3A on the upper surface side of the semiconductor substrate SUB using photolithography and ion implantation.

[0089] In region 1A, a p-type body region PB is formed in the semiconductor substrate SUB so as to be shallower than the depth of the trench TR. In region 2A, a p-type well region PW1 and an n-type well region NW1 are formed in the semiconductor substrate SUB. Note that the well region PW1 and the well region NW1 are formed in the well region HPW. In region 3A, a p-type well region PW2, an n-type well region NW2, a p-type well region PW3, and an n-type well region NW3 are formed in the semiconductor substrate SUB. Note that the well region PW2 and the well region NW2 are formed in the well region HPW.

[0090] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB. After these ion implantations, the through film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0091] 26 and 27, first, a gate insulating film made of a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB by thermal oxidation. Here, the gate insulating film formed on the well regions PW1 and NW1 in region 2A is shown as gate insulating film GI2. Also, the gate insulating film formed on the well regions PW2, NW2, PW3, and NW3 in region 3A is shown as gate insulating film GI3.

[0092] Next, a conductive film CF2 is formed on the gate insulating film GI2, the gate insulating film GI3, and the cap film CP1. The material contained in the conductive film CF2 has a sheet resistance higher than that of the material contained in the conductive film CF1 (gate electrode GE1). The conductive film CF2 is, for example, a stacked film of an n-type polycrystalline silicon film formed by a CVD method and a tungsten silicide film formed by a CVD method.

[0093] Next, an insulating film IF3 made of a silicon oxide film is formed on the conductive film CF2 by, for example, a CVD method. Next, a resist pattern RP2 is formed on the insulating film IF3 so as to selectively cover part of the region 2A and part of the region 3A.

[0094] 28 and 29, anisotropic etching is performed using the resist pattern RP2 as a mask to pattern the insulating film IF3 and the conductive film CF2. This removes the insulating film IF3 and the conductive film CF2 that are not covered by the resist pattern RP2. Then, a gate electrode GE2 and a cap film CP2 are formed on the upper surface of the semiconductor substrate SUB in region 2A with a gate insulating film GI2 interposed therebetween. Furthermore, a gate electrode GE3 and a cap film CP3 are formed on the upper surface of the semiconductor substrate SUB in region 3A with a gate insulating film GI3 interposed therebetween.

[0095] Next, the resist pattern RP2 is removed by ashing, followed by a cleaning process using an aqueous solution containing hydrofluoric acid to remove the gate insulating films GI2 and GI3 exposed from the gate electrodes GE2 and GE3.

[0096] Here, the features of the first embodiment will be described in the manufacturing process from Figures 16 and 17 to Figures 28 and 29. These features will be described in comparison with Study Examples 1 to 3 using Figures 54 to 65. Note that Study Examples 1 to 3 are not conventional technology, but are new findings obtained through studies by the inventors of the present application.

[0097] 54 and 55 show the state immediately after the gate insulating film GI1 is formed. In the study example 1, the gate insulating film GI1 is formed with the hard mask HM2 removed, whereas in the first embodiment, the gate insulating film GI1 is formed with the hard mask HM2 remaining.

[0098] 56 and 57, a conductive film CF1 is formed to fill the inside of the trench TR. Next, as shown in FIGS. 58 and 59, an anisotropic etching process is performed on the conductive film CF1 to remove the conductive film CF1 outside the trench TR and to recede the conductive film CF1 inside the trench TR. The conductive film CF1 remaining inside the trench TR becomes the gate electrode GE1.

[0099] At this point, the position of the upper surface of the conductive film CF1 in Study Example 1 is significantly lower than the position of the upper surface of the semiconductor substrate SUB. On the other hand, the position of the upper surface of the conductive film CF1 in Embodiment 1 is slightly lower than the position of the upper surface of the semiconductor substrate SUB, but is closer to the upper surface of the semiconductor substrate SUB by the thickness of the hard mask HM2.

[0100] 60 and 61, a cap film CP1 is formed on the upper surface of the conductive film CF1 by thermal oxidation treatment. At this point, the position of the upper surface of the cap film CP1 in Study Example 1 is lower than the position of the upper surface of the semiconductor substrate SUB.

[0101] On the other hand, the position of the upper surface of the conductive film CF1 in the first embodiment is lower than the position of the upper surface of the semiconductor substrate SUB. The difference between these positions is shown as height H1. Moreover, the position of the upper surface of the cap film CP1 in the first embodiment is higher than the position of the upper surface of the semiconductor substrate SUB. The difference between these positions is shown as height H2. In other words, the upper surface of the semiconductor substrate SUB is located within the thickness range of the cap film CP1. Moreover, the thickness of the cap film CP1 is thicker than the thickness of the gate insulating film GI1.

[0102] 62 and 63 show a state in which the hard mask HM2 is removed, the conductive film CF2 and the like are formed, and then an anisotropic etching process is performed to pattern the conductive film CF2. Here, in Study Example 1, since the position of the upper surface of the cap film CP1 is low, there is a problem in that the conductive film CF2 is left inside the trench TR as a sidewall-like residue.

[0103] Such residues may, for example, hinder the formation of the hole CH2 in the gate electrode GE1, preventing the hole CH2 from being formed properly. Furthermore, there is a risk that the residues may peel off and scatter during each manufacturing process, and the residues may remain as foreign matter on the semiconductor substrate SUB. This may result in problems such as a decrease in the reliability of the semiconductor device 100 or a decrease in yield. In contrast, the first embodiment can suppress the formation of such residues.

[0104] In order to suppress the generation of residues, it is possible to take measures such as those in Study Example 2 of FIG. 64 and Study Example 3 of FIG. 65.

[0105] In Study Example 2, by increasing the thickness of the gate insulating film GI1, the position of the upper surface of the gate electrode GE1 can be brought closer to the upper surface of the semiconductor substrate SUB, even if the recession amount of the conductive film CF1 is the same. However, the thicker the gate insulating film GI1, the more difficult it is for the on-current to flow. In other words, the on-resistance increases, and the performance of the semiconductor device 100 deteriorates.

[0106] In the study example 3, by increasing the thickness of the hard mask HM2 (thickness of the insulating film IF1), even if the recession amount of the conductive film CF1 is the same, the position of the upper surface of the gate electrode GE1 is higher than the position of the upper surface of the semiconductor substrate SUB. In this case, the generation of residue inside the trench TR can be suppressed.

[0107] However, when the hard mask HM2 is removed and the conductive film CF2 is subjected to an anisotropic etching process, sidewall-like residues of the conductive film CF2 are left on the side surfaces of the protruding gate electrode GE1. This residue may also become a foreign substance on the semiconductor substrate SUB. Furthermore, if the residue remains on the side surfaces of the protruding gate electrode GE1, this residue may become a leak path between the gate electrode GE1 and the source region NS.

[0108] The first embodiment was devised in consideration of the problems occurring in the study examples 1 to 3, and can suppress the generation of residues due to the conductive film CF2. Furthermore, since there is no need to adjust the thickness of the gate insulating film GI1, an increase in on-resistance can also be suppressed. That is, according to the first embodiment, the reliability of the semiconductor device 100 can be improved while ensuring the performance of the semiconductor device 100, and a decrease in yield can also be suppressed.

[0109] As described above, when removing the insulating film IF1, which is a silicon nitride film, of the hard mask HM2, an isotropic etching process using an aqueous solution containing phosphoric acid is used. At this time, if the upper surface of the gate electrode GE1 is exposed, the gate electrode GE1 will be etched by the phosphoric acid. However, the cap film CP1 formed on the gate electrode GE1 can prevent such etching.

[0110] The cap film CP1 is formed by thermally oxidizing the upper surface of the gate electrode GE1 made of a polycrystalline silicon film, but the upper portion of the gate electrode GE1 has a pointed shape before the thermal oxidation process, as shown in Fig. 58. Such a pointed portion is a place where electric field concentration is likely to occur, and is likely to be a factor in localized deterioration of the dielectric strength.

[0111] As shown in FIG. 60, by appropriately adjusting the time of the thermal oxidation treatment, the upper part of the gate electrode GE1 is rounded. Therefore, electric field concentration at the upper part of the gate electrode GE1 can be suppressed. For example, by adjusting the time of the thermal oxidation treatment so that the thickness of the cap film CP1 is 40 nm or more and 60 nm or less, the upper part of the gate electrode GE1 is rounded to such an extent that electric field concentration can be suppressed. In other words, it is preferable to perform the thermal oxidation treatment until the thickness of the cap film CP1 becomes thicker than the thickness (10 nm to 20 nm) of the gate insulating film GI1.

[0112] It is also possible to oxidize the upper surface of the gate electrode GE1 when forming the gate insulating film GI2 without forming the cap film CP1. However, since the thickness of the gate insulating film GI2 is, for example, 10 nm or more and 20 nm or less, there is a possibility that the upper part of the gate electrode GE1 will not be sufficiently rounded. Taking this into consideration, it is preferable to perform the thermal oxidation treatment until the thickness of the cap film CP1 becomes thicker than the thickness of the gate insulating film GI2.

[0113] The manufacturing process from FIG. 28 to FIG. 29 onward will be described below.

[0114] As shown in FIGS. 30 and 31, first, impurity regions are selectively formed in the regions 2A and 3A of the semiconductor substrate SUB on the upper surface side of the semiconductor substrate SUB using photolithography and ion implantation.

[0115] In region 2A, an n-type impurity region N1 is formed in well region PW1, and a p-type impurity region P1 is formed in well region NW1. In region 3A, an n-type impurity region N1 is formed in well region PW2, and a p-type impurity region P1 is formed in well region NW3.

[0116] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB. After these ion implantations, the through film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0117] Next, an insulating film such as a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB in the regions 1A to 4A by, for example, a CVD method. Next, the insulating film is subjected to an anisotropic etching process to remove the insulating film on the upper surface of the semiconductor substrate SUB, and sidewall spacers SW are formed on the side surfaces of the gate electrodes GE2 and GE3.

[0118] As shown in FIGS. 32 and 33, first, an insulating film IF4 made of, for example, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB by, for example, a CVD method so as to cover the gate electrodes GE1 to GE3 and the element isolation portion LOC.

[0119] Next, a conductive film CF3 is formed on the insulating film IF4 by, for example, a CVD method. The material contained in the conductive film CF3 has a sheet resistance higher than that of the material contained in the conductive films CF1 and CF2 (gate electrodes GE1 to GE3). The conductive film CF3 is a polycrystalline silicon film. Next, impurities such as boron (B) are ion-implanted into the conductive film CF3 to convert the conductive film CF3 into a p-type polycrystalline silicon film. Next, a resist pattern RP3 is formed on the conductive film CF3 so as to selectively cover a portion of the region 4A.

[0120] 34 and 35, first, the conductive film CF3 is patterned by performing an anisotropic etching process using the resist pattern RP3 as a mask. This forms the resistor element RS. Next, the resist pattern RP3 is removed by an ashing process. Next, a cleaning process is performed using an aqueous solution containing hydrofluoric acid to remove the insulating film IF4 exposed from the resistor element RS.

[0121] As shown in FIGS. 36 and 37, first, impurity regions are selectively formed in the regions 1A to 3A of the semiconductor substrate SUB on the upper surface side of the semiconductor substrate SUB using photolithography and ion implantation.

[0122] In region 1A, an n-type source region NS is formed in body region PB. In region 2A, an n-type impurity region N2 is formed in well region PW1, and a p-type impurity region P2 is formed in well region NW1. In this way, in region 2A, the source and drain regions of MOSFET 2Qn including impurity regions N1 and N2 are formed, and the source and drain regions of MOSFET 2Qp including impurity regions P1 and P2 are formed.

[0123] In region 3A, an n-type impurity region N2 is formed in well region PW2, an n-type impurity region N2 is formed in well region NW2, a p-type impurity region P2 is formed in well region NW3, and a p-type impurity region P2 is formed in well region PW3. In this manner, in region 3A, a source region of MOSFET 3Qn including impurity regions N1 and N2 is formed, and a drain region of MOSFET 3Qn including well region NW2 and impurity region N2 is formed. Also in region 3A, a source region of MOSFET 3Qp including impurity regions P1 and P2 is formed, and a drain region of MOSFET 3Qp including well region PW3 and impurity region P2 is formed.

[0124] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB. After these ion implantations, the through film may be removed by a cleaning process using an aqueous solution containing hydrofluoric acid, but the through film may also be left.

[0125] Next, the source and drain regions of MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp are subjected to heat treatment. This heat treatment is performed in a nitrogen atmosphere under conditions such as 850°C and 20 minutes. This heat treatment activates the impurities contained in the source and drain regions of MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp.

[0126] Through the above manufacturing steps, the basic structures of MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp are obtained.

[0127] Next, a silicon nitride film SN1 is formed by, for example, a CVD method on the upper surface of the semiconductor substrate SUB in the regions 1A to 4A so as to cover the gate electrodes GE1 to GE3 and the resistor element RS. The thickness of the silicon nitride film SN1 is, for example, not less than 10 nm and not more than 20 nm.

[0128] 38 and 39, an insulating film IF5 made of a silicon oxide film, a silicon nitride film SN2, and an insulating film IF6 made of a silicon oxide film are sequentially formed on the silicon nitride film SN1 by, for example, a CVD method. The thickness of the insulating film IF5 is, for example, 80 nm or more and 120 nm or less. The thickness of the silicon nitride film SN2 is, for example, 120 nm or more and 160 nm or less. The thickness of the insulating film IF6 is, for example, 1000 nm or more and 1400 nm or less.

[0129] 40 and 41, first, a resist pattern RP4 is formed on the insulating film IF6 so as to selectively open a part of the region 1A. Next, an anisotropic etching process is performed using the resist pattern RP4 as a mask, thereby forming an opening OP0 in the insulating film IF6 located above the body region PB. At this time, the silicon nitride film SN2 functions as an etching stopper.

[0130] Next, ion implantation is performed inside the opening OP0 so as to pass through the silicon nitride film SN1, the insulating film IF5, and the silicon nitride film SN2. This forms a p-type column region PC in the semiconductor substrate SUB located below the body region PB. This ion implantation uses, for example, boron (B) as an impurity, and is performed multiple times while changing the implantation energy. Thereafter, the resist pattern RP4 is removed by ashing.

[0131] Here, the column region PC is preferably formed after heat treatment for activating the impurities contained in the source and drain regions of each of MOSFETs 1Qn, 2Qn, 2Qp, 3Qn, and 3Qp. If the activation heat treatment is performed after the formation of the column region PC, the impurities contained in the column region PC may diffuse, causing the column region PC to expand. If the position of the column region PC expands too much from the designed value, the on-resistance of MOSFET 1Qn may increase. Furthermore, since it is difficult to control the diffusion position of the column region PC by heat treatment, there is a risk of variations in the expansion of the depletion layer, and the expected breakdown voltage may not be achieved. For this reason, in the first embodiment, the column region PC is formed after the activation heat treatment.

[0132] 42 and 43, first, an isotropic etching process is performed using an aqueous solution containing hydrofluoric acid to remove the insulating film IF6, using the silicon nitride film SN2 as an etching stopper. Next, an isotropic etching process is performed using an aqueous solution containing phosphoric acid to remove the silicon nitride film SN2, using the insulating film IF5 as an etching stopper. Since the insulating film IF5 was formed between the silicon nitride films SN1 and SN2, the silicon nitride film SN1 can be prevented from being removed when the silicon nitride film SN2 is removed.

[0133] Thereafter, the insulating film IF5 may be removed by isotropic etching using an aqueous solution containing hydrofluoric acid, or the insulating film IF5 may be left as part of the interlayer insulating film IL1. Here, the case where the insulating film IF5 is left will be exemplified.

[0134] As shown in FIGS. 44 and 45, an interlayer insulating film IL1 is formed on the upper surface of the semiconductor substrate SUB in the regions 1A to 4A so as to cover the gate electrodes GE1 to GE3 and the resistor element RS.

[0135] First, a silicon oxide film is formed on the silicon nitride film SN1, for example, by CVD. Next, a BPSG film is formed on the silicon oxide film, for example, by coating. Next, a heat treatment is performed on the BPSG film. This heat treatment is performed in a nitrogen atmosphere, for example, at 850°C for 20 minutes. This heat treatment may cause boron or phosphorus to diffuse from the BPSG film toward the semiconductor substrate SUB, but the silicon oxide film prevents such diffusion. Note that if the insulating film IF5 remains, the formation of the silicon oxide film is not essential.

[0136] Next, the interlayer insulating film IL1 is polished by a polishing process using a CMP (Chemical Mechanical Polishing) method, thereby flattening the upper surface of the interlayer insulating film IL1.

[0137] 46 and 47, first, a hole CH1 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB in the region 1A by photolithography and anisotropic etching. The bottom of the hole CH1 is located inside the body region PB.

[0138] During etching of the interlayer insulating film IL1, the silicon nitride film SN1 functions as an etching stopper. Then, by changing the gas and other conditions, the silicon nitride film SN1 and the semiconductor substrate SUB are sequentially etched. Because the etching process is stopped once at the silicon nitride film SN1, it becomes easier to uniformize the depth of the multiple holes CH1 across the wafer surface.

[0139] Next, for example, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by ion implantation, thereby forming a p-type high-concentration diffusion region PR.

[0140] 48 and 49, a hole CH2 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, and the cap film CP1 in the region 1A by photolithography and anisotropic etching. The hole CH2 reaches the gate electrode GE1. As in the manufacturing process of the hole CH1, the silicon nitride film SN1 functions as an etching stopper when the interlayer insulating film IL1 is etched.

[0141] As shown in FIGS. 50 and 51, photolithography and anisotropic etching are used to form a plurality of holes CH3 in the interlayer insulating film IL1 and the silicon nitride film SN1 in regions 2A to 4A. In region 2A, the plurality of holes CH3 reach the source and drain regions of each of MOSFETs 2Qn and 2Qp. In region 3A, the plurality of holes CH3 reach the source and drain regions of each of MOSFETs 3Qn and 3Qp. In region 4A, the plurality of holes CH3 reach the resistor element RS. As in the manufacturing process of the holes CH1, the silicon nitride film SN1 functions as an etching stopper when etching the interlayer insulating film IL1.

[0142] Although not shown here, holes CH3 reaching the gate electrodes GE2 and GE3 are also formed in the interlayer insulating film IL1 and the silicon nitride film SN1.

[0143] The process for manufacturing hole CH1 requires etching to a deeper position than the processes for manufacturing holes CH2 and CH3, and also requires etching of the semiconductor substrate SUB. Furthermore, after the formation of hole CH1, a process for manufacturing high-concentration diffusion region PR is also performed. Therefore, it is preferable that the process for manufacturing hole CH1, the process for manufacturing holes CH2, and the process for manufacturing holes CH3 are separate processes.

[0144] Furthermore, since the cap film CP1 is etched in the manufacturing process of the hole CH2, it is preferable that the manufacturing process of the hole CH2 and the manufacturing process of the hole CH3 are also separate processes.

[0145] However, since the thickness of the cap film CP1 is relatively thin compared to the interlayer insulating film IL1 and the like, the manufacturing process for the holes CH2 and CH3 may be the same process as long as the etching damage to the source and drain regions of each of the MOSFETs 2Qn, 2Qp, 3Qn, and 3Qp is within an allowable range. In particular, in the first embodiment, the position of the upper surface of the gate electrode GE1 is close to the position of the upper surface of the semiconductor substrate SUB, so the time it takes for the holes CH2 to reach the gate electrode GE1 can be shortened. Therefore, even when the manufacturing process for the holes CH2 and CH3 is the same process, the above-mentioned etching damage can be reduced compared to the first example.

[0146] As shown in FIGS. 52 and 53, plugs PG are formed inside each of the holes CH1 to CH3. First, a barrier metal film is formed inside each of the holes CH1 to CH3 and on the interlayer insulating film IL1, for example, by sputtering. Next, a conductive film is formed on the barrier metal film, for example, by CVD, so as to fill the inside of each of the holes CH1 to CH3. Next, the barrier metal film and the conductive film formed outside each of the holes CH1 to CH3 are removed by, for example, anisotropic etching. This forms plugs PG in the interlayer insulating film IL1. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0147] Next, a first barrier metal film, a conductive film, and a second barrier metal film are sequentially formed on the interlayer insulating film IL1 by, for example, sputtering or CVD. Next, the first barrier metal film, the conductive film, and the second barrier metal film are patterned to form wiring M1 connected to the plug PG on the interlayer insulating film IL1. The first barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum film or an aluminum alloy film doped with copper or silicon. The second barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film.

[0148] Thereafter, the following manufacturing steps are performed to obtain the structure shown in FIGS.

[0149] An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the wiring M1. To form the interlayer insulating film IL2, first, a first silicon oxide film is formed on the interlayer insulating film IL1 by, for example, a high density plasma CVD (HDP-CVD) method. Next, a second silicon oxide film is formed on the first silicon oxide film by, for example, a CVD method. Next, the first silicon oxide film and the second silicon oxide film are planarized by a polishing process using a CMP method. As a result, the interlayer insulating film IL2 including the first silicon oxide film and the second silicon oxide film is formed.

[0150] Note that a hydrogen alloy process may be performed after the interlayer insulating film IL2 is formed and before the via V1 (described later) is formed. This hydrogen alloy process is a heat treatment performed in a hydrogen atmosphere under conditions such as 400°C and 20 minutes. This hydrogen alloy process terminates dangling bonds near the upper surface of the semiconductor substrate SUB, thereby improving the variation in the threshold voltage of the MOSFET 1Qn.

[0151] Next, a via V1 is formed in the interlayer insulating film IL2 so as to connect to the wiring M1. To form the via V1, first, a contact hole is formed in the interlayer insulating film IL2 by photolithography and anisotropic etching. Next, a barrier metal film is formed inside the contact hole and on the interlayer insulating film IL2 by, for example, a CVD method. Next, a conductive film is formed on the barrier metal film by, for example, a CVD method so as to fill the inside of the contact hole. Next, the barrier metal film and the conductive film formed outside the contact hole are removed by, for example, anisotropic etching. This forms the via V1 in the interlayer insulating film IL2. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0152] Next, a wiring M2 is formed on the interlayer insulating film IL2 so as to connect to the via V1. Next, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the wiring M2. Next, a via V2 is formed in the interlayer insulating film IL3 so as to connect to the wiring M2. The manufacturing processes for the wiring M2, the interlayer insulating film IL3, and the via V2 can be performed using the same method as the manufacturing processes for the wiring M1, the interlayer insulating film IL2, and the via V1.

[0153] Note that, after the interlayer insulating film IL3 is formed and before the via V2 is formed, a hydrogen alloy treatment may be performed under the same conditions as described above. The hydrogen alloy treatment may be performed only after the interlayer insulating film IL2 is formed, only after the interlayer insulating film IL3 is formed, or both.

[0154] Next, a wiring M3 is formed on the interlayer insulating film IL3 so as to connect to the via V2. To form the wiring M3, first, a barrier metal film and a conductive film are sequentially formed on the interlayer insulating film IL3 by, for example, sputtering or CVD. Next, the barrier metal film and the conductive film are patterned to form the wiring M3 on the interlayer insulating film IL3. The barrier metal film is, for example, a titanium tungsten film. The conductive film is, for example, an aluminum film or an aluminum alloy film doped with copper or silicon.

[0155] Next, a protective film PVF is formed on the interlayer insulating film IL3 by, for example, a coating method so as to cover the wiring M3. The protective film PVF is, for example, a polyimide film. Next, openings OP1 and OP2 are formed in the protective film PVF on the wiring M3 so as to expose a portion of the wiring M3 (see FIGS. 67 and 70). The portion of the wiring M3 exposed in the openings OP1 and OP2 forms a source pad PADs or a pad PAD for connection to an external connection member BW.

[0156] Thereafter, the lower surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface of the semiconductor substrate SUB by sputtering.

[0157] If the semiconductor substrate SUB is a laminate of an n-type silicon substrate and an n-type semiconductor layer, the n-type silicon substrate is thinned by the polishing. If the n-type silicon substrate is left behind, the remaining n-type silicon substrate can function as the drain region ND, and therefore the formation of the drain region ND by the ion implantation method is not necessary.

[0158] In this way, the semiconductor device 100 is manufactured.

[0159] <Pad structure> The features of the source pads PADs and the pads PAD in the first embodiment will be described below with reference to FIGS.

[0160] Fig. 66 is a plan view corresponding to an enlarged region 10 surrounded by a dashed line in the source pad PADs shown in Fig. 1. Fig. 67 is a cross-sectional view taken along line CC in Fig. 66. Note that although vias V1 and V2 are not actually shown in Fig. 67, they are shown by dashed lines to make it easier to understand the hierarchical relationship between the components.

[0161] 66 and 67, at positions overlapping with the source pads PADs in plan view, the wiring M2 is provided with a plurality of slits SL penetrating the wiring M2, the wiring M1 is provided with a plurality of slits SL penetrating the wiring M1, and the semiconductor substrate SUB is provided with a plurality of MOSFETs 1Qn. Note that such slits SL are not provided in the source pads PADs that are part of the wiring M3.

[0162] In the wiring M1 and the wiring M2, the plurality of slits SL are rectangular in plan view and are arranged in a matrix with their long sides aligned in the column direction. In FIG. 66, the column direction is the Y direction and the row direction is the X direction. The plurality of slits SL in the wiring M2 are arranged at positions that overlap the plurality of slits SL in the wiring M1 in plan view. The plurality of plugs PG, the plurality of vias V1, and the plurality of vias V2 are each arranged between each row of the plurality of slits SL.

[0163] According to the study by the present inventors, when the wiring M2 and wiring M1 under the source pads PADs are not provided with the plurality of slits SL, cracks are likely to occur in the interlayer insulating film IL3 due to stress from the external connection member BW when the external connection member BW is formed on the source pads PADs. Furthermore, it was found that cracks are likely to occur not only in the interlayer insulating film IL3 but also in the interlayer insulating films IL2 and IL1 below it.

[0164] As in the first embodiment, the wiring M2 and the wiring M1 are provided with a plurality of slits SL, which allows the stress to be easily released downward through the plurality of slits SL, thereby suppressing the occurrence of cracks and improving the reliability of the semiconductor device 100.

[0165] As described above, in the first embodiment, the hydrogen alloy treatment is performed at least either after the interlayer insulating film IL2 is formed and before the via V1 is formed, or after the interlayer insulating film IL3 is formed and before the via V2 is formed. This hydrogen alloy treatment terminates dangling bonds near the top surface of the semiconductor substrate SUB, thereby improving the variation in the threshold voltage of the MOSFET 1Qn.

[0166] However, according to the study of the present inventors, it has been found that hydrogen alloy processing tends to be easily absorbed by the barrier metal films (titanium film and titanium nitride film) included in the wiring M1 and wiring M2. As in the first embodiment, by providing multiple slits SL in the wiring M1 and wiring M2, hydrogen can easily pass downward through the multiple slits SL, and can reach the vicinity of the upper surface of the semiconductor substrate SUB.

[0167] Fig. 68 is a graph showing the results of an experiment conducted by the inventors of the present application, in which the vertical axis represents the normal probability distribution and the horizontal axis represents the amount of variation (ΔVth) in the threshold voltage of MOSFET 1Qn.

[0168] 68, for those that have not undergone hydrogen alloy processing (□, △), the slope of the graph is gentle regardless of whether or not there is a slit SL. This means that there is a large variation in ΔVth among multiple MOSFETs 1Qn on the wafer surface.

[0169] On the other hand, in the case where the hydrogen alloy treatment was performed and the slit SL was provided (◯), the slope of the graph is steep, and it is clear that the variation in ΔVth has been improved.

[0170] Fig. 69 is a plan view corresponding to each pad PAD shown in Fig. 1. Fig. 70 is a cross-sectional view taken along line DD in Fig. 69. Note that although the plug PG and via V2 are not actually shown in Fig. 70, they are shown by dashed lines to make it easier to understand the hierarchical relationship of each component.

[0171] 69 and 70, at positions overlapping with the pads PAD in plan view, the wiring M2 is provided with a plurality of slits SL penetrating the wiring M2, and the wiring M1 is provided with a plurality of slits SL penetrating the wiring M1. Note that such slits SL are not provided in the pads PAD that are part of the wiring M3.

[0172] Furthermore, the semiconductor substrate SUB is not provided with the MOSFETs 2Qn, 2Qp, 3Qn, and 3Qp and the resistor element RS at positions overlapping with the pad PAD in plan view. The MOSFETs 2Qn, 2Qp, 3Qn, and 3Qp and the resistor element RS are electrically connected to the pad PAD via other wirings M1 to M3.

[0173] An element isolation portion LOC is provided in the semiconductor substrate SUB at a position overlapping the pad PAD in plan view. A conductive film PL is provided on this element isolation portion LOC. The conductive film PL is connected to the wiring M1 via a plug PG. The conductive film PL is a film in the same layer as the conductive film CF2 or the conductive film CF3, and is formed in the same process as the conductive film CF2 or the conductive film CF3.

[0174] Furthermore, in the semiconductor substrate SUB located below the conductive film PL (below the element isolation portion LOC), a p-type well region HPW0 and a p-type well region PW0 are formed so as to surround the conductive film PL and the element isolation portion LOC in plan view. The well region PW0 is formed in the well region HPW0. The well region HPW0 and the well region PW0 are not electrically connected to the MOSFETs and wirings M1 to M3, etc., and are in an electrically floating state. The well region HPW0 is formed in the same process as the well region HPW, and the well region PW0 is formed in the same process as the well regions PW1 to PW3.

[0175] Also under the pad PAD, in the wiring M1 and wiring M2, the plurality of slits SL are rectangular in plan view and are arranged in a matrix with their long sides aligned in the column direction. The plurality of slits SL in the wiring M2 are arranged at positions overlapping the plurality of slits SL in the wiring M1 in plan view. The plurality of plugs PG, the plurality of vias V1, and the plurality of vias V2 are each arranged between each row of the plurality of slits SL.

[0176] By providing the plurality of slits SL in the wiring M2 and the wiring M1, when an external connection member BW is formed on the pad PAD, stress from the external connection member BW can be easily released downward through the plurality of slits SL. Therefore, the occurrence of cracks can be suppressed even under the pad PAD, and the reliability of the semiconductor device 100 can be improved.

[0177] (Embodiment 2) 71 to 76, the semiconductor device 100 and the manufacturing method thereof according to the second embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0178] In the first embodiment, the silicon nitride film SN1 is provided between the semiconductor substrate SUB and the interlayer insulating film IL1 in the regions 1A to 4A. In the second embodiment, the silicon nitride film SN1 is left in the regions 2A to 4A, but is removed in the region 1A.

[0179] FIG. 71 shows a manufacturing process after the formation of the hole CH1 in FIG. 46. As shown in FIG. 71, in the second embodiment, the interlayer insulating film IL1 is recessed by performing an isotropic etching process on the interlayer insulating film IL1. For example, an aqueous solution containing hydrofluoric acid is used for this isotropic etching process. As a result, the opening width of the hole CH1 located on the upper surface of the semiconductor substrate SUB becomes wider than the opening width of the hole CH1 in the semiconductor substrate SUB. Note that the recession amount of the interlayer insulating film IL1 due to the isotropic etching process is, for example, 20 nm or more and 40 nm or less.

[0180] By widening the opening width of the hole CH1, the aspect ratio is improved when forming the plug PG in FIG. 52. This makes it easier to properly embed the plug PG inside the hole CH1. Furthermore, by recessing the interlayer insulating film IL1, the upper surface of the source region NS is exposed. Therefore, inside the hole CH1, the plug PG contacts not only the side surface of the source region NS but also the upper surface of the source region NS. This reduces the contact resistance between the plug PG and the source region NS.

[0181] 72 shows a manufacturing process of a semiconductor device in Study Example 4. Study Example 4 is not a conventional technique, but a new finding obtained through the study of the present inventors.

[0182] First, to obtain the hole CH1 shown in FIG. 71, the silicon nitride film SN1 in region 1A must be removed. However, as in Study Example 4, if a silicon oxide film is formed between the semiconductor substrate SUB and the silicon nitride film SN1, not only the interlayer insulating film IL1 but also the silicon oxide film will recede by isotropic etching. For example, such a silicon oxide film can be the through film used when forming the source region NS by ion implantation in FIG. 36. Here, the silicon oxide film used in the ion implantation in FIG. 36 is shown as the through film TH2.

[0183] By retracting the through film TH2 together with the interlayer insulating film IL1, the upper surface of the source region NS is exposed. However, because the silicon nitride film SN1 remains in an eave-like shape, when forming the barrier metal film of the plug PG, there are portions within the hole CH1 where it is difficult to deposit the barrier metal film. For example, it is difficult to uniformly deposit the barrier metal film in the space between the eave-like silicon nitride film SN1 and the upper surface of the semiconductor substrate SUB. Therefore, portions where the barrier metal film is disconnected are likely to occur within the hole CH1, and such portions can cause defects. Considering these problems, when widening the opening width of the hole CH1, it is preferable to remove the silicon nitride film SN1 in the region 1A.

[0184] 73 to 76 show manufacturing steps performed between the manufacturing step of FIG. 36 and the manufacturing step of FIG. 38, and show a step of selectively removing the silicon nitride film SN1 in region 1A. Note that regions 3A and 4A will be described in substantially the same manner as region 2A, and therefore will not be shown. In the state of FIG. 73, the through film TH2 may be left or removed. Here, a case where the through film TH2 is removed will be illustrated.

[0185] 73, after the silicon nitride film SN1 is formed in Fig. 36, an insulating film IF7 made of a silicon oxide film is formed on the silicon nitride film SN1 by, for example, a CVD method. The thickness of the insulating film IF7 is, for example, not less than 10 nm and not more than 30 nm.

[0186] 74, first, a resist pattern RP5 is formed on the insulating film IF7 so as to open the region 1A and cover the regions 2A to 4A. Next, an anisotropic etching process is performed using the resist pattern RP5 as a mask to remove the insulating film IF7 in the region 1A. Next, the resist pattern RP5 is removed by ashing.

[0187] 75, the silicon nitride film SN1 in the region 1A is removed by performing an isotropic etching process using an aqueous solution containing phosphoric acid using the insulating film IF7 in the regions 2A to 4A as a mask. Thereafter, the insulating film IF7 may be removed by performing an isotropic etching process using an aqueous solution containing hydrofluoric acid, or the insulating film IF7 may be left in the regions 2A to 4A. When the insulating film IF7 is left, the insulating film IF7 constitutes a part of the interlayer insulating film IL1, similar to the insulating film IF5.

[0188] 75 and subsequent manufacturing steps are the same as those in Embodiment 1. Fig. 76 shows a state in which the insulating film IF5, the silicon nitride film SN2, and the insulating film IF6 made of a silicon oxide film are formed in this order as described in Fig. 38.

[0189] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0190] 100 Semiconductor device 10 Expanded Area 1A area (output circuit area) 2A, 3A, 4A area (control circuit area) 1Qn, 2Qn, 3Qn n-type MOSFETs 2Qp, 3Qp p-type MOSFET BW external connection materials CF1~CF3 Conductive film CP1~CP3 cap film CH1~CH3 hole DE drain electrode GE1~GE3 gate electrodes GI1~GI3 gate insulating film GW Gate wiring HM1, HM2 hard mask HPW, HPW0 well region IF1~IF7 insulating film IL1~IL3 Interlayer insulating films LOC element isolation section M1~M3 wiring N1, N2 impurity region ND drain region NS Source Region NV drift region NW1~NW3 well region OP0~OP2 opening P1, P2 impurity region PAD PADs Source Pads PB body region PC, PC1~PC3 column area PG plug PL conductive film PR high concentration diffusion region PVF protective film PW0~PW3 well area RP1~RP5 resist patterns RS resistive element SE source electrode SL Slit SN1, SN2 silicon nitride film SUB Semiconductor substrate SW Sidewall Spacer TH1, TH2 through membrane TR Trench V1, V2 vias

Claims

1. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the step (a), forming a first hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate; (c) after the step (b), forming a trench in the semiconductor substrate exposed from the first hard mask; (d) after the step (c), forming a first gate insulating film inside the trench; (e) after the step (d), forming a first conductive film on the first gate insulating film and the first hard mask; (f) after the step (e), performing an anisotropic etching process on the first conductive film to remove the first conductive film on the first hard mask and form a first gate electrode inside the trench so as to fill the inside of the trench via the first gate insulating film; (g) after the step (f), forming a first cap film made of an insulating film on the upper surface of the first gate electrode; (h) after the step (g), removing the first hard mask; (i) after the step (h), forming a second gate insulating film on the upper surface of the semiconductor substrate; (j) after the step (i), forming a second conductive film on the second gate insulating film and the first cap film; (k) after the step (j), patterning the second conductive film to remove the second conductive film on the first cap film and form a second gate electrode on the upper surface of the semiconductor substrate via the second gate insulating film; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (k), the position of the upper surface of the first cap film is higher than the position of the upper surface of the semiconductor substrate.

3. 3. The method for manufacturing a semiconductor device according to claim 2, In the step (f), the position of the upper surface of the first gate electrode is lower than the position of the upper surface of the semiconductor substrate.

4. 3. The method for manufacturing a semiconductor device according to claim 2, In the step (k), the thickness of the first cap film is greater than the thickness of the first gate insulating film or the thickness of the second gate insulating film.

5. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (g), the first cap film is formed by oxidizing a portion of the first gate electrode through a first thermal oxidation treatment; The method for manufacturing a semiconductor device, wherein the first thermal oxidation treatment rounds off an upper portion of the first gate electrode.

6. 2. The method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein a material contained in the second conductive film has a sheet resistance lower than a sheet resistance of a material contained in the first conductive film.

7. 2. The method for manufacturing a semiconductor device according to claim 1, (l) forming a first through film made of a silicon oxide film on the upper surface of the semiconductor substrate between the steps (a) and (b); (m) between the step (l) and the step (b), performing ion implantation from the upper surface side of the semiconductor substrate so as to pass through the first through film, thereby forming a first well region in the semiconductor substrate; (n) forming a first insulating film made of a silicon nitride film on the first through film between the step (m) and the step (b); Further provided with In the step (b), the first through film and the first insulating film are patterned to form the first hard mask.

8. 8. The method for manufacturing a semiconductor device according to claim 7, (o) performing a first heat treatment on the first well region between the steps (m) and (n); The method for manufacturing a semiconductor device further comprises:

9. 8. The method for manufacturing a semiconductor device according to claim 7, (p) a step between the step (n) and the step (b), of forming a second insulating film made of a silicon oxide film on the first insulating film; Further provided with In the step (b), the first through film, the first insulating film, and the second insulating film are patterned to form the first hard mask; The method for manufacturing a semiconductor device, wherein the second insulating film is removed between the step (c) and the step (d).

10. 8. The method for manufacturing a semiconductor device according to claim 7, (q) forming a second hard mask on the upper surface of the semiconductor substrate so as to selectively cover the upper surface of the semiconductor substrate between the steps (a) and (l); (r) performing a second thermal oxidation treatment between the step (q) and the step (l) to form an isolation portion in the semiconductor substrate exposed from the second hard mask; (s) removing the second hard mask between the steps (r) and (l); Further provided with the element isolation portion is formed between a first region in which a first MOSFET including the first gate electrode is formed and a second region in which a second MOSFET including the second gate electrode is formed.

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