Data processing method and second communication device

Abstract

In order to solve the problem of the relatively long data synchronization time in the prior art, the present application provides a data processing method and a second communication device, which may be applied to augmented reality (AR), virtual reality (VR), artificial intelligence (AI), cloud applications, or other fields. The data processing method includes: a second optical module receives first data from the first optical module, and determines synchronous lock out based on the first data; the second optical module sends first indication information to the second host, which indicates that the second optical module is in a synchronous lock out state; the second optical module receives second data from the first optical module, and determines synchronous lock based on the second data, and sends second indication information to the second host, which indicates that the second optical module is in a synchronous lock state.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202210220031.2, entitled "Data Processing Method and Second Communication Device," filed with the State Intellectual Property Office of the People's Republic of China on March 8, 2022, which is incorporated herein by reference in its entirety.

[0002]

[0002] Technical field The present application relates to the field of data processing technology, and in particular to a data processing method and a second communication device. [Background technology]

[0003]

[0003] As data traffic continues to grow rapidly, the capabilities of communication devices are also increasing rapidly, thereby placing higher requirements on Ethernet transmission rates. (I The IEEE 802.3 Ethernet protocol specifies 100 Gigabit Ethernet (GE), 200GE, and 400GE interface protocols. However, 400GE network port technology cannot meet the requirements, and next-generation Ethernet technology with throughput rates exceeding 400 Gigabits per second (Gbps) (e.g., 800 Gbps or 1.6 Tbps) is urgently needed.

[0004] However, the increase in Ethernet transmission rate increases the bit error rate of transmission, which requires data synchronization and alignment to be performed first in the data transmission process. Currently, the synchronization and alignment mechanism for 400GE mainly involves alignment markers. (AThis is implemented by capturing an AM (AM) subsequence. An AM subsequence can typically be found once every 163840 x 257 bits. If it is found that the AM subsequence can be correctly matched two times in a row, the data is determined to be synchronized. If it is found that the AM subsequence cannot be correctly matched five times in a row, the data is determined to be unsynchronized. A large interval between AM subsequences results in a long data synchronization, increasing data transmission delays.

[0005]

[0005] In conclusion, how to reduce the data synchronization duration is currently a technical problem that needs to be urgently solved. Summary of the Invention

[0006]

[0006] The present application provides a data processing method and a second communication device for reducing data synchronization duration.

[0007]

[0007] According to a first aspect, the present application provides a data processing method. The method includes: a second communication device receives first data from a first communication device and determines, based on the first data, an out-of-synchronization lock (also referred to as asynchronous, inconsistent, asynchronous and inconsistent, etc.); and sends first indication information to a fourth communication device, where the first indication information indicates that the second communication device is in an out-of-synchronization lock state. The second communication device receives second data from the first communication device and determines, based on the second data, a synchronization lock (also referred to as synchronized, inconsistent, synchronized and inconsistent, etc.); and sends second indication information to the fourth communication device, where the second indication information indicates that the second communication device is in a synchronization lock state.

[0008]

[0008] Based on the above solution, after determining the synchronization lock out, the second communication device sends first indication information to the fourth communication device, indicating that the second communication device is in a synchronization lock out state, so that the fourth communication device can determine that the first data is invalid data, which helps to reduce the calculation overhead of the fourth communication device.Furthermore, after determining the synchronization lock, the second communication device sends second indication information to the fourth communication device, indicating that the second communication device is in a synchronization lock state, which helps the fourth communication device to quickly start (or enter) the synchronization process without waiting for a long time, which helps to reduce the data synchronization duration.

[0009]

[0009] In a possible implementation, the second communication device includes a second optical module, the first communication device includes a first optical module, and the fourth communication device includes a second host.

[0010]

[0010] In order to facilitate the description of the solution, the following description uses an example in which the second communication device is a second optical module, the first communication device is a first optical module, the third communication device is a first host, and the fourth communication device is a second host. In other words, in the following description, the first communication device may be replaced by a first optical module, the second communication device may be replaced by a second optical module, the third communication device may be replaced by a first host, and the fourth communication device may be replaced by a second host.

[0011]

[0011] In a possible implementation, the second optical module transmits third data to the second host, and the third data is obtained by replacing a portion of the data in the second data with a first predetermined sequence, and the first predetermined sequence is for synchronization of the second host.

[0012]

[0012] Replacing partial data in the second data with the first predetermined sequence helps to save bandwidth between the second optical module and the second host. Furthermore, the second host can perform synchronization based on the first predetermined sequence in the third data, without waiting a long time for the first host to determine whether synchronization is performed by using the AM subsequence inserted at large intervals in the second data, which helps to further reduce data synchronization duration.

[0013]

[0013] In a possible implementation, the first predetermined sequence is at least one subsequence in the AM group and may be referred to as an AM subsequence.

[0014]

[0014] In a possible implementation, the second optical module may send the second indication information to the second host via an indication signal path of an attachment unit interface (AUI). Alternatively, the second optical module may send the second indication information to the second host via a management data input / output (MDIO) interface. The indication signal path may be, for example, inst:IS_SIGNAL.indication, where inst represents an instance. For example, if inst is an FEC sublayer, the indication signal path may be expressed as FEC:IS_SIGNAL.indication. The inst:IS_SIGNAL.indication is generated through a signal indication logic (SIL) group to report the validity of a signal received from a lower layer processing unit. The multiple types of detection indication signals generated by the second optical module are converged onto a path inst:IS_SIGNAL.indication via a signal indication logic SIL and sent to the second host.

[0015]

[0015] The second optical module is capable of transmitting second instruction information to the second host in real time at high speed via the instruction signal path of the AUI; and the second instruction information is capable of being transmitted to the second host via the MDIO interface without changing the existing data stream processing procedure.

[0016]

[0016] In a possible implementation, the second optical module may transmit the third data to the second host via a first data stream path of the AUI, which may be, for example, inst:IS_UNITDATA.indication.

[0017]

[0017] In a possible implementation, the second optical module can send the first instruction information to the second host via the instruction signal path of the AUI.

[0018]

[0018] In a possible implementation, the second optical module is capable of transmitting the first data to the second host via the first data stream path of the AUI.

[0019]

[0019] Below, as examples, three possible ways of replacing a portion of data in the second data with the first predetermined sequence are given.

[0020] Scheme A: Substitute the complete second codeword with a first predetermined sequence.

[0021]

[0021] In a possible implementation, the second data includes N second code words, where N is an integer greater than 1; and the second optical module permutes w second code words in the N second code words with a first predetermined sequence to obtain the third data, where w is a positive integer less than or equal to N. Furthermore, w is a positive integer greater than 1 and less than or equal to N.

[0022]

[0022] Furthermore, the length of the first predetermined sequence is equal to a positive integer multiple of the code length of one second codeword.

[0023]

[0023] The complete second codeword is replaced with the first predetermined sequence, so that the second host can quickly determine the boundary of each second codeword in the received second data. In this way, the duration required for synchronization can be shortened, and the complexity of the synchronization operation on the second host side can be reduced.

[0024] Scheme B: The second overhead block in the second codeword is replaced with the first predetermined sequence.

[0025]

[0025] In a possible implementation, the second data includes N second code words, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; the second optical module replaces the second overhead blocks in w second code words among the N second code words with a first predetermined sequence to obtain the third data.

[0026]

[0026] Furthermore, the length of the first predetermined sequence is less than or equal to the length of one second overhead block.

[0027]

[0027] The second overhead block in the second codeword is replaced with the first predetermined sequence, so that normal transmission of valid data will not be affected. Furthermore, if the length of the first predetermined sequence is equal to the length of the second overhead block, the second host can quickly determine the boundary of the second codeword in the received second data, thereby reducing the duration required for synchronization.

[0028] Scheme C: The second information block in the second codeword is replaced with the first predetermined sequence.

[0029]

[0029] In a possible implementation, the second data includes N second code words, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; the second optical module replaces the first information block in w second code words among the N second code words with a first predetermined sequence to obtain the third data.

[0030]

[0030] Furthermore, the length of the first predetermined sequence is less than or equal to the length of one second information block.

[0031]

[0031] When the second overhead block needs to be discarded at the second optical module side, the second information block is replaced with the first predetermined sequence, so that the second host performs synchronization based on the first predetermined sequence, which helps to reduce the duration required for synchronization of the second host.

[0032]

[0032] In a possible implementation, the w second codewords are w consecutive or non-consecutive second codewords within the N second codewords. The intervals between the w non-consecutive second codewords may be the same or different. For example, the second codeword may be permuted with a first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the second information block within the second codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j may be a positive integer such as 1, 2, 3, or 4.

[0033]

[0033] The w consecutive first predetermined sequences can enable the second host to quickly detect the w first predetermined sequences, thereby further shortening the duration required for synchronization. The w discontinuous second codewords can avoid a case where the second host cannot detect the first predetermined sequence because part of the data is missing in the transmission process. Furthermore, when w is greater than 2, it can avoid a case where the second host cannot accurately determine the synchronization state because part of the data in the second data is missing in the transmission process. This helps to improve the synchronization accuracy of the second host.

[0034]

[0034] In a possible implementation, the second data may include a second predetermined sequence, and the second optical module replaces the second code word with the first predetermined sequence from the boundary position of any of the N second code words, and stops the replacement when it detects that the second predetermined sequence matches the second optical module's second known predetermined sequence at least once, thereby obtaining the third data.

[0035]

[0035] When the second data includes a second predetermined sequence, the second optical module can stop the substitution when it detects that the second predetermined sequence matches the second optical module's second known predetermined sequence at least once, thereby assisting the second optical module in reducing the quantity of second code words to be substituted.

[0036]

[0036] In a possible implementation, the second predetermined sequence is at least one subsequence in the AM group.

[0037]

[0037] The second predetermined sequence is set to at least one subsequence in the AM group and is compatible with existing AM synchronization mechanisms.

[0038]

[0038] Below, as examples, two possible implementations of performing synchronization based on second data are given.

[0039]

[0039] Implementation A

[0040] In a possible implementation, the second data includes N second codewords, where N is an integer greater than 1. The second optical module decodes the second data based on a sliding window using a predetermined number of bits; after determining that the decoding has been successful at least once, performs decoding based on a sliding window using a code length of the second codeword and collects statistics on the number of successful decodings among the second decoding results; and determines synchronization lock when determining that the number of successful decodings among the second decoding results is greater than a third threshold, and the predetermined number of bits is less than the code length of the second codeword.

[0040]

[0041] The second optical module needs to track the synchronization status of the received data in real time, and the above implementation A is compatible with existing synchronization mechanisms, which simplifies the processing of the received data by the second optical module.

[0041]

[0042] Implementation B

[0043] In a possible implementation, the second data includes N second code words, the second code words including a second information block and a second overhead block, and the second overhead block including a third predetermined sequence; and the second optical module determines synchronization lock when it detects that the quantity of the third predetermined sequence is greater than a fifth threshold within a predetermined time window.

[0042]

[0044] Synchronization lock is determined by detecting the quantity of the third predetermined sequence within a predetermined time window; no decoding is required. Implementation is simple. Furthermore, the third predetermined sequence occupies a portion of the bits in the first overhead block. Therefore, the amount of data transmitted is not increased.

[0043]

[0045] Below, as examples, two possible implementations of determining the synchronization state of the second optical module based on the first data are given.

[0044]

[0046] Implementation 1: The synchronization state is determined based on the decoding result.

[0045]

[0047] In a possible implementation, the second optical module decodes the first data to obtain M first decoding results, the first decoding results including successful decoding or failed decoding, where M is an integer greater than 1; if the number of failed decodings among the M first decoding results is greater than a first threshold, the second optical module determines that synchronization is out of lock; or if the number of successful decodings among the M first decoding results is greater than a second threshold, the second optical module determines that synchronization is locked.

[0046]

[0048] Implementation 2: Synchronization is determined based on a third predetermined sequence included in a first overhead block within the first codeword.

[0047]

[0049] In a possible implementation, the first data includes Q first code words, the first code words including a first information block and a first overhead block, the first overhead block including a third predetermined sequence, Q being an integer greater than 1; if the second optical module detects that the quantity of the third predetermined sequence is less than a fifth threshold within a predetermined time window, the second optical module determines that the synchronization has lost lock; or if the second optical module detects that the quantity of the third predetermined sequence is greater than or equal to a fifth threshold within a predetermined time window, the second optical module determines that the synchronization has locked.

[0048]

[0050] In a possible implementation, the second optical module receives third indication information from the second host via the MDIO interface, and the third indication information indicates that the second host is in a synchronous out-of-lock state.

[0049]

[0051] In a possible implementation, the second optical module includes a second physical medium attachment (PMA) sublayer, or includes a second PMA sublayer and a second forward error correction (FEC) sublayer; and the second host includes a second physical coding sublayer (PCS), or includes a second PCS and a fourth FEC sublayer.

[0050]

[0052] According to a second aspect, the present application provides a data processing method. The method includes: a second host receiving first indication information from a second optical module, the first indication information indicating that the second optical module is in a synchronous lock out state; the second host determining the synchronous lock out state based on the first indication information; the second host receiving second indication information from the second optical module, the second indication information indicating that the second optical module is in a synchronous lock state; and the second host starting synchronization based on the second indication information.

[0051]

[0053] Based on the above solution, after receiving the first indication information indicating that the second optical module is in a synchronization out-of-lock state, the second host may determine that the received first data is invalid data, and the second host may determine that the second optical module is in a synchronization out-of-lock state.Furthermore, after receiving the second indication information indicating that the second optical module is in a synchronization locked state, the second host can quickly start (or enter) synchronization without waiting for a long time, which helps shorten the data synchronization duration.

[0052]

[0054] In a possible implementation, the second host may receive the first indication information from the second optical module via the MDIO interface; or the second host may receive the first indication information from the second optical module via the indication signal path of the AUI.

[0053]

[0055] In a possible implementation, the second host may receive the second instruction information from the second optical module via the MDIO interface; or the second host may receive the second instruction information from the second optical module via the instruction signal path of the AUI.

[0054]

[0056] In one possible implementation, the method further includes the second host receiving third data from the second optical module, the third data being obtained by replacing a portion of the data in the second data with a first predetermined sequence, the third data including the second predetermined sequence, and the second data being received from the first optical module by the second optical module. If the second host detects that the first predetermined sequence matches the second host's first known predetermined sequence at least once and that the second predetermined sequence matches the second host's fourth known predetermined sequence at least once, this indicates AM lock. Furthermore, for each physical coding sublayer lane, the second host determines that the quantity of the second predetermined sequence is 1, indicating that the conditions for lane reordering are met. Furthermore, the second host reorders m physical coding sublayer lanes, where m is an integer greater than 1.

[0055]

[0057] The second host detects that the first predetermined sequence matches at least once with the second host's first known predetermined sequence, and detects that the second predetermined sequence matches at least once with the second host's fourth known predetermined sequence. By using AM subsequences inserted at large intervals in the second data, the first host does not need to wait a long time to determine whether synchronization is to be performed, thereby reducing the duration required for synchronization of the second host.

[0056]

[0058] According to a third aspect, the present application provides a data processing method, the method including: a first optical module receiving fourth data from a first host, the fourth data including k second predetermined sequences, where k is an integer greater than 1; the first optical module determining synchronization lock loss based on the fourth data, and transmitting the fourth data to the first host.

[0057]

[0059] Based on the above solution, the first host receives the fourth data from the first optical module, determines that the first optical module is in a synchronization lock out state, and enters a loopback mode. This helps to avoid the case where the second optical module cannot accurately identify the received data because the first optical module transmits synchronization lock out data to the second optical module. Furthermore, this helps to avoid the case where the first optical module exceeds the specified processing delay limit.

[0058]

[0060] Furthermore, the first optical module is capable of receiving fifth data from the first host, where the fifth data includes h second predetermined sequences, where h is greater than k.

[0059]

[0061] The fifth data is obtained by inserting the second predetermined sequence more densely so that the first optical module can quickly perform synchronization locking.

[0060]

[0062] In a possible implementation, the first optical module may receive fourth indication information from the first host via the MDIO interface, the fourth indication information indicating that the first host is in a synchronous out-of-lock state.

[0061]

[0063] The first host sends the fourth instruction information to the first optical module, thereby enabling the first optical module to quickly enter the loopback mode.

[0062]

[0064] According to a fourth aspect, the present application provides a data processing method, including: a second optical module receiving sixth data from a first optical module, determining a loss of synchronization lock based on the sixth data, and substituting a portion of the seventh data with a fourth predetermined sequence to obtain eighth data, the seventh data being received by the second optical module from a second host; the second optical module transmitting the eighth data to the first optical module and receiving ninth data from the first optical module, the ninth data being obtained by the first optical module by substituting tenth data with the fourth predetermined sequence, the tenth data being received by the first optical module from the first host; the second optical module detecting the fourth predetermined sequence at least twice in the ninth data and substituting the fourth predetermined sequence in the eighth data with a fifth predetermined sequence to obtain eleventh data, the fifth predetermined sequence being different from the fourth predetermined sequence. The second optical module transmits eleventh data to the first optical module and receives twelfth data from the first optical module, the twelfth data being obtained by replacing the fourth predetermined sequence in the ninth data with a fifth predetermined sequence when the first optical module detects at least two of the fourth predetermined sequences in the eighth data. The second optical module detects at least two of the fifth predetermined sequences and determines synchronization lock.

[0063]

[0065] Based on the above solution, the synchronization between the first optical module and the second optical module may be independent of the processing procedures of the first host and the second host, so the existing host synchronization procedures do not need to be changed.

[0064]

[0066] Below, as an example, three possible ways of replacing a part of the data in the seventh data with the fourth predetermined sequence are shown.

[0065]

[0067] In a possible implementation, the seventh data includes P third code words, each of which includes a third information block and a third overhead block, where P is an integer greater than 1.

[0066]

[0068] Scheme 1: Replace the complete third codeword with a fourth predetermined sequence.

[0067]

[0069] In a possible implementation, the second optical module replaces z third code words among the P third code words with a fourth predetermined sequence to obtain eighth data, where z is a positive integer greater than 1 and less than or equal to P.

[0068]

[0070] Furthermore, the length of the fourth predetermined sequence is equal to a positive integer multiple of the code length of one third codeword.

[0069]

[0071] The complete third codeword is replaced with the fourth predetermined sequence, so that the first optical module can quickly determine the boundary of each third codeword in the received eighth data, thereby shortening the duration required for synchronization and reducing the complexity of the synchronization calculation on the first optical module side.

[0070]

[0072] Scheme 2: The third overhead block in the third codeword is replaced with a fourth predetermined sequence.

[0071]

[0073] In a possible implementation, the second optical module permutes third overhead blocks in z third codewords in the P third codewords with a fourth predetermined sequence to obtain eighth data.

[0072]

[0074] Furthermore, the length of the fourth predetermined sequence is less than or equal to the length of one third overhead block.

[0073]

[0075] The third overhead block in the third codeword is replaced with a fourth predetermined sequence, so that normal transmission of valid data will not be affected. Furthermore, if the length of the fourth predetermined sequence is equal to the length of the third overhead block, the first optical module can quickly determine the boundary of the third codeword in the received eighth data, thereby reducing the duration required for synchronization.

[0074]

[0076] Scheme 3: Replace the third information block in the third codeword with a fourth predetermined sequence.

[0075]

[0077] In a possible implementation, the second optical module replaces the third information blocks in z third code words among the P third code words with a fourth predetermined sequence to obtain eighth data.

[0076]

[0078] Furthermore, the length of the fourth predetermined sequence is equal to or less than the length of one third information block.

[0077]

[0079] If the second overhead block needs to be discarded at the second optical module side, the third information block is replaced with a fourth predetermined sequence, so that the first optical module performs synchronization based on the fourth predetermined sequence, which helps to reduce the duration required for synchronization of the first optical module.

[0078]

[0080] In a possible implementation, the z third codewords are z consecutive or non-consecutive third codewords within the P third codewords. The intervals between the z non-consecutive third codewords may be the same. For example, 4The codeword may be permuted by the first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the third information block in the third codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j may be a positive integer such as 1, 2, 3, or 4. Alternatively, the intervals between z non-consecutive third codewords may be different, which is not a limitation in the present application.

[0079]

[0081] In a possible implementation, after the second optical module detects at least two fifth predetermined sequences and determines synchronization lock, the second optical module may send second instruction information to the second host via the instruction signal path of the AUI or via the MDIO interface, and send thirteenth data to the second host via the first data stream path of the AUI.

[0080]

[0082] In a possible implementation, after the second optical module determines that synchronization lock has been lost based on the sixth data, the second optical module may send first instruction information to the second host via the instruction signal path of the AUI or via the MDIO interface, and send the sixth data to the second host via the first data stream path of the AUI.

[0081]

[0083] In a possible implementation, the second optical module includes a second PMA sublayer, or includes a second PMA sublayer and a second FEC sublayer; the second host includes a second PCS, or includes a second PCS and a fourth FEC sublayer; the first optical module includes a first PMA sublayer, or includes a first PMA sublayer and a first FEC sublayer; and the first host includes a first PCS, or includes a first PCS and a first FEC sublayer.

[0082]

[0084] According to a fifth aspect, the present application provides a data processing method. The method includes: a second layer receiving first data from a first layer, the second layer including a second PMA sublayer, or including a second PMA sublayer and a second FEC sublayer; the first layer including a first PMA sublayer, or including a first PMA sublayer and a first FEC sublayer; the second layer determining synchronization lock loss (also referred to as being out of synchronization, being misaligned, being both out of synchronization, etc.) based on the first data; the second layer transmitting first indication information to a fourth layer, the fourth layer including a second PCS, or including a second PCS and a second FEC sublayer, the first indication information being transmitted to the fourth layer. layer The second layer receives second data from the first layer, determines synchronous lock (also referred to as synchronized, aligned, synchronized and aligned, etc.) based on the second data, and sends second indication information to the fourth layer, where the second indication information indicates that the second optical module is in a synchronous lock state.

[0083]

[0085] Based on the above solution, after determining the synchronization lock out, the second layer sends first indication information to the fourth layer, indicating that the second layer is in a synchronization lock out state, so that the fourth layer can determine that the first data is invalid data, which helps to avoid operation errors in the fourth layer.Furthermore, after determining the synchronization lock, the second layer sends second indication information to the fourth layer, indicating that the second layer is in a synchronization lock state, which helps the fourth layer to quickly start (or enter) the synchronization process without waiting for a long time, which helps to reduce the data synchronization duration.

[0084]

[0086] In a possible implementation, the second layer transmits third data to the fourth layer, and the third data is obtained by replacing a portion of the data in the second data with a first predetermined sequence, and the first predetermined sequence is for synchronization of the fourth layer.

[0085]

[0087] In a possible implementation, the first predetermined sequence is at least one subsequence in the AM group.

[0086]

[0088] In a possible implementation, the second layer can transmit the second indication information to the fourth layer via an indication signal path of the AUI. Alternatively, the second layer can transmit the second indication information to the fourth host via the MDIO interface.

[0087]

[0089] In a possible implementation, the second layer may transmit the third indication information to the fourth layer via the first data stream path of the AUI.

[0088]

[0090] In a possible implementation, the second layer may send the first indication information to the fourth layer via an indication signal path of the AUI.

[0089]

[0091] In a possible implementation, the second layer may transmit the first data to the fourth layer via a first data stream path of the AUI.

[0090]

[0092] Below, as examples, three possible ways of replacing a portion of data in the second data with the first predetermined sequence are given.

[0091]

[0093] Scheme A: Substitute the complete second codeword with the first predetermined sequence.

[0092]

[0094] In a possible implementation, the second data includes N second code words, where N is an integer greater than 1; the second layer replaces w second code words in the N second code words with a first predetermined sequence to obtain third data, where w is a positive integer less than or equal to N. Furthermore, w is a positive integer greater than 1 and less than or equal to N.

[0093]

[0095] Furthermore, the length of the first predetermined sequence is equal to a positive integer multiple of the code length of one second codeword.

[0094]

[0096] Scheme B: The second overhead block in the second codeword is replaced with the first predetermined sequence.

[0095]

[0097] In a possible implementation, the second data includes N second codewords, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; and the second layer permutes first overhead blocks in w second codewords among the N second codewords with a first predetermined sequence to obtain third data.

[0096]

[0098] Furthermore, the length of the first predetermined sequence is less than or equal to the length of one second information block.

[0097]

[0099] Scheme C: The second information block in the second codeword is replaced with the first predetermined sequence.

[0098]

[0100] In a possible implementation, the second data includes N second codewords, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; the second layer permutes the second overhead blocks in w second codewords among the N second codewords with a first predetermined sequence to obtain the third data.

[0099]

[0101] Furthermore, the length of the first predetermined sequence is less than or equal to the length of one second overhead block.

[0100]

[0102] In a possible implementation, the w second codewords are w consecutive or non-consecutive second codewords within the N second codewords. The intervals between the w non-consecutive second codewords may be the same or different. For example, the second codeword may be permuted with a first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the second information block within the second codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j may be a positive integer such as 1, 2, 3, or 4.

[0101]

[0103] In a possible implementation, the second data includes a second predetermined sequence; and the second layer replaces the second codeword with the first predetermined sequence from a boundary position of any second codeword among the N second codewords, stopping the replacement when it detects that the second predetermined sequence matches the second known predetermined sequence of the second layer at least once, to obtain the third data.

[0102]

[0104] In a possible implementation, the second predetermined sequence is at least one subsequence within the alignment marker AM group.

[0103]

[0105] Below, as examples, two possible implementations for performing synchronization based on second data are given.

[0104]

[0106] Implementation A

[0107] In a possible implementation, the second data includes N second codewords, where N is an integer greater than 1; the second layer decodes the second data based on a sliding window using a predetermined number of bits; after determining that the decoding has been successful at least once, performs decoding based on a sliding window using a code length of the second codewords and collects statistics on the number of successful decodings among the second decoding results; and determines synchronization lock when it determines that the number of successful decodings among the second decoding results is greater than a third threshold, and the predetermined number of bits is less than the code length of the second codewords.

[0105]

[0108] Implementation B

[0109] In a possible implementation, the second data includes N second code words, the second code words including a second information block and a second overhead block, and the second overhead block including a third predetermined sequence; and the second layer determines synchronization lock when it detects that the quantity of the third predetermined sequence is greater than a fifth threshold within a predetermined time window.

[0106]

[0110] Below, as examples, we present two possible implementations for determining second layer synchronization based on first data.

[0107]

[0111] Implementation 1: Synchronization is determined based on the decoding result.

[0108]

[0112] In a possible implementation, the second layer decodes the first data to obtain M first decoding results, the first decoding results including successful decoding or failed decoding, where M is an integer greater than 1; if the number of failed decodings among the M first decoding results is greater than a first threshold, the second layer determines that synchronization lock has been lost; or if the number of successful decodings among the M first decoding results is greater than a second threshold, the second layer determines that synchronization lock has been achieved.

[0109]

[0113] Implementation 2: Synchronization is determined based on a third predetermined sequence included in a first overhead block within the first codeword.

[0110]

[0114] In a possible implementation, the first data includes Q first code words, the first code words including a first information block and a first overhead block, the first overhead block including a third predetermined sequence, Q being an integer greater than 1; the second layer determines synchronization lock loss if it detects that the quantity of the third predetermined sequence is less than a fifth threshold within a predetermined time window; or the second layer determines synchronization lock if it detects that the quantity of the third predetermined sequence is greater than or equal to a fifth threshold within a predetermined time window.

[0111]

[0115] In a possible implementation, the second layer receives third indication information from the fourth layer via the MDIO interface, and the third indication information indicates that the fourth layer is in a synchronous out-of-lock state.

[0112]

[0116] For technical effects that can be achieved by any aspect in the fifth aspect, please refer to the description of the advantageous effects in the first aspect, and the details will not be described again here.

[0113]

[0117] According to a sixth aspect, the present application provides a data processing method. The method includes: a fourth layer receiving first indication information from a second layer, the first indication information indicating that the second layer is in a synchronization out-of-lock state; the fourth layer determining synchronization out-of-lock based on the first indication information; the fourth layer receiving second indication information from the second layer, the second indication information indicating that the second layer is in a synchronization locked state; and the fourth layer initiating synchronization based on the second indication information. The second layer includes a second PMA sublayer, or includes a second PMA sublayer and a second FEC sublayer; the fourth layer includes a second PCS, or includes a second PCS and a second FEC sublayer.

[0114]

[0118] Based on the above solution, after receiving the first indication information indicating that the second layer is in a synchronization out-of-lock state, the fourth layer may determine that the received first data is invalid data, and may determine that the fourth layer is in a synchronization out-of-lock state. Furthermore, after receiving the second indication information indicating that the second layer is in a synchronization locked state, the fourth layer can quickly start (or enter) the synchronization process without waiting for a long time, which helps shorten the data synchronization duration.

[0115]

[0119] In a possible implementation, the fourth layer may receive the first indication information from the second layer via the MDIO interface; or the fourth layer may receive the first indication information from the second layer via an indication signal path of the AUI.

[0116]

[0120] In a possible implementation, the fourth layer may receive the second indication information from the second layer via the MDIO interface; or the fourth layer may receive the second indication information from the second layer via an indication signal path of the AUI.

[0117]

[0121] In one possible implementation, the method further includes: the fourth layer receiving third data from the second layer, where the third data is obtained by replacing a portion of the data in the second data with a first predetermined sequence; the second data received by the second layer from the first layer, where the third data further includes the second predetermined sequence; if the fourth layer detects that the first predetermined sequence matches the first known predetermined sequence of the fourth layer at least once and that the second predetermined sequence matches the fourth known predetermined sequence of the fourth layer at least once, the method further determines that the quantity of the second predetermined sequence is 1; and reorders the m physical coding sublayer lanes, where m is an integer greater than 1.

[0118]

[0122] For technical effects that can be achieved by any aspect in the sixth aspect, please refer to the description of the advantageous effects in the second aspect, and the details will not be described again here.

[0119]

[0123] According to a seventh aspect, the present application provides a data processing method. The method includes: a first layer receiving fourth data from a third layer, the fourth data including k second predetermined sequences, where k is an integer greater than 1; the first layer determining synchronization lock loss based on the fourth data, and transmitting the fourth data to the third layer; the first layer including a first PMA sublayer or including a first PMA sublayer and a first FEC sublayer; and the third layer including a first PCS or including a first PCS and a first FEC sublayer.

[0120]

[0124] In a possible implementation, the first layer may further receive fifth data from the third layer, the fifth data including h second predetermined sequences, where h is greater than k.

[0121]

[0125] In a possible implementation, the first layer may receive fourth indication information from the third layer via the MDIO interface, the fourth indication information indicating that the third layer is in a synchronous out-of-lock state.

[0122]

[0126] For technical effects that can be achieved by any aspect in the seventh aspect, please refer to the description of the advantageous effects in the third aspect, and the details will not be described again here.

[0123]

[0127] According to a fourth aspect, the present application provides a data processing method, the method including: a second layer receiving sixth data from a first layer, determining a loss of synchronization lock based on the sixth data, and substituting a portion of data in the seventh data with a fourth predetermined sequence to obtain eighth data, the seventh data being received by the second layer from the fourth layer; the second layer transmitting the eighth data to the first layer and receiving ninth data from the first layer, the ninth data being substituting tenth data by the first layer; Part of the data inThe tenth data is obtained by replacing the fourth predetermined sequence with a fourth predetermined sequence, and the tenth data is received by the first layer from the third layer. The second layer detects the fourth predetermined sequence at least twice in the ninth data and replaces the fourth predetermined sequence in the eighth data with a fifth predetermined sequence to obtain eleventh data, the fifth predetermined sequence being different from the fourth predetermined sequence. The second layer transmits the eleventh data to the first layer and receives twelfth data from the first layer. The twelfth data is obtained by replacing the fourth predetermined sequence in the ninth data with a fifth predetermined sequence if the first layer detects at least two occurrences of the fourth predetermined sequence in the eighth data. The second layer detects at least two occurrences of the fifth predetermined sequence and determines synchronization lock. The first layer includes a first PMA sublayer or includes a first PMA sublayer and a first FEC sublayer; the second layer includes a second PMA sublayer or includes a second PMA sublayer and a second FEC sublayer; the third layer includes a first PCS or includes a first PCS and a first FEC sublayer; and the fourth layer includes a second PCS or includes a second PCS and a second FEC sublayer.

[0124]

[0128] Below, as an example, three possible ways of replacing a part of the data in the seventh data with the fourth predetermined sequence are shown.

[0125]

[0129] In a possible implementation, the seventh data includes P third code words, each of which includes a third information block and a third overhead block, where P is an integer greater than 1.

[0126]

[0130] Scheme 1: Replace the complete third codeword with a fourth predetermined sequence.

[0127]

[0131] In a possible implementation, the second layer replaces z third codewords in the P third codewords with a fourth predetermined sequence to obtain eighth data, where z is a positive integer less than or equal to P.

[0128]

[0132] Furthermore, the length of the fourth predetermined sequence is equal to a positive integer multiple of the code length of one third codeword.

[0129]

[0133] Scheme 2: The third overhead block in the third codeword is replaced with a fourth predetermined sequence.

[0130]

[0134] In a possible implementation, the second layer permutes the third overhead blocks in z third codewords in the P third codewords with a fourth predetermined sequence to obtain eighth data.

[0131]

[0135] Furthermore, the length of the fourth predetermined sequence is equal to or less than the length of one third information block.

[0132]

[0136] Scheme 3: Replace the third information block in the third codeword with a fourth predetermined sequence.

[0133]

[0137] In a possible implementation, the second layer permutes the third overhead blocks in z third codewords in the P third codewords with a fourth predetermined sequence to obtain eighth data.

[0134]

[0138] Furthermore, the length of the fourth predetermined sequence is less than or equal to the length of one third overhead block.

[0135]

[0139] In a possible implementation, the z third codewords are z consecutive or non-consecutive third codewords within the P third codewords. The intervals between the z non-consecutive third codewords may be the same. For example, one third codeword may be replaced by a first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the third information block within the third codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j may be a positive integer such as 1, 2, 3, or 4. Alternatively, the intervals between the z non-consecutive third codewords may be different. This is not a limitation in the present application.

[0136]

[0140] In a possible implementation, after the second layer detects at least two fifth predetermined sequences and determines synchronization lock, the second layer may send second indication information to the fourth layer via the indication signal path of the AUI or via the MDIO interface, and send thirteenth data to the fourth layer via the first data stream path of the AUI.

[0137]

[0141] In a possible implementation, after the second layer determines that synchronization lock has been lost based on the sixth data, the second layer may send first indication information to the fourth layer via the indication signal path of the AUI or via the MDIO interface, and send the sixth data to the fourth layer via the first data stream path of the AUI.

[0138]

[0142] In possible implementations, the second layer includes a second PMA sublayer or includes a second PMA sublayer and a second FEC sublayer; the fourth layer includes a second PCS or includes a second PCS and a fourth FEC sublayer; the first layer includes a first PMA sublayer or includes a first PMA sublayer and a first FEC sublayer; and the third layer includes a first PCS or includes a first PCS and a first FEC sublayer.

[0139]

[0143] For technical effects that can be achieved by any aspect in the eighth aspect, please refer to the description of the advantageous effects in the fourth aspect, and the details will not be described again here.

[0140]

[0144] According to a ninth aspect, the present application provides a communication device, the communication device comprising: a method according to the first aspect or any one of the possible implementations of the first aspect; a method according to the second aspect or any one of the possible implementations of the second aspect; a method according to the third aspect or any one of the possible implementations of the third aspect; a method according to the fourth aspect or any one of the possible implementations of the fourth aspect; a method according to the fifth aspect or any one of the possible implementations of the fifth aspect; a method according to the sixth aspect or any one of the possible implementations of the sixth aspect; A device configured to perform a method according to the seventh aspect or any one of the possible implementations of the seventh aspect, or a method according to the eighth aspect or any one of the possible implementations of the eighth aspect, and including corresponding functional modules individually configured to implement steps of said methods. The functions may be implemented by using hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to said functions.

[0141]

[0145] In a possible implementation, the communication device may be a second optical module. For advantageous effects, please refer to the description of the first aspect. Details will not be described again here. The communication device may include an interface circuit and a processor. The processor is configured to perform corresponding functions in the first aspect by logic circuits or by executing code instructions. The interface circuit is configured to receive signals from a communication device other than the communication device and transmit the signals to the processor; or to transmit signals from the processor to a device other than the communication device. The interface circuit may be an interface circuit that integrates receiving and transmitting functions. Optionally, the communication device may further include a memory. The memory may be coupled to the processor, and the memory stores program instructions and data required for the communication device.

[0142]

[0146] The interface circuit is configured to receive first data from the first optical module. The processor is configured to determine a loss of synchronous lock based on the first data. The interface circuit is configured to send first indication information to the second host and receive second data from the first communication device, the first indication information indicating that the second communication device is in a loss of synchronous lock state. The processor is further configured to determine a synchronous lock based on the second data and send second indication information to the second host, the second indication information indicating that the second optical module is in a synchronous lock state.

[0143]

[0147] In a possible implementation, the interface circuit is further configured to transmit third data to the second host, the third data being obtained by replacing a portion of data in the second data with a first predetermined sequence, the first predetermined sequence being for synchronization of the second host.

[0144]

[0148] In a possible implementation, the interface circuitry is specifically configured to transmit the third data to the second host via the first data stream path of the AUI.

[0145]

[0149] In a possible implementation, the interface circuitry is specifically configured to transmit the first data to the second host via a first data stream path of the AUI.

[0146]

[0150] In a possible implementation, the interface circuit is specifically configured to transmit the second instruction information to the second host via an instruction signal path of the AUI or via the MDIO interface.

[0147]

[0151] In a possible implementation, the second data includes N second code words, where N is an integer greater than 1; and the processor is further configured to permute w second code words among the N second code words with the first predetermined sequence to obtain the third data, where w is a positive integer less than or equal to N. Furthermore, w is a positive integer greater than 1 and less than or equal to N.

[0148]

[0152] In a possible implementation, the length of the first predetermined sequence is equal to a positive integer multiple of the code length of one second codeword.

[0149]

[0153] In a possible implementation, the second data includes N second code words, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; the processor is further configured to permute the first information blocks in w second code words among the N second code words with a first predetermined sequence to obtain the third data.

[0150]

[0154] In a possible implementation, the length of the first predetermined sequence is less than or equal to the length of one second information block.

[0151]

[0155] In a possible implementation, the second data includes N second code words, each of which includes a second information block and a second overhead block, where N is an integer greater than 1; and the processor is further configured to permute the second overhead blocks in w second code words among the N second code words with the first predetermined sequence to obtain the third data.

[0152]

[0156] In a possible implementation, the length of the first predetermined sequence is less than or equal to the length of one second overhead block.

[0153]

[0157] In a possible implementation, the w second codewords are w consecutive or non-consecutive second codewords within the N second codewords. The intervals between the w non-consecutive second codewords may be the same or different. For example, the second codeword may be permuted with a first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the second information block within the second codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j may be a positive integer such as 1, 2, 3, or 4.

[0154]

[0158] In a possible implementation, the second data may include a second predetermined sequence, and the processor is further configured to replace the second codeword with the first predetermined sequence from a boundary position of any second codeword within the N second codewords, and stop the replacement when detecting that the second predetermined sequence matches the second known predetermined sequence of the second optical module at least once, to obtain the third data.

[0155]

[0159] In a possible implementation, the second predetermined sequence is set to at least one subsequence in the AM group.

[0156]

[0160] In a possible implementation, the second data includes N second code words, where N is an integer greater than 1; the processor is specifically configured to decode the second data based on a sliding window using a predetermined number of bits when the predetermined number of bits is less than the code length of the second code words; after determining that the decoding has been successful at least once, perform decoding based on a sliding window using the code length of the second code words and collect statistics on the number of successful decodings among the second decoding results; and determine synchronization lock when it is determined that the number of successful decodings among the second decoding results is greater than a third threshold.

[0157]

[0161] In a possible implementation, the second data includes N second code words, the second code words including a second information block and a second overhead block, and the second overhead block including a third predetermined sequence; and the processor is specifically configured to determine synchronization lock when detecting, within a predetermined time window, a quantity of the third predetermined sequence greater than a fifth threshold.

[0158]

[0162] In a possible implementation, the first predetermined sequence is at least one subsequence in the AM group.

[0159]

[0163] In a possible implementation, the processor is specifically configured to decode the first data to obtain M first decoding results, where the first decoding results include successful decoding or failed decoding, and M is an integer greater than 1; and determine loss of synchronization lock when the number of failed decodings in the M first decoding results is greater than a first threshold.

[0160]

[0164] In a possible implementation, the first data includes Q first code words, the first code words including a first information block and a first overhead block, the first overhead block including a third predetermined sequence, Q being an integer greater than 1; and the processor is specifically configured to determine a synchronization lockout if it detects that the quantity of the third predetermined sequence is less than a fifth threshold within a predetermined time window.

[0161]

[0165] In a possible implementation, the interface circuit is configured to receive a third indication from the second host via the MDIO interface, the third indication indicating that the second host is in a synchronous out-of-lock state.

[0162]

[0166] In another possible implementation, the communication device may alternatively be a first optical module. The first optical module may include an interface circuit and a processor, and may perform the corresponding functions of the first optical module in the above-mentioned method example. For details, please refer to the detailed description in the method example. The details will not be described again here.

[0163]

[0167] In another possible implementation, the communication device may alternatively be a second host. The second host may include an interface circuit and a processor, and may perform the corresponding functions of the second host in the above-mentioned method example. For details, please refer to the detailed description in the method example. The details will not be described again here.

[0164]

[0168] According to a tenth aspect, the present application provides a communication device, the communication device comprising: a method according to the first aspect or any one of possible implementations of the first aspect; a method according to the second aspect or any one of possible implementations of the second aspect; a method according to the third aspect or any one of possible implementations of the third aspect; a method according to the fourth aspect or any one of possible implementations of the fourth aspect; a method according to the fifth aspect or any one of possible implementations of the fifth aspect; a method according to the sixth aspect or any one of possible implementations of the sixth aspect; A device configured to perform a method according to the seventh aspect or any one of the possible implementations of the seventh aspect, or a method according to the eighth aspect or any one of the possible implementations of the eighth aspect, and including corresponding functional modules individually configured to implement steps of said methods. The functions may be implemented by using hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to said functions.

[0165]

[0169] In a possible implementation, the communication device may be a second optical module. The second optical module may include a processing unit and a transceiver unit. These units may perform the corresponding functions of the second optical module in the above-described method example. For details, please refer to the detailed description in the method example. The details will not be described again here.

[0166]

[0170] In another possible implementation, the communication device may alternatively be a first optical module. The first optical module may include a transceiver unit and a processing unit. These units may perform the corresponding functions of the first optical module in the aforementioned method example. For details, please refer to the detailed description of the method example. The details will not be described again here.

[0167]

[0171] In another possible implementation, the communication device may alternatively be a second host. The second host may include a transceiver unit and a processing unit. These units may perform the corresponding functions of the second host in the above-mentioned method example. For details, please refer to the detailed description in the method example. The details will not be described again here.

[0168]

[0172] According to an eleventh aspect, the present application provides a communication system. The communication system includes a first optical module, a second optical module, and a second host. The second optical module may be configured to perform a method according to the first aspect or any one of possible implementations of the first aspect, the second host may be configured to perform a method according to the second aspect or any one of possible implementations of the second aspect, and the first optical module may be configured to perform a method according to the third aspect or any one of possible implementations of the third aspect. Alternatively, the communication system may include a first optical module and a second optical module. The second optical module may be configured to perform a method according to the fourth aspect or any one of possible implementations of the fourth aspect, and the first optical module may be configured to perform a method according to the fifth aspect or any one of possible implementations of the fifth aspect.

[0169]

[0173] According to a twelfth aspect, the present application provides a chip including at least one processor and an interface circuit. Optionally, the chip may further include a memory. The processor is configured to execute computer programs or instructions stored in the memory, thereby causing the chip to perform a method according to the first aspect or any one of its possible implementations, the second aspect or any one of its possible implementations, the third aspect or any one of its possible implementations, the fourth aspect or any one of its possible implementations, the fifth aspect or any one of its possible implementations, the sixth aspect or any one of its possible implementations, the seventh aspect or any one of its possible implementations, or the eighth aspect or any one of its possible implementations.

[0170]

[0174] According to a thirteenth aspect, the present application provides a computer-readable storage medium storing a computer program or instructions that, when executed by a communication device, enables the communication device to perform a method according to the first aspect or any one of possible implementations of the first aspect, a method according to the second aspect or any one of possible implementations of the second aspect, a method according to the third aspect or any one of possible implementations of the third aspect, a method according to the fourth aspect or any one of possible implementations of the fourth aspect, a method according to the fifth aspect or any one of possible implementations of the fifth aspect, a method according to the sixth aspect or any one of possible implementations of the sixth aspect, a method according to the seventh aspect or any one of possible implementations of the seventh aspect, or a method according to the eighth aspect or any one of possible implementations of the eighth aspect.

[0171]

[0175] According to a fourteenth aspect, the present application provides a computer program product. The computer program product includes computer programs or instructions that, when executed by a communications device, enable the communications device to perform a method according to the first aspect or any one of possible implementations of the first aspect, a method according to the second aspect or any one of possible implementations of the second aspect, a method according to the third aspect or any one of possible implementations of the third aspect, a method according to the fourth aspect or any one of possible implementations of the fourth aspect, a method according to the fifth aspect or any one of possible implementations of the fifth aspect, a method according to the sixth aspect or any one of possible implementations of the sixth aspect, a method according to the seventh aspect or any one of possible implementations of the seventh aspect, or a method according to the eighth aspect or any one of possible implementations of the eighth aspect.

[0172]

[0176] For the technical effects that can be achieved in any one of the ninth to fourteenth aspects, please refer to the description of the advantageous effects in the corresponding method, and the details will not be described again here. [Brief explanation of the drawings]

[0173] [Figure 1]

[0177] FIG. 1 is a diagram of the architecture of a communication system according to the present application. [Figure 2a]

[0178] FIG. 2a is a structural diagram of an optical module according to the present application. [Figure 2b]

[0179] FIG. 2b is a structural diagram of another optical module according to the present application. [Figure 2c]

[0180] FIG. 2c is a structural diagram of a host according to the present application. [Figure 3]

[0181] FIG. 3 is a diagram of communication between an optical module and a host according to the present application. [Figure 4]

[0182] FIG. 4 is a diagram of communication between optical modules according to the present application. [Figure 5]

[0183] FIG. 5 is a schematic flow chart of the method steps of the data processing method according to the present application. [Figure 6a]

[0184] FIG. 6a is a schematic flowchart of a method for acquiring first data by a first optical module according to the present application. [Figure 6b]

[0185] FIG. 6b is a schematic flow chart of another method for acquiring first data by a first optical module according to the present application. [Figure 7a]

[0186] FIG. 7a is a diagram of the structure of data sent by the host according to the present application. [Figure 7b]

[0187] FIG. 7b is a structural diagram of data obtained by inserting a second predetermined sequence according to the present application. [Figure 7c]

[0188] FIG. 7c is a structural diagram of data obtained by processing the data to be sent by the first host according to the present application. [Figure 7d]

[0189] FIG. 7d is a structural diagram of an AM subsequence according to the present application. [Figure 8a]

[0190] FIG. 8a is a structural diagram of the first data according to the present application. [Figure 8b]

[0191] FIG. 8b is another structural diagram of the first data according to the present application. [Figure 9]

[0192] FIG. 9 is a schematic flowchart of a synchronization state determination method according to the present application. [Figure 10]

[0193] FIG. 10 is a schematic flowchart of another synchronization determination method according to the present application. [Figure 11]

[0194] FIG. 11 is another structural diagram of the first data according to the present application. [Figure 12a]

[0195] FIG. 12a is a schematic flow chart of the method steps of another data processing method according to the present application. [Figure 12b]

[0196] FIG. 12b is a schematic flow chart of the method steps of another data processing method according to the present application. [Figure 13]

[0197] FIG. 13 is a schematic flow chart of the method steps of yet another data processing method according to the present application. [Figure 14]

[0198] FIG. 14 is a schematic flow chart of the method steps of another data processing method according to the present application. [Figure 15]

[0199] FIG. 15 is a schematic flow chart of the method steps of another data processing method according to the present application. [Figure 16]

[0200] FIG. 16 is a schematic flow chart of the method steps of another data processing method according to the present application. [Figure 17]

[0201] FIG. 17 is a structural diagram of a communication device according to the present application. [Figure 18]

[0202] FIG. 18 is a structural diagram of a communication device according to the present application. DETAILED DESCRIPTION OF THE INVENTION

[0174]

[0203] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0175]

[0204] 1 is a diagram of the architecture of a communication system to which the present application is applicable. The communication system may include a transmitting end 101 and a receiving end 102. Optionally, the transmitting end 101 may further include a first communication device 1011 and a third communication device 1012, and the third communication device 1012 may be referred to as a next-stage communication device of the first communication device 1011. The receiving end 102 may include a second communication device 1021 and a fourth communication device 1022. The fourth communication device 1022 may be referred to as a next-stage communication device of the second communication device 1021, and the second communication device 1021 may be referred to as a next-stage communication device of the first communication device 1011. The first communication device 1011 and the third communication device 1012 may be integrated or may be two independent physical entities. The second communication device 1021 and the fourth communication device 1022 may be integrated or may be two independent physical entities. The communication system may be, for example, an Ethernet communication system (both the transmitting end 101 and the receiving end 102 support the IEEE 802.3 Ethernet protocol), an optical transmission communication system, an optical access communication system, a 5th-generation (5G) fronthaul communication system, or another communication system that uses FEC coding.

[0176]

[0205] For example, the first communication device 1011 and the second communication device 1021 may both be optical modules. FIG. 2a is a structural diagram of an optical module according to the present application. The optical module may include a physical media dependent (PMD) sublayer and a physical medium attachment (PMA) sublayer. Furthermore, the PMA sublayer includes a unit capable of implementing the functions of an inner FEC sublayer. Alternatively, the functions of the inner FEC sublayer may be understood as being integrated into the PMA sublayer. FIG. 2b is a structural diagram of another optical module according to the present application. The optical module may include a PMD sublayer, a PMA sublayer, and an inner FEC sublayer. Alternatively, the inner FEC sublayer and the PMA sublayer may be understood as two independent sublayers.

[0177]

[0206] The third communication device 1012 and the fourth communication device 1022 may both be hosts, for example. Figure 2c is a diagram of the structure of a host according to the present application. The host may include a physical coding sublayer (PCS) and an inner FEC sublayer. Alternatively, the host may include a PCS, which includes a unit for performing the functions of the inner FEC sublayer.

[0178]

[0207] FIG. 3 is a diagram of communication between an optical module and a host according to the present application based on the foregoing content. The structure shown in FIG. 2b is used as an example of the structure of the optical module in this example. The optical module and the host can communicate with each other via an AUI between the PMA sublayer in the optical module and the PCS in the host. Furthermore, the AUI between the PMA sublayer in the optical module and the PCS in the host includes a first data stream path, a second data stream path, and an indication signal path (also referred to as a data validity indication signal path). The first data stream path is a path for the optical module to send data to the host, the second data stream path is a path for the host to send data to the optical module, and the indication signal path is a path for the optical module to send indication information to the host. The first data stream path is, for example, inst:IS_UNITDATA.indication. The second data stream path is, for example, inst:IS_UNITDATA.request. If the PCS is connected to the FEC sublayer at the next stage, the second data stream path in the AUI, inst:IS_UNITDATA.request, can be expressed as FEC:IS_UNITDATA.request. The indication signal path is, for example, inst:IS_SIGNAL.indication. Note that the AUI between the host and the optical module may also be referred to as a serializer / deserializer (SerDes) interface in product implementations. Furthermore, optionally, an MDIO interface may be included between the optical module and the host, and the optical module and the host may alternatively exchange indication information, data, or the like via the MDIO interface.The Optical Internetworking Forum (OIF), an international standardization organization, also calls the MDIO interface the common management interface specification (CMIS) interface. Generally, the MDIO interface is called the MDIO interface from the host side and the CMIS interface from the optical module side.

[0179]

[0208] FIG. 4 is a diagram of communication between optical modules according to the present application. In this example, the optical module at the transmitting end may be referred to as the first optical module, and the optical module at the receiving end may be referred to as the second optical module. The structure shown in FIG. 2b is used as an example of both the structure of the first optical module and the structure of the second optical module in this example. The first optical module and the second optical module may be connected to each other via a transmission medium (e.g., optical fiber, backplane, copper cable, or active optical cable). Specifically, the PMD sublayer in the first optical module may communicate with the PMD sublayer in the second optical module via the transmission medium. For example, the first optical module may load data to be transmitted onto an optical carrier, couple the data to be transmitted to an optical fiber, and transmit the data to be transmitted to the PMD sublayer in the second optical module via the optical fiber. Furthermore, the PMD sublayer may transmit the data to be transmitted to the PMA sublayer.

[0180]

[0209] It should be noted that the communications shown in Figure 3 or Figure 4 may be duplex communications independent of each other, or may be duplex communications using feedback, which is not limited in this application.

[0181]

[0210] The communication system may be used in several fields, for example in the field of augmented reality / virtual reality (AR / VR), in the field of artificial intelligence (AI), in the field of data centers or in the field of cloud applications.

[0182]

[0211] It should be noted that the system architecture described in this application is intended to more clearly explain the technical solutions in this application, and does not constitute limitations on the technical solutions provided in this application.

[0183]

[0212] As explained in the background section, currently used data synchronization methods require a long time and result in long data delays.

[0184]

[0213] In view of this, the present application provides a data processing method, which helps to shorten the data synchronization time.

[0185]

[0214] Based on the above, the data processing method provided in the present application will be described in detail below with reference to FIGS.

[0186]

[0215] To facilitate the description of the solution, the following description uses an example in which the second communication device is a second optical module, the first communication device is a first optical module, the third communication device is a first host, and the fourth communication device is a second host. In other words, in the following description, the first communication device may be replaced by a first optical module, the second communication device may be replaced by a second optical module, the third communication device may be replaced by a first host, and the fourth communication device may be replaced by a second host.

[0187]

[0216] Embodiment 1 5 is a schematic flowchart of the method steps of the data processing method according to the present application. The first optical module in the method may be the first communication device 1011 in FIG. 1, and the second optical module may be the second communication device 1021 in FIG. 1. For specific structures of the first optical module and the second optical module, please refer to the description of FIG. 2a or 2b. The method includes the following steps:

[0188]

[0217] Step 501: A first optical module transmits first data to a second optical module, and in response, the second optical module receives the first data from the first optical module.

[0189]

[0218] 4, the first optical module can transmit first data to the second optical module through a transmission medium. The data transmitted by the first optical module to the second optical module can be an optical signal, and the transmission medium can be called an optical lane. The second optical module can convert the received optical signal into an electrical signal, then convert the electrical signal into a digital signal, and then perform subsequent processing based on the digital signal.

[0190]

[0219] Regarding how the first optical module acquires the first data, please refer to the following description in Figures 6a and 6b, and the details will not be described here.

[0191]

[0220] Step 502: The second optical module determines a synchronization state based on the first data.

[0192]

[0221] The synchronization state includes synchronization out of lock or synchronization locked. If synchronization out of lock is determined, the following steps 503 to 505 are executed; or if synchronization locked is determined, the second optical module sends second indication information to the second host.

[0193]

[0222] Loss of synchronization lock may also be referred to as data misalignment, data block misalignment, codeword boundary misalignment, inner codeword boundary misalignment, Hamming codeword boundary misalignment, or the like. Because the second optical module performs synchronization based on an inner codeword, loss of synchronization lock may also be referred to as inner codeword lock loss, inner codeword synchronization loss, or the like. Synchronization lock may also be referred to as data alignment, data block alignment, codeword boundary alignment, inner codeword lock, inner codeword synchronization lock, Hamming codeword boundary alignment, or the like.

[0194]

[0223] For the process by which the second optical module determines the synchronization state based on the first data, please refer to the descriptions of possible implementation 1 (FIG. 9) and implementation 2 (FIG. 10) below.

[0195]

[0224] Step 503: The second optical module sends the first instruction information to the second host, and in response, the second host receives the first instruction information from the second optical module.

[0196]

[0225] The first indication indicates that the second optical module is in a synchronous out-of-lock state.

[0197]

[0226] 3, in a possible implementation, the second optical module can transmit the first indication information to the second host via an indication signal path of the AUI, which may be, for example, inst:IS_SIGNAL.indication. In another possible implementation, the second optical module may alternatively transmit the first indication information to the second host via an MDIO interface (also called a CMIS interface).

[0198]

[0227] The specific format of the first indication information may be specified in the protocol or may be negotiated in advance between the second optical module and the second host, which is not limited in the present application. For example, the first indication information is represented by using “0”.

[0199]

[0228] Step 504: The first optical module transmits the second data to the second optical module, and in response, the second optical module receives the second data from the first optical module.

[0200]

[0229] The second data and the first data belong to the same data stream. In other words, the first optical module transmits a data stream to the second optical module, where the first data and the second data are two parts of data in the data stream. It should be noted that the manner in which the first optical module obtains the second data is the same as the manner in which the first optical module obtains the first data. For details, please refer to the following description of Figures 6a and 6b. Details will not be described here.

[0201]

[0230] It should be noted that the above steps 503 and 504 are not in sequence. Step 503 may be performed before step 504, or step 504 may be performed before step 503, or steps 503 and 504 may be performed simultaneously. Figure 5 is just a possible example.

[0202]

[0231] Step 505: The second optical module determines synchronization lock based on the second data, and sends second indication information to the second host.

[0203]

[0232] The second indication information indicates that the second optical module is in a synchronous lock state. It should be noted that the specific format of the second indication information may be specified in the protocol or may be negotiated in advance between the second optical module and the second host. This is not limited in the present application. For example, the second indication information is expressed by using “1”.

[0204]

[0233] 3, in a possible implementation, the second optical module can transmit the second indication information to the second host via an indication signal path of the AUI, which may be, for example, inst:IS_SIGNAL.indication. In another possible implementation, the second optical module may alternatively transmit the second indication information to the second host via an MDIO interface (also called a CMIS interface).

[0205]

[0234] In a possible implementation, the second optical module may first perform synchronization based on the second data until synchronization lock is achieved. The second data may include N second codewords, where N is an integer greater than 1. The second codeword may be, for example, an FEC codeword. The structure of the FEC codeword may be (N, K, m), where N is the number of bits included in the code length of the FEC codeword, K is the number of bits included in the information bits, and m is the order of the Galois field in which the FEC codeword is located. The value of m is not considered in this application. For ease of explanation of the solution, the FEC codeword is then expressed by using (N, K). Specifically, the FEC codeword may include, but is not limited to, a Hamming codeword or a Bose, Ray-Chaudhuri, and Hocquenghem (BCH) codeword. The Hamming codeword may include, but is not limited to, a Hamming codeword (128,120) or a Hamming codeword (180,170).

[0206]

[0235] Specifically, the second optical module may decode the second data based on a sliding window using a predetermined number of bits, where the predetermined number of bits is smaller than the code length of the second codeword included in the second data. After determining that the decoding has been successful at least once, the second optical module may perform decoding based on a sliding window using the code length of the second codeword and collect statistics on the number of second decoding results (including successful decoding and unsuccessful decoding); if the number of successful decoding results in the second decoding results is greater than a third threshold, the second optical module may determine synchronization lock; or if the number of unsuccessful decoding results in the second decoding results is greater than a fourth threshold, the second optical module may determine synchronization lock loss and continue to perform synchronization based on new data received from the first optical module (i.e., another portion of data belonging to the same data stream as the first data and the second data).

[0207] Furthermore, the second decoding result may be a decoding success identifier or a decoding failure identifier output by the decoder, or may be an intermediate parameter (also called a syndrome) generated in the decoding process. For example, the second decoding result may be expressed using 8 bits. 00000000 indicates a decoding success. If a non-zero bit appears among the 8 bits, it indicates a decoding failure. Alternatively, the second decoding result may be expressed in another format that can distinguish between a decoding success and a decoding failure. This is not limited in the present application. When the second decoding result is a decoding success identifier or a decoding failure identifier output by the decoder, statistics may be collected regarding whether the number of decoding success identifiers is greater than a third threshold and whether the number of decoding failure identifiers is greater than a fourth threshold. If the second decoding result is a syndrome generated in the decoding process, statistics may be collected regarding whether the number of cases where the 8 bits are all zero is greater than a third threshold, and whether the number of cases where there is a non-zero bit in the 8 bits is greater than a fourth threshold.

[0208]

[0236] For example, the length of the second data is x × 128 bits, where x is an integer greater than or equal to 2. For example, the code length of the second codeword included in the second data is 128 bits. For example, the predetermined number of bits is 1. One decoder A is used as an example. Specifically, the 0th to 127th bits of the second data are input to decoder A. Then, decoding is performed based on a 1-bit sliding window. That is, the 1st to 128th bits are input to decoder A next time. The remaining bits can be estimated by analogy. Until decoding is successful at least once, decoding is performed based on a sliding window using the code length (128 bits) of the second codeword, and statistics on the number of second decoding results (including decoding successes and decoding failures) begin to be collected.

[0209] For example, the 0th to 127th bits of the second data are input to decoder A, and decoder A outputs a decoding failure; Then, the 1st to 128th bits are input to decoder A, and decoder A outputs a decoding failure; Then, the 2nd to 129th bits are input to decoder A, and decoder A outputs a decoding failure; Next, the 3rd to 130th bits are input to decoder A, which outputs a decoding success. Statistics about the second decoding results are collected. For example, the number of successful decodings in the second decoding results may be recorded as 1 (or 0). Then, the 131st to 258th bits are input to decoder A. Decoding is performed based on a 128-bit sliding window. The rest can be inferred by analogy to obtain H second decoding results. If decoder A outputs successful decoding, it can be understood that this indicates that one complete second codeword in one second data has been input to decoder A. In other words, the 3rd to 130th bits correspond to the complete second codeword, which indicates that the 0th to 255th bits are lost in the process of the first optical module transmitting the second data to the second optical module.

[0210]

[0237] Using two decoders (decoder B and decoder C) as an example, the 0th to 127th bits of the second data are input to decoder B, the 1st to 128th bits are input to decoder C, the 2nd to 129th bits are input to decoder B, the 3rd to 130th bits are input to decoder C, and so on. The bits input to decoder B are decoded based on a 1-bit sliding window. Until the decoding is successful at least once, decoding is performed based on a 128-bit sliding window, and statistics on the second decoding results are started to be collected. The bits input to decoder C are decoded based on a 1-bit sliding window. Until the decoding is successful at least once, decoding is performed based on a 128-bit sliding window, and statistics on the second decoding results are started to be collected. The H second decoding results obtained by decoding the second data are the sum of the number of second decoding results of decoder B and the number of second decoding results of decoder C.

[0211]

[0238] 3, in a possible implementation, the second optical module can send second indication information to the second host via an indication signal path of the AUI, and the indication signal path may be, for example, inst:IS_SIGNAL.indication. In another possible implementation, the second optical module may send the second indication information to the second host via the MDIO interface.

[0212]

[0239] It can be known from the above steps 501 to 505 that after determining the synchronization lock out, the second optical module sends first indication information to the second host, indicating that the second optical module is in a synchronization lock out state, so that the second host can determine that the first data is invalid data, which helps to reduce the calculation overhead of the second host. Furthermore, after determining the synchronization lock, the second optical module sends second indication information to the second host, indicating that the second optical module is in a synchronization lock state, so that the second host can quickly start (or enter) the synchronization process without waiting for a long time, which helps to shorten the data synchronization duration of the second host and helps to shorten the waiting delay of the communication system.

[0213]

[0240] Below, two possible ways for the first optical module to obtain the first data are given as examples.

[0214]

[0241] Method a: The first optical module is not synchronized with the data A from the first host.

[0215]

[0242] 6a is a schematic flowchart of a method for acquiring first data by a first optical module according to the present application. The method includes the following steps:

[0216]

[0243] Step 601: The first host processes the data a to be transmitted and obtains the data A.

[0217]

[0244] In a possible implementation, the first host performs insertion of a second predetermined sequence (see FIG. 7b), interleaving, encoding, etc. on data a (see FIG. 7a) to obtain data A (see FIG. 7c). It can be understood that the processing performed by the first host on data a may further include Gray mapping, etc. This is not limited in the present application.

[0218]

[0245] For example, the second predetermined sequence may be at least one sub-sequence in the AM group. To facilitate the description of the solution, the following description will be given by using an example in which the second predetermined sequence is an AM sub-sequence.

[0219]

[0246] Specifically, for each physical coding sublayer lane, a corresponding AM subsequence can be inserted into data a, where one physical coding sublayer lane corresponds to one AM subsequence. For example, for physical coding sublayer lane D0, an AM0 subsequence is inserted into data a; for physical coding sublayer lane D1, an AM1 subsequence is inserted into data a, and so on. An AM subsequence is a sequence within an AM group, where the AM group includes an AM0 subsequence, an AM1 subsequence, ...

[0220]

[0247] Figure 7d shows the structure of an AM subsequence according to the present application. The AM subsequence includes a common marker (CM) and a unique marker (UM). The CM is the first half of the AM subsequence and is used for AM lock and deskew. The UM is the second half of the AM subsequence and is used for physical coding sublayer lane reordering.

[0221]

[0248] Furthermore, the interval between two adjacent AM subsequences may be equal to the total number of codewords for m physical sublayer lanes × the length of one codeword / the number of physical sublayer lanes, m. For example, for each physical coding sublayer lane, an AM subsequence is inserted once every 8192 × 5440 / 16 bits, where 8192 represents the total number of codewords for 16 physical sublayer lanes, 5440 represents the length of one codeword, and 16 represents the number of physical sublayer lanes.

[0222]

[0249] Referring to Figure 2c, 100GE Ethernet encoding is used as an example. Data a from clients at the media access control (MAC) layer and higher layers passes through the reconciliation sublayer. The reconciliation sublayer converts data a from clients at the MAC layer and higher layers and transmits the converted data a to the 100GBASE-R physical coding sublayer (PCS) via a 100 Gbit / s media independent interface (CGMII). Operations such as AM insertion on data a are performed in the PCS, and the processed data a is sent to the internal FEC sublayer for encoding. The internal FEC sublayer may be, for example, a Reed-Solomon forward error correction (RS-FEC) encoder. The RS-FEC encoder in 100GE Ethernet uses one RS (544,514,10) codeword.

[0223]

[0250] The 200GE Ethernet encoding scheme is used as an example. Data a from clients at the MAC layer and higher layers passes through the conditioning sublayer. The conditioning sublayer converts data a from clients at the MAC layer and higher layers and sends the converted data a to the 200GBASE-R PCS via the 200GMII. Operations such as AM insertion on the data are performed in the PCS, and the processed data a is sent to the RS-FEC encoder for encoding. The 200GE Ethernet RS-FEC encoder uses two RS (544, 514, 10) codewords, and data from the PCS is sent to the two RS codewords in a 10-bit round-robin distribution fashion.

[0224]

[0251] The 400GE Ethernet encoding scheme is used as an example. Data from clients at the MAC layer and higher layers passes through the conditioning sublayer. The conditioning sublayer converts data a from clients at the MAC layer and higher layers and sends the converted data a to the 400GBASE-R PCS via the 400GMII. Operations such as AM insertion on data a are performed in the PCS, and the processed data a is sent to the RS-FEC encoder for encoding. The 400GE Ethernet RS-FEC encoder uses two RS (544, 514, 10) codewords, and data a from the PCS is sent to the two RS codewords in a 10-bit round-robin distribution fashion.

[0225]

[0252] The above provides an example in which RS coding is used in 100GE, 200GE, and 400GE Ethernet coding schemes in PCS. When Ethernet evolves to 800GE, the single wavelength rate increases from 100 Gbps in 400GE to 200 Gbps, and coding may alternatively be implemented in a different scheme. The coding scheme is not limited in this application.

[0226]

[0253] The interleaving may be performed by an interleaver, for example an interleaver with a π e The interleaver π can be expressed as e may be an interleaver consisting of a multiplexer (Mux) and a 10-bit symbol distribution.

[0227]

[0254] Step 602: The first host transmits data A to the first optical module. In response, the first optical module receives data A from the first host.

[0228]

[0255] In a possible implementation, the first host may transmit data A to the first optical module via the second data stream path of the AUI. In response, the first optical module may receive data A from the first host via the second data stream path of the AUI. Alternatively, the first host may transmit data A to the first optical module via the MDIO interface. In response, the first optical module may receive data A from the first host via the CMIS interface.

[0229]

[0256] Step 603: The first optical module processes the data A to obtain first data.

[0230]

[0257] Specifically, the first optical module performs encoding, interleaving, and other processing on data A to obtain first data. Here, it is possible to refer to the above-mentioned processing performed by the first host on data a. Specifically, it is sufficient to replace "data a" with "data A". The details will not be described again here.

[0231]

[0258] See FIG. 8A for the structure of the first data acquired based on the above steps 601 to 603. The first data includes Q first code words, where Q is an integer greater than 1. The first code word includes a first information block and a first overhead block. The first information block is for carrying valid data and may be referred to as data bits. The first overhead block is for correctly recovering the data and may be referred to as parity bits. The first overhead block is usually added after the first optical module encodes the valid data. Alternatively, it can be understood that the AM subsequence in the first data acquired by the first optical module based on the above scheme a is spread for distribution.

[0232]

[0259] Method b: The first optical module performs synchronization based on data A from the first host.

[0233]

[0260] 6b is a schematic flowchart of another method for acquiring first data by a first optical module according to the present application. The method includes the following steps:

[0234]

[0261] Step 611: The first host processes the data a to be transmitted to obtain the data A.

[0235]

[0262] For step 611, please refer to the above description of step 601. The details will not be described again here.

[0236]

[0263] Step 612: The first host transmits data A to the first optical module. In response, the first optical module receives data A from the first host.

[0237]

[0264] For step 612, please refer to the description of step 602 above. The details will not be repeated here.

[0238]

[0265] Step 613: The first optical module performs synchronization based on the data A.

[0239]

[0266] Specifically, for each physical coding sublayer lane, if it is determined that the CM in the AM subsequence (i.e., the second predetermined sequence) in data A matches at least once with the CM in the known AM subsequence of the first optical module, synchronization lock is determined. Referring to Figure 7d, physical coding sublayer lane D0 is used as an example. If it is detected that the CM in the AM0 subsequence in data A matches at least once with the AM in the known AM0 subsequence of the first optical module, synchronization lock is determined. The symbol (10-bit) boundaries of the RS codeword on the first host side are aligned. The AM subsequence is inserted at the RS symbol boundary, so that finding the AM subsequence is equivalent to finding the RS symbol boundary, and subsequent processing can be performed based on the length of the RS symbol.

[0240]

[0267] It can be seen that during synchronization, the first optical module will not send valid data to the second optical module until the first optical module is in a synchronous locked state.

[0241]

[0268] It should be noted that if the first optical module cannot perform synchronization based on data A, the first optical module may return data A to the first host. In response, the first host receives data A from the first optical module and decodes data A. If the first host fails to decode data A, it indicates that the AUI between the first host and the first optical module is faulty. If the first host successfully decodes data A, it indicates that the first optical module is faulty in the synchronization process. Furthermore, AM subsequences may be inserted more densely into data a for the first optical module to perform synchronization. For example, if an AM0 subsequence is inserted into data a once every 8192×5440 / 16 bits in the aforementioned step 611, the more dense insertion may be to insert an AM0 subsequence once every 8192×5440 / 16 bits.

[0242]

[0269] Step 614: The first optical module determines synchronization lock, and processes the data A to obtain the first data.

[0243]

[0270] Specifically, the first optical module removes the AM subsequence (i.e., the second predetermined sequence) from data A; interleaves the data A obtained by removing the AM subsequence; then, after interleaving, re-inserts the removed AM subsequence to obtain data B; and performs encoding and other operations on data B to obtain the first data. Alternatively, it can be understood that if the processing performed by the first optical module on data A includes interleaving, the AM subsequence skips the interleaver, so that the AM subsequence is not distributed. It can be understood that the AM subsequence is a fixed sequence both before and after encoding.

[0244]

[0271] Please refer to Fig. 8b for the structure of the first data acquired based on the above steps 611 to 614. In other words, based on the above scheme b, the AM subsequence in the first data acquired by the first optical module is not spread and is completely distributed within the data.

[0245]

[0272] Below, as examples, two possible implementations are given in which the second optical module determines the synchronization status based on the first data.

[0246]

[0273] Implementation 1: The second optical module determines the synchronization status based on the first decoding result.

[0247]

[0274] 9 is a schematic flowchart of a synchronization status determination method according to the present application, which includes the following steps:

[0248]

[0275] Step 901: The second optical module decodes the first data to obtain M first decoding results.

[0249]

[0276] In a possible implementation, the first data may include Q first codewords. The first codewords may be, for example, FEC codewords. For the structure of the FEC codewords, please refer to the related description above. The details will not be described again here.

[0250]

[0277] The first decoding result may include a successful decoding or a failed decoding. Specifically, each time a first codeword is input to the decoder, the decoder outputs a first decoding result for the first codeword. For example, the first codeword may be a Hamming codeword (128,120). Every 128 bits are used as a first codeword input to the decoder for decoding, and the decoder outputs a first decoding result for the first codeword. By analogy, statistics on the M first decoding results may be collected by decoding the first data.

[0251]

[0278] Step 902: If the second optical module determines that the quantity of decoding failures in the M first decoding results is greater than a first threshold, the second optical module determines that synchronization is out of lock.

[0252]

[0279] Step 903: If the second optical module determines that the quantity of successful decoding in the M first decoding results is greater than a second threshold, the second optical module determines synchronization lock.

[0253]

[0280] The second threshold is different from the first threshold. For example, the first threshold may be, for example, M×90% rounded up, and the second threshold may be, for example, M×50% rounded up. It should be noted that the specific values ​​of the first threshold and the second threshold are not limited in the present application.

[0254]

[0281] In a possible implementation, the first decoding result may be a decoding success identifier or a decoding failure identifier output by the decoder, or may be an intermediate parameter (also called a syndrome) generated in the decoding process. For example, the first decoding result may be expressed using 8 bits. 00000000 indicates a decoding success. If a non-zero bit appears among the 8 bits, it indicates a decoding failure. Alternatively, the first decoding result may be expressed in another format that can distinguish between a decoding success and a decoding failure. This is not limited in the present application. If the first decoding result is a decoding success identifier or a decoding failure identifier output by the decoder, statistics may be collected regarding whether the number of decoding success identifiers is greater than a first threshold and whether the number of decoding failure identifiers is greater than a second threshold. If the first decoding result is a syndrome generated in the decoding process, statistics may be collected regarding whether the number of cases where the 8 bits are all 0 is greater than a first threshold, and whether the number of cases where there is a non-zero bit in the 8 bits is greater than a second threshold.

[0255]

[0282] Furthermore, to improve the accuracy of the determined decoding success or decoding failure, the following is performed:

[0256] For example, the code length of the first codeword is 128 bits. The last bit of the 128 bits in each first codeword in the first data may be obtained by performing a first operation on the first 127 bits. After the decoder outputs a first decoding result indicating successful decoding, the first operation may be further performed on the first 127 bits of the 128 bits to determine whether the bit obtained in the operation result matches the last bit of the 128 bits input to the decoder. If the two match, it is determined that the decoding is successful; or if the two do not match, it is determined that the decoding is unsuccessful.

[0257] In another example, the code length of the first codeword is 128 bits. The last three bits of the 128 bits in each first codeword in the first data may be obtained by performing a first operation on the first 125 bits. After the decoder outputs a first decoding result indicating successful decoding, the first operation may be further performed on the first 125 bits of the 128 bits to determine whether the three bits obtained in the operation result match the last three bits of the 128 bits input to the decoder. If the two match, it is determined that the decoding is successful; alternatively, if the two do not match, it is determined that the decoding is unsuccessful.

[0258] In another example, the code length of the first codeword is 180 bits. The last two bits of the 180 bits in each first codeword in the first data may be obtained by performing a first operation on the first 178 bits. After the decoder outputs a first decoding result indicating successful decoding, the first operation may be further performed on the first 178 bits of the 180 bits to determine whether the two bits obtained in the operation result match the last two bits of the 180 bits input to the decoder. If the two match, it is determined that the decoding is successful; or, if the two do not match, it is determined that the decoding failed. The method of the first operation between the first optical module and the second optical module may be negotiated in advance or stored in advance. This is not a limitation in the present application.

[0259]

[0283] It should be noted that the above steps 902 and 903 do not show a sequence: if step 902 is performed, step 903 is not performed; alternatively, if step 903 is performed, step 902 is not performed.

[0260]

[0284] Implementation 2: The second optical module determines synchronization depending on whether a first overhead block (also called overhead, OH) in a first codeword included in the first data includes a third predetermined sequence.

[0261]

[0285] The predetermined sequence in this application is a sequence having a fixed length or bit value, and is known to both the receiving side and the transmitting side. For example, the third predetermined sequence may be an AM subsequence.

[0262]

[0286] 10 is a schematic flowchart of another synchronization determination method according to the present application. The method includes the following steps:

[0263]

[0287] Step 1001: The second optical module detects whether the quantity of the third predetermined sequence contained in the first data is greater than or equal to a fifth threshold within a predetermined time window; if the quantity is greater than the fifth threshold, the second optical module performs step 1002; or if the quantity is less than the fifth threshold, the second optical module performs step 1003.

[0264]

[0288] FIG. 11 is another structural diagram of the first data into which the third predetermined sequence according to the present application is inserted. In this example, the structure shown in FIG. 8A is used as an example of the structure of the first data. For example, the length of one first codeword is 128 bits. The first 120 bits are the first information block, and 8 bits are the first overhead block. The third predetermined sequence occupies a portion of the bits in the first overhead block. For example, the third predetermined sequence may be three bits, such as 001, 100, or 010. For example, the last three bits in the first overhead block are the third predetermined sequence. In another example, the first three bits in the first overhead block are the third predetermined sequence. It can be understood that the third predetermined sequence may occupy any three bits in the first overhead block. For example, the third predetermined sequence may alternatively be two bits, such as 01 or 10. For example, the last two bits in the first overhead block are the third predetermined sequence. Furthermore, the third predetermined sequence may alternatively be more or less than three bits. This is not a limitation in the present application.

[0265]

[0289] There is a correlation between the predetermined time window and the fifth threshold. For example, the predetermined time window may be, for example, 200 nanoseconds (ns), and the corresponding fifth threshold may be, for example, 128 times. For another example, the predetermined time window may be, for example, 100 ns, and the corresponding fifth threshold may be, for example, 64 times. Furthermore, the predetermined number of bits is equal to the product of the predetermined time window and the transmission rate.

[0266]

[0290] Step 1002: The second optical module determines synchronization lock.

[0267]

[0291] Step 1003: The second optical module determines whether the synchronization is out of lock.

[0268]

[0292] Through the aforementioned steps 1001 to 1003, the third predetermined sequence occupies a portion of the bits in the first overhead block without increasing the amount of data to be transmitted. Furthermore, the first overhead block is added after the first optical module encodes the useful data. Therefore, the second optical module can determine whether synchronization is performed based on the amount of the third predetermined sequence included in the first data without decoding the first data. Implementation is simple.

[0269]

[0293] Based on how the first module obtains the first data, two different data processing methods are provided below as examples.

[0270]

[0294] Method 1: The first optical module acquires the first data according to the above method a.

[0271]

[0295] 12a is a schematic flowchart of the method steps of another data processing method according to the present application. The method mainly includes data processing on the second optical module side. The method includes the following steps:

[0272]

[0296] Step 1201: A first optical module transmits first data to a second optical module, and in response, the second optical module receives the first data from the first optical module.

[0273]

[0297] In this example, the first optical module acquires the first data by the above-mentioned method a. For step 1201, please refer to the above-mentioned description of step 501. The details will not be described again here.

[0274]

[0298] Step 1202: The second optical module determines a synchronization state based on the first data.

[0275]

[0299] If it is determined that the synchronization is out of lock, the following steps 1203 to 1206 are executed; otherwise, if the second optical module is in a synchronization lock state, the following step 1208 is executed.

[0276]

[0300] For step 1202, please refer to the description of step 502 above. The details will not be described again here.

[0277]

[0301] Step 1203: The second optical module transmits the first instruction information and the first data to the second host, and in response, the second host receives the first instruction information and the first data from the second optical module.

[0278]

[0302] In a possible implementation, the second optical module is capable of transmitting first instruction information to the second host via an instruction signal path of the AUI or via the MDIO interface, and is capable of transmitting first data to the second host via a first data stream path of the AUI.

[0279]

[0303] The second optical module can transmit the first data to the second host via the first data stream path of the AUI. For a detailed description of the second optical module transmitting the first indication information to the second host, please refer to the description of step 503 above. The details will not be described again here.

[0280]

[0304] The second optical module transmits first indication information to the second host, indicating that the second optical module is in an out-of-sync state, and notifies the second host that the first data is invalid. Therefore, after receiving the first indication information, the second host may determine that the first data is invalid and further discard the first data.

[0281]

[0305] Step 1204: The first optical module transmits the second data to the second optical module, and in response, the second optical module receives the second data from the first optical module.

[0282]

[0306] For step 1204, please refer to the description of step 504 above, and the details will not be described again here.

[0283]

[0307] Step 1205: The second optical module performs synchronization based on the second data.

[0284]

[0308] For step 1205, please refer to the description of step 505 above. The details will not be described again here.

[0285]

[0309] Step 1206: The second optical module determines synchronization lock and replaces (in other words, overwrites, updates, modifies, or the like) a portion of the data in the second data with the first predetermined sequence to obtain third data.

[0286]

[0310] In a possible implementation, the second data includes N second code words, and the second code words include a second information block and a second overhead block.

[0287]

[0311] Below, three possible ways of obtaining the third data are shown as examples.

[0288]

[0312] Scheme A: Substitute the complete second codeword with the first predetermined sequence.

[0289]

[0313] In a possible implementation, on each physical coding sublayer lane, w second codewords among the N second codewords are replaced with the first predetermined sequence, where w is a positive integer not greater than N. Furthermore, w is a positive integer greater than 1 and not greater than N. If w is greater than 2, it can further avoid a case where the second host cannot accurately determine the synchronization state because a portion of the second data is lost in the transmission process. In other words, if w is greater than 2, it helps improve the synchronization accuracy of the second host.

[0290]

[0314] Furthermore, optionally, the length of the first predetermined sequence is equal to a positive integer multiple of the code length of one second codeword. For example, the code length of the second codeword is 128 bits, and the length of the first predetermined sequence is also 128 bits. In another example, the code length of the second codeword is 128 bits, and the length of the first predetermined sequence is 2 x 128 bits.

[0291]

[0315] The complete second codeword is replaced with the first predetermined sequence, so that the second host can quickly determine the boundaries of each second codeword in the received second data. In this way, the duration required for synchronization can be shortened, and the complexity of the synchronization operation on the second host side can be reduced.

[0292]

[0316] Scheme B: The second overhead block in the second codeword is replaced with the first predetermined sequence.

[0293]

[0317] In a possible implementation, on each physical coding sublayer lane, second overhead blocks in w second codewords among the N second codewords are permuted with a first predetermined sequence.

[0294]

[0318] Further, optionally, the length of the first predetermined sequence is equal to or less than the length of the second overhead block, for example, the code length of the second codeword may be 128 bits, the length of the second information block may be 120 bits, the length of the second overhead block may be 8 bits, and the length of the first predetermined sequence may be 8 bits.

[0295]

[0319] The second overhead block in the second codeword is replaced with the first predetermined sequence, so that normal transmission of valid data should not be affected. Furthermore, if the length of the first predetermined sequence is equal to the length of the second overhead block, the second host can quickly determine the boundary of the second codeword in the received second data, thereby reducing the duration required for synchronization.

[0296]

[0320] Scheme C: The second information block in the second codeword is replaced with the first predetermined sequence.

[0297]

[0321] In a possible implementation, on each physical coding sublayer lane, the second information blocks in w second codewords among the N second codewords are replaced with a first predetermined sequence.

[0298]

[0322] Further, optionally, the length of the first predetermined sequence is equal to or less than the length of the second information block in the second codeword (e.g., the code length of the second codeword is 128 bits, the length of the second information block is 120 bits, the length of the second overhead block is 8 bits, and the length of the first predetermined sequence is 120 bits).

[0299]

[0323] When the second overhead block needs to be discarded at the second optical module side, the second information block is replaced with the first predetermined sequence, so that the second host performs synchronization based on the first predetermined sequence, which helps to reduce the duration required for synchronization of the second host.

[0300]

[0324] It should be noted that the w second codewords to be replaced can be any w second codewords among the N second codewords, and the w second codewords can be w consecutive or non-consecutive second codewords. This is not limited in the present application. The intervals between the w non-consecutive second codewords can be the same. Furthermore, the second codewords can be replaced with a first predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the second information block in the second codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j can be a positive integer such as 1, 2, 3, or 4.

[0301] For example, L=170 bits and PCSL=16. The second codeword may be replaced with the first predetermined sequence every 2×1×5440 / 16 / 170=4 second codewords. In another example, L=120 bits and PCSL=16. The second codeword may be replaced with the first predetermined sequence every 2×3×5440 / 16 / 120=17 second codewords. Alternatively, the intervals between w non-consecutive second codewords may be different. This is not a limitation in the present application.

[0302]

[0325] Step 1207: The second optical module sends the second instruction information and the third data to the second host.

[0303]

[0326] In a possible implementation, the second optical module may transmit second instruction information to the second host via the instruction signal path of the AUI or via the MDIO interface, and may transmit third data to the second host via the first data stream path of the AUI.

[0304]

[0327] The second optical module transmits second indication information to the second host, indicating that the second optical module is in a synchronous lock state, and notifying the second host that the third data is valid data.

[0305]

[0328] Step 1208: The second optical module sends the second instruction information and the first data to the second host.

[0306]

[0329] For step 1208, please refer to the above description of step 1207. The details will not be described again here.

[0307]

[0330] Through the above steps 1201 to 1208, it is possible to reduce the duration required for data synchronization without increasing the bandwidth of the communication system.

[0308]

[0331] 12b is a schematic flowchart of the method steps of another data processing method according to the present application. The method mainly includes data processing on the second host side. The method includes the following steps:

[0309]

[0332] Step 1211: The second host detects the indication information through the AUI or MDIO interface.

[0310]

[0333] In a possible implementation, when the second host detects the second indication information via inst:IS_SIGNAL.indication of the AUI and receives the third data from the first optical module via inst:IS_UNITDATA.indication of the AUI, the second host performs the following steps 1212 and 1213. When the second host detects the first indication information via inst:IS_SIGNAL.indication of the AUI and receives the first data from the second optical module via inst:IS_UNITDATA.indication of the AUI, the second host determines that the first data is invalid data.

[0311]

[0334] Step 1212: The second host performs synchronization based on the third data.

[0312]

[0335] In the process of the second optical module transmitting the third data to the second host, a part of the data in the third data may be lost. Therefore, after receiving the third data, the second host may first perform synchronization based on the third data.

[0313]

[0336] In a possible implementation, the synchronization of the second host involves four processes: Process 1: Alignment marker (AM) lock.

[0314] Process 2: Lane deskew.

[0315] Process 3: Determine whether the lane reorder condition is met.

[0316] Process 4: Lane reorder.

[0317]

[0337] Process 1: AM Lock

[0338] For each physical coding sublayer lane (i.e., within a lane), using physical coding sublayer lane D0 as an example, if the first host inserts an AM0 subsequence into the second data and the first predetermined sequence is also an AM0 subsequence, the second host may recover the second predetermined sequence through de-interleaving. If a CM in the AM0 subsequence is detected in the third data to match a CM in the second host's known AM0 subsequence at least twice consecutively, the second host determines that AM lock is achieved in physical coding sublayer lane D0. It can be understood that if 16 physical coding sublayer lanes are included, process 1 needs to be performed for each physical coding sublayer lane until AM lock is achieved for all 16 physical coding sublayer lanes, which indicates that the second host has achieved AM lock. It should be noted that the second host's known AM0 subsequence may be pre-stored, which is not a limitation in the present application.

[0318]

[0339] If the first host inserts an AM0 subsequence into the second data and the first predetermined sequence is not an AM0 subsequence, the second host detects at least one time in the third data that the first predetermined sequence matches the second host's first known predetermined sequence, and the second host detects at least one time that the CM in the AM0 subsequence matches the CM in the second host's known AM0 subsequence, and determines that AM lock is implemented in the physical coding sublayer lane D0. It can be understood that both the second host's first known predetermined sequence and the second host's known AM0 subsequence may be pre-stored. This is not a limitation in the present application.

[0319]

[0340] Since the interval between the first predetermined sequence and the AM subsequence is smaller than the interval between two consecutive AM subsequences, the second host can match the first predetermined sequence with the AM subsequence to help shorten the AM lock time and accelerate the synchronization process of the second host.

[0320]

[0341] Process 2: Deskew

[0342] Deskewing is the process of determining the delay between physical coding sublayer lanes caused by the distance difference between transmissions and eliminating the relative delay. Three aligned bits in a second optical module are used as an example. If the arrival time through physical coding sublayer lane D0 is t1, the arrival time through physical coding sublayer lane D1 is t2, and the arrival time through physical coding sublayer lane D2 is t3, and t1 is earlier than t2 and t2 is earlier than t3, then t1, t2, and t3 may be combined into t3.

[0321]

[0343] Process 3: Determine whether the lane re-order condition is met.

[0322]

[0344] For example, 16 physical coding sublayer lanes are included. The number of AM subsequences in the 16 physical coding sublayer lanes (i.e., among the lanes) is detected. Specifically, among the 16 physical coding sublayer lanes, one AM0 subsequence is detected for physical coding sublayer lane D0, one AM1 subsequence is detected for physical coding sublayer lane D1, and so on, indicating that the lane reordering condition is met. If the number of AM subsequences corresponding to any one of the physical coding sublayer lanes is detected to be two or more, it indicates that the lane reordering condition is not met. In this case, it is necessary to wait until the next time when the AM subsequence matches a UM sequence in the pre-stored AM subsequence, which indicates that the lane reordering condition is met.

[0323]

[0345] Process 4: Physical Coding Sublayer Lane Reordering

[0346] The second host cannot determine the order of the sequence numbers of the physical coding sublayer lanes, so it must rely on the UMs in the AM subsequence. Each UM corresponds one-to-one to a physical coding sublayer lane sequence number. For example, UM0 corresponds to physical coding sublayer lane D0, UM1 corresponds to physical coding sublayer lane D1, and so on. Once each UM in the AM subsequence is determined, the UM is mapped to the sequence number of the corresponding physical coding sublayer lane, and the physical coding sublayer lanes can be reordered.

[0324]

[0347] Based on the above four processes, the second host performs synchronization until the synchronization lock.

[0325]

[0348] Step 1213: The second host determines synchronization lock and processes the third data.

[0326]

[0349] In a possible implementation, the second host may perform de-interleaving, decoding, and other processing on the third data to recover the data sent by the first host.

[0327]

[0350] It should be noted that if the second host cannot achieve synchronous lock, that is, if the second host determines that the synchronous lock is lost, the second host may send third indication information to the second optical module, where the third indication information indicates that the second host is in a synchronous lock-out state. Further, optionally, the second host sends the third indication information to the second optical module via the MDIO interface.

[0328]

[0351] Through the aforementioned steps 1211 to 1213, data synchronization on the second host side can be implemented through slight modifications on the second host side (adding lane reordering conditions). Furthermore, by detecting the instruction information sent by the second optical module, the synchronization process can be started as early as possible, which can help shorten the duration required for synchronization.

[0329]

[0352] Based on the above-mentioned method 1, the time required for the second optical module to synchronize and lock may be referred to as a waiting delay T1, and the time required for the second host to synchronize and lock may be referred to as a waiting delay T2. The second host includes m physical coding sublayer lanes, and the time required for mutual deskew between the m physical coding sublayer lanes may be referred to as a waiting delay T3. Therefore, the waiting delay required for synchronization of the communication system is T sync =T1+T2+T3.

[0330]

[0353] Method 2: The first optical module acquires the first data according to the above method b.

[0331]

[0354] 13 is a schematic flowchart of the method steps of yet another data processing method according to the present application. The method mainly includes data processing on the second optical module side. The method includes the following steps:

[0332]

[0355] Step 1301: A first optical module transmits first data to a second optical module, and in response, the second optical module receives the first data from the first optical module.

[0333]

[0356] In this example, the first optical module acquires the first data by the above-mentioned method b. For step 1301, please refer to the above-mentioned description of step 501. The details will not be described again here.

[0334]

[0357] Step 1302: The second optical module determines a synchronization state based on the first data.

[0335]

[0358] For step 1302, please refer to the above description of step 1202. The details will not be described again here.

[0336]

[0359] If it is determined that the synchronization is out of lock, the following steps 1303 to 1307 are executed; otherwise, if it is determined that the second optical module is in a synchronization lock state, the following step 1308 is executed.

[0337]

[0360] Step 1303: The second optical module sends the first instruction information and the first data to the second host.

[0338]

[0361] For step 1303, please refer to the above description of step 1203. The details will not be described again here.

[0339]

[0362] Step 1304: The first optical module transmits the second data to the second optical module, and in response, the second optical module receives the second data from the first optical module.

[0340]

[0363] In this example, the first optical module acquires the second data in the above-described manner b, and the second data includes a second predetermined sequence.

[0341]

[0364] For step 1304, please refer to the above description of step 1204. The details will not be described again here.

[0342]

[0365] Step 1305: The second optical module performs synchronization based on the second data.

[0343]

[0366] In a possible implementation, the process of step 1305 may be the same as the process of the above-mentioned step 1205. For details, please refer to the description of the above-mentioned step 1205. The synchronization process may be referred to as synchronization mechanism 1.

[0344]

[0367] In another possible implementation, based on the above-mentioned method b, the second predetermined sequence inserted into the second data by the first host is not dispersed, and the second optical module can perform synchronization based on the second predetermined sequence included in the second data. For example, the second predetermined sequence is an AM subsequence. When the second optical module detects in the second data that a CM in the AM subsequence matches a CM in a known AM subsequence of the second optical module at least twice consecutively, synchronization lock is determined. This synchronization process may be referred to as synchronization mechanism 2.

[0345]

[0368] It should be noted that the second optical module may alternatively initiate synchronization mechanism 1 and synchronization mechanism 2 simultaneously to perform synchronization in coordination with each other.

[0346]

[0369] Step 1306: The second optical module determines that the second optical module is in a synchronous lock state, and replaces a portion of the data in the second data with the first predetermined sequence to obtain third data.

[0347]

[0370] In a possible implementation, the second data further includes N second code words, the second code words including a second information block and a second overhead block.

[0348]

[0371] Below, as examples, three possible ways of obtaining the third data are given.

[0349]

[0372] Scheme D: Substitute the complete second codeword with the first predetermined sequence.

[0350]

[0373] In one possible implementation, in each physical coding sublayer lane, the substitution with the first predetermined sequence starts from the boundary of any second codeword among the N second codewords, and the substitution is stopped when it is detected that the second predetermined sequence matches the second known predetermined sequence of the second optical module at least once. Physical coding sublayer lane D0 is used as an example. For example, the second predetermined sequence is an AM0 subsequence. The substitution with the first predetermined sequence starts from the boundary of any second codeword among the N second codewords, and the substitution is stopped when it is detected that the AM0 subsequence matches the second known AM0 subsequence of the second optical module at least once. This thus helps to reduce the number of second codewords to be substituted.

[0351]

[0374] It should be noted that the second optical module's initiation of substituting the second codeword with the first predetermined sequence and the second optical module's detection of the second predetermined sequence may be performed synchronously, and when the second predetermined sequence is first detected at least once, w / 2 second codewords may be substituted with the first predetermined sequence.

[0352]

[0375] In Method D, for the length of the first predetermined sequence, please refer to the description in Method A above, and the details will not be described again here.

[0353]

[0376] Scheme E: The second overhead block in the second codeword is replaced with the first predetermined sequence.

[0354]

[0377] In a possible implementation, in each physical coding sublayer lane, the substitution with the first predetermined sequence starts from the boundary of the second overhead block in any second codeword among the N second codewords, and the substitution is stopped when the second predetermined sequence is detected to match at least once with the second known predetermined sequence of the second optical module.

[0355]

[0378] In Scheme E, for the length of the first predetermined sequence, please refer to the description in Scheme B above. The details will not be described again here.

[0356]

[0379] Scheme F: The second information block in the second codeword is replaced with the first predetermined sequence.

[0357]

[0380] In a possible implementation, in each physical coding sublayer lane, the substitution with the first predetermined sequence starts from the boundary of the second information block in any second codeword among the N second codewords, and the substitution is stopped when it is detected that the second predetermined sequence matches the second known predetermined sequence of the second optical module at least once.

[0358]

[0381] In scheme F, for the length of the first predetermined sequence, please refer to the description in scheme C above. The details will not be described again here.

[0359]

[0382] Step 1307: The second optical module sends the second instruction information and the third data to the second host.

[0360]

[0383] For step 1307, please refer to the above description of step 1207. The details will not be described again here.

[0361]

[0384] Step 1308: The second optical module sends the second instruction information and the first data to the second host.

[0362]

[0385] For step 1308, please refer to the explanation of step 1208 above.

[0363]

[0386] Through the aforementioned steps 1301 to 1308, whether synchronization is performed can be determined without decoding the second data. The implementation process is simple, which can help to further reduce the synchronization duration of the communication system.

[0364]

[0387] In a possible implementation, for a second host-side data processing method based on the above-mentioned Method 2, please refer to the description of Fig. 12b, and the details will not be described again here.

[0365]

[0388] Embodiment 2 14 is a schematic flowchart of the method steps of another data processing method according to the present application. The method includes the following steps:

[0366]

[0389] Step 1401: The first host inserts k second predetermined sequences into the data b to be transmitted to obtain the fourth data.

[0367]

[0390] Alternatively, the fourth data may be understood as including k second predetermined sequences, where k is an integer greater than one.

[0368]

[0391] Step 1402: The first host transmits fourth data to the first optical module, and in response, the first optical module receives the fourth data from the first host.

[0369]

[0392] In a possible implementation, the first host may transmit the fourth data to the first optical module via the second data stream path of the AUI; or the first host may transmit the fourth data to the first optical module via the MDIO interface.

[0370]

[0393] Step 1403: The first optical module determines the synchronization state based on the fourth data.

[0371]

[0394] If synchronization is determined to be out of lock, steps 1404 through 1409 below are performed; alternatively, if synchronization is determined to be locked, step 1410 below is performed.

[0372]

[0395] Step 1404: The first optical module transmits the fourth data to the first host. In response, the first host receives the fourth data from the first optical module.

[0373]

[0396] In a possible implementation, the first optical module may transmit the fourth data to the first host via the first data stream path of the AUI; or the first optical module may transmit the fourth data to the first host via the MDIO interface.

[0374]

[0397] The first host receives the fourth data from the first optical module, and can determine that the first optical module is in a synchronous out-of-lock state, and enters a loopback mode.

[0375]

[0398] Step 1405: The first host decrypts the fourth data and determines whether the decryption is successful.

[0399] If the decoding performed by the first host on the fourth data does not fail three consecutive times, the first host sends the fourth data and information indicating that the decoding has not failed three consecutive times to the first optical module via the MDIO interface. Further, after multiple attempts, the first host automatically enters a warning state. If the decoding performed by the first host on the fourth data fails three consecutive times, the following step 1406 may be executed to notify that the first optical module is faulty in the process of performing synchronization based on the fourth data.

[0376]

[0400] Step 1406: The first host inserts h second predetermined sequences into the data c to be transmitted to obtain fifth data.

[0401] The fifth data includes h second predetermined sequences, where h is greater than k.

[0377]

[0402] Alternatively, the first host may insert a denser second predetermined sequence into data c to be transmitted than the second predetermined sequence inserted into data b. For example, the first host may insert one second predetermined sequence into data b every 8192 x 5440 / 16 bits and one second predetermined sequence into data c every 8192 x 5440 / 16 / 2 bits. Data c and data b belong to two portions of data within the same data stream.

[0378]

[0403] Step 1407: The first host transmits the fifth data to the first optical module, and in response, the first optical module receives the fifth data from the first host.

[0379]

[0404] In a possible implementation, the first host may transmit the fifth data to the first optical module via the MDIO interface, or the first host may transmit the fifth data to the first optical module via the second data stream path.

[0380]

[0405] Step 1408: The first optical module determines the synchronization state based on the fifth data.

[0381]

[0406] For step 1408, please refer to the description of step 1403. Specifically, the "fourth data" in step 1403 should be replaced with "fifth data." Details will not be described again here.

[0382]

[0407] It should be noted that when the first optical module is determined to have lost synchronization lock based on the fifth data, steps similar to the above-described steps 1403 to 1406 may be periodically executed. Specifically, the "fourth data" can be replaced with the "fifth data." The first host inserts a second predetermined sequence, which is denser than that in the above-described step 1406, into the data following the data c to be transmitted to obtain new data, and transmits the new data to the first optical module.

[0383]

[0408] Step 1409: The first optical module determines synchronization lock and sends the fifth data to the second optical module, and in response, the second optical module receives the fifth data from the first optical module.

[0384]

[0409] Step 1410: The first optical module transmits the fourth data to the second optical module, and in response, the second optical module receives the fourth data from the first optical module.

[0385]

[0410] Through the aforementioned steps 1401 to 1410, the first host may receive the fourth data from the first optical module and determine that the first optical module is in a synchronous lock-out state, and enter loopback mode. This helps to avoid a case where the second optical module cannot accurately identify the received data, and the first optical module transmits the synchronous lock-out data to the second optical module. This also helps to avoid a case where the first optical module exceeds the allocated processing delay limit. Furthermore, in order for the first optical module to quickly achieve synchronous lock, the first host obtains the fifth data by inserting the second predetermined sequence more closely.

[0386]

[0411] In a possible implementation, for the steps after step 1410, please refer to the description of Method 1 or Method 2. Specifically, you can just replace "first data" in Method 1 or Method 2 with "fifth data". The details will not be described again here.

[0387]

[0412] It should be noted that when the second host and the second optical module are used as a transmitting end for transmitting data, the method shown in Fig. 14 can also be applied to the second host and the second optical module, specifically, by replacing the "first optical module" with the "second optical module" and by replacing the "first host" with the "second host".

[0388]

[0413] In a possible implementation, the second embodiment may alternatively be combined with the method b in the first embodiment, specifically by replacing "data A" in the method b with "fourth data".

[0389]

[0414] Embodiment 3 15 is a schematic flowchart of another data processing method according to the present application. In this method, a first optical module communicates with a second optical module in full-duplex mode. In other words, the first optical module can receive data when transmitting data, and can also receive data when the second optical module also transmits data. The method includes the following steps:

[0390]

[0415] Step 1501: The first optical module transmits sixth data to the second optical module, and in response, the second optical module receives the sixth data from the first optical module.

[0391]

[0416] The sixth data includes a plurality of fourth codewords.

[0392]

[0417] Step 1502: The second optical module determines a synchronization state based on the sixth data.

[0393]

[0418] For step 1502, please refer to the description of step 502 above. The details will not be repeated here.

[0394]

[0419] If it is determined that the synchronization lock is lost, the following steps 1503 to 1509 are executed; or if it is determined that the second optical module is in a synchronization lock state, the following step 1510 is executed. It can be seen that after determining that the synchronization lock is lost, the second optical module determines that the received sixth data is invalid data.

[0395]

[0420] Step 1503: The second optical module sends the first instruction information and the sixth data to the second host.

[0396]

[0421] The second optical module transmits the first indication information to the second host via the indication signal path inst:IS_SIGNAL.indication of the AUI or MDIO interface, and transmits the sixth data to the second host via the first data stream path inst:IS_UNITDATA.indication of the AUI or MDIO interface.

[0397]

[0422] Step 1504: The second optical module replaces a portion of the data in the seventh data with the fourth predetermined sequence to obtain eighth data.

[0398]

[0423] In a possible implementation, the seventh data may be data transmitted by the second host to the second optical module and obtained by the second host by processing (e.g., encoding or interleaving) the data d to be transmitted.

[0399]

[0424] The fourth predetermined sequence indicates that the second optical module is not in a synchronous lock state.

[0400]

[0425] In a possible implementation, the seventh data may include P third code words, each of which includes a third information block and a third overhead block, where P is an integer greater than 1.

[0401]

[0426] Below, three possible ways of acquiring the eighth data are shown as examples.

[0402]

[0427] Scheme 1: Replace the complete third codeword with a fourth predetermined sequence.

[0403]

[0428] In a possible implementation, in each physical coding sublayer lane, z third codewords among the P third codewords are replaced with a fourth predetermined sequence to obtain eighth data, where z is a positive integer greater than 1 and less than or equal to P.

[0404]

[0429] Furthermore, optionally, the length of the fourth predetermined sequence may be equal to a positive integer multiple of the code length of one third codeword, for example, the code length of the third codeword is 128 bits, and the length of the fourth predetermined sequence is also 128 bits.

[0405]

[0430] The complete third codeword is replaced with the fourth predetermined sequence, so that the first optical module can quickly determine the boundary of each third codeword in the received eighth data, thereby shortening the period required for synchronization and reducing the complexity of the synchronization calculation on the first optical module side.

[0406]

[0431] Scheme 2: The third overhead block in the third codeword is replaced with a fourth predetermined sequence.

[0407]

[0432] In a possible implementation, in each physical coding sublayer lane, the third overhead blocks in z third codewords among the P third codewords are replaced with a fourth predetermined sequence.

[0408]

[0433] Furthermore, optionally, the length of the fourth predetermined sequence may be equal to or less than the length of the third overhead block in the third codeword, for example, if the code length of the third codeword is 128 bits, the length of the third information block is 120 bits, the length of the third overhead block is 8 bits, and the length of the fourth predetermined sequence is 8 bits.

[0409]

[0434] The third overhead block in the third second codeword is replaced with a fourth predetermined sequence, so that normal transmission of valid data will not be affected. Furthermore, when the length of the fourth predetermined sequence is equal to the length of the third overhead block, the first optical module can quickly determine the boundary of the third codeword in the received eighth data, thereby reducing the duration required for synchronization.

[0410]

[0435] Scheme 3: Replace the third information block in the third codeword with a fourth predetermined sequence.

[0411]

[0436] In a possible implementation, in each physical coding sublayer lane, the third information blocks in z third codewords among the P third codewords are replaced with a fourth predetermined sequence.

[0412]

[0437] Furthermore, optionally, the length of the fourth predetermined sequence may be equal to or less than the length of the third information block in the third codeword (e.g., the code length of the third codeword may be 128 bits, the length of the third information block may be 120 bits, the length of the third overhead block may be 8 bits, and the length of the fourth predetermined sequence may be 120 bits).

[0413]

[0438] If the second overhead block needs to be discarded at the second optical module side, the third information block is replaced with a fourth predetermined sequence, so that the first optical module performs synchronization based on the fourth predetermined sequence, which helps to reduce the duration required for synchronization of the first optical module.

[0414]

[0439] It should be noted that the z replaced third codewords can be any z third codewords among the P third codewords, and the z third codewords can be z consecutive or non-consecutive third codewords. This is not limited in the present application. The intervals between the z non-consecutive third codewords can be the same. Furthermore, one third codeword can be replaced by a fourth predetermined sequence every 2×j×5440 / PCSL / L bits, where L represents the length of the third information block in the third codeword, PCSL represents the number of physical coding sublayer lanes, and the value of j can be a positive integer such as 1, 2, 3, or 4.

[0415] For example, L=170 bits, PCSL=16. One third codeword may be replaced with the fourth predetermined sequence every 2×1×5440 / 16 / 170=4 third codewords. In another example, L=120 bits, PCSL=16. One third codeword may be replaced with the fourth predetermined sequence every 2×3×5440 / 16 / 120=17 third codewords. Alternatively, the intervals between z non-consecutive third codewords may be different. This is not a limitation in the present application.

[0416]

[0440] Step 1505: The second optical module transmits the eighth data to the first optical module, and in response, the first optical module receives the eighth data from the second optical module.

[0417]

[0441] In a possible implementation, the second optical module may transmit the eighth data via a transmission medium connected to the first optical module.

[0418]

[0442] The ninth data is obtained by replacing a part of the data in the tenth data with the fourth predetermined sequence by the first optical module. The specific process is the same as that of step 1504, specifically, by replacing the "seventh data" in step 1504 with the "tenth data."

[0419]

[0443] Step 1506: The first optical module detects the fourth predetermined sequence in the eighth data at least twice, and replaces at least two occurrences of the fourth predetermined sequence in the ninth data with the fifth predetermined sequence to obtain eleventh data.

[0420]

[0444] The fifth predetermined sequence is different from the fourth predetermined sequence. For example, the fourth predetermined sequence may be the S1 sequence, and the fifth predetermined sequence may be the S2 sequence. Optionally, the length of the fourth predetermined sequence may be the same as the length of the fifth predetermined sequence. Furthermore, the lengths of the fourth and fifth predetermined sequences may be equal to the length of the third codeword.

[0421]

[0445] Step 1507: The first optical module transmits the eleventh data to the second optical module. In response, the second optical module receives the eleventh data from the first optical module.

[0422]

[0446] Step 1508: The second optical module detects at least two fifth predetermined sequences in the eleventh data and determines synchronization lock.

[0423]

[0447] It should be noted that the second optical module directly detects the fifth predetermined sequence without decoding the eleventh data.

[0424]

[0448] Step 1509: The second optical module sends the second instruction information and the eleventh data to the second host.

[0425]

[0449] Through the aforementioned steps 1501 to 1509, the synchronization of the second optical module may be independent of the processing procedures of the second host, and therefore the existing synchronization procedures of the second host do not need to be changed.

[0426]

[0450] In a possible implementation, for the data processing method on the second host side, please refer to the description of Fig. 12b, and the details will not be described again here.

[0427]

[0451] Furthermore, optionally, the second host can send fifth instruction information to the second optical module, where the fifth instruction information indicates a synchronization status of the second host, and the synchronization status may include synchronization locked or synchronization unlocked. In other words, the second optical module can determine the synchronization status of data from the first optical module and can also determine the synchronization status of data from the second host. For example, the second host can send the fifth instruction information to the second optical module via the MDIO interface.

[0428]

[0452] 16 is a schematic flow chart of the method steps of yet another data processing method according to the present application. The method includes the following steps:

[0429]

[0453] Step 1601: The second optical module transmits thirteenth data to the first optical module, and in response, the first optical module receives the thirteenth data from the second optical module.

[0430]

[0454] Step 1602: The first optical module determines the synchronization state based on the thirteenth data.

[0431]

[0455] For step 1602, please refer to the description of step 502 above. The details will not be described again here.

[0432]

[0456] If it is determined that the synchronization lock has been lost, the following steps 1603 to 1609 are executed; alternatively, if it is determined that the first optical module is in a synchronization lock state, the following step 1610 is executed.

[0433]

[0457] Step 1603: The first optical module sends the first instruction information and the thirteenth data to the first host.

[0434]

[0458] Step 1604: The first optical module replaces a portion of the data in the tenth data with the fourth predetermined sequence to obtain ninth data.

[0435]

[0459] For step 1604, please refer to the above description of step 1504. The details will not be described again here.

[0436]

[0460] Step 1605: The first optical module transmits the ninth data to the second optical module, and in response, the second optical module receives the ninth data from the first optical module.

[0437]

[0461] Step 1606: The second optical module detects the fourth predetermined sequence in the ninth data at least twice, and replaces the fourth predetermined sequence in the eighth data with the fifth predetermined sequence to obtain twelfth data.

[0438]

[0462] Step 1607: The second optical module transmits the twelfth data to the first optical module. In response, the first optical module receives the twelfth data from the second optical module.

[0439]

[0463] Step 1608: The first optical module detects at least two fifth predetermined sequences in the twelfth data and determines synchronization lock.

[0440]

[0464] Step 1609: The first optical module transmits the thirteenth data to the second optical module, and in response, the second optical module receives the thirteenth data from the first optical module.

[0441]

[0465] The thirteenth data is normal data obtained by processing the data e to be transmitted by the first host, and the normal data does not include the fourth predetermined sequence or the fifth predetermined sequence. The first optical module and the second optical module may alternatively be understood as exchanging normal data.

[0442]

[0466] Through the aforementioned steps 1601 to 1609, the synchronization of the first optical module may be independent of the processing procedure of the first host, and therefore the existing synchronization procedure of the first host does not need to be changed.

[0443]

[0467] The synchronous locking of the second optical module may be performed according to Fig. 15, and the synchronous locking of the first optical module may be performed according to Fig. 16. A combination of the method shown in Fig. 15 and the method shown in Fig. 16 can further reduce the time required for synchronization.

[0444]

[0468] It should be noted that in this application, the steps (or processes) performed by the first optical module may alternatively be performed by the first PMA sublayer, or the first PMA sublayer and the first FEC sublayer. For ease of explanation of the solution, the first PMA sublayer, or the first PMA sublayer and the first FEC sublayer may be referred to as the first layer.

[0445] The steps (or processes) performed by the second optical module may be performed by the second PMA sublayer, or the second PMA sublayer and the second FEC sublayer. For ease of explanation of the solution, the second PMA sublayer, or the second PMA sublayer and the second FEC sublayer may be referred to as the second layer.

[0446] The steps (or processes) performed by the first host may be performed by the first PCS, or the first PCS and the first FEC sublayer. For ease of explanation of the solution, the first PCS, or the first PCS and the first FEC sublayer may be referred to as a third layer.

[0447] The steps (or processes) performed by the second host may be performed by a second PCS, or a second PCS and a second FEC sublayer, which may be referred to as a fourth layer for ease of explanation of the solution.

[0448] In other words, in the above description of the present application, the first optical module may be used in place of the first layer, the second optical module may be used in place of the second layer, the first host may be used in place of the third layer, and the second host may be used in place of the fourth layer. The specific execution process will not be described again here.

[0449]

[0469] It can be understood that to implement the functions in the above embodiments, the first optical module, the second optical module, the first host, and the second host include corresponding hardware structures and / or software modules for performing the functions. Those skilled in the art will easily recognize that the present application can be implemented by hardware or a combination of hardware and computer software with reference to the modules and method steps in the examples described in the embodiments disclosed in the present application. Whether the functions are performed by hardware or by hardware driven by computer software depends on the specific application scenario and design constraints of the technical solution.

[0450]

[0470] 17 and 18 are structural diagrams of possible communication devices according to the present application based on the above content and the same concept. These communication devices may be configured to implement the functions of the first optical module, the second optical module, the first host, or the second host in the above-mentioned method embodiments, and thus can also implement the beneficial effects of the above-mentioned method embodiments. In the present application, the communication device may be the first communication device 1011, the third communication device 1012, the second communication device 1021, or the fourth communication device 1022 shown in FIG. 1, or may be a module (e.g., a chip) used in the first communication device 1011, the third communication device 1012, the second communication device 1021, or the fourth communication device 1022.

[0451]

[0471] As shown in Figure 17, the communication device 1700 includes a processing unit 1701 and a transceiver unit 1702. The communication device 1700 is configured to perform the functions of the first optical module, the second optical module, the first host, or the second host in the method embodiments shown in Figure 5, 6a, 6b, 9, 10, 12a, 12b, 13, 14, 15, or 16.

[0452]

[0472] When the communication device 1700 is configured to perform the functions of the second optical module in the embodiment of the method shown in FIG. 5, the transceiver unit 1702 is configured to receive first data from the first optical module; the processing unit 1701 is configured to determine a synchronization lock out state based on the first data; the transceiver unit 1702 is further configured to send first indication information to the second host indicating that the second optical module is in a synchronization lock out state and receive second data from the first optical module; the processing unit 1701 is further configured to determine synchronization lock based on the second data and send second indication information to the second host via the transceiver unit, the second indication information indicating that the second optical module is in a synchronization lock state.

[0453]

[0473] When the communication device 1700 is configured to perform the functions of the second host in the embodiment of the method shown in FIG. 5, the transceiver unit 1702 is configured to receive first instruction information from the second optical module, the first instruction information indicating that the second optical module is in a synchronous lock-out state; the processing unit 1701 is configured to determine the synchronous lock-out based on the first instruction information; the transceiver unit 1702 is further configured to receive second instruction information from the second optical module, the second instruction information indicating that the second optical module is in a synchronous lock state; and the processing unit 1701 is further configured to initiate synchronization based on the second instruction information.

[0454]

[0474] For a more detailed description of the processing unit 1701 and the transceiver unit 1702, please directly refer to the relevant description in the method embodiment shown in Figure 5. The details will not be described one by one again here.

[0455]

[0475] It should be understood that the processing unit 1701 in this embodiment of the present application may be implemented by a processor or processor-related circuitry, and the transceiver unit 1702 may be implemented by an interface circuit or interface circuit-related circuitry.

[0456]

[0476] Based on the above content and the same concept, the present application further provides a communication device 1800, as shown in Fig. 18. The communication device 1800 may include a processor 1801 and an interface circuit 1802. The processor 1801 and the interface circuit 1802 are connected to each other. It can be understood that the interface circuit 1802 may be an interface circuit or an input / output interface. Optionally, the communication device 1800 may further include a memory 1803 configured to store instructions to be executed by the processor 1801, input data required by the processor 1801 to execute the instructions, or data generated after the processor 1801 executes the instructions.

[0457]

[0477] When the communication device 1800 is configured to perform the method shown in FIG. 5, the processor 1801 is configured to perform the functions of the processing unit 1701, and the interface circuit 1802 is configured to perform the functions of the transceiver unit 1702.

[0458]

[0478] Based on the above and the same concept, the present application further provides a communication system. The communication system may include a second optical module and a second host, and the device may include a first optical module and a first host. For possible implementations of the second optical module, the second host, and the first optical module, please refer to the above description. Details will not be described again here.

[0459]

[0479] It can be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0460]

[0480] The method steps in the embodiments of the present application may be implemented in hardware or by a processor executing software instructions. The software instructions may be configured as corresponding software modules. The software modules may be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium known in the art. For example, the storage medium may be coupled to the processor, such that the processor can read information from and write information to the storage medium. Of course, the storage medium may be a component of the processor. The processor and the storage medium may be located in an ASIC. Further, the ASIC may reside in a network device or terminal device. Of course, the processor and the storage medium may alternatively reside as discrete components in a communications device.

[0461]

[0481] All or part of the above-described embodiments may be implemented using software, hardware, firmware, or any combination thereof. When software is used to implement an embodiment, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded into a computer and executed, all or part of the procedures or functions of the embodiments of the present application are performed. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, or another programmable device. The computer program or instructions may be stored on a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer program or instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center via wired or wireless connections. The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device, such as a server or data center, that integrates one or more available media. Alternatively, the usable medium may be a magnetic medium such as a floppy disk, hard disk, or magnetic tape, an optical medium such as a digital video disc (DVD), or a semiconductor medium such as a solid state drive (SSD).

[0462]

[0482] In the embodiments of the present application, unless otherwise stated or logically contradictory, the terms and / or descriptions in the various embodiments are consistent and may be cross-referenced, and the technical features in the various embodiments may be combined based on their internal logical relationships to form new embodiments.

[0463]

[0483] In this application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of a single item or multiple items. For example, at least one of a, b, or c may refer to a, b, c, "a and b," "a and c," "b and c," or "a, b, and c," where a, b, and c may be singular or plural. "And / or" describes an association relationship between related objects and indicates that three relationships may exist. For example, A and / or B may represent the following cases: only A exists, both A and B exist, or only B exists, where A and B may be singular or plural. In the text description of this application, the character " / " indicates an "or" relationship between related objects. In mathematical formulas in this application, the character " / " indicates a "division by" relationship between related objects. Furthermore, the word "example" in this application is intended to express serving as an example, illustration, or explanation. Any embodiment or design manner described in this application as an "example" should not be described as preferred or having more advantages over other embodiments or design manners. Alternatively, the word "example" can be used to present concepts in a particular way and can be understood not to constitute limitations on the application.

[0464]

[0484] It will be understood that the numbers in the embodiments of the present application are merely for distinction purposes to facilitate description and are not used to limit the scope of the embodiments of the present application. The sequence numbers of the above processes do not imply an execution sequence, and the execution sequence of the processes should be determined based on the functions and internal logic of the processes. Terms such as "first," "second," etc. are intended to distinguish between similar objects, but do not necessarily indicate a particular order or sequence. Furthermore, the terms "comprise," "have," and any conjugation thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or modules. A method, system, product, or device is not necessarily limited to the explicitly enumerated steps or modules, but may include other steps or modules that are not explicitly enumerated or that are inherent to such a process, method, product, or device.

[0465]

[0485] It is apparent that those skilled in the art can make various modifications and variations to the present application without departing from the scope of the present application, and the present application is intended to cover such modifications and variations of the present application, provided that they fall within the scope of the claims of the present application and their equivalent techniques.

Claims

1. 1. A data processing method comprising: receiving, by the second communication device, second data from the first communication device; and the second communication device determining internal codeword synchronization lock based on the second data; generating a second indication, the second indication indicating that the second communication device is in an internal codeword synchronization lock state; the second data includes N second codewords, where N is an integer greater than 1; The step of determining, by the second communication device, internal codeword synchronization lock based on the second data includes: the second communication device decoding the second data based on a sliding window using a predetermined number of bits; After determining that the decoding has been successful at least once, the second communication device performs decoding based on a code length of the second codeword, and collects statistics on the number of successful decodings among the second decoding results; and determining, by the second communication device, when the second communication device determines that the number of successful decodings among the second decoding results is greater than a third threshold, that the second communication device is locked to an internal codeword synchronization; A method comprising:

2. 10. The method of claim 1, further comprising: receiving, by the second communication device, first data from the first communication device; determining, by the second communication device, that an internal codeword synchronization lock has been lost based on the first data; generating a first indication by the second communication device, the first indication indicating that the second communication device is in an internal codeword synchronization out-of-lock state; A method comprising:

3. 10. The method of claim 1, further comprising: a fourth communication device receiving the second indication information via an attachment unit interface (AUI) or via a management data input / output (MDIO) interface; A method comprising:

4. 3. The method of claim 2, further comprising: a fourth communication device receiving the first indication information via an attachment unit interface (AUI) or via a management data input / output (MDIO) interface; A method comprising:

5. The method of claim 1 , wherein the second instruction information is one.

6. The method of claim 2 , wherein the first indication information is zero.

7. 3. The method of claim 2, wherein the step of determining, by the second communication device, an internal codeword synchronization loss of lock based on the first data comprises: the second communication device decoding the first data to obtain M first decoding results, where the first decoding results include successful decoding or failed decoding, and M is an integer greater than 1; and determining that the internal codeword synchronization lock has been lost when the number of decoding failures in the M first decoding results is greater than a first threshold; A method comprising:

8. 2. The method of claim 1, wherein the predetermined number of bits is less than a code length of the second codeword.

9. 10. The method of claim 1, wherein a syndrome is generated in the process of decoding the second data.

10. 5. The method of claim 3 or 4, wherein the second communication device includes a second optical module, the first communication device includes a first optical module, and the fourth communication device includes a second host.

11. 5. The method of claim 3 or 4, wherein the second communication device includes a second Physical Medium Attachment (PMA) sublayer, or includes the second PMA sublayer and a second Forward Error Correction (FEC) sublayer; and the fourth communication device includes a second Physical Coding Sublayer (PCS), or includes the second PCS and a fourth FEC sublayer.

12. A second communication device including one or more processors and at least one interface circuit, the at least one interface circuit comprising: configured to receive second data from the first communication device; The one or more processors: determining an internal codeword synchronization lock based on the second data; configured to generate second indication information, the second indication information indicating that the second communication device is in an internal codeword synchronization lock state; The second data includes N second codewords, where N is an integer greater than 1: The one or more processors: decoding the second data based on a sliding window using a predetermined number of bits; After determining that the decoding has been successful at least once, performing decoding based on a code length of the second codeword, and collecting statistics regarding the number of successful decodings among the second decoding results; and The second communication device is configured to determine that an internal codeword synchronization lock has been achieved when it is determined that the number of successful decodings among the second decoding results is greater than a third threshold.

13. 13. The second communication device of claim 12, wherein the at least one interface circuit comprises: configured to receive first data from a first communication device; The one or more processors: determining an internal codeword synchronization loss of lock based on the first data; A second communication device configured to generate a first indication, the first indication indicating that the second communication device is in an internal codeword synchronization out-of-lock state.

14. 13. The second communication device according to claim 12, wherein the second instruction information is one.

15. 14. The second communication device according to claim 13, wherein the first instruction information is zero.

16. 14. The second communication device of claim 13, wherein the one or more processors: Decoding the first data to obtain M first decoding results, where the first decoding results include successful decoding or failed decoding, and M is an integer greater than 1; and The second communication device is configured to determine that the inner codeword synchronization has lost lock when the number of decoding failures in the M first decoding results is greater than a first threshold.

17. 13. The second communication device according to claim 12, wherein the predetermined number of bits is less than a code length of the second codeword.

18. 13. The second communication device of claim 12, wherein a syndrome is generated in the process of decoding the second data.

19. 1. A communication system including a second optical module and a second host, the second optical module comprising: receiving second data from the first communication device, the second data including N second code words, where N is an integer greater than 1; decoding the second data based on a sliding window using a predetermined number of bits; After determining that the decoding has been successful at least once, performing decoding based on a code length of the second codeword, and collecting statistics regarding the number of successful decodings among the second decoding results; determining that the internal codeword synchronization is locked when it is determined that the number of successful decodings among the second decoding results is greater than a third threshold; configured to generate second indication information, the second indication information indicating that the second optical module is in an internal codeword synchronization lock state; The second host: The communication system is configured to obtain the second indication information via an attachment unit interface (AUI) or via a management data input / output (MDIO) interface.

Images