Filtering based on range specifiers

Abstract

A data processing apparatus, method, and computer program are disclosed. A range definition register is configured to store a range specifier, and a filtering operation is performed on a specified transaction by referencing the range definition register. The range definition register stores the range specifier in a format including a mantissa and an exponent, and a range of data identifiers is defined at least in part by the range specifier. If the specified transaction is for a data identifier within a range of data identifiers, the filtering operation performed depends on attribute data associated with the range of data identifiers.

Description

[Technical Field]

[0001] This invention was made with government support under Contract No. HR001118C0016 awarded by the Defense Advanced Research Projects Agency (DARPA). The government has certain rights in this invention.

[0002] FIELD OF THE DISCLOSURE The present disclosure relates to data processing, and in particular to filtering operations based on range specifiers. [Background technology]

[0003] The data processing device may include filtering circuitry that performs filtering operations on particular transactions within the device. When configured to do this, at least some of the filtering may be required to be applied only to a particular subset of transactions, for example transactions relating to a specified range of memory addresses, or transactions relating to a specified range of data values. Summary of the Invention

[0004] In one exemplary embodiment described herein, a data processing apparatus is provided, comprising: a range definition register configured to store a range specifier; and a filtering circuit configured to perform a filtering operation on a specified transaction by referencing the range definition register, the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by a range specifier and the specified transaction is for a data identifier within the range of data identifiers, There is a data processing apparatus in which the filtering operation performed by the filtering circuit depends on attribute data associated with a range of data identifiers.

[0005] In one exemplary embodiment described herein, storing a range specifier in a range definition register; performing a filtering operation on the specified transaction by referencing the range definition register; A method comprising: the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by a range specifier and the specified transaction is for a data identifier within the range of data identifiers, There is a method for modifying filtering behavior depending on attribute data associated with a range of data identifiers.

[0006] In one exemplary embodiment described herein, a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: range definition register logic configured to store a range specifier; filtering logic that performs filtering operations on transactions specified by referencing range definition register logic; the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by a range specifier and the specified transaction is for a data identifier within the range of data identifiers, There is a computer program in which the filtering operations performed by the filtering logic depend on attribute data associated with a range of data identifiers. [Brief explanation of the drawings]

[0007] The present invention will be further described, by way of example only, with reference to embodiments thereof as illustrated in the accompanying drawings, in which:

[0008] [Figure 1A] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 1B] 1 illustrates a schematic diagram of a range specifier according to an exemplary embodiment; [Figure 1C] 1 is a diagram illustrating a range specifier according to an exemplary embodiment; [Figure 2A] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 2B] 1 illustrates a schematic diagram of a basis specifier according to an exemplary embodiment; [Figure 3A] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 3B] 10A and 10B illustrate schematic diagrams of memory region base specifier and range specifier pairs stored in a table in memory, according to an exemplary embodiment; [Figure 4A] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 4B] 1 illustrates a schematic diagram of a memory region range specifier according to an exemplary embodiment; [Figure 5A] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 5B] 1 illustrates a schematic diagram of an apparatus according to an exemplary embodiment; [Figure 6] 3 illustrates the sequence of steps followed in the method of an exemplary embodiment. [Figure 7] 3 illustrates the sequence of steps followed in the method of an exemplary embodiment. [Figure 8] 1 illustrates a schematic diagram of a simulator implementation of an exemplary embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0009] Before discussing the embodiments with reference to the accompanying drawings, the following embodiments will be described.

[0010] In one exemplary configuration, a data processing apparatus comprising: a range definition register configured to store a range specifier; and a filtering circuit configured to perform a filtering operation on a specified transaction by referencing the range definition register, the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by a range specifier and the specified transaction is for a data identifier within the range of data identifiers, A data processing apparatus is provided in which the filtering operation performed by the filtering circuit depends on attribute data associated with a range of data identifiers.

[0011] A range of data identifiers, such as a range of memory addresses or a range of data values, is typically defined by the limits of the range (e.g., a start value and an end value), and it is implicit that data identifiers that fall within the range limits form a set that satisfies a predetermined condition. For example, a particular data processing operation may only be applied (or not be applied) if the target data identifier falls within the range. Thus, in a data processing device provided with a range definition register configured to store a range specifier, the range specifier may conventionally provide a value that represents the limit of the range (e.g., an upper limit, with a lower limit specified or assumed elsewhere). However, the present technique recognizes that configuring a range definition register to hold range specifiers in this format is inflexible. Furthermore, bit space is often at a premium within a data processing device's registers.

[0012] In this context, the technique provides an arrangement in which the range definition register is configured to store the range specifier in a format including a mantissa and an exponent. In other words, the range definition register holds the range specifier in a floating-point format with a fixed set of digits (the mantissa), to which scaling (using the exponent) is applied. This scaling therefore uses the exponent in a given base, so that the scaling factor is the base exponent. In the context of a data processing device, for ease of implementation, this base may be, for example, 2. The range of the data identifier is then defined in this floating-point format, at least in part, by the range specifier. This provides a useful element of flexibility in the way the range of the data identifier is defined, where the precision with which the range of the data identifier is specified can be traded off against the size of the specified range. Smaller ranges (defined using smaller exponents) can, for example, be precisely defined down to the level of individual data identifiers, whereas larger ranges may need to take into account groupings of data identifiers (e.g., blocks of memory in the case of memory addresses, which is a type of memory alignment), but allow for the specification of larger ranges than would otherwise be possible, subject to the constraint of a limited number of encoding bits to represent this range.

[0013] Thus, the filtering circuit may construct a range from the mantissa and exponent of the range specifier stored in the range definition register, and then use the range specifier to identify transactions occurring with respect to data identifiers that fall within the defined range. The filtering operation performed by the filtering circuit further depends on attribute data associated with the range of the data identifier. This attribute data may be variously defined, and the definition of that attribute data may be variously maintained, but in some embodiments, the range specifier further includes at least a portion of the attribute data. Indeed, within the space-constrained environment of the range definition register, the flexibility provided by the present technique in defining the range specifier in terms of the mantissa and exponent may allow a greater proportion of the bits of the range definition register to be used to define the attribute data of the defined range of the data identifier.

[0014] As mentioned above, the definition of a range of a data identifier may include a lower limit (or upper limit) that is assumed or separately defined, and thus a range may be constructed by reference to its reference (upper or lower) limit and a range size given by a range specifier stored in a range definition register. In some embodiments, the data processing apparatus further comprises a base definition register configured to store a base specifier, and the range of the data identifier includes a set of data identifiers spanning a range between a first data identifier indicated by the base specifier and a second data identifier dependent on the first data identifier, and a data identifier range indicated by the range specifier.

[0015] Additionally, the attribute data may be defined, at least in part, by its base specifier, and in some embodiments the base specifier further comprises at least a portion of the attribute data.

[0016] The present technique may find applicability to a variety of data identifiers for which a range is to be defined. However, in some embodiments, the range definition register is a memory region range definition register, the range specifier is a memory region range specifier, and the range of the data identifier is a memory region defined at least in part by the memory region range specifier. Thus, the present technique allows for significant flexibility in defining the memory range to which the filtering operation is to be applied. By defining the memory range with reference to the mantissa and exponent of the memory region range specifier, it is possible to define memory ranges that cover only a small number of memory addresses, to memory ranges that cover large sections of memory.

[0017] While the memory region range specifier may be used in various ways to define a range of memory addresses, in some embodiments the data processing apparatus further comprises a memory region base definition register configured to store a memory region base specifier, wherein the memory region comprises a set of memory addresses spanning a range of a first address indicated by the memory region base specifier and a second address that depends on the first address and the memory range indicated by the memory region range specifier.

[0018] A memory region defined at least in part by a memory region range specifier may, in some examples, be relatively static, such that the filtering circuitry is configured to perform its filtering operation only with respect to that memory region. However, in other examples, the memory region range specifier may be updated depending on the memory address being accessed. For example, in some embodiments, the filtering circuitry, in response to a specified memory access, performs a memory region specifier lookup procedure that attempts to read replacement contents for the memory region range definition register and memory region base definition register corresponding to the specified memory access if the memory region does not correspond to the specified memory access. This configuration allows the device to maintain a different set of attribute data for each defined memory region. When several memory accesses are made to a defined region of memory covered by a memory region range definition, the memory accesses can be filtered by reference to the same attribute data, allowing a particular area of ​​memory to be defined as read-only, restricted to allow access only by specific agents, permitted / prohibited to execute instructions stored therein, etc. Thus, a memory region range specifier in a memory region range definition register (possibly in combination with a memory region base specifier in a memory region base definition register) may be applicable to an ongoing set of memory accesses, for example, when a given processing agent accesses a particular portion of memory for a given type of processing task. However, if a next access is made to a different region of memory (outside the memory region range definition), the lookup procedure may read replacement contents for the memory region range definition register, so that, among other things, a new set of attribute data is then referenced for the new memory access, to which different rules may then be applied.

[0019] The memory region specifier lookup procedure may be performed in various ways, but in some embodiments, performing the memory region specifier lookup procedure includes performing a table walk on a table of memory region specifiers stored in memory; A table walk is a convergent iterative process that involves examining a sequence of candidate memory region base specifiers. At each iteration of the convergent iterative process, a comparison is made between the candidate memory region base specifier and the memory address of the specified memory access. For subsequent iterations of the convergent iterative process, the candidate memory region base specifier depends on the results of the comparison in the previous iteration of the convergent iterative process. Thus, the iterative process references the base specifier values ​​and uses them to inform the next iteration of the process. Thus, a search guided by the base value is performed. For example, at each iteration, a determination can be made as to whether the base value is greater than or less than the address of the memory access being processed, and the required memory region base specifier can be located. Then, once the base specifier is deemed to be appropriately close to the address of the memory access, only the memory region range specifier (and the range constructed from the mantissa and exponent) needs to be examined.

[0020] Thus, in some embodiments, the table walk further includes a verification step that is performed after the convergent iteration process to determine whether the candidate memory range indicated by the candidate memory region base specifier and the candidate memory region range specifier of the last iteration of the convergent iteration process defines a candidate memory region that includes the memory address of the specified memory access.

[0021] However, the examination of the memory region range specifiers may be interleaved as part of the steps of the iterative process, and in some embodiments, performing a memory region specifier lookup procedure includes performing a table walk on a table of memory region specifiers stored in memory, the table walk being a convergent iterative process that includes examining a sequence of candidate memory region base specifiers, and in a first step of each iteration of the convergent iterative process, a candidate first address is determined from each candidate memory region base specifier, and if the candidate first address represents a boundary of a candidate memory region that fits the specified memory access, a second step of each iteration is performed to determine whether the candidate memory range indicated by the candidate first address and the candidate memory region range specifier defines a candidate memory region that includes the memory address of the specified memory access.

[0022] By separately defining the memory region base specifier and the memory region range specifier as distinct items read from memory, the manner and order in which these two items of information are processed can be further modified. For example, in some embodiments, the first step of each iteration of the convergent iterative process includes fetching a candidate memory region base specifier and a candidate memory region range specifier from a table in memory, and when the second step of each iteration is performed, the second step of each iteration is performed concurrently with the next first step of the next iteration of the convergent iterative process, which includes fetching the next candidate memory region base specifier and the next candidate memory region range specifier from the table in memory. This parallelization can enable faster retrieval of the required memory region range specifiers and memory region base specifiers.

[0023] The data identifier may take forms other than a memory address, and in some embodiments the range definition register is a data value range definition register, the range specifier is a data value range specifier, and the range of the data identifier is a range of data values ​​defined at least in part by the data value range specifier. Thus, filtering operations may be performed based on the defined range of data values ​​and whether a given transaction includes a data value that is in that defined range of data values.

[0024] Although a data processing device supporting the present technique may be configured in a variety of ways, in some embodiments the data processing device comprises: processing circuitry for performing data processing operations; at least one capability register configured to store at least one capability pointer; a decoding circuit responsive to the sequence of instructions to generate control signals for the processing circuitry to cause the processing circuitry to perform data processing operations in accordance with the sequence of instructions; the data processing instructions include at least one capability pointer processing instruction; In response to the at least one capability pointer processing instruction specifying the at least one capability register, the processing circuitry performs at least one capability pointer-specific data processing operation with respect to the at least one capability register, and the range definition register is the capability register.

[0025] Thus, in a data processing apparatus configured to perform data processing on at least one capability register that holds at least one capability pointer, the present technique can exploit that configuration to enable range specifiers held in range definition registers to be treated as capability pointers. This allows the apparatus's mechanisms for handling such capability pointers (or "fat pointers") to be applied to memory range definitions, with enhanced security measures specifically associated with such capability pointers. Improved memory region definition security is therefore supported.

[0026] Various aspects of the capability processing functionality of such data processing apparatus may be utilized in this manner. In some such exemplary embodiments, the data processing instruction includes a capability pointer generation instruction, and the decode circuitry is responsive to the capability pointer generation instruction to cause the processing circuitry to generate a range specifier when the capability pointer generation instruction specifies a range defining register as a destination register.

[0027] While the attribute data may be used in various ways to modify the filtering operation performed, in some embodiments the filtering circuit is a memory protection circuit and the filtering operation with respect to a specified memory access includes preventing the specified memory access from accessing a memory address if the attribute data associated with the memory region indicates that access to the memory address is prohibited.

[0028] In some embodiments, the filtering circuit is a monitoring circuit, and the filtering operation with respect to the specified transaction includes generating a notification when attribute data associated with the memory region indicates that an access to the memory address should be subject to a monitoring action.

[0029] In some embodiments, the monitoring circuitry is debug circuitry, and the filtering operation with respect to the specified transaction comprises a debug operation.

[0030] In some embodiments, the monitoring circuitry is a tracing circuitry, and the filtering operation with respect to the specified transaction comprises a tracing operation.

[0031] In some embodiments, the monitoring circuitry is a watchpoint circuitry, and the filtering action with respect to the specified transaction comprises a watchpoint action.

[0032] Another exemplary configuration includes storing a range specifier in a range definition register; performing a filtering operation on the specified transaction by referencing the range definition register; A method comprising: the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by a range specifier and the specified transaction is for a data identifier within the range of data identifiers, A method is provided for modifying filtering operations depending on attribute data associated with a range of data identifiers.

[0033] In one example herein, 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program including: range definition register logic configured to store a range specifier; and filtering logic configured to perform a filtering operation on transactions specified by referencing the range definition register logic; the range definition register is configured to store a range specifier in a format including a mantissa and an exponent; A computer program is provided in which, if a range of data identifiers is defined at least in part by a range specifier and a specified transaction relates to a data identifier within the range of data identifiers, the filtering operation performed by the filtering logic depends on attribute data associated with the range of data identifiers.

[0034] Specific embodiments will now be described with reference to the drawings.

[0035] FIG. 1A illustrates a data processing apparatus 10 according to some embodiments. The apparatus 10 includes a filtering circuit 12 having access to a range definition register 14. The filtering circuit 12 receives transactions as part of a data processing operation performed by a broader data processing system of which the illustrated apparatus forms a part. The filtering circuit 12 is configured to modify the filtering operation it performs with respect to transactions it processes based on the data identifiers forming part of the transactions and the range of the data identifiers specified at least in part by the contents of the range definition register. The range definition register 14 is configured to store a range specifier, exemplary formats of which are shown in FIGS. 1B and 1C. In particular, a range specifier includes two parts: an exponent and a mantissa. The exponent and mantissa of the range specifier together define the range of the data identifier in floating-point format, i.e., the value defined by the mantissa is scaled (applied to an assumed base value) using the exponent. FIG. 1C illustrates the contents of a range specifier in some embodiments, where it can be seen that the range specifier includes not only an exponent and a mantissa, but also a set of attributes. Filtering circuit 12 of device 10 utilizes attribute data in the filtering operations it performs, and the associated attribute data associated with identified data ranges is defined at least in part by the contents of range definition register 14. Thus, in exemplary embodiments in which range specifiers are configured as shown in Figure 1B, the attribute data is defined (or implied) elsewhere, whereas in embodiments in which range specifiers are configured as shown in Figure 1C, at least a portion of the attribute data is provided within range definition register 14.

[0036] FIG. 2A schematically illustrates an apparatus 20 in some exemplary embodiments. The apparatus 20 includes a filtering circuit 22, a range definition register 24, and a base definition register 26. The filtering circuit 22 has access to the range definition register 24 and the base definition register 26. When the filtering circuit 22 performs a filtering operation on a transaction it processes, it determines whether the data identifier specified by the transaction is within a range of data identifiers defined by the contents of the range definition register 24 and the base definition register 26. More specifically, the base definition register 26 holds a base specifier, while the range definition register 24 holds a range specifier, and the combination of the two provides a definition of a range of data identifiers. For example, the base specifier can define a numerically smallest data identifier, while the range specifier defines a set of data identifiers starting from that base value. FIG. 2B schematically illustrates a base specifier in some embodiments, where the base specifier includes a base value and a set of attributes. Attributes are not a required part of a base specifier, and it is possible to define a base specifier that does not include attributes, as can be seen in the range specifier of Figure 1B. Alternatively, both the base specifier and the range specifier can include at least some of the attribute data, and filtering circuitry 22 can combine them to form a complete definition of the attribute data that applies to the defined range.

[0037] The data identifier can take various forms, such as a memory address or a data value. FIG. 3A schematically illustrates a data processing apparatus according to some embodiments in which the data identifier is a memory address. The apparatus 30 includes a filtering circuit 32 that filters transactions including memory accesses. The filtering circuit 32 includes a memory region range definition register (MRRDR) 34 and a memory region base definition register (MRBDR) 36. The apparatus 30 is on the path that the memory access takes on its way to the memory 40. So positioned, the apparatus 30 acts as a protection device, ensuring that memory accesses to the memory 40 follow defined rules within the data processing system. When a transaction accessing memory is received by the filtering circuit 32, the filtering circuit 32 determines whether the memory address targeted by the memory access is within the memory region defined by the current contents of the MRRDR 34 and the MRBDR 36. If it is within the memory region, the filtering circuit further determines whether the memory access conforms to the rules defined by attribute data associated with the defined memory region. This attribute data could be provided separately, but in this exemplary embodiment is provided as part of the contents of MRRDR 34 and MRBDR 36. Nevertheless, filtering circuit 32 is not restricted to only performing filter operations with respect to one defined memory region. To this end, alternative contents of MRRDR register 34 and MRBDR register 36 are stored in memory 40 in the form of further memory region definitions 42. In particular, when filtering circuit 32 processes a memory access request that is not within the memory region defined by the current contents of the two registers, filtering circuit 32 can access memory region definition 42 in memory 40 to read the corresponding memory region definition (assuming it is there) so that the filtering operation to be performed by filtering circuit 32 with respect to this memory access can be defined by the appropriate attribute data.Memory region definitions 42 are stored in memory 40 in tabular form and can be freely defined to constitute any possible subdivision of the accessible memory space. For example, at one extreme, only one memory region may be defined (possibly covering the entire available memory space), while at the other extreme, many different memory regions may be defined, each containing a small set of memory addresses. As a result of this flexibility in memory region definitions, the filtering circuitry does not know in advance where to find the memory region specifier it needs. As a result, the filtering circuitry is configured to perform an iterative lookup procedure (table walk) to find the required memory region specifier. Memory region range specifiers and memory region base specifiers are stored in association with each other because only when taken in combination do they define a memory region. Figure 3B schematically illustrates pairs of memory region base specifiers and range specifiers stored in a table in memory in some exemplary embodiments. While in some examples, both the memory region range specifier and the memory region base specifier are read at each step, in this example, the memory region base specifier is accessed first. Next, it can be determined whether the current memory address of the current memory access conforms to that memory region base specifier. For example, if the memory region base specifier provides the numerically lowest memory address in a given memory region definition, determining whether the current memory address is less than or greater than the base specifier indicates whether this memory region definition is a candidate for further consideration. For clarity, when a memory region base specifier provides the numerically lowest memory address within the region, if the current memory address is less than the memory region base specifier, it cannot be a required memory region definition. Further constraints may also exclude other candidate memory region definitions. For example, if a memory region definition is constrained to have a maximum size, if the current memory address differs from the memory region base specifier by more than that size, it also cannot be a required memory region definition.If a memory region base specifier is found that is potentially applicable to the current memory address, the memory region range specifier can be examined to determine whether the memory region range specifier and the memory region base specifier together define a memory region that encompasses the current memory address. This examination of the memory region range specifier can be done immediately, if the memory region range specifier is being read in parallel with the memory region base specifier, or in the next iteration step, if the memory region range specifier is read only if a valid candidate memory region base specifier is found. The reading of the memory region range specifier and the memory region base specifier can be offset relative to each other, in which case the next candidate memory region base specifier is read in parallel with the current candidate memory region range specifier to amortize read latency. In the final iteration, the current candidate memory region range specifier is found to be correct, and the next memory region base specifier that was read in parallel is discarded. Thus, the iterative lookup procedure continues as long as the required memory region base specifier / range specifier pair is not found, for example because the range does not extend far enough to cover the current memory address. The address space may be examined, for example, by iterative partitioning to locate the required memory region definition.

[0038] FIG. 4 schematically illustrates an apparatus 50 according to some embodiments. It will be appreciated that a more complete data processing system is illustrated here, including processing circuitry 52 to which a sequence of instructions is supplied by fetch / decode circuitry 54 for execution by the fetch / decode circuitry 54. The instructions are read from memory (not explicitly shown). Furthermore, the data processing operations performed by processing circuitry 52 in accordance with these instructions include memory accesses (e.g., loading a data value subject to the data processing operation into a local register before the modified data value is written back to be stored in a specified memory location). As shown in FIG. 4, apparatus 50 includes two types of local registers: general-purpose registers 56 and capability registers 58. Apparatus 50 is further illustrated as including a memory protection unit 60 in the memory access path for all memory accesses generated by apparatus 50. Memory protection unit 60 may be configured according to any of the example filtering circuitry arrangements described herein (e.g., with reference to FIGS. 1A, 2A, and 3). Accordingly, memory protection unit 60 performs memory access filtering operations with respect to memory accesses that must pass through it. Each of these memory accesses is compared by memory protection unit 60 with attribute data defined for the memory region in which it resides. In the example of FIG. 4A , the memory region range definition register is provided as one of capability registers 58. Processing circuit 52 uses capability register 58 for storing capability pointers. Furthermore, decode circuit 54 is configured to recognize several capability-related instructions from among a sequence of instructions executed by processing circuit 52. These capability-related instructions enable processing circuit 52 to efficiently and safely process the contents of capability register 58. Various capability-specific instructions can be defined; for example, one such instruction is configured to generate a capability pointer in a format suitable for storage in capability register 58.Thus, the device 50 can be programmed to use this instruction to create a memory range specifier in a format suitable for a memory region range definition register (as a capability register).

[0039] Figure 4B illustrates the configuration of a memory region range specifier in some embodiments that may be used, such as in the exemplary device of Figure 4A. In such embodiments, the specifier is formed as a capability pointer and stored in one of the capability registers 58. This exemplary 32-bit specifier includes the following portions: ●Permission data ([31:29]) ●Metadata ([28:22]) ●Shareability ([21:20]) ●Access permission ([19:18]) ● Execution prohibition flag (

[17] ) ●Interpretation marker (

[16] ) ●Interpretation marker (

[15] ) ●Range definition data ([14:9]) ● Range definition data ([8:0]) Here, the lower four parts of the specifier together constitute the mantissa and exponent definition of the defined range. Furthermore, note that the mantissa and exponent need not be stored in the specifier as two separate, distinct data items, as in the example of FIG. 4B; rather, the information defining the mantissa and exponent can be stored in a more distributed, mixed format. This provides further flexibility in using the specifier's limited bit space, with two interpretation markers signaling how the two sets of range-defining data should be interpreted. Also, note that the metadata bits ([28:22]) in this 32-bit format were previously unavailable using traditional memory region specifiers (a pair of specifiers that explicitly define a lower (base) memory address and an upper (limit) memory address for a given memory region definition). These seven bits can therefore be made available by the present technique for encoding further attribute data associated with the defined memory region.

[0040] FIG. 5A schematically illustrates an apparatus 100 according to some embodiments. As in the example of FIG. 4, the apparatus includes a processing circuit 102 that is supplied with a sequence of instructions to be executed by a fetch / decode circuit 104. The instructions are read from a memory (not explicitly shown). Furthermore, data processing operations performed by the processing circuit 102 in accordance with these instructions include memory accesses (e.g., loading a data value subject to the data processing operation into a local register before writing the modified data value back to be stored in a specified memory location). In the example of FIG. 5A, the apparatus 100 includes a memory protection unit 106 that is in the memory access path for all memory accesses generated by the apparatus 100. Also shown is a debug circuit 108 that monitors all memory accesses generated by the instruction processing operations of the processing circuit 102. The debug circuit 108 may be configured according to any of the example filtering circuit arrangements described herein (e.g., with reference to FIGS. 1A, 2A, and 3). Thus, the debug circuit 108 performs memory access filtering operations with respect to memory accesses that must pass through it. The operation of debug circuitry 108 is configured by the contents of memory region range definition register (MRRDR) 110 and memory region base definition register (MRBDR) 112. Thus, for each transaction accessing memory monitored by debug circuitry 108, the debug circuitry determines whether the memory address targeted by the memory access is within the memory region defined by the contents of MRRDR 110 and MRBDR 112. Debug circuitry 108 is configured to generate debug output depending on the memory accesses it observes, and in particular for memory accesses involving memory addresses within the memory region defined by the contents of MRRDR 110 and MRBDR 112. Attribute data associated with the memory region further configures the debug output generated by debug circuitry 108. For example, more detailed debug output may be generated for a particular set of memory addresses and / or when a particular process is the source of the memory access.The debug output may be further processed in a variety of ways, for example it may be written to a local buffer or to a separate storage device for subsequent analysis.

[0041] FIG. 5B schematically illustrates an apparatus 120 according to some example embodiments. The apparatus includes a processing circuit 122 that is supplied with a sequence of instructions to be executed by a fetch / decode circuit 124. The instructions are read from a memory (not explicitly shown). In this example, a monitoring circuit 126 is associated with the processing circuit 122 and configured to monitor certain transactions that form part of the processing circuit's 122 data processing operations. Generally, these may be transactions that access memory (as in the example of FIG. 5A), but may also be any other transactions observable as part of the data processing operations. The monitoring circuit 126 may be configured according to any of the filtering circuitry examples described herein (e.g., with reference to FIGS. 1A, 2A, and 3). In the example shown in FIG. 5B, only a range definition register 128 is provided, and the monitoring circuit 126 uses a predetermined base value. In this example, the monitoring circuit 126 filters transactions monitored in the processing circuit 122 for transactions that reference data values ​​that fall within a range defined by the contents of the range definition register 128. For these transactions, a monitoring output is generated, the content of which depends on the attribute data associated with the defined range. 5B may be embodied as a trace circuit, which monitors data processing being performed by processing circuit 122, with the monitor output taking the form of a trace stream which may be stored in a trace buffer within the device for later retrieval or exported directly from the device for analysis. In another example represented by Figure 5B, the monitor circuit may take the form of a watchpoint circuit, where the filtering operations on specified transactions include, for example, a watchpoint operation to suspend instruction execution when a memory address within a range defined by range definition register 128 is accessed.

[0042] 6 illustrates the sequence of steps followed in an exemplary embodiment method when processing observed transactions. Observation of a transaction in step 150 initiates the flow of steps. In step 152, a range definition is constructed from the mantissa and exponent of the range specifier. Note that in instances where the range definition is not changing (at least temporarily), the range construction of step 152 only needs to be performed once with reference to the range specifier, and the defined range can be kept local. In step 154, it is determined whether the observed transaction specifies a data identifier that is within the range defined by the range specifier. If not, the flow ends in step 158. For observed transactions that specify a data identifier within the range defined by the range specifier, a filtering operation is performed on the transaction in step 156 depending on the attribute data associated with the range. The flow then ends in step 158.

[0043] FIG. 7 illustrates a sequence of steps followed in an exemplary embodiment method in which a transaction accessing memory is observed. For example, memory protection unit 60 in the example of FIG. 4A may perform such a sequence of steps in some implementations. Receipt of a memory transaction in step 200 begins the flow of steps. In step 202, a memory region range definition is constructed from the mantissa and exponent of a memory region range specifier. As in FIG. 6, the memory region range definition needs to be constructed only once with reference to the memory region range specifier, and the defined range can then be retained locally for further use. In step 204, it is determined whether the observed memory access specifies a memory address that is within the defined memory region. If not, flow proceeds to step 206, where a memory region lookup procedure is performed to retrieve the memory region range specifier required for the memory access being processed. Flow then returns to step 202, where a replacement memory region range definition is constructed from the mantissa and exponent of the new memory region range specifier. If, in step 204, it is determined that the observed memory access does not specify a memory address that is within the defined memory region, flow proceeds to step 208, where the memory access is filtered depending on the attribute data associated with the defined memory region. A range of filtering operations are possible, such as completely blocking the memory access if it is not permitted, or simply modifying aspects associated with a particular memory access, such as whether the data it reads can be cached.

[0044] FIG. 8 illustrates a schematic diagram of an exemplary embodiment of a simulator implementation. While the above-described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the techniques, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented through the use of a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 310 that supports the simulator program 302, optionally running a host operating system 308. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or may provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0045] While embodiments have been described above with reference to particular hardware components or features, equivalent functionality may be provided in the simulated embodiments by appropriate software components or features. For example, particular circuitry may be implemented as computer program logic in the simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the simulated embodiments. In arrangements where one or more of the hardware elements referenced in the foregoing embodiments reside in host hardware (e.g., host processor 310), some simulated embodiments may use the host hardware where appropriate.

[0046] Simulator program 302 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provide target code 300 (which may include an application, an operating system, and a hypervisor) with a program interface (an instruction execution environment) that is the same as the interface of the hardware architecture modeled by simulator program 302. Thus, program instructions of target code 300 may be executed from within the instruction execution environment using simulator program 302, and thus a host computer 310 that does not actually have the hardware capabilities of the devices described above (e.g., the devices shown in Figures 1A, 2A, 3A, 4A, 5A, and 5B) may emulate these capabilities by providing filtering logic 304 and range definition register logic 306 that form part of simulator program 302.

[0047] By way of a brief general overview, a data processing apparatus, method, and computer program are disclosed. A range definition register is configured to store a range specifier, and a filtering operation is performed with respect to a specified transaction by referencing the range definition register. The range definition register stores the range specifier in a format including a mantissa and an exponent, and a range of data identifiers is defined at least in part by the range specifier. If the specified transaction is for a data identifier within the range of data identifiers, the filtering operation performed depends on attribute data associated with the range of data identifiers.

[0048] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a method of arranging or interconnecting hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0049] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various changes, additions, and modifications can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, various combinations of the features of the following dependent claims can be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. 1. A data processing apparatus comprising: a range definition register configured to store a range specifier; and a filtering circuit configured to perform a filtering operation on a specified transaction by referencing the range definition register, the range definition register is configured to store the range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by said range specifier, and said specified transaction is for a data identifier within said range of data identifiers, the filtering operation performed by the filtering circuit depends on attribute data associated with the range of data identifiers; the range definition register is a memory region range definition register, and the range specifier is a memory region range specifier; the data identifier range is a memory region defined at least in part by the memory region range specifier; If the memory region does not correspond to the specified transaction, the filtering circuitry performs a memory region specifier lookup procedure to read replacement contents of the memory region range definition register.

2. The data processing apparatus of claim 1 , wherein the range specifier further includes at least a portion of the attribute data.

3. 3. The data processing apparatus of claim 1, further comprising a base definition register configured to store a base specifier, wherein the range of data identifiers includes a set of data identifiers spanning a range between a first data identifier indicated by the base specifier and a second data identifier dependent on the first data identifier, and a data identifier range indicated by the range specifier.

4. The data processing apparatus of claim 3 , wherein the base specifier further includes at least a portion of the attribute data.

5. 2. The data processing apparatus of claim 1, further comprising a memory region base definition register configured to store a memory region base specifier, the memory region including a set of memory addresses ranging from a first address indicated by the memory region base specifier to a second address dependent on the first address, and a memory range indicated by the memory region range specifier.

6. The data processing device of claim 5, wherein the memory area specifier lookup procedure includes reading out the replacement contents of the memory area base definition register corresponding to the specified transaction.

7. performing the memory region specifier lookup procedure includes performing a table walk on a table of memory region specifiers stored in a memory; 7. A data processing apparatus as claimed in claim 6, wherein the table walk is a convergent iterative process involving examination of a sequence of candidate memory region base specifiers, and in each iteration of the convergent iterative process a comparison is made between a candidate memory region base specifier and the memory address of the specified transaction, and for subsequent iterations of the convergent iterative process, the candidate memory region base specifier depends on the result of the comparison in a previous iteration of the convergent iterative process.

8. 8. The data processing apparatus of claim 7, wherein the table walk further comprises a verification step performed after the convergent iteration process to determine whether the candidate memory region base specifier of a last iteration of the convergent iteration process and the candidate memory range indicated by a candidate memory region range specifier define a candidate memory region that includes the memory address of the specified transaction.

9. performing the memory region specifier lookup procedure includes performing a table walk on a table of memory region specifiers stored in a memory; 7. A data processing apparatus as claimed in claim 6, wherein the table walk is a convergent iterative process comprising examining a sequence of candidate memory region base specifiers, and wherein in a first step of each iteration of the convergent iterative process a candidate first address is determined from each candidate memory region base specifier, and when the candidate first address represents a boundary of a candidate memory region that fits the specified transaction, a second step of each iteration is performed to determine whether the candidate first address and a candidate memory range indicated by a candidate memory region range specifier define a candidate memory region that includes the memory address of the specified transaction.

10. the first step of each iteration of the convergent iterative process includes fetching the candidate memory region base specifiers and the candidate memory region range specifiers from the table in memory; 9. A data processing apparatus as claimed in claim 7 or claim 8, wherein when the second step of each iteration is performed, the second step of each iteration is performed simultaneously with the next first step of the next iteration of the convergent iterative process, which includes fetching a next candidate memory region base specifier and a next candidate memory region range specifier from the table in memory.

11. 4. A data processing apparatus according to claim 1, wherein the range definition register is a data value range definition register, the range specifier is a data value range specifier, and the range of the data identifier is a range of data values ​​defined at least in part by the data value range specifier.

12. processing circuitry for performing data processing operations; at least one capability register configured to store at least one capability pointer; a decoding circuit responsive to a sequence of instructions for generating control signals for said processing circuitry to cause said processing circuitry to perform said data processing operations in accordance with said sequence of instructions; the data processing instructions include at least one capability pointer processing instruction; In response to the at least one capability pointer processing instruction specifying the at least one capability register, the processing circuitry performs at least one data processing operation with respect to the at least one capability register; the range definition register is a capability register; The data processing device according to any one of claims 1 to 11.

13. 13. A data processing apparatus according to claim 12, wherein the data processing instruction includes a capability pointer generation instruction, and wherein the decoding circuitry is responsive to the capability pointer generation instruction to cause the processing circuitry to generate the range specifier when the capability pointer generation instruction specifies the range definition register as a destination register.

14. 11. The data processing device of claim 1, wherein the filtering circuit is a memory protection circuit, and the filtering operation with respect to the specified transaction includes preventing the specified transaction from accessing the memory address if the attribute data associated with the memory region indicates that access to the memory address is prohibited.

15. 15. A data processing apparatus according to claim 1, wherein the filtering circuit is a monitoring circuit, and wherein the filtering operation with respect to the specified transaction comprises generating a notification when the attribute data associated with the memory region indicates that an access to the memory address should be subject to a monitoring action.

16. The monitoring circuit the debug circuitry and the filtering operation with respect to the specified transaction constitute a debug operation; the tracing circuitry and the filtering operation with respect to the specified transaction constitute a tracing operation; the watchpoint circuit and the filtering operation with respect to the specified transaction constitute a watchpoint operation; 16. The data processing apparatus of claim 15, wherein the data processing apparatus is one of:

17. A processor-implemented method comprising: storing a range specifier in a range definition register; performing a filtering operation on a specified transaction by referencing the range definition register; A method comprising: the range definition register is configured to store the range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by said range specifier, and said specified transaction is for a data identifier within said range of data identifiers, modifying the filtering operation in dependence on attribute data associated with the range of data identifiers; the range definition register is a memory region range definition register, and the range specifier is a memory region range specifier; the data identifier range is a memory region defined at least in part by the memory region range specifier; If the memory region does not correspond to the specified transaction, a memory region specifier lookup procedure is performed to read replacement contents of the memory region range definition register.

18. 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: range definition register logic configured to store a range specifier; and filtering logic configured to perform a filtering operation on transactions specified by referencing the range definition register logic; the range definition register is configured to store the range specifier in a format including a mantissa and an exponent; If a range of data identifiers is defined at least in part by said range specifier, and said specified transaction is for a data identifier within said range of data identifiers, the filtering operation performed by the filtering logic depends on attribute data associated with the range of data identifiers; the range definition register is a memory region range definition register, and the range specifier is a memory region range specifier; the data identifier range is a memory region defined at least in part by the memory region range specifier; If the memory region does not correspond to the specified transaction, the filtering logic performs a memory region specifier lookup procedure to read replacement contents of the memory region range definition register.

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