Data transfer device and data transfer system including the same

Abstract

To provide a data transfer apparatus configured to properly transfer data even when high-priority data and low-priority data exist together.SOLUTION: A DMA unit 1 includes: a calculation unit 14 which calculates required transfer time TR necessary for executing transfer requests, for each of the transfer requests, and sets the order of executing the transfer requests so that the required transfer time TR for each of the transfer requests may fall within allowable transfer time TA for the transfer request; and a transfer control unit 15 which executes the transfer requests in the order set by the calculation unit 14. The allowable transfer time TA for each of the transfer requests is set in accordance with priority of the transfer request.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a data transfer device and a data transfer system including the same. [Background technology]

[0002] In a computer system, the CPU (Central Processing Unit) and multiple peripheral circuits are connected by a system bus, and data is transferred between each component. If the CPU were to directly operate the system bus to transfer data, calculations would not be possible during that time, so data transfers using DMA (Direct Memory Access) are used, which does not involve the CPU.

[0003] For example, Japanese Patent Application Laid-Open Publication No. 2007-183692 (Patent Document 1) discloses a technology that reduces the occupancy rate of the system bus and enables efficient data transfer by providing a dedicated line for making DMA transfer requests in addition to the system bus on which DMA transfers are performed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-183692 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional DMA data transfers, when multiple components simultaneously request data transfers, the data transfers are often performed based on a predefined priority order. For example, data transfers with a first peripheral circuit are given high priority, and data transfers with a second peripheral circuit are given low priority.

[0006] However, in this data transfer method, the priority of data transfer is fixed, so if high-priority data and low-priority data are transferred together, the data cannot be transferred with appropriate priority.

[0007] For example, even if a first peripheral circuit wants to transfer low-priority data, the data may be transferred as high-priority data, which may interfere with the data transfer of a second peripheral circuit. Also, when a first peripheral circuit wants to transfer high-priority data, if another component transfers data set with an even higher priority, the data transfer of the first peripheral circuit may be delayed longer than expected.

[0008] Therefore, the main object of the present disclosure is to provide a data transfer device and a data transfer system equipped with the same that are capable of appropriately transferring data even when high-priority data and low-priority data are mixed. [Means for solving the problem]

[0009] The data transfer device disclosed herein is a data transfer device that transfers data in accordance with multiple transfer requests. Each transfer request includes first information related to the required transfer time for executing the transfer request, and second information indicating the maximum allowable transfer time, which is the maximum time allowed for completing the data transfer for the transfer request. This data transfer device includes a calculation unit that sets the order in which the multiple transfer requests are to be executed based on the first and second information of each transfer request, and a transfer control circuit that executes the multiple transfer requests in the order set by the calculation unit. [Effects of the Invention]

[0010] In the data transfer device disclosed herein, the order in which transfer requests are executed is set for each transfer request, so that data can be transferred appropriately even if high-priority data and low-priority data are mixed. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing a configuration of a data transfer system according to a first embodiment. [Figure 2] 2 is a diagram illustrating the operation of the data transfer system shown in FIG. [Figure 3] 1. FIG. 4 is another diagram illustrating the operation of the data transfer system shown in FIG. [Figure 4] 1. FIG. 4 is yet another diagram illustrating the operation of the data transfer system shown in FIG. [Figure 5] 1. FIG. 4 is yet another diagram illustrating the operation of the data transfer system shown in FIG. [Figure 6] 6 is a flowchart showing part of the operation of the transfer control circuit shown in FIGS. 2 to 5. [Figure 7] 7 is a flowchart showing the remaining part of the operation of the transfer control circuit shown in FIG. 6. [Figure 8] 6 is a flowchart showing the operation of an individual counter included in the transfer time counter shown in FIGS. [Figure 9] 6 is a flowchart showing part of the operation of the transfer time calculation unit shown in FIGS. 2 to 5. [Figure 10] 10 is a flowchart showing the remaining part of the operation of the required transfer time calculation unit shown in FIG. [Figure 11] 10 is a flowchart showing a part of the operation of a modification of the first embodiment. [Figure 12] 12 is a flowchart showing the remaining part of the operation of the modified example shown in FIG. 11. [Figure 13] FIG. 10 is a block diagram showing a configuration of a data transfer system according to a second embodiment. [Figure 14] 14 is a flowchart showing a main part of the operation of the required transfer time calculation unit shown in FIG. 13. [Figure 15] FIG. 11 is a block diagram showing a configuration of a data transfer system according to a third embodiment. [Figure 16] 16 is a flowchart showing a main part of the operation of the required transfer time calculation unit shown in FIG. 15. DETAILED DESCRIPTION OF THE INVENTION

[0012] Embodiment 1 1 is a block diagram showing the configuration of a data transfer system according to the first embodiment. In this data transfer system, when each component wants to transfer a mixture of high-priority data and low-priority data, the data with the highest priority is transferred first. In FIG. 1, this data transfer system includes a DMA unit 1, a system bus 2, a RAM (Random Access Memory) 3, peripheral circuits 4 and 5, and an MPU (Micro Processor Unit) 6.

[0013] The DMA unit 1 (data transfer device) is a circuit used to transfer data from one component to another. Each of the peripheral circuits 4 and 5 is a block that outputs a data transfer request to the DMA unit 1. Examples of the peripheral circuits 4 and 5 include a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), and an IF (Interface) that communicates with the outside. The MPU 6 includes a CPU and performs various calculations and controls. In this data transfer system, data is transferred by DMA without going through the CPU of the MPU 6.

[0014] In a typical data transfer system, a data transfer request includes a source address, a destination address, and a transfer data capacity. The transfer data capacity constitutes an example of first information related to the required transfer time TR. In the first embodiment, the data transfer request further includes second information indicating the allowable transfer time TA. The required transfer time TR and the allowable transfer time TA will be described later.

[0015] RAM 3 is a memory shared by DMA unit 1, peripheral circuit 4, peripheral circuit 5, and MPU 6. RAM 3 writes and reads data in response to a data transfer request from DMA unit 1. In the first embodiment, peripheral circuits 4 and 5 transmit a data transfer request to DMA unit 1 via system bus 2, and DMA unit 1 transfers data to RAM 3.

[0016] DMA unit 1 includes an allowable transfer time holding unit 11, a data buffer 12, a BUS / IF (Interface) 13, a required transfer time calculation unit 14, a transfer control circuit 15, a transfer time counter 16, a destination address pointer 17, and a source address pointer 18. Hereinafter, allowable transfer time holding unit 11 and required transfer time calculation unit 14 may be simply referred to as "holding unit 11" and "calculation unit 14", respectively.

[0017] The data buffer 12 temporarily stores data read from the data transfer source by the transfer control circuit 15. When a write request is output from the transfer control circuit 15, the data buffer 12 writes the data stored in the data buffer 12 to the transfer destination.

[0018] The BUS / IF 13 is a block that aligns the bus protocol between the system bus 2 and the data buffer 12. In accordance with the specifications of the system bus 2, the BUS / IF 13 exchanges signals in accordance with the rules required for transfer, such as the transfer method and data capacity.

[0019] The holding unit 11 holds the allowable transfer time TA for transfer from the transfer request source, and outputs the allowable transfer time TA to the calculation unit 14. The calculation unit 14 calculates the required transfer time TR. The required transfer time TR is the time required from when the DMA unit 1 receives a transfer request from the transfer request source until when the DMA unit 1 sends a completion notification to the transfer request source.

[0020] The calculation unit 14 calculates the required transfer time TR based on the calculation request, transfer data capacity, transfer request, and current transfer order sent from the transfer control circuit 15, as well as information on the bus protocol (bus bit width, burst length, transfer interval, etc.). The method for calculating the required transfer time TR will be described later.

[0021] The calculation unit 14 also receives the allowable transfer time TA for each data transfer request from the holding unit 11 and determines whether the transfer will be completed within the allowable transfer time TA. If the required transfer time TR exceeds the allowable transfer time TA, the data transfer cannot be completed within the requested allowable transfer time TA, and an error is notified to the transfer request source (peripheral circuits 4 and 5 in this example).

[0022] Furthermore, regardless of the relationship between the required transfer time TR and the allowable transfer time TA, the calculation unit 14 responds to the transfer control circuit 15 with the transfer order determined from the calculation result of the required transfer time TR as a new transfer order. That is, the calculation unit 14 reconsiders the appropriate transfer order based on the current transfer order and the recalculation result of the required transfer time TR, and responds with the new transfer order.

[0023] If a second or third transfer request is input to DMA unit 1 while a transfer is in progress, calculation unit 14 recalculates the required transfer time TR. Based on the result, calculation unit 14 determines in what order the newly input transfer requests should be inserted into the current transfer order, and notifies transfer control circuit 15 of the new transfer order obtained as a result. The detailed operation of calculation unit 14 will be described later.

[0024] When a transfer request is made to the DMA unit 1 from the peripheral circuits 4 and 5, the transfer control circuit 15 acquires the right to occupy the system bus 2 and outputs the data to be transferred from the data buffer 12 to the RAM 3 and the peripheral circuits 4 and 5.

[0025] Furthermore, when transfer control circuit 15 receives a transfer request from peripheral circuits 4, 5, etc., it outputs a start command to transfer time counter 16. Furthermore, transfer control circuit 15 outputs a calculation command for the required transfer time TR and the currently held transfer order to calculation unit 14. Furthermore, transfer control circuit 15 holds the transfer order received from calculation unit 14.

[0026] The transfer time counter 16 (timekeeping unit) measures the time that has elapsed since the arrival of a transfer request from a peripheral component of the DMA unit 1. This elapsed time corresponds to the "processed time" described later, and is used to refer to the remaining transfer time, which is the value obtained by subtracting the time measured by the counter from the first transfer allowable time TA, when a second data transfer request arrives. When multiple transfer requests arrive, the transfer time counter 16 has a counter for the maximum number of transfer requests that can occur during one transfer, in order to calculate the remaining transfer time for each of them.

[0027] The destination address pointer 17 indicates the address of the transfer destination. The source address pointer 18 indicates the address of the transfer source. The transfer control circuit 15 transfers data from the transfer source address indicated by the source address pointer 18 to the transfer destination address indicated by the destination address pointer 17.

[0028] The DMA unit 1 in this embodiment 1 is characterized by receiving an additional constraint, the allowable transfer time TA, from the transfer request source (peripheral circuits 4 and 5 in this example), which is not present in general DMA, and thereby flexibly determining the priority of data transfer and transferring data.

[0029] Here, the allowable transfer time TA is the maximum allowable time from when a transfer request source requests a data transfer until the transfer request source receives notification that the data transfer has been completed. In other words, the allowable transfer time TA means the time limit within which the data transfer requested by the transfer request source must be completed. Each transfer request source sets a short allowable transfer time TA for data transfer requests with high priority and a long allowable transfer time TA for data transfer requests with low priority.

[0030] Based on the allowable transfer time TA and related information (such as the required transfer time TR, which will be described later), the DMA unit 1 performs priority control to determine the order in which data transfer requests should be executed so that the data transfer is completed within the allowable transfer time TA for each data transfer request.

[0031] If the transfer cannot be completed within the allowed time TA, the DMA unit 1 notifies the transfer request source that the transfer cannot be completed in time as an error. By adopting this allowed transfer time TA, the DMA unit 1 can determine the transfer request with the highest priority from among multiple data transfer requests, and can execute the transfer with the highest priority first even in a data transfer with mixed priorities.

[0032] Figure 2 is a diagram showing the data transfer operation of this data transfer system. In Figure 2, we consider a case where data transfer requests are made from two transfer request sources, RS1 (peripheral circuit 4 in this example) and RS2 (peripheral circuit 5 in this example), and transfer data is read from transfer request source RS1 and transfer request source RS2 and written to the same RAM 3. When actually using this data transfer system, the data transfer request source, transfer source (source address), transfer destination (destination address), and the number and type of components are not important.

[0033] When a data transfer request R1 is sent from data transfer request source RS1 to transfer control circuit 15, transfer control circuit 15 first outputs a start command to counter C1 in transfer time counter 16, and counter C1 counts the time from the time of acceptance of data transfer request R1. This transfer time counter 16 and transfer control circuit 15 are required to perform a calculation to determine the priority of transfer requests R1 and R2 when a second data transfer request R2 occurs.

[0034] At the same time, transfer control circuit 15 writes allowable transfer time TA1 to holding unit 11. Holding unit 11 notifies calculation unit 14 of allowable transfer time TA1. Thereafter, transfer control circuit 15 requests calculation unit 14 to calculate required transfer time TR1. This required transfer time TR1 is the time required from receiving data transfer request R1 from transfer request source RS1 to completing data transfer to the transfer destination (RAM3).

[0035] The transfer time TR1 is calculated from the values ​​of the transfer data capacity, system frequency, and bus protocol (bus bit width, burst length, transfer interval, etc.). The transfer data capacity is the size of the data D1 specified by the transfer request source RS1. The system frequency is the clock frequency that operates the DMA unit 1 itself, and is determined by the system design. The burst length is the data size that can be transferred in one transaction (read and write) as determined by the bus protocol. The transfer interval is the time that must be left between the end of the previous transaction and the start of the current transaction when multiple transactions are issued consecutively.

[0036] The transfer rate (bits / sec) per unit time of data transfer is calculated from the system frequency and bus protocol. The transfer data capacity (bits) is then divided by the transfer rate to calculate the required transfer time TR. The calculation unit 14 (FIG. 1) calculates the required transfer time TR from the data transfer request information in this way, and notifies the transfer control circuit 15 of the transfer order determined from the result.

[0037] Here, if the transfer rate is Rt [bit / sec], the data bit width of the bus is Wb, the burst length is Lb, the number of clocks required per burst is Nc [clk], the system frequency is Fs [clk / sec], and the transfer interval is Dt [sec], then Rt = (Wb x Lb) / [(Nc / Fs) + Dt]. Also, if the required transfer time is TR [sec] and the transfer data capacity is Dc [bit], then TR = Dc / Rt.

[0038] The calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 notified by the holding unit 11, and if TR1≦TA1, it responds with the transfer order to the transfer control circuit 15. At this point, there is only one transfer request R1, so the transfer order sent from the calculation unit 14 to the transfer control circuit 15 indicates that data D1 for which transfer request R1 has been made will be transferred first. Thereafter, the transfer control circuit 15 reads data D1 from the data transfer source (transfer request source RS1 in this example) and stores that data D1 in the data buffer 12. Note that the operation when TR1>TA1 will be described later (FIG. 4).

[0039] Next, the transfer control circuit 15 starts the transfer process from the data buffer 12 to the transfer destination (RAM 3 in this example). Specifically, the transfer control circuit 15 receives the transfer data from the data buffer 12 in an amount that can be transferred at one time, and starts writing it to RAM 3. The amount of data that can be transferred at one time depends on the bus protocol.

[0040] Regarding the operation of reading transfer data D1 from data transfer request source RS1 and storing it in data buffer 12 and writing it to RAM3, in FIG. 2, data D1 is written to RAM3 after all data D1 has been written to data buffer 12, but if a bus protocol or the like is used in which the data read channel and write channel are independent, the two operations may be performed in parallel.

[0041] Next, suppose that a second data transfer request R2 is issued from data transfer request source RS2 during execution of data transfer based on data transfer request R1. In this case, transfer control circuit 15 temporarily stops writing data to RAM 3 and suspends the data transfer. At the same time, transfer control circuit 15 starts counter C2 in transfer time counter 16 and writes permissible transfer time TA2 to holding unit 11.

[0042] Then, transfer control circuit 15 commands calculation unit 14 to calculate required transfer times TR1 and TR2. In this case, required transfer time TR1 is recalculated. At this time, since a certain amount of data transfer has already been completed in response to transfer request R1, calculation unit 14 replaces the transfer data capacity in the calculation formula with the remaining amount of data that must be transferred (remaining data amount). The remaining amount of data D1 is notified to calculation unit 14 by data buffer 12.

[0043] At the same time, transfer control circuit 15 outputs a count value output command to counters C1 and C2 in transfer time counter 16 to cause them to output the times they have measured as processed times TP1 and TP2 to calculation unit 14, so that calculation unit 14 can calculate a new transfer order according to the priority from among the multiple transfer requests. Also, holding unit 11 notifies calculation unit 14 of allowable transfer times TA1 and TA2.

[0044] Here, consider a case where, as a result of calculation by the calculation unit 14, the following condition (1) is false and the following condition (2) is true. Condition (1): TR1+TR2≦TA2-TP2 Condition (2): TR1+TR2≦TA1-TP1

[0045] In this case, if condition (1) is false, it means that the remaining required time (TR1+TR2) is greater than the remaining allowable time (TA2-TP2), and therefore data D2 must be transferred before data D1 in order to complete the transfer of data D2 within the remaining allowable time (TA2-TP2).

[0046] Furthermore, the fact that condition (2) is true indicates that the remaining required time (TR1+TR2) is equal to or less than the remaining allowable time (TA1-TP1), which means that the order in which data D2 and data D1 are transferred can be either in order to complete the transfer of data D1 within the remaining allowable time (TA1-TP1).

[0047] Therefore, if condition (1) is false and condition (2) is true, calculation unit 14 determines that data D2 needs to be transferred before data D1, and transmits information indicating this to transfer control circuit 15 as the transfer order.

[0048] In other words, the calculation unit 14 sets the order in which the transfer requests R1 and R2 are executed so that the sum of the recalculated required transfer time TR1 and the waiting time TR2 required to execute another transfer request R2 scheduled before the start of the transfer request R1 falls within the allowable transfer time (TA1-TP1) of the transfer request R1.

[0049] Further details on which transfer request is given priority for transmission based on the required transfer time TR will be described later. If condition (1) is false and condition (2) is true, transfer control circuit 15 receives the transfer order (information that data D2 is to be transferred with priority over data D1) from calculation unit 14, and then reads data D2 from transfer request source RS2 and writes that data D2 to RAM3. At this time, transfer control circuit 15 writes data D2 read from transfer request source RS2 to data buffer 12, just like data D1, and writes data D2 read from data buffer 12 to RAM3.

[0050] When writing of data D2 to RAM 3 is completed, transfer control circuit 15 notifies data transfer request source RS2 of the completion of the data transfer. At the same time, transfer control circuit 15 outputs a command to transfer time counter 16 to stop counter C2.

[0051] After that, the transfer control circuit 15 resumes the interrupted writing of the data D1. When the transfer control circuit 15 completes writing of the data D1 and outputs a data transfer completion notification to the data transfer request source RS1, it simultaneously outputs an initialization command to the counter C1 in the transfer time counter 16.

[0052] 3 is another diagram showing the data transfer operation of this data transfer system. Fig. 3 shows the operation when, when a data transfer request R2 occurs while a data transfer request R1 is being executed, the transfer request R1 is given priority and the transfer request R2 is executed next. This operation is the same as the operation shown in Fig. 2 until the data transfer request R2 occurs, but differs from the operation shown in Fig. 2 in that the calculation unit 14 then determines that the transfer request R1 should be executed with priority.

[0053] That is, when a transfer request R2 is sent from the data transfer request source RS2 to the transfer control circuit 15, the transfer control circuit 15 outputs a command to the calculation unit 14 to recalculate the required transfer times TR1 and TR2.

[0054] Here, consider a case where the calculation unit 14 recalculates the required transfer times TR1 and TR2, and as a result, the following condition (1) is true and the following condition (3) is true. Condition (1): TR1+TR2≦TA2-TP2 Condition (3): TA1-TP1-TR1≦TA2-TP2-TR2

[0055] If condition (1) is true, it means that the remaining required time (TR1+TR2) is less than or equal to the remaining allowable time (TA2-TP2), and that the order in which data D1 and data D2 are transferred can be either one in order to complete the transfer of data D2 within the remaining allowable time (TA2-TP2).

[0056] Furthermore, condition (3) indicates that the difference between the remaining allowable time (TA1-TP1) and the required time TR1 (i.e., the time available for transferring data D1) is equal to or less than the difference between the remaining allowable time (TA2-TP2) and the required time TR2 (i.e., the time available for transferring data D2). Therefore, calculation unit 14 determines that data D1 needs to be transferred before data D2, and transmits this transfer order to transfer control circuit 15.

[0057] In this case, the sum (TR2+TR1) of the required transfer time TR2 and the waiting time TR1 required to execute another transfer request R1 scheduled before the start of transfer request R2 falls within the remaining allowable time (TA2-TP2) of transfer request R2.

[0058] The transfer control circuit 15 resumes writing data D1 to RAM3 in the order of transfer from the calculation unit 14. After the transfer of data D1 is completed, the transfer control circuit 15 transfers a data transfer completion notification to the data transfer request source RS1 and starts transferring data D2. After the transfer of data D2 to RAM3 is completed, the transfer control circuit 15 sends a data D2 transfer completion notification to the data transfer request source RS2.

[0059] On the other hand, if condition (1) is true and condition (3) is false, the time available for the transfer of data D1 is greater than the time available for the transfer of data D2. Therefore, calculation unit 14 determines that data D2 needs to be transferred before data D1, and transmits this transfer order to transfer control circuit 15. In this case, the operation of transfer control circuit 15 is the same as in FIG. 2. Furthermore, required transfer time TR2 is the waiting time until the transfer of data D1 is resumed.

[0060] 4 is yet another diagram showing the data transfer operation of this data transfer system. Fig. 4 shows the operation when the required transfer time TR1 calculated by the calculation unit 14 in response to the first transfer request R1 from the transfer request source RS1 exceeds the allowable transfer time TA1 (TR1>TA1).

[0061] When the transfer request source RS1 transmits the destination address, the source address, the capacity of the transfer data D1, and the allowable transfer time TA1 to the transfer control circuit 15, the transfer control circuit 15 outputs a counter start command to the counter C1 in the transfer time counter 16 and writes the allowable transfer time TA1 to the holding unit 11.

[0062] Next, the transfer control circuit 15 transmits the capacity of the transfer data D1 to the calculation unit 14, and the holding unit 11 outputs the allowable transfer time TA1 to the calculation unit 14. The calculation unit 14 calculates the required transfer time TR1 from the capacity of the transfer data D1 and the transfer interval based on the bus protocol or the like, and compares the required transfer time TR1 with the allowable transfer time TA1.

[0063] Here, we will explain the case where TR1≦TA1 is false, that is, the required transfer time TR1 is greater than the allowable transfer time TA1, and the data transfer cannot be completed within the allowable transfer time TA1. In this case, the calculation unit 14 sends the transfer order and an error detection signal indicating that an error has been detected to the transfer control circuit 15. At this point, only one transfer request R1 has been generated, so the transfer order indicates that data D1 corresponding to transfer request R1 will be transferred first. In response to the error detection signal, the transfer control circuit 15 sends an error notification E1 to the transfer request source RS1.

[0064] After the error notification E1 is issued, the user can select whether to execute the transfer request R1 or to abandon the transfer request R1. If the user abandons the transfer request R1, the DMA unit 1 returns to the state it was in before receiving the data transfer request R1 and enters a standby state.

[0065] The operation when executing transfer request R1 will be described below. After outputting error notification E1, transfer control circuit 15 reads transfer data D1 from transfer request source RS1, and transfer request source RS1 writes data D1 to data buffer 12.

[0066] Thereafter, the transfer control circuit 15 writes the data in the data buffer 12 to the RAM 3. When the transfer of the data D1 is completed, the transfer control circuit 15 outputs a transfer completion notification of the data D1 to the transfer request source RS1, and at the same time outputs an initialization command to the counter C1 in the transfer time counter 16.

[0067] Figure 5 is yet another diagram showing the data transfer operation of this data transfer system. Figure 5 shows the operation when, when the transfer of data D2 is requested while data D1 is being transferred, if data D1 is transferred first, data D2 cannot be transferred within the allowable transfer time TA2, and if data D2 is transferred first, data D1 cannot be transferred within the allowable transfer time TA1.

[0068] That is, when a transfer request R1 is output from a transfer request source RS1 to the transfer control circuit 15, the transfer control circuit 15 starts a counter C1 in the transfer time counter 16 and writes an allowable transfer time TA1 in the holding unit 11.

[0069] Next, transfer control circuit 15 requests calculation unit 14 to calculate required transfer time TR1, and holding unit 11 outputs allowable transfer time TA1 to calculation unit 14. Calculation unit 14 calculates required transfer time TR1 and outputs a transfer order to transfer control circuit 15. This transfer order indicates that data D1 will be transferred first. Transfer control circuit 15 reads data D1 from transfer request source RS1 and writes it to RAM3 until a second data transfer request R2 is input from transfer request source RS2.

[0070] When transfer request R2 is output from transfer request source RS2 to transfer control circuit 15, transfer control circuit 15 outputs a start command for counter C2 to transfer time counter 16. At the same time, transfer control circuit 15 stops writing of data D1 from data buffer 12 to RAM 3, outputs a command to calculate required times TR1 and TR2 to calculation unit 14, and outputs count value output commands to counters C1 and C2 in transfer time counter 16 to output processed times TP1 and TP2 to calculation unit 14. At the same time, transfer control circuit 15 outputs the current transfer order to calculation unit 14.

[0071] The calculation unit 14 receives from the transfer time counter 16 the processed times TP1 and TP2 that have elapsed since the start of the counters C1 and C2 for the transfer requests R1 and R2, respectively, receives from the transfer control circuit 15 the capacity of the data D2 for the transfer request R2, receives from the data buffer 12 the capacity of the data D1, and receives from the holding unit 11 the allowable transfer times TA1 and TA2.

[0072] Here, consider a case where, as a result of the calculation of the required transfer times TR1 and TR2 by the calculation unit 14, the following condition (1) is false and the following condition (2) is false. Condition (1): TR1+TR2≦TA2-TP2 Condition (2): TR1+TR2≦TA1-TP1

[0073] If condition (1) is false, it means that the remaining required time (TR1+TR2) is greater than the remaining allowable time (TA2-TP2), and therefore data D2 must be transferred before data D1 in order to complete the transfer of data D2 within the remaining allowable time (TA2-TP2).

[0074] Furthermore, if condition (2) is false, it means that the remaining required time (TR1+TR2) is greater than the remaining allowable time (TA1-TP1), and therefore data D1 must be transferred before data D2 in order to complete the transfer of data D1 within the remaining allowable time (TA1-TP1).

[0075] In this case, since only one of the allowable time (TA1-TP1) and the allowable time (TA2-TP2) can be satisfied, priority is given to the transfer request R1 that was already being executed. The calculation unit 14 sends an error detection signal to the transfer control circuit 15 to notify it of the transfer order. This transfer order indicates that data D1 is to be transferred first, and data D2 is to be transferred second.

[0076] After receiving the error detection signal and the transfer order from calculation unit 14, transfer control circuit 15 outputs error notification E2 to transfer request source RS2. Thereafter, transfer control circuit 15 resumes writing of data D1 to RAM3, and when writing of data D1 is completed, outputs a transfer completion notification of data D1 to transfer request source RS1, and outputs an initialization command to counter C1 in transfer time counter 16.

[0077] The user can then select whether or not to execute transfer request R2. If transfer request R2 is to be executed, transfer control circuit 15 starts writing data D2 to RAM 3. When the transfer of data D2 is completed, transfer control circuit 15 outputs a transfer completion notification of data D2 to transfer request source RS2, and outputs an initialization command to counter C2 in transfer time counter 16.

[0078] Fig. 6 is a flowchart showing part of the operation of transfer control circuit 15 shown in Fig. 2 to Fig. 5, and Fig. 7 is a flowchart showing the remaining part of the operation. When transfer control circuit 15 is started, transfer control circuit 15 is initialized in step S1. In step S2, transfer control circuit 15 waits until a data transfer request is input from a system component.

[0079] When a data transfer request R1 is input from the transfer request source RS1 (peripheral circuit 4 in this example), in step S3, the transfer control circuit 15 outputs a start command (activation command) to the counter C1 in the transfer time counter 16, activating the counter C1.

[0080] In step S4, transfer control circuit 15 transfers the permissible transfer time TA1 transmitted from transfer request source RS1 to holding unit 11. In step S5, transfer control circuit 15 outputs a calculation request for required transfer time TR1 to calculation unit 14. In step S6, transfer control circuit 15 waits until calculation unit 14 transmits a transfer order or error detection signal.

[0081] In step S7, the transfer control circuit 15 determines whether an error detection signal has been sent, and if it determines that an error detection signal has been sent, in step S8 it outputs an error notification E1 to the transfer request source RS1, and then in step S8A it determines whether the user has abandoned the transfer request R1.

[0082] Note that whether or not the user has discarded the transfer request R1 may be determined in any manner, and one example is a method in which whether or not to discard the transfer request R1 when it is determined in step S7 that an error detection signal has been transmitted is set in advance in the DMA unit 1. Alternatively, when it is determined in step S7 that an error detection signal has been transmitted, this fact may be notified to the transfer request source RS1, and an instruction as to whether or not to discard the transfer request R1 may be received from the transfer request source RS1, thereby determining whether or not the user has discarded the transfer request R1.

[0083] If the transfer control circuit 15 determines in step S8A that the user has discarded the transfer request R1, it returns to step S2, and if it determines that the user has not discarded the transfer request R1, it proceeds to step S10.

[0084] If it is determined in step S7 that an error detection signal has not been sent, in step S9 the transfer control circuit 15 determines whether or not there is a transfer request R2 from the transfer request source RS2 (in this example, the peripheral circuit 5), and if there is a transfer request R2, proceeds to step S14 (Figure 7), and if there is no transfer request R2, proceeds to step S10.

[0085] In step S10, the transfer control circuit 15 acquires data D1 from the transfer data source DS1 (in this example, the peripheral circuit 4) and continues to transfer the data D1 to the transfer destination DD1 (in this example, the RAM 3). In step S11, the transfer control circuit 15 determines whether the transfer of data D1 is complete or not, and returns to step S9 if the transfer of data D1 is not complete, and proceeds to step S12 if the transfer of data D1 is complete.

[0086] In step S12, the transfer control circuit 15 sends a data transfer completion notification to the transfer request source RS1. In step S13, the transfer control circuit 15 outputs an initialization command to the counter C1 in the transfer time counter 16, and returns to step S2 to wait until the next transfer request is generated.

[0087] If a second data transfer request R2 occurs in step S9, in step S14 (Figure 7), the transfer control circuit 15 outputs a start command to counter C2 in the transfer time counter 16 to measure the time that has elapsed since the data transfer request R2 occurred.

[0088] In step S15, the transfer control circuit 15 writes the permissible transfer time TA2 transmitted from the transfer request source RS2 into the holding unit 11. In step S16, the transfer control circuit 15 outputs a command to the calculation unit 14 to recalculate the required transfer times TR1 and TR2. In step S16A, the transfer control circuit 15 outputs a count value output command to the transfer time counter 16 to output the processed times TP1 and TP2. In step S17, the transfer control circuit 15 waits until the calculation unit 14 transmits a transfer order or error detection signal.

[0089] In step S18, the transfer control circuit 15 determines whether an error detection signal has been sent, and if it determines that an error detection signal has been sent, in step S19 it outputs an error notification E2 to the transfer request source RS2, and then in step S19A it determines whether the user has discarded the transfer request R2.

[0090] Note that whether or not the user has discarded the transfer request R2 may be determined in any manner, and one example is a method in which whether or not to discard the transfer request R2 when it is determined in step S18 that an error detection signal has been transmitted is set in advance in the DMA unit 1. Alternatively, when it is determined in step S18 that an error detection signal has been transmitted, this fact may be notified to the transfer request source RS2, and an instruction as to whether or not to discard the transfer request R2 may be received from the transfer request source RS2, thereby determining whether or not the user has discarded the transfer request R2.

[0091] If the transfer control circuit 15 determines in step S19A that the user has discarded the transfer request R2, it proceeds to step S29, and if it determines that the user has not discarded the transfer request R2, it proceeds to step S21. If it determines in step S18 that an error detection signal has not been transmitted, it proceeds to step S20.

[0092] In step S20, the transfer control circuit 15 determines whether or not to prioritize the transfer request R1 based on the transfer order sent from the calculation unit 14. If it determines that the transfer request R1 is not prioritized, the process proceeds to step S27, and if it determines that the transfer request R1 is prioritized, the process proceeds to step S21.

[0093] In step S21, the transfer control circuit 15 transfers all data D1 from the transfer data source DS1 to the transfer destination DD1, in step S22 it sends a data transfer completion notification to the transfer request source RS1, and in step S23 it outputs an initialization command to the counter C1 in the transfer time counter 16.

[0094] Next, in step S24, transfer control circuit 15 transfers all data D2 from transfer data source DS2 (peripheral circuit 5 in this example) to transfer destination DD2 (RAM3 in this example), sends a data transfer completion notification to transfer request source RS2 in step S25, and outputs an initialization command to counter C2 in transfer time counter 16 in step S26. Thereafter, transfer control circuit 15 returns to step S2 (FIG. 6) and waits until the next transfer request R1 is input.

[0095] If it is determined in step S20 that the transfer request R1 does not have priority, the transfer control circuit 15 transfers all data D2 from the transfer data source DS2 (in this example, peripheral circuit 5) to the transfer destination DD2 (in this example, RAM3) in step S27, sends a data transfer completion notification to the transfer request source RS2 in step S28, and outputs an initialization command to the counter C2 in the transfer time counter 16 in step S29.

[0096] Next, in step S30, transfer control circuit 15 transfers all data D1 from transfer data source DS1 to transfer destination DD1, in step S31 sends a data transfer completion notification to transfer request source RS1, and in step S32 outputs an initialization command to counter C1 in transfer time counter 16. Thereafter, transfer control circuit 15 returns to step S2 (FIG. 6) and waits until the next transfer request R1 is input.

[0097] 8 is a flowchart showing the operation of an individual counter C included in the transfer time counter 16. The transfer time counter 16 includes a plurality of independent individual counters C. Each individual counter C operates independently for each data transfer, and measures the processed time TP for each data transfer.

[0098] When the DMA unit 1 is started, the individual counter C is initialized in step S60. At this time, the count value of the individual counter C is set to the initial value. In step S61, the individual counter C waits until a start command is input from the transfer control circuit 15.

[0099] In step S62, the count value of the individual counter C to which the start command has been input is incremented (+1) in response to each pulse of the system clock. In step S63, the individual counter C determines whether or not there is a count value output command from the transfer control circuit 15. If it is determined that there is a count value output command, the process proceeds to step S65, and if it is determined that there is no count value output command, the process proceeds to step S64.

[0100] In step S64, the individual counter C determines whether or not there is an initialization command from the transfer control circuit 15, and if it determines that there is an initialization command, it returns to step S60, and if it determines that there is no initialization command, it returns to step S62.

[0101] If it is determined in step S63 that there is a count value output command, then in step S65, the individual counter C transmits the current count value to the calculation unit 14, and then the process returns to step S62.

[0102] Next, a method for determining which of the transfer request R1 input first and the transfer request R2 input later should be given priority will be described. It is assumed that the required transfer time TR1 of the transfer request R1 is equal to or less than the allowable transfer time TA1 (TR1≦TA1), and similarly, the required transfer time TR2 of the transfer request R2 is equal to or less than the allowable transfer time TA2 (TR2≦TA2). If this assumption is not met, an error notification is sent to the transfer request source at the time the data transfer request is accepted, as shown in steps S6 to S8 (FIG. 6) and steps S17 to S19 (FIG. 7).

[0103] First, we will explain case CA1, where when transfer request R2 is executed after transfer request R1 is executed, it falls within the transfer allowable time TA2 and the slack time TM1 is equal to or less than the slack time TM2. Here, the slack time TM is time information that indicates how much leeway there is in the time required for issuing a transfer completion notification for a certain data transfer request compared to the transfer allowable time TA.

[0104] Before a certain data transfer request (e.g., R2) can begin to be executed, another data transfer request (e.g., R1) may be executed first, and in that case the start of the own transfer request (R2 in this case) must wait the time required for the other data transfer request (R1 in this case) (TR1 in this case). For this reason, the slack time TM is calculated as follows:

[0105] Here, if there are a total of n data transfer requests, the lowercase letter n is used to distinguish each transfer request from the others, and they are represented as transfer request R1, transfer request R2, ..., transfer request Rn, and the uppercase letter N indicates the order in which each transfer request is executed, and they are represented as 1st, 2nd, ..., Nth.

[0106] The slack time TMn when transfer request Rn is transferred Nth is TMn = TAn - SUM(N-1) - TRn - TPn, where SUM(N-1) = [TR1 + TR2 + ... + TR(N-1)], and SUM(N-1) is the sum of the transfer times TR required for the transfer requests executed from the first to the (N-1)th.

[0107] In the above example, since it is being determined which of the two transfer requests R1 and R2 will be transferred first, there are no transfer requests that are made before transfer requests R1 and R2. Therefore, the "sum SUM(N-1) of the transfer times TR required to be executed before transfer request Rn" in the above formula is 0. In other words, SUM(1-1) = SUM(0) = 0. Therefore, TM1 = TA1 - TP1 - TR1, and TM2 = TA2 - TP2 - TR2.

[0108] Even if data transfer by transfer request R1 is resumed and then data transfer by transfer request R2 is performed, if the data transfer falls within the allowable transfer time TA2 and the surplus time TM1 is equal to or less than the surplus time TM2 (TM1≦TM2, i.e., TA1-TP1-TR1≦TA2-TP2-TR2), transfer request R2 is executed after transfer request R1.

[0109] For case CA1 to be true, condition (1), ie, TR1+TR2≦TA2−TP2, must be true, and condition (3), ie, TA1−TP1−TR1≦TA2−TP2−TR2, must be true.

[0110] Next, we will explain case CA2, where when transfer request R2 is executed after transfer request R1 is executed, it falls within the transfer allowable time TA2 and the surplus time TM1 is greater than the surplus time TM2 (TM1>TM2, i.e., TA1-TP1-TR1>TA2-TP2-TR2).

[0111] In this case, even if the transfer of data D1 is resumed and then data D2 is transferred, the transfer will still be within the allowable transfer time TA2, but the slack time TM2 is shorter than the slack time TM1. Therefore, if a new data transfer request R3 occurs when data D2 is transferred after data D1, if data transfer request R3 is executed before data transfer request R2, there is a high possibility that the allowable time TA2 for data transfer request R2 will not be met. For this reason, in order to meet the allowable time TA as much as possible when there are multiple data transfer requests, transfer request R2 is executed first, followed by transfer request R1.

[0112] For case CA2 to be true, condition (1), ie, TR1+TR2≦TA2−TP2, must be true, and condition (3), ie, TA1−TP1−TR1≦TA2−TP2−TR2, must be false.

[0113] Next, we will explain case CA3, where the transfer of data D2 is too late after the transfer of data D1, but by transferring data D2 first, the allowable transfer time TA2 is satisfied, and then by transferring data D1, the allowable transfer time TA1 is satisfied. In this case, if data D2 is transferred first and then data D1 is transferred, the allowable transfer time TA will not be exceeded, so data D2 is transferred with priority.

[0114] For case CA3 to be true, condition (1), ie, TR1+TR2≦TA2−TP2, must be false, and condition (2), ie, TR1+TR2≦TA1−TP1, must be true.

[0115] Next, case CA4 will be described, where if data D2 is transferred first, the transfer of data D2 will be in time, but the transfer of data D1 will not be in time. In this case, data D1, which was already being transferred, is transferred first, and an error notification E2 is sent to the transfer request source RS2.

[0116] For case CA4 to be true, condition (1), ie, TR1+TR2≦TA2−TP2, must be false, and condition (2), ie, TR1+TR2≦TA1−TP1, must be false.

[0117] As a supplement, in cases CA1 and CA2, the part where the transfer order is determined based on the slack time TM can be selected by the user because a transfer that satisfies the transfer allowable time TA can be achieved without performing this, and whichever of transfer requests R1 and R2 is performed first will be in time for the respective allowable times TA. If the determination based on the slack time TM is not performed, then if condition (1), i.e., TR1 + TR2 ≦ TA2 - TP2, is true, transfer request R1 is performed first and transfer request R2 is performed second.

[0118] 9 is a flowchart showing a part of the operation of the calculation unit 14, and FIG. 10 is a flowchart showing the remaining part of the operation. When the calculation unit 14 is started, the calculation unit 14 is initialized in step S81. In step S82, the calculation unit 14 waits until a calculation request is input from the transfer control circuit 15.

[0119] When a calculation request is input, the calculation unit 14 determines in step S83 whether the calculation request is caused by the first data transfer request R1. If the calculation unit 14 determines that the calculation request is not caused by the data transfer request R1 (if the calculation request is caused by a second or subsequent data transfer request), the calculation unit 14 proceeds to step S90 (FIG. 10), and if the calculation unit 14 determines that the calculation request is caused by the data transfer request R1 (if there are no other data transfer requests), the calculation unit 14 proceeds to step S84.

[0120] In step S84, the calculation unit 14 obtains the permissible transfer time TA1 from the holding unit 11, and in step S85 obtains the capacity of the data D1 from the transfer control circuit 15. In step S86, the calculation unit 14 calculates the required transfer time TR1 based on the capacity of the data D1, the clock frequency, and the transfer interval according to the bus protocol.

[0121] In step S87, calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 transferred from transfer control circuit 15 to determine whether TR1≦TA1.

[0122] If TR1≦TA1 is not satisfied, then in step S88, the calculation unit 14 outputs the transfer order and error notification E1 to the transfer control circuit 15, and the process returns to step S82. If TR1≦TA1 is satisfied, then in step S89, the calculation unit 14 outputs the transfer order to the transfer control circuit 15, and the process returns to step S82.

[0123] If it is determined in step S83 (FIG. 9) that the transfer is not caused by the data transfer request R1 (if the transfer is caused by a second or subsequent data transfer request), then in step S90 (FIG. 10), the calculation unit 14 obtains the transfer allowable times TA1 and TA2 from the storage unit 11.

[0124] In step S91, the calculation unit 14 obtains the capacity of data D1 and D2 from the data buffer 12, and obtains the transfer order from the transfer control circuit 15. In step S92, the calculation unit 14 obtains the count values ​​from counters C1 and C2 in the counter 16. In step S93, the calculation unit 14 recalculates the transfer times TR1 and TR2.

[0125] In step S94, the calculation unit 14 compares the calculated required transfer time TR2 with the allowable transfer time TA2 transferred from the transfer control circuit 15 to determine whether TR2≦TA2.

[0126] If TR2≦TA2 (YES in step S94), the calculation unit 14 determines in step S95 whether condition (1), i.e., TR1+TR2≦TA2−TP2, is true. If condition (1) is true (YES in step S95), the calculation unit 14 determines in step S96 whether condition (3), i.e., TA1−TP1−TR1≦TA2−TP2−TR2, is true.

[0127] If the condition (3) is true (YES in step S96), the above case CA1 applies, so in step S97, the calculation unit 14 outputs a transfer order to the transfer control circuit 15 indicating that data D1 is to be sent first and data D2 is to be sent second, and then the process returns to step S82 (Figure 9).

[0128] If the condition (3) is false (NO in step S96), the above case CA2 applies, so in step S98 the calculation unit 14 outputs a transfer order to the transfer control circuit 15 indicating that data D2 will be sent first and data D1 will be sent second, and then the process returns to step S82.

[0129] If the condition (1) is false (NO in step S95), the calculation unit 14 determines in step S99 whether the condition (2), ie, TR1+TR2≦TA1−TP1, is true.

[0130] If the condition (2) is true (YES in step S99), the above case CA3 applies, so in step S98 the calculation unit 14 outputs to the transfer control circuit 15 a transfer order indicating that data D2 will be sent first and data D1 will be sent second, and then the process returns to step S82.

[0131] If the condition (2) is false (NO in step S99), the above case CA4 applies, so in step S100 the calculation unit 14 sends an error notification E2 to the transfer request source RS2, and outputs a transfer order indicating that data D1 will be sent first and data D2 will be sent second to the transfer control circuit 15, and then returns to step S82. However, as described above, the user can select whether to transfer data D2 or discard transfer request R2.

[0132] If TR2≦TA2 is not satisfied (NO in step S94), in step S100, the calculation unit 14 sends an error notification E2 to the transfer request source RS2, and outputs a transfer order indicating that data D1 will be sent first and data D2 will be sent second to the transfer control circuit 15, and then returns to step S82. However, even in this case, the user can select whether to transfer data D2 or discard transfer request R2.

[0133] As described above, in the first embodiment, the required transfer time TR is calculated for each transfer request, and the order in which multiple transfer requests are executed is set so that the required transfer time TR for each transfer request falls within the allowable transfer time TA for that transfer request. Furthermore, the allowable transfer time TA is set to a shorter time the higher the priority of the transfer request. Therefore, even when high-priority data and low-priority data are mixed, the high-priority data can be transferred before the low-priority data.

[0134] 11 is a flowchart showing a part of the operation of the calculation unit 14 included in the modification of the first embodiment, and FIG. 12 is a flowchart showing the remaining part of the operation. In the first embodiment, the case where two transfer requests R1 and R2 are generated has been described, but the transfer order can also be determined in a similar manner when three or more transfer requests are generated. In this modification, a data transfer system will be described that can transfer high-priority data before low-priority data even when any number of transfer requests are generated.

[0135] 11, steps S120 to S128 are the same as steps S81 to S89 (FIG. 9). That is, when the calculation unit 14 is started, the calculation unit 14 is initialized and waits until a calculation request is input from the transfer control circuit 15 (steps S120, S121).

[0136] When a calculation request is input, the calculation unit 14 determines whether the calculation request is due to the first data transfer request R1 (step S122), and if it determines that the calculation request is not due to the data transfer request R1 (if it is due to a second or subsequent data transfer request), it proceeds to step S129 (Figure 12), and if it determines that the calculation request is due to the data transfer request R1 (if there are no other data transfer requests), it proceeds to step S123.

[0137] The calculation unit 14 acquires the allowable transfer time TA1 from the holding unit 11 (step S123), acquires the capacity of the data D1 from the transfer control circuit 15 (step S124), and calculates the required transfer time TR1 based on the allowable transfer time TA1, the capacity of the data D1, the clock frequency, and the transfer interval according to the bus protocol (step S125).

[0138] Next, calculation unit 14 compares the calculated required transfer time TR1 with the allowable transfer time TA1 transferred from transfer control circuit 15 to determine whether TR1≦TA1 (step S126).

[0139] If TR1≦TA1 is not satisfied, the calculation unit 14 outputs the transfer order and error notification E1 to the transfer control circuit 15 and returns to step S121 (step S127). If TR1≦TA1 is satisfied, the calculation unit 14 outputs the transfer order to the transfer control circuit 15 and returns to step S121 (step S128).

[0140] If it is determined in step S122 (FIG. 11) that the transfer is not caused by the first data transfer request R1 (if it is caused by a second or subsequent data transfer request), then in step S129 (FIG. 12), the calculation unit 14 acquires the transfer allowable time TA stored in the storage unit 11.

[0141] In step S130, calculation unit 14 obtains the capacity of data D from data buffer 12 and transfer control circuit 15, and obtains the transfer order from transfer control circuit 15. In step S131, calculation unit 14 obtains the count value from counter C in counter 16. In step S132, calculation unit 14 recalculates all required transfer times TR. Although required transfer times TR may have been calculated in the past, recalculation is performed because there is a possibility that the transfer processing has progressed due to data transfer and the amount of transferred data has decreased.

[0142] In step S133, if the total number of transfer requests R is n, the calculation unit 14 sets X=N-1. Now, a newly generated data transfer request Rn will be described, where n is an integer equal to or greater than 2. There are only (n-1) data transfer requests R that were scheduled to be transferred before the data transfer request Rn, and the transfer order of the data D1 to D(n-1) is anywhere from 1st to (N-1).

[0143] The calculation unit 14 repeatedly determines whether transfer request Rn can be executed before transfer requests R1 to R(n-1) that were scheduled before transfer request Rn, starting from the last scheduled transfer request (i.e., the (N-1)th transfer request in the transfer order). For this reason, in step S133, the initial value of variable X for the repetitive processing is expressed as (N-1).

[0144] Here, a method for determining whether to execute transfer request Rn before transfer requests R1 to R(n-1) will be described. It is assumed that, for all transfer requests R, the required transfer time TR is equal to or less than the allowable transfer time TA (TR≦TA). If this assumption is not met, an error is notified to the transfer request source RS at the time of accepting data transfer request R in step S127 (FIG. 11) and step S141 (FIG. 12).

[0145] First, we will explain case CA11, where, after the first through Xth data transfers have been performed, the nth data transfer is performed within the allowable transfer time TAn and the margin time TMX for the Xth data transfer is equal to or less than the margin time TMn. In this case, since the Xth data transfer has a higher priority, the nth data transfer will be performed (X+1).

[0146] To determine that the case is CA11, the following condition (11) and condition (12) must be true (steps S135, S136, S140). Here, SUM(X) is the sum of the required transfer times TR from the first to the Xth transfers. Condition (12) compares the slack times TMn and TMX that would occur if the transfer request Rn and the transfer request originally scheduled for the Xth were executed in the Xth order. Condition (11): TRn+SUM(X)≦TAn-TPn Condition (12): TMX≦TMn, i.e., TAX-(TPX+TRX+SUM(X-1))≦TAn-(TPn+TRn+SUM(X-1))

[0147] Next, we will explain case CA12, where when the nth data transfer is performed after the first to Xth data transfers have been performed, the transfer time falls within the allowable transfer time TAn and the margin time TMX of the Xth data transfer is greater than the margin time TMn.

[0148] In this case, even if the Xth data transfer is performed and then the nth data transfer Rn is performed, it will still fit within the allowable transfer time TAn, but as in case CA2, when a new transfer request, i.e., a transfer request for the (n+1)th or later transfer, occurs, in order to increase the possibility that each data transfer request can be transferred within the allowable time TA, the transfer order of the Xth data transfer and data transfer Rn is swapped (step S137A).As a result, transfer request Rn is executed Xth, and the data transfer that was originally scheduled to be executed Xth is executed (X+1).

[0149] This is the same as swapping the execution order of transfer requests R1 and R2 in case CA2 above. In case CA2, transfer request R1 was originally executed first, but because the slack time TM2 of transfer request R2 is smaller than the slack time TM1 of transfer request R1, transfer request R2 is executed first and transfer request R1 is executed second.

[0150] Furthermore, although transfer request Rn is to be executed Xth, there is a possibility that the margin time TMX of the (X-1)th data transfer executed immediately before transfer request Rn is greater than the margin time TMn of transfer request Rn. Therefore, the value of X is decreased by 1 for the repeated processing, and the determination is made again from case CA11 (steps S138, S139). To be determined as case CA12, the above condition (11) must be true and the above condition (12) must be false (steps S135, S136, S137A).

[0151] Next, as case CA13, we will explain the case where if transfer request Rn is executed after the first to Xth data transfers have been executed, the data transfer will not be completed in time, but if transfer request Rn is transferred before the original Xth data transfer, the original allowable transfer time TA for the Xth data transfer will be satisfied.

[0152] In this case, the allowable time TA is satisfied even if the transfer request that was originally Xth is executed after the transfer request Rn, so the transfer request Rn is executed Xth so that it is executed first, and the data transfer that was originally Xth is executed as (X+1)th.

[0153] To be determined as case CA13, the above condition (11) must be false and the following condition (13) must be true (steps S135, S137, S137A). Condition (11): TRn+SUM(X)≦TAn-TPn Condition (13): TRX+TRn+SUM(X-1)≦TAX-TPX

[0154] In determining case CA13, it should be noted that the order X in conditions (11) and (13) is the original order of the Xth transfer request before swapping the order with transfer request Rn.

[0155] Furthermore, the fact that the condition (11) is false means that the allowable time TAn of the transfer request Rn cannot be satisfied unless the transfer request Rn and the original X-th transfer request are swapped.

[0156] Furthermore, the fact that condition (13) is true means that even if transfer request Rn is executed before data transfer request RX, which was originally the Xth (i.e., even if transfer request Rn is executed Xth and transfer request RX is executed (X+1)th), the allowable transfer time TA of transfer request RX is satisfied.

[0157] Furthermore, after case CA13, in order to determine whether the transfer allowable time TAn can be met and whether it is necessary to further advance the order of transfer request Rn depending on the relative magnitude of the slack time TMn of transfer request Rn and the slack time TM of the transfer immediately before transfer request Rn [the (X-1)th transfer], the value of X is decreased by 1, as in case CA12, and the determination from case CA11 is made again.

[0158] However, in the case of case CA12 and case CA13, if subtracting 1 from X results in 0, there are no more transfer requests to be executed before transfer request Rn, so transfer request Rn is set to be first and the loop is exited (steps S139, S140).

[0159] Furthermore, even if the calculation of the slack time in Cases CA1 and CA2 is not performed, TRn≦TAn and no operational problems occur, so the user can select whether to perform step S136. If step S136 is not performed, the loop ends when the minimum necessary transfer order for transfer request Rn to satisfy the transfer allowable time TAn is determined in step S135.

[0160] As a supplementary explanation, since it is determined in step S134 that TRn≦TAn, even if the order of transfer request Rn becomes the earliest (transfer request Rn becomes the first), an event will not occur in which the transfer allowable time TAn is not met.

[0161] Next, as case CA14, we will explain a case where the allowable transfer time TAn cannot be met after executing the first to Xth data transfers, and when the transfer request Rn is executed before the original Xth transfer request RX, the allowable transfer time TAX of the original Xth transfer request RX cannot be met.

[0162] In this case, the Xth data transfer is executed first. An error notification is sent to the transfer request source that sent the transfer request Rn. If the above condition (11) is false and the condition (13) is false, it is determined that the case is CA14 (steps S135, S137, S141).

[0163] In this case, an error notification for the transfer request Rn is sent to the transfer control circuit 15. The user can select whether or not to implement the transfer request Rn in which the error occurred. If the transfer request Rn is implemented, the transfer request Rn is implemented as the (X+1)th request (step S141).

[0164] Furthermore, if the transfer request Rn that resulted in an error is implemented, there is a high possibility that newly generated transfer requests R(n+1) and thereafter will result in an error until the execution of transfer request Rn is completed. Therefore, depending on the purpose of the system, it may be effective not to implement the transfer request that resulted in an error.

[0165] Referring again to FIG. 12, in step S134, the calculation unit 14 compares the required transfer time TRn with the allowable transfer time TAn for the newly generated transfer request Rn, and determines whether TRn≦TAn.

[0166] If TRn≦TAn (YES in step S134), the calculation unit 14 determines whether or not the condition (11) is true in step S135. If the condition (11) is true (YES in step S135), the calculation unit 14 determines whether or not the condition (12) is true in step S136.

[0167] If the condition (12) is true (YES in step S136), the above case CA11 applies, so in step S140, the calculation unit 14 sends a transfer order to the transfer control circuit 15 indicating that the latest data transfer request Rn will be executed in the (X+1)th order.

[0168] If condition (12) is false (NO in step S136), the above case CA12 applies, so calculation unit 14 swaps the transfer order of the Xth data transfer and data transfer Rn in step S137A, decreases the value of X by 1 in step S138, and determines whether X=0 in step S139. If X=0 (YES in step S139), calculation unit 14 executes step S140. If X=0 is not (NO in step S139), calculation unit 14 returns to step S135.

[0169] If the condition (11) is false (NO in step S135), the calculation unit 14 determines whether the condition (13) is true in step S137. If the condition (13) is true (YES in step S137), the calculation unit 14 corresponds to the above case CA13, and therefore the calculation unit 14 proceeds to step S137A.

[0170] If the condition (13) is false (NO in step S137), the above case CA14 applies, so in step S141 the calculation unit 14 issues an error notification En to the n-th transfer request Rn, responds to the transfer control circuit 15 with a transfer order indicating that the transfer request Rn will be executed in the (X+1)th order, and returns to step S121 (FIG. 11).

[0171] As described above, in this modification, even when an arbitrary number n of transfer requests are generated, data with a higher priority can be transferred before data with a lower priority.

[0172] Embodiment 2 In the first embodiment, if the transfer allowable time TAn cannot be met when the transfer request Rn is executed after the first to Xth data transfers have been executed, and if the transfer request Rn is executed before the original Xth transfer request RX, the transfer allowable time TAX of the original Xth transfer request RX cannot be met (case CA14 above), the transfer request Rn is always executed after the transfer request RX (step S100 in FIG. 10, step S141 in FIG. 12).

[0173] However, depending on the product or system, if a newly generated data transfer request Rn is important, there may be cases where it is required to give priority to the execution of the important transfer request Rn even if it means making the previous transfer request RX wait. This second embodiment aims to solve this problem.

[0174] Figure 13 is a block diagram showing the configuration of a data transfer system according to the second embodiment, and is to be compared with Figure 1. Figure 13 differs from Figure 1 in that peripheral circuits 4 and 5 are replaced with peripheral circuits 21 and 22, respectively, and DMA unit 1 is replaced with DMA unit 25.

[0175] Each of the peripheral circuits 21, 22, as a transfer request source RS, transmits a data transfer request R to the DMA unit 25. This data transfer request R includes a source address, a destination address, first information relating to the required transfer time TR (i.e., the transfer data capacity), and second information indicating the allowable transfer time TA, as well as third information indicating the importance IM of the transfer request R. The importance IM may be defined in any way, but for example, the importance IM is represented by one of the numbers 1, 2, or 3, with the more important the transfer request R, the larger the number.

[0176] DMA unit 25 differs from DMA unit 1 in that importance holding unit 26 is added, and required transfer time calculation unit 14 and transfer control circuit 15 are respectively replaced by required transfer time calculation unit 27 and transfer control circuit 28. Note that required transfer time calculation unit 27 may also be referred to simply as "calculation unit 27" below.

[0177] The importance holding unit 26 holds the importance IM transferred from the transfer request source TS and outputs the importance IM to the calculation unit 27. The calculation unit 27 performs the same operation as the calculation unit 14, and also acquires the importance IM from the importance holding unit 26 when acquiring the permissible transfer time TA from the holding unit 11 (step S123 in FIG. 11, step S129 in FIG. 12).

[0178] Furthermore, if the calculation unit 27 determines that the above case CA14 is true because the above condition (11) is false and the condition (13) is false (NO in step S137 of Figure 12), it compares the importance IMX of the transfer request RX that is Xth in the transfer order with the importance IMn of the newly generated transfer request Rn.

[0179] If the importance IMn of the transfer request Rn is higher than the importance IMX of the transfer request RX, the calculation unit 27 swaps the transfer order of the transfer request Rn and the transfer request RX and notifies the transfer request source RSX of the transfer request RX of an error EX.

[0180] On the other hand, if the importance IMn of the transfer request Rn is equal to or less than the importance IMX of the transfer request RX, the calculation unit 27 does not change the transfer order of the transfer request Rn and the transfer request RX, and notifies the transfer request source RSn of the transfer request Rn of an error En.

[0181] The transfer control circuit 28 performs the same operation as the transfer control circuit 15, and also transfers the importance IM to the importance holding unit 26 when transferring the transfer allowable time TA to the holding unit 11 (step S4 in Figure 6, step S15 in Figure 7).

[0182] Fig. 14 is a flowchart showing the main part of the operation of calculation unit 27, and is a diagram to be compared with Fig. 12. Fig. 14 differs from Fig. 12 in that steps S151 and S152 are added.

[0183] If the result of step S137 is NO, the calculation unit 27 determines in step S151 whether the following condition (14) is true. Condition(14):IMX <IMn

[0184] If the condition (14) is true (YES in step S151), the importance IMn of the transfer request Rn is higher than the importance IMX of the transfer request RX, so the calculation unit 27 sends an error notification EX to the requestor RSX of the transfer request RX in step S152, and then swaps the transfer order of the transfer request RX and the transfer request Rn in step S137A. As a result, the more important transfer request Rn is executed before the transfer request RX.

[0185] In step S152, an error notification EX is sent to the source RSX of the transfer request RX because condition (13) is false (NO in step S137). If the transfer order of the transfer request RX and the transfer request Rn is swapped, the transfer allowable time TAX of the transfer request RX, which was originally the Xth one, cannot be satisfied.

[0186] When condition (14) is false (NO in step S151), since the importance IMn of the transfer request Rn is less than or equal to the importance IMX of the transfer request RX, the calculation unit 27 sends an error notification En to the source RSn of the transfer request Rn in step S141 and responds with the transfer order such that the transfer request Rn is executed after the transfer request RX. Since other configurations and operations are the same as those in the first embodiment, the description thereof will not be repeated.

[0187] As described above, in the second embodiment, in the case of case CA14 (NO in step S137 of FIG. 14), the importance IMX of the transfer request RX and the importance IMn of the transfer request Rn are compared. When IMX < IMn, the transfer request Rn is executed before the transfer request RX. Therefore, although the transfer request RX is made to wait, the transfer request Rn, which is more important than the transfer request RX, can be executed first.

[0188] In the second embodiment, the transfer control circuit 28 transfers the importance IM included in the transfer request R to the importance holding unit 26, but it is not limited thereto, and the source of the transfer request (peripheral circuits 21, 22) may register the importance IM of the transfer request R in the importance holding unit 26.

[0189] Embodiment 3. In the second embodiment, in the case of case CA14, the calculation unit 27 (FIG. 13) of the DMA unit 25 determines the truth or falsehood of condition (14) based on the importance IMX and IMn of the transfer requests RX and Rn. When condition (14) is true, the execution order (transfer order) of the transfer requests RX and Rn is swapped (steps S151, S152, S137A in FIG. 14).

[0190] However, depending on the product or system, it may be difficult to uniformly define the importance IM for all transfer requests R. Also, the situation may change after a transfer request R is issued, causing the importance IM of that transfer request R to change. If the transfer order is changed in such a case, an unintended situation may occur in the product or system. This third embodiment aims to solve this problem.

[0191] Figure 15 is a block diagram showing the configuration of a data transfer system according to the third embodiment, and is to be compared with Figure 1. Figure 15 differs from Figure 1 in that peripheral circuits 4 and 5 are replaced with peripheral circuits 31 and 32, respectively, and DMA unit 1 is replaced with DMA unit 33.

[0192] Each of the peripheral circuits 31 and 32 performs the same operation as each of the peripheral circuits 4 and 5, and in addition, when an inquiry is made from the DMA unit 33 as to whether or not the transfer order can be changed, the peripheral circuits 31 and 32 transmit a response to the inquiry to the DMA unit 33.

[0193] DMA unit 33 differs from DMA unit 1 in that required transfer time calculation unit 14 is replaced with required transfer time calculation unit 34. Note that required transfer time calculation unit 34 may also be simply referred to as "calculation unit 34" below. In addition to performing the same operations as calculation unit 14, calculation unit 34, in case of case CA14, inquires of the requester RSX of transfer request RX (for example, peripheral circuit 31) whether or not the order in which transfer requests RX and Rn are executed can be changed.

[0194] If the calculation unit 34 receives a response from the request source RSX indicating that the transfer requests RX and Rn can be switched, it switches the order of the transfer requests Rn and RX and notifies the transfer request source RSX of the transfer request RX of an error EX.

[0195] On the other hand, if the calculation unit 34 receives a response from the request source RSX indicating that it is not possible to switch the transfer requests RX and Rn, it does not switch the order of the transfer requests Rn and RX, and notifies the transfer request source RSn (for example, the peripheral circuit 32) of the transfer request Rn of an error En.

[0196] Fig. 16 is a flowchart showing the main part of the operation of the calculation unit 34, and is to be compared with Fig. 12. Fig. 16 differs from Fig. 12 in that steps S161 to S164 are added.

[0197] If the answer is NO in step S137, the calculation unit 34 inquires at step S161 of the requestor RSX of the transfer request RX (for example, the peripheral circuit 31) whether or not the transfer requests RX and Rn can be swapped. The transfer requestor RSX considers the inquiry from the calculation unit 34 and transmits a response to the calculation unit 34 indicating whether or not the transfer requests RX and Rn can be swapped.

[0198] The calculation unit 34 receives a response from the transfer request source RSX in step S162, and determines in step S163 whether or not the transfer requests RX and Rn can be swapped based on the received response.

[0199] If it is possible to switch the transfer requests RX and Rn (YES in step S163), the calculation unit 34 sends an error notification EX to the requestor RSX of the transfer request RX in step S164, and then switches the transfer order of the transfer request RX and the transfer request Rn in step S137A. As a result, the important transfer request Rn is executed before the transfer request RX.

[0200] In step S164, an error notification EX is sent to the requestor RSX of the transfer request RX because condition (13) is false (NO in step S137), and therefore if the transfer order of the transfer request RX and the transfer request Rn is swapped, the allowable transfer time TAX of the transfer request RX, which was originally Xth, will no longer be met.

[0201] If it is not possible to switch the transfer requests RX and Rn (NO in step S163), the calculation unit 34 sends an error notification En to the request source RSn of the transfer request Rn in step S141, and also responds with a transfer order so that the transfer request Rn is executed after the transfer request RX. The other configurations and operations are the same as those in the first embodiment, and therefore the description thereof will not be repeated.

[0202] As described above, in the third embodiment, in case of case CA14 (NO in step S137 of FIG. 16), the requester RSX of the transfer request RX is inquired as to whether or not the transfer requests RX and Rn can be swapped, and if the answer is that they can be swapped, the transfer request Rn is executed before the transfer request RX. Therefore, in addition to obtaining the same effects as the first embodiment, even if it is difficult to define the importance IM for all transfer requests R uniformly or if the importance IM of a transfer request R changes after the transfer request R is issued, it is possible to execute the important transfer request Rn first without causing a situation contrary to the intention of the system.

[0203] When inquiring of the RSX that made the transfer request RX as to whether or not the transfer requests RX and Rn can be swapped, the RSX that made the transfer request may be informed of information such as the extent to which the transfer allowable time TAX will be exceeded if the transfer requests RX and Rn are swapped, as information for determining whether or not the transfer requests RX and Rn can be swapped.

[0204] Furthermore, in the third embodiment, only the request source RSX of the transfer request RX is inquired as to whether or not the transfer request can be swapped, but this is not limited to this, and all transfer request sources RS0 to RSX other than the transfer request source RSn may be inquired as to whether or not the transfer request can be swapped, and the transfer request that becomes swappable may be swapped with the transfer request Rn.

[0205] Also, when the transfer requests RX and Rn can be swapped, a new transfer allowable time TAX1 shall also be included in the response, and the transfer allowable time TAX held in the holding unit 11 may be rewritten with the new transfer allowable time TAX1. In this case, after swapping the transfer order, there will be no error.

[0206] Moreover, it is possible to appropriately combine and use Embodiment 2 and Embodiment 3. For example, it is determined based on the importance levels IMX and IMn whether the transfer requests RX and Rn can be swapped. When IMX < IMn, the transfer order is swapped (Embodiment 2), and when IMX = IMn, a method of inquiring the request source RSX about whether the transfer requests RX and Rn can be swapped (Embodiment 3) can be considered.

[0207] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The technical scope shown by this disclosure is indicated by the claims rather than the above-described embodiments, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Explanation of Signs

[0208] 1, 25, 33 DMA unit, 2 System bus, 3 RAM, 4, 5, 21, 22, 31, 32 Peripheral circuits, 6 MPU, 11 Transfer allowable time holding unit, 12 Data buffer, 13 BUS / IF, 14, 27, 34 Transfer required time calculation unit, 15 Transfer control circuit, 16 Transfer time counter, 17 Destination address pointer, 18 Source address pointer, 26 Importance holding unit.

Claims

1. A data transfer device that transfers data in accordance with a plurality of transfer requests, comprising: Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request; The data transfer device a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests; a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit; The calculation unit calculating the required transfer time for each of the transfer requests based on the first information; setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request; When the order cannot be set so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request, the calculation unit: inquiring of a requester of another transfer request scheduled before the start of the transfer request whether or not it is possible to change the order of the transfer request and the other transfer request; If it is answered that the order can be changed, the order is set so that each of the transfer requests is executed before the other transfer requests; If the response is that the order cannot be changed, the data transfer device sets the order so that each of the transfer requests is executed after the other transfer requests.

2. A data transfer device that transfers data in accordance with a plurality of transfer requests, comprising: Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request; The data transfer device a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests; a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit; The calculation unit calculating the required transfer time for each of the transfer requests based on the first information; setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request; a timer unit for measuring the elapsed time from the time when each of the transfer requests is notified; Each time the transfer request is notified, the calculation unit: calculates the remaining time of the permissible transfer time for each of the transfer requests based on the time measurement result of the time measurement unit; recalculating the required transfer time for executing each of the transfer requests based on the remaining amount of data in each of the transfer requests; a data transfer device that resets the order in which the plurality of transfer requests are executed so that the recalculated required transfer time falls within the remaining time of the allowed transfer time.

3. A data transfer device that transfers data in accordance with a plurality of transfer requests, comprising: Each transfer request includes first information relating to a required transfer time required to execute the transfer request, and second information indicating an allowed transfer time, which is a maximum time allowed for completing a data transfer for the transfer request; The data transfer device a calculation unit that sets an order of execution of the plurality of transfer requests based on the first and second information of each of the transfer requests; a transfer control circuit that executes the plurality of transfer requests in an order set by the calculation unit; The calculation unit calculating the required transfer time for each of the transfer requests based on the first information; setting an order in which the plurality of transfer requests are to be executed so that the required transfer time of each of the transfer requests falls within the transfer allowable time of the transfer request; Each time the transfer request is notified, the calculation unit: calculate a first margin time, which is the difference between the permissible transfer time and the required transfer time of the transfer request; For another transfer request scheduled to be executed before the transfer request, a second margin time is calculated, which is the difference between the transfer allowable time and the transfer required time of the other transfer request; If the first margin time is greater than the second margin time, the transfer request is executed after the other transfer requests; When the first margin time is smaller than the second margin time, the data transfer device sets the order of execution of the transfer request to precede the other transfer requests.

4. 4. The data transfer device according to claim 1, wherein the first information includes a data volume to be transferred in response to the transfer request.

5. 5. The data transfer device according to claim 1, wherein the allowable transfer time for each of the transfer requests is set to a shorter time as the priority of the transfer request increases.

6. The data transfer device according to any one of claims 1 to 5; a transfer request source that transmits the plurality of transfer requests.

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