Power circuit
The power supply circuit addresses the limitation of conventional circuits by using transistor configurations and a Zener diode to manage large input voltages, ensuring circuit integrity by preventing inrush currents.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-09-26
- Publication Date
- 2026-03-03
AI Technical Summary
Conventional switch circuits in power supply circuits are unable to handle large input voltages due to limitations on the Vgs withstand voltage of transistors when the power supply and ground are connected in reverse.
A power supply circuit design incorporating specific transistor configurations and a Zener diode to manage large input voltages, including NMOS and PMOS transistors, capacitors, and a gate controller to control transistor states, preventing inrush currents.
The circuit effectively handles large input voltages by preventing inrush currents through transistor control, ensuring the circuit's integrity even when power supply and ground are reversely connected.
Smart Images
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Abstract
Description
[Technical Field]
[0001] FIELD An embodiment of the present invention relates to a power supply circuit. [Background technology]
[0002] In a power supply circuit, a switch circuit is inserted into the power supply line to prevent the internal circuit from being destroyed when the power supply and ground are connected in reverse.
[0003] However, conventional switch circuits had the problem of being unable to handle large input voltages due to limitations on the Vgs withstand voltage of the transistors. [Prior art documents] [Patent documents]
[0004] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 67501 Summary of the Invention [Problem to be solved by the invention]
[0005] Therefore, an object of the embodiment is to provide a power supply circuit that can also handle a large input voltage when the power supply and ground are connected in reverse. [Means for solving the problem]
[0006] The power supply circuit of the embodiment includes a first transistor having a source connected to an input terminal and a gate connected to a first node, a second transistor having a drain connected to the drain of the first transistor and a source connected to an output terminal, a third transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a second node, and a Zener diode having an anode connected to the input terminal and a cathode connected to the second node, a fourth transistor and a fifth transistor connected between the second node and a reference potential and having a gate and a source commonly connected; It has. [Brief explanation of the drawings]
[0007] [Figure 1] FIG. 1 is a circuit diagram showing an example of a power supply circuit according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a power supply circuit showing the internal configuration of a gate controller. [Figure 3] FIG. 10 is a circuit diagram showing an example of a power supply circuit according to a second embodiment. [Figure 4] FIG. 10 is a circuit diagram showing an example of a power supply circuit according to a first modified example of the second embodiment. [Figure 5] FIG. 10 is a circuit diagram showing an example of a power supply circuit according to a second modification of the second embodiment. [Figure 6] FIG. 10 is a circuit diagram showing an example of a power supply circuit according to a third modification of the second embodiment. [Figure 7] FIG. 10 is a circuit diagram showing an example of a power supply circuit according to a fourth modified example of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0008] Hereinafter, an embodiment will be described with reference to the drawings. (First embodiment) FIG. 1 is a circuit diagram showing an example of a power supply circuit according to the first embodiment. The power supply circuit 1 of this embodiment includes an input terminal 11 to which an input voltage VIN is supplied as an external power supply, an output terminal 12 that outputs an output voltage VOUT to an external load circuit, a gate controller 13, transistors M1, M2, M3, M4, M5, M6, M7, and M8, a Zener diode ZD, and a capacitor C1. The transistors M1 to M8 are NMOS transistors.
[0009] The source of the transistor M1 is connected to the input terminal 11, and the drain of the transistor M2 is connected to the drain of the transistor M2. The gate of the transistor M1 is connected between the gate controller 13 and the drain of the transistor M3.
[0010] The transistor M2 has a source connected to the output terminal 12 and a drain connected to the drain of the transistor M1. The transistor M2 also has a gate connected to a gate controller 13.
[0011] The transistor M3 has a source connected to the input terminal 11, a drain connected to the node N1, and a gate connected to the node N2.
[0012] The drain of the transistor M4 is connected to the node N2. The drain of the transistor M5 is connected to the reference potential GND. The gates and sources of the transistors M4 and M5 are commonly connected. That is, the transistors M4 and M5 are back-to-back connected.
[0013] The source of the transistor M6 is connected between the transistor M2 and the output terminal 12. The gate and drain of the transistor M6 are connected in common and to the reference potential GND.
[0014] The source of transistor M7 is connected to input terminal 11. The source of transistor M8 is connected to external reference potential GND via the GND terminal. The gates and sources of transistors M7 and M8 are commonly connected to substrate reference potential SUB. In other words, transistors M7 and M8 are back-to-back connected. This prevents a through current from flowing from input terminal 11 to reference potential GND when the input voltage VIN and reference potential GND are reverse-connected.
[0015] The Zener diode ZD has an anode connected to the input terminal 11 and a cathode connected to the node N1.
[0016] Capacitor C1 is connected in parallel to transistors M4 and M5, with one end connected to node N1 and the other end connected to reference potential GND. Capacitor C1 is a high-speed response capacitor that quickly turns on transistor M3 when the input voltage VIN becomes lower than the reference potential GND.
[0017] The gate controller 13 inputs gate control signals to the transistors M1 and M2 to control the on / off of the transistors M1 and M2.
[0018] FIG. 2 is a circuit diagram of a power supply circuit showing the internal configuration of the gate controller. As shown in FIG. 2, the gate controller 13 includes a charge pump circuit CP and transistors M9, M10, M11, and M12.
[0019] The charge pump circuit CP boosts the input voltage VIN supplied from the input terminal 11 and supplies the boosted voltage to the sources of the transistors M9 and M10.
[0020] Transistors M9 and M10 are PMOS transistors, and transistors M11 and M12 are NMOS transistors.
[0021] The source of the transistor M9 is connected to the charge pump circuit CP, and the drain is connected to the drain of the transistor M11.
[0022] The source of the transistor M10 is connected to the charge pump circuit CP, and the drain of the transistor M10 is connected to the drain of the transistor M12.
[0023] The transistor M11 has a drain connected to the drain of the transistor M9 and a source connected to the output terminal 12.
[0024] The transistor M12 has a drain connected to the drain of the transistor M10 and a source connected to the input terminal 11.
[0025] Control signals are supplied to the gates of the transistors M9 to M12. These control signals are supplied from outside the power supply circuit 1. For example, when a control signal is supplied to turn on the transistors M9 and M10 and turn off the transistors M11 and M12, a voltage boosted by the charge pump circuit CP is supplied to the gates of the transistors M1 and M2.
[0026] When the transistors M1 and M2 are turned on, the power supply circuit 1 outputs an input voltage VIN input to an input terminal 11 from an output terminal 12 as an output voltage VOUT.
[0027] On the other hand, if the input voltage VIN is suddenly pulled down and a large negative voltage is supplied, a reverse current flows through the Zener diode ZD. This causes an inrush current to flow through transistors M4 and M5, charging node N2. Once node N2 is fully charged, transistors M4 and M5 automatically cut off the inrush current. As a result, if, for example, a large negative voltage of -60V is supplied to the input voltage VIN, node N2 will be charged to -55V.
[0028] When a voltage of −60 V is supplied to the input voltage VIN and the voltage at the node N2 is charged to −55 V, a voltage of 5 V is applied to the gate-source voltage Vgs of the transistor M3, turning on the transistor M3.
[0029] When the transistor M3 is turned on, the potential of the node N1 connected to the gate of the transistor M1 is rapidly discharged to the input terminal 11. As a result, the transistor M1 is turned off, and an inrush current between the input terminal 11 and the output terminal 12 can be prevented.
[0030] In this way, the power supply circuit 1 of this embodiment can also handle a large input voltage when the power supply and ground are connected in reverse.
[0031] (Second embodiment) Fig. 3 is a circuit diagram showing an example of a power supply circuit according to the second embodiment. In Fig. 3, the same components as those in Fig. 1 are given the same reference numerals and the description thereof will be omitted.
[0032] The power supply circuit 1A includes a resistor R1 instead of the transistors M4 and M5 of the power supply circuit 1 in Figure 1. The resistor R1 is a resistor for pulling up the potential of the node N2 when the input voltage VIN is less than the reference potential GND. The other configurations are the same as those of the power supply circuit 1 of the first embodiment.
[0033] When a large negative voltage is supplied to the input voltage V, a reverse current flows through the Zener diode ZD, causing the potential at node N2 to become higher than the input voltage V. For example, when a voltage of -60 V is supplied to the input voltage V, the potential at node N2 becomes -55 V, which is higher than the input voltage V.
[0034] When a voltage of −60 V is supplied to the input voltage VIN and the voltage at the node N2 becomes −55 V, a voltage of 5 V is applied to the gate-source voltage Vgs of the transistor M3, turning on the transistor M3.
[0035] When the transistor M3 is turned on, the potential of the node N1 connected to the gate of the transistor M1 is rapidly discharged to the input terminal 11. As a result, the transistor M1 is turned off, and an inrush current between the input terminal 11 and the output terminal 12 can be prevented.
[0036] Therefore, similar to the first embodiment, the power supply circuit 1A can also handle a large input voltage when the power supply and ground are connected in reverse.
[0037] (Variation 1) Fig. 4 is a circuit diagram showing an example of a power supply circuit according to Modification 1 of the second embodiment. In Fig. 4, the same components as those in Fig. 3 are given the same reference numerals and descriptions thereof will be omitted.
[0038] The power supply circuit 1B includes a plurality of diodes D1, D2, ..., Dn (hereinafter, one or more diodes will be referred to as diodes D) instead of the Zener diode ZD of the power supply circuit 1A. The other configuration is the same as that of the power supply circuit 1A of the second embodiment.
[0039] The plurality of diodes D are connected in the forward direction between the power supply terminal 11 and the node N2. When a voltage of −60 V is supplied to the input voltage VIN, the plurality of diodes D step down the voltage by, for example, 5 V to make the node N2 −55 V.
[0040] With the above configuration, when a large negative voltage is supplied to the input voltage VIN, the transistor M3 is turned off. As a result, the potential of the node N1 is rapidly discharged to the input terminal 11, turning off the transistor M1 and preventing an inrush current between the input terminal 11 and the output terminal 12.
[0041] Therefore, similar to the second embodiment, the power supply circuit 1B can also handle a large input voltage when the power supply and ground are connected in reverse.
[0042] (Variation 2) Fig. 5 is a circuit diagram showing an example of a power supply circuit according to Modification 2 of the second embodiment. In Fig. 5, the same components as those in Fig. 3 are given the same reference numerals and description thereof will be omitted.
[0043] In the power supply circuit 1A of FIG. 3, the other end of the capacitor C1 and the other end of the resistor R1 are connected to the reference potential GND.
[0044] In contrast, in the power supply circuit 1C of the second modification, the other end of the capacitor C1 and the other end of the resistor R1 are connected to the output terminal 12. The other configuration is the same as that of the power supply circuit 1A of the second embodiment.
[0045] When a large negative voltage is supplied to the input voltage VIN, the transistor M1 turns off, and the output terminal 12 is equivalent to the reference potential GND, so the power supply circuit 1C can perform the same function as the power supply circuit 1A.
[0046] Therefore, similar to the second embodiment, the power supply circuit 1C can also handle a large input voltage when the power supply and ground are connected in reverse.
[0047] (Variation 3) Fig. 6 is a circuit diagram showing an example of a power supply circuit according to Modification 3 of the second embodiment. In Fig. 6, the same components as those in Fig. 3 are given the same reference numerals and description thereof will be omitted.
[0048] In the power supply circuit 1A of FIG. 3, the other end of the capacitor C1 and the other end of the resistor R1 are connected to the reference potential GND.
[0049] In contrast, in the power supply circuit 1D of the third modification, the other end of the capacitor C1 and the other end of the resistor R1 are connected to a node N3 between the transistors M1 and M2. The other configuration is the same as that of the power supply circuit 1A of the second embodiment.
[0050] When a large negative voltage is supplied to the input voltage VIN, the transistor M1 turns off, and the node N3 becomes equivalent to the reference potential GND, so the power supply circuit 1D can function similarly to the power supply circuit 1A.
[0051] Therefore, similar to the second embodiment, the power supply circuit 1D can also handle a large input voltage when the power supply and ground are connected in reverse.
[0052] (Variation 4) Fig. 7 is a circuit diagram showing an example of a power supply circuit according to Modification 4 of the second embodiment. In Fig. 7, the same components as those in Fig. 3 are given the same reference numerals and descriptions thereof will be omitted.
[0053] The power supply circuit 1E includes transistors M13, M14, and M15 instead of the transistors M6, M7, and M8 of the power supply circuit 1A.
[0054] The transistors M13, M14, and M15 are PMOS transistors. That is, the power supply circuit 1E includes PMOS transistors M13, M14, and M15 instead of the NMOS transistors M6, M7, and M8 of the power supply circuit 1A. The other configurations are the same as those of the power supply circuit 1A of the second embodiment.
[0055] The transistor M13 has a drain connected to the reference potential GND, and a gate and a source connected in common to the output terminal 12.
[0056] The gate and source of the transistor M14 are commonly connected to the input terminal 11. The gate and source of the transistor M15 are commonly connected to the reference potential GND. The drains of the transistors M14 and M15 are commonly connected to the reference potential SUB.
[0057] The transistors M14 and M15 are connected back to back. As a result, the power supply circuit 1E prevents a through current from flowing from the input terminal 11 to the reference potential GND when the input voltage VIN and the reference potential GND are connected in reverse.
[0058] The configurations of the first to fourth modifications of the second embodiment can also be applied to the configuration of the power supply circuit 1 of the first embodiment.
[0059] Although several embodiments of the present invention have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as set forth in the claims. [Explanation of symbols]
[0060] 1, 1A to 1E... power supply circuit, 11... input terminal, 12... output terminal, 13... gate controller, M1 to M15... transistor, ZD... Zener diode, CP... charge pump circuit, D1 to Dn... diode, C1... capacitor, R1... resistor.
Claims
1. a first transistor having a source connected to the input terminal and a gate connected to a first node; a second transistor having a drain connected to the drain of the first transistor and a source connected to an output terminal; a third transistor having a source connected to the input terminal, a drain connected to the first node, and a gate connected to a second node; a Zener diode having an anode connected to the input terminal and a cathode connected to the second node; a fourth transistor and a fifth transistor, each of which is an NMOS transistor, connected between the second node and a reference potential, and having a gate and a source commonly connected; A power supply circuit having:
2. a capacitor connected in parallel to the fourth transistor and the fifth transistor; 2. The power supply circuit according to claim 1.
3. a sixth transistor connected between the reference potential and the output terminal; 2. The power supply circuit according to claim 1.
4. a sixth transistor and a seventh transistor connected between the input terminal and the reference potential, the sixth transistor and the seventh transistor having a gate and a source commonly connected to a substrate reference potential; 2. The power supply circuit according to claim 1.
5. a gate controller for outputting gate control signals to the gates of the first transistor and the second transistor; 2. The power supply circuit according to claim 1.
6. The gate controller outputs the gate control signal to the gate of the first transistor via the first node.
6. The power supply circuit according to claim 5.
Citation Information
Patent Citations
Low-noise preamplifier circuit for biological signal amplification
CN106452372A
Polarity error protection circuit
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US2020/67501