Application Programming Interface for Monitoring Resource Usage

Abstract

Apparatus, systems, and techniques for generating one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, the one or more data structures to be used to monitor use of information by a computer program are generated based on, for example, CUDA or other parallel computing platform code.

Description

[Technical Field]

[0001] This application is related to U.S. Provisional Application No. 63 / 174,999, filed April 14, 2021 (Attorney Docket No. 0112912-270PR0), entitled "REFERENCE COUNTED DESTRUCTORS," U.S. Patent Application No. 17 / 720,231, filed April 13, 2022 (Attorney Docket No. 0112912-270US0), entitled "APPLICATION PROGRAMMING INTERFACE TO MONITOR RESOURCE USAGE," U.S. Patent Application No. 17 / 720,234, filed April 13, 2022 (Attorney Docket No. 0112912-505US0), entitled "APPLICATION PROGRAMMING INTERFACE TO INDICATE INCREASED RESOURCE USAGE," and U.S. Patent Application No. 17 / 720,234, filed April 13, 2022 (Attorney Docket No. 0112912-505US0), entitled "APPLICATION PROGRAMMING INTERFACE TO INDICATE INCREASED RESOURCE USAGE," the entire contents of each of which are incorporated herein by reference. This application claims the benefit of U.S. patent application Ser. No. 17 / 720,236 (Attorney Docket No. 0112912-506US0), entitled "PROGRAMMING INTERFACE TO INDICATE REDUCED RESOURCE USAGE."

[0002] At least one embodiment relates to a processing resource used to monitor computer program resource usage, for example, a processor or computing system used to monitor computer program resource usage that implements various novel techniques described herein. [Background technology]

[0003] Monitoring resource usage in a computer program can be difficult because resources can be used in a variety of different operations. Therefore, techniques for monitoring resource usage in a computer program can be improved using CUDA or other parallel computing platform code. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 illustrates an example of a program that uses graphs, according to at least one embodiment. [Figure 2] FIG. 1 illustrates an example of the techniques described herein, according to at least one embodiment. [Figure 3] FIG. 10 is a diagram of a User Object Create API call, according to at least one embodiment. [Figure 4] FIG. 10 is a diagram of a User Object Retain API call, according to at least one embodiment. [Figure 5] FIG. 10 is a diagram of a User Object Release API call, according to at least one embodiment. [Figure 6] FIG. 1 illustrates an example process for generating a data structure to be used to monitor the use of information by a computer program, according to at least one embodiment. [Figure 7] FIG. 1 illustrates an example process that causes increased information usage by a computer program, according to at least one embodiment. [Figure 8] FIG. 1 illustrates an example process that causes information usage by a computer program to be reduced, according to at least one embodiment. [Figure 9] FIG. 1 illustrates an exemplary data center, according to at least one embodiment. [Figure 10]FIG. 1 illustrates a processing system according to at least one embodiment. [Figure 11] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 12] FIG. 1 illustrates a system according to at least one embodiment. [Figure 13] FIG. 1 illustrates an exemplary integrated circuit according to at least one embodiment. [Figure 14] FIG. 1 illustrates a computing system according to at least one embodiment. [Figure 15] FIG. 1 illustrates an APU, according to at least one embodiment. [Figure 16] FIG. 1 illustrates a CPU according to at least one embodiment. [Figure 17] FIG. 2 illustrates an exemplary accelerator integration slice, according to at least one embodiment. [Figure 18A] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 18B] FIG. 1 illustrates an exemplary graphics processor according to at least one embodiment. [Figure 19A] FIG. 1 illustrates a graphics core according to at least one embodiment. [Figure 19B] FIG. 1 illustrates a GPGPU, according to at least one embodiment. [Figure 20A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 20B] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 20C] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 21] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 22] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 23] FIG. 1 illustrates a processor according to at least one embodiment. [Figure 24] FIG. 1 illustrates a graphics processor core according to at least one embodiment. [Figure 25] FIG. 1 illustrates a PPU, according to at least one embodiment. [Figure 26] FIG. 1 illustrates a GPC, according to at least one embodiment. [Figure 27] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 28] FIG. 1 illustrates a software stack for a programming platform according to at least one embodiment. [Figure 29] FIG. 29 illustrates a CUDA implementation of the software stack of FIG. 28, according to at least one embodiment. [Figure 30] FIG. 29 illustrates an ROCm implementation of the software stack of FIG. 28 according to at least one embodiment. [Figure 31] FIG. 29 illustrates an OpenCL implementation of the software stack of FIG. 28 according to at least one embodiment. [Figure 32] FIG. 1 illustrates software supported by a programming platform according to at least one embodiment. [Figure 33] FIG. 32 illustrates compiling code for execution on the programming platform of FIGS. 28-31 according to at least one embodiment. [Figure 34] FIG. 32 illustrates in more detail compiling code for execution on the programming platform of FIGS. 28-31 according to at least one embodiment. [Figure 35] FIG. 1 illustrates translating source code prior to compiling the source code, according to at least one embodiment. [Figure 36A]FIG. 1 illustrates a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment. [Figure 36B] FIG. 36B illustrates a system configured to compile and execute the CUDA source code of FIG. 36A using a CPU and a CUDA-enabled GPU, according to at least one embodiment. [Figure 36C] FIG. 36B illustrates a system configured to compile and execute the CUDA source code of FIG. 36A using a CPU and a non-CUDA-enabled GPU, according to at least one embodiment. [Figure 37] FIG. 36D illustrates an example kernel translated by the CUDA-to-HIP translation tool of FIG. 36C, in accordance with at least one embodiment. [Figure 38] FIG. 36D illustrates the non-CUDA GPU of FIG. 36C in more detail, according to at least one embodiment. [Figure 39] FIG. 39 illustrates how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 38, according to at least one embodiment. [Figure 40] FIG. 1 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] In at least one embodiment, one or more programming models utilize a graph to perform various operations. In at least one embodiment, the one or more programming models include models such as the Compute Unified Device Architecture (CUDA) model, the Heterogeneous Compute Interface for Portability (HIP) model, the oneAPI model, various hardware accelerator programming models, and / or variations thereof. In at least one embodiment, a graph is a set of operations performed on one or more processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), and / or variations thereof. In at least one embodiment, the graph is a data object, also referred to as a graph data structure, graph code, and / or variations thereof, that defines a set of operations, such as kernel launches, connected by dependencies. In at least one embodiment, the dependencies of the graph are defined separately from the execution of the graph, and in at least one embodiment, the graph is defined once and can be invoked one or more times.

[0006] In at least one embodiment, operations correspond to nodes in the graph. In at least one embodiment, dependencies between operations form edges of the graph. In at least one embodiment, dependencies constrain the execution sequence of operations. In at least one embodiment, an operation can be scheduled at any time once the node on which it depends has completed (e.g., the operation indicated by the node has been executed / performed). In at least one embodiment, operations indicated by nodes can include operations such as kernel, CPU function calls, memory management / manipulation operations, waiting for an event, recording an event, signaling an external semaphore, waiting for an external semaphore, as well as other graphs (e.g., child graphs). In at least one embodiment, graphs are created through various programming model application programming interface (API) functions. In at least one embodiment, operations on the graph are executed through various programming model API functions.

[0007] In at least one embodiment, a graph is created through one or more operations, sometimes referred to as stream capture. In at least one embodiment, one or more operations are defined, and stream capture is utilized to capture the one or more operations in the graph. In at least one embodiment, for example, an API call indicates the start of a series of operations, also referred to as a stream, and a different API call indicates the end of the series of operations, which are then instantiated as the graph. In at least one embodiment, an API function that indicates the start of the series of operations may be referred to as a Stream Begin Capture API function. In at least one embodiment, an API function that indicates the end of the series of operations may be referred to as a Stream End Capture API function. It should be noted that in at least one embodiment, API functions such as those described herein may be referred to in any suitable manner using any suitable terminology that may or may not relate to one or more functionality of the API function.

[0008] In at least one embodiment, various objects are utilized in various operations exhibited by the graph and / or other suitable computer program. In at least one embodiment, the graph and / or other suitable computer program may define operations that utilize various user-specified data and / or user-managed resources, also referred to as objects. In at least one embodiment, objects include kernel arguments, host function arguments, workspace buffers, and / or variations thereof. In at least one embodiment, the objects include any suitable computing resources, information, and / or data utilized throughout execution of one or more operations of the graph and / or other suitable computer program. In at least one embodiment, the objects are created through a constructor, which refers to the type of function called to create the object. In at least one embodiment, the objects are destroyed through a destructor function, also referred to as a destructor, which is the type of function called to destroy the object. In at least one embodiment, the destructor function destroys the object by at least deallocating memory corresponding to the object and / or any suitable process that deletes or otherwise destroys the object. In at least one embodiment, constructors and / or destructors may be defined by a user, various software libraries, and / or variations thereof.

[0009] In at least one embodiment, graphs are utilized in various operations of a program. FIG. 1 illustrates an example program 100 that uses graphs, according to at least one embodiment. In at least one embodiment, example 100 includes various graph data structure operations associated with the graphs that the program includes. In at least one embodiment, the operations include creating a graph, cloning a graph, instantiating a graph into an executable file (e.g., Aexec in FIG. 1), launching a graph, executing a graph (e.g., Async execute in FIG. 1), destroying a graph, destroying an executable graph, and / or various other operations not illustrated in FIG. 1. In at least one embodiment, as illustrative examples, as part of the program, the graph is created, the graph is instantiated as an executable graph, the graph is deleted, the executable graph is launched, the executable graph is executed, and the executable graph is deleted. In at least one embodiment, the objects utilized by one or more operations of the graph must persist until each use of the graph in the program is complete. In at least one embodiment, the techniques described herein provide a way to determine when the objects utilized by one or more operations of the graph can be released or otherwise destroyed (e.g., via a destructor).

[0010] In at least one embodiment, one or more systems, such as systems of one or more programming models, such as CUDA, HIP, oneAPI, and / or variations thereof, perform various operations and / or techniques described herein. In at least one embodiment, the system determines when a new graph handle is created for use with a graph. In at least one embodiment, as exemplary examples, the graph handle is created when the graph is created, when the graph is instantiated as an executable graph, when the executable graph is launched, and / or various other graph operations. In at least one embodiment, as exemplary examples, the graph handle is deleted when the graph is destroyed, when the executable graph is executed, when the executable graph is destroyed, and / or various other graph operations. In at least one embodiment, the system utilizes a counter, also referred to as a reference counter, to track the creation and destruction of graph handles, the counter being incremented by one when the graph handle is created (e.g., via an API call that results in the creation of the graph handle) and decremented by one when the graph handle is destroyed (e.g., via an API call that results in the destruction of the graph handle) or otherwise destroyed. In at least one embodiment, when the reference counter reaches a value of zero, the system determines that the objects used by the graph can be released (e.g., memory allocated for the objects can be released) or otherwise destroyed (e.g., via destructors).

[0011] In at least one embodiment, the system provides the ability to track a computer program's use of the object or other suitable computing resource through the counter. In at least one embodiment, the computer program's use of the object is tracked through references associated with the computer program to the object. In at least one embodiment, the system provides the ability to utilize the counter, also referred to as a reference counter, to track references to the object, the counter being incremented by one for new references to the object and decremented by one when a reference to the object is no longer used. In at least one embodiment, when the reference counter reaches a value of zero, the system determines that the object used by the computer program can be released (e.g., memory allocated for the object can be released) or otherwise destroyed (e.g., via a destructor).

[0012] In at least one embodiment, the techniques described herein are used with various software libraries, such as the NVIDIA Collective Communications Library (NCCL), various collective communication libraries, and / or any suitable software library, to provide dynamically sized data to host nodes in the graph without leaking memory. FIG. 2 illustrates an example 200 of the techniques described herein used in connection with stream capture for NCCL, in accordance with at least one embodiment. In at least one embodiment, the techniques described herein are utilized with a graph created using one or more stream capture processes, or any suitable process. In at least one embodiment, referring to "202" in FIG. 2, setup code is performed in API calls (e.g., enqueue ops, launch helper threads). In at least one embodiment, referring to "204 (When a capture is detected)" in FIG. 2, techniques described herein enable setup code that would normally occur in an API call to be moved to a host node when a capture is detected to support restarting a graph using an NCCL operation (e.g., an NCCL API call) so that it will execute for every graph invocation. In at least one embodiment, techniques described herein are utilized to associate a workplace lifetime with the graph. In at least one embodiment, techniques described herein enable lifetime management of dynamic objects usable in the graph or other suitable computer program. In at least one embodiment, techniques described herein support trivially copyable objects.In at least one embodiment, the techniques described herein support operations for graphs and / or other suitable computer programs that reference dynamic user objects, the operations including an instantiation operation, a clone operation, a child graph insertion operation, an asynchronous destroy operation, an executable graph update from a new source graph operation, and / or various other graph operations.

[0013] In at least one embodiment, the techniques described herein support graphs and / or other suitable computer programs that reference non-trivially copyable objects, such as objects that require user-provided destruction code and / or copy code. In at least one embodiment, the techniques described herein allow users to synchronize destruction of user objects when user-provided destruction code is supported. In at least one embodiment, the techniques described herein allow object destruction to involve various architecture-specific API calls (e.g., CUDA API calls). In at least one embodiment, the techniques described herein allow node updates using one or more software libraries and / or original task description code.

[0014] In at least one embodiment, the techniques described herein utilize constructors and destructors for object creation and destruction. In at least one embodiment, the techniques described herein utilize callbacks. In at least one embodiment, a callback refers to a function passed as an argument to other code that can execute a callback function (e.g., callback). In at least one embodiment, a callback includes code such as constructor and / or destructor code. In at least one embodiment, the techniques described herein utilize user-supplied destructor code. In at least one embodiment, the techniques described herein utilize C++ wrappers that accept various C++ objects (e.g., destructor code and / or constructor code) and convert them for use with one or more techniques described herein. In at least one embodiment, the techniques described herein allow user object references to be utilized or otherwise owned by graphs, individual nodes, other objects, and / or variations thereof.

[0015] In at least one embodiment, destructor execution (e.g., to release or otherwise destroy the object) is performed in any suitable manner. In at least one embodiment, a synchronization reference refers to a reference managed by action from a CPU. In at least one embodiment, an object must survive any graph execution that utilizes the object. In at least one embodiment, a graph execution has access to any user object that the graph held as a synchronization reference in the launch call. In at least one embodiment, techniques described herein track graph operations such that all graph executions have access to any appropriate user objects. In at least one embodiment, techniques described herein utilize an ordering denoted as No CUDA ordering, where one or more systems of a programming model schedule execution of the destructor once all synchronization references to the object (e.g., an object utilized by one or more graphs) have been released and all graph executions with access to the object have completed. In at least one embodiment, the system may block behind other destructors or previously enqueued tasks. In at least one embodiment, the techniques described herein utilize a total ordering scheme, where given a user object denoted by O and a statement denoted by S, all synchronous releases of O precede S in base causality order, all graph executions with access to O precede S in base causality order, and one or more systems of the programming model guarantee that the destruction of O precedes S in base causality order. In at least one embodiment, the techniques described herein utilize a CPU ordering only scheme, which is similar to total ordering, where the total ordering definition applies only to statement S executed by a CPU thread.

[0016] In at least one embodiment, references owned or otherwise utilized by the graph are preserved through any copying (e.g., cloning, instantiation). In at least one embodiment, in the event that an executable graph is destroyed asynchronously (e.g., it is launched but not synchronized), one or more systems ensure that user objects survive the execution of the graph. In at least one embodiment, after the launch is synchronized, remaining references are released and the destructor will execute asynchronously. In at least one embodiment, references owned by a graph in a child graph node are associated with the child graph. In at least one embodiment, when a child graph is updated or deleted, the references change accordingly. In at least one embodiment, when an executable graph or a child graph is updated (e.g., through one or more API functions such as cudaGraphExecUpdate or cudaGraphExecChildGraphNodeSetParams, or any suitable API function), the references in the new source graph are cloned to replace the references in the target graph. In at least one embodiment, if a previous invocation (e.g., a graph invocation for execution) is not synchronized, the reference to be released is held until the invocation finishes executing. In at least one embodiment, when the last reference to a user object is released, one or more systems will call a destruction function (e.g., a destructor) for the user object.

[0017] In at least one embodiment, the reference to the object refers to a pointer to the object or other use of the object in one or more operations of one or more computer programs and / or graphs. In at least one embodiment, one or more systems attach references to individual nodes of the graph. In at least one embodiment, one or more systems query references owned by particular objects. In at least one embodiment, the one or more systems schedule object cleanup to occur after last execution (e.g., via one or more destructors) when the graph is destroyed.

[0018] In at least one embodiment, the techniques described herein allow a user to register callbacks (e.g., destructors) that use an internal reference counting mechanism (e.g., a counter) to be called after various conditions are met (e.g., the counter reaches zero). In at least one embodiment, a callback may be registered with the graph and will not be called until the graph handle and any clones are destroyed and any asynchronous execution is completed. In at least one embodiment, the callback is used for object destruction (e.g., via a destructor). In at least one embodiment, the techniques described herein provide a mechanism for tracking operations on graph handles necessary for object lifetime management. In at least one embodiment, the techniques described herein defer execution of the callback until the reference count (e.g., indicated via a counter) reaches zero.

[0019] In at least one embodiment, the techniques described herein allow a user to cause a handle (e.g., a CUDA handle) to wait for execution of a destructor callback. In at least one embodiment, the techniques described herein allow references to be attached and / or manipulated in various places, such as a graph, a node of a graph, a dependency, and / or variations thereof. In at least one embodiment, the techniques described herein are applicable to streams, and references may be attached to various asynchronous workloads (e.g., stream workloads). In at least one embodiment, the techniques described herein allow destructor callbacks to recursively call one or more drivers (e.g., CUDA drivers).

[0020] 3-5 illustrate graphical representations of API functions according to at least one embodiment. In at least one embodiment, the API functions illustrated in FIGS. 3-5 are utilized as part of one or more techniques, such as those described herein (e.g., the techniques described with respect to FIGS. 1-2 and 6-8). In at least one embodiment, the API functions illustrated in FIGS. 3-5 are performed by any suitable processor and / or combination of processors, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof, and in any suitable order and / or manner, such as in parallel. In at least one embodiment, each of FIGS. 3-5 illustrates a particular set of information that may be included in an API call and response, although variations are within the scope of this disclosure and an API call may have fewer or more information components, which may be illustrated in any suitable manner. In at least one embodiment, not all API calls made using the same API function include the same information components. In at least one embodiment, the type and / or presence of critical information for one parameter can depend, as an illustrative example, on the value of another parameter. In at least one embodiment, the type and / or presence of critical information for a component of a response depends on the value of another parameter and / or a parameter of the API call that triggered the response.

[0021] In at least one embodiment, an API, such as those described herein, is a driver API or a runtime API. In at least one embodiment, a driver API is a low-level API that may be referred to in terms of a programming model (e.g., a CUDA driver API). In at least one embodiment, a driver API interacts directly with one or more devices. In at least one embodiment, a runtime API is a high-level API that may be referred to in terms of a programming model (e.g., a CUDA runtime API). In at least one embodiment, a runtime API operates utilizing a driver API. More information regarding driver APIs and runtime APIs may be found in the description of FIG. 29.

[0022] In at least one embodiment, the API call is made as part of the execution of code that represents at least an API function corresponding to the API call. In at least one embodiment, as an illustrative example, one or more systems make the API call and obtain a response as part of the execution of code related to one or more programming models, such as CUDA, HIP, oneAPI, and / or variations thereof.

[0023] FIG. 3 illustrates a diagram 300 of user object creation API calls, according to at least one embodiment. More information regarding the user object creation API calls may be found in the description of FIG. 6. In at least one embodiment, the user object creation API is illustrated as cudaUserObjectCreate, UserObjectCreate, and / or any suitable notation that may relate to a programming model (e.g., CUDA, HIP, oneAPI, and / or variants thereof). In at least one embodiment, the user object creation API causes one or more systems of one or more programming models (e.g., CUDA, HIP, oneAPI, and / or variants thereof) to create a user object that points to a data structure indicating a destructor and a reference count. In at least one embodiment, the user object indicates a specified destructor callback and an initial reference count. In at least one embodiment, the user object corresponds to a computing resource, such as the object, a region of memory, a data object, a data structure, and / or any suitable computing resource, utilized in the operation of a computer program. In at least one embodiment, the user object is utilized to track references to the computing resource, and when the reference count reaches zero, the destructor is called to destroy or otherwise clean the computing resource.

[0024] In at least one embodiment, parameters for the user object creation API call include “object_out,” “ptr,” “destroy,” “initialRefcount,” “flags,” and may include other parameters that further define aspects of the user object. In at least one embodiment, the parameter “object_out” indicates a location for returning a handle to the user object. In at least one embodiment, the parameter “ptr” indicates a pointer to pass to a destruction function (e.g., a destructor). In at least one embodiment, the parameter “destroy” indicates a callback for releasing one or more computing resources when the one or more computing resources are no longer in use. In at least one embodiment, the parameter “initialRefcount” indicates an initial reference count value for creating the object, the initial reference being owned by the calling thread. In at least one embodiment, the parameter “flags” indicates one or more flags that refer to values ​​that are signals for a function or process (e.g., an API function) that determine one or more characteristics of the function or process. In at least one embodiment, the flags for the user object creation API include a flag shown as "UserObjectNoDestructorSync" indicating that the destruction callback may not be waited for by the API.

[0025] In at least one embodiment, one or more systems implement the user object creation API by creating the user object that encodes or otherwise indicates at least one or more functions (e.g., a destructor) and a value indicating a count of references, also referred to as a reference count. In at least one embodiment, a response to the user object creation API call includes a status. In at least one embodiment, following the user object creation API call indicating the creation of the user object, the user object is created and a handle to the user object is returned in a location specified by a parameter "object_out." In at least one embodiment, the status is returned in response to the user object creation API call to indicate a status indication of the user object creation API call. In at least one embodiment, the status indication indicates whether one or more operations of the user object creation API succeeded, failed, or whether another error occurred.

[0026] FIG. 4 illustrates a diagram 400 of user object retention API calls, according to at least one embodiment. More information regarding the user object retention API calls may be found in the description of FIG. 7. In at least one embodiment, the user object retention API is illustrated as cudaUserObjectRetain, UserObjectRetain, and / or any suitable notation, which may relate to a programming model (e.g., CUDA, HIP, oneAPI, and / or variants thereof). In at least one embodiment, the user object retention API causes one or more systems of one or more programming models (e.g., CUDA, HIP, oneAPI, and / or variants thereof) to retain a reference to the user object by at least incrementing the reference count of the user object by a specified value. In at least one embodiment, one or more systems utilize the user object retention API to track the number of references to and / or usage of a computing resource, or any suitable information, by one or more computing programs.

[0027] In at least one embodiment, parameters for the user object retention API call include “object,” “count,” and may include other parameters further defining aspects of the user object. In at least one embodiment, the parameter “object” indicates the user object. In at least one embodiment, the parameter “count” indicates a number of references to be retained. In at least one embodiment, one or more systems implement the user object retention API by at least increasing or otherwise incrementing a count of references associated with the user object (e.g., by the indicated number of references to be retained). In at least one embodiment, a response to the user object retention API call includes a status. In at least one embodiment, following the user object retention API call, the reference count of the user object indicated by the parameter “object” is incremented by a value specified by the parameter “count.” In at least one embodiment, the status is returned in response to the user object retention API call to indicate a status indication of the user object retention API call. In at least one embodiment, the status indication indicates whether one or more operations of the user object persistence API succeeded, failed, or whether another error occurred.

[0028] In at least one embodiment, a graph-maintaining user object API implements one or more processes of the user object-maintaining API. In at least one embodiment, the user object-maintaining API may be utilized to implement one or more processes of the graph-maintaining user object API. In at least one embodiment, the graph-maintaining user object API is utilized to maintain references to the user objects from the graph and / or associate the user objects with one or more graphs, and the parameters for the graph-maintaining user object API call include a "graph" indicating the graph to associate the references with, an "object" indicating the user object to maintain the references with, a "count" indicating the number of references to add to the graph, and a "flag" indicating various flags, such as a "GraphUserObjectMove" flag to transfer references from the calling thread (e.g., indicating the association of the user object with the graph).

[0029] FIG. 5 illustrates a diagram 500 of user object release API calls, according to at least one embodiment. More information regarding the user object release API calls may be found in the description of FIG. 8. In at least one embodiment, the user object release API is illustrated as cudaUserObjectRelease, UserObjectRelease, and / or any suitable notation, which may relate to a programming model (e.g., CUDA, HIP, oneAPI, and / or variants thereof). In at least one embodiment, the user object release API causes one or more systems of one or more programming models (e.g., CUDA, HIP, oneAPI, and / or variants thereof) to release references to the user object by at least decrementing the reference count of the user object by a specified value. In at least one embodiment, one or more systems utilize the user object release API to track the number of references to and / or usage of a computing resource, or any suitable information, by one or more computing programs.

[0030] In at least one embodiment, parameters for the user object release API call include “object,” “count,” and may include other parameters further defining aspects of the user object. In at least one embodiment, the parameter “object” indicates the user object. In at least one embodiment, the parameter “count” indicates a number of references to be released. In at least one embodiment, one or more systems implement the user object release API call by at least decreasing or otherwise decrementing a count of references associated with the user object (e.g., by the indicated number of references to be released). In at least one embodiment, a response to the user object release API call includes a status. In at least one embodiment, following the user object release API call, the reference count of the user object indicated by the parameter “object” is decremented by a value specified by the parameter “count.” In at least one embodiment, the status is returned in response to the user object release API call to indicate a status indication of the user object release API call. In at least one embodiment, the status indication indicates whether one or more operations of the user object release API succeeded, failed, or whether another error occurred.

[0031] In at least one embodiment, a graph release user object API implements one or more processes of the user object release API. In at least one embodiment, the user object release API may be utilized to implement one or more processes of the graph release user object API. In at least one embodiment, the graph release user object API is utilized to release the user object reference from the graph, and the parameters for the graph release user object API call include a "graph" indicating the graph to release the reference from, an "object" indicating the user object to release the reference from, and a "count" indicating the number of references to be released.

[0032] FIG. 6 illustrates an example process 600 for generating a data structure to be used to monitor use of information by a computer program, according to at least one embodiment. In at least one embodiment, some or all of process 600 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems comprised of computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that collectively executes on one or more processors via hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to implement process 600 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0033] In at least one embodiment, process 600 is performed by one or more systems, such as those described in this disclosure. In at least one embodiment, process 600 is performed by a system of one or more programming models. In at least one embodiment, one or more processes of process 600 are performed in any suitable order, including serially, in parallel, and / or variations thereof, and using any suitable processing unit, such as a CPU, a GPU, a PPU, and / or variations thereof.

[0034] In at least one embodiment, the system implementing at least a portion of process 600 includes, at 602, executable code for obtaining at least code indicating an API for generating one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, the API is a user object creation API, such as that described with reference to FIG. 3. In at least one embodiment, the one or more data structures include the user object. In at least one embodiment, the information includes any suitable computing resources utilized by the computer program, such as the object, input data, data objects, data structures, regions of memory, and / or variations thereof. In at least one embodiment, the API includes parameter values, such as those described with reference to FIG. 3. In at least one embodiment, the API includes parameter values ​​indicating locations corresponding to the one or more data structures (e.g., locations for handles corresponding to the one or more data structures), a number of references, one or more functions (e.g., destructors), and / or variations thereof.

[0035] In at least one embodiment, the computer program, such as those described herein, is any suitable program executable by any suitable processing unit, such as one or more CPUs, GPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the computer program, such as those described herein, corresponds to one or more graph data structures, graph code, and / or variations thereof. In at least one embodiment, the code is written using any suitable programming language and for any suitable programming model, such as CUDA, HIP, oneAPI, and / or variations thereof.

[0036] In at least one embodiment, the system implementing at least a portion of process 600 includes executable code for implementing an API to generate one or more data structures to be used to monitor use of information by a computer program, at 604. In at least one embodiment, the system implements the API as part of execution of the code that implements the API. In at least one embodiment, the system generates the one or more data structures that encode or otherwise indicate at least the one or more functions (e.g., destructors) and a value indicating a count of references associated with the computer program, also referred to as a reference count. In at least one embodiment, the system monitors the use of the information by the computer program by at least monitoring the number of references to the information utilized by the computer program. In at least one embodiment, the system associates the one or more data structures with one or more graph data structures to monitor use of information by the one or more graph data structures. In at least one embodiment, the system triggers execution of the one or more functions when the value reaches zero.

[0037] FIG. 7 illustrates an example process 700 for causing information usage by a computer program to be increased, according to at least one embodiment. In at least one embodiment, some or all of process 700 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems comprised of computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that collectively executes on one or more processors via hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to implement process 700 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0038] In at least one embodiment, process 700 is performed by one or more systems, such as those described in this disclosure. In at least one embodiment, process 700 is performed by a system of one or more programming models. In at least one embodiment, one or more processes of process 700 are performed in any suitable order, including serially, in parallel, and / or variations thereof, and using any suitable processing unit, such as a CPU, a GPU, a PPU, and / or variations thereof.

[0039] In at least one embodiment, the system implementing at least a portion of process 700 includes, at 702, executable code for obtaining at least code indicating an API for causing information usage by a computer program to be increased at least in part based on one or more data structures used to monitor information usage. In at least one embodiment, the API is a user object retention API or a graph retention user object API, such as those described with respect to FIG. 4. In at least one embodiment, the API includes parameter values, such as those described with respect to FIG. 4. In at least one embodiment, the API includes parameter values ​​indicating the one or more data structures, number of references to retain, and / or variations thereof. In at least one embodiment, the API includes parameter values ​​indicating one or more graph data structures and / or one or more flags.

[0040] In at least one embodiment, the computer program is any suitable program executable by any suitable processing unit, such as one or more CPUs, GPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the computer program is associated with the one or more graph data structures, and the system implements the API by at least associating the one or more data structures with the one or more graph data structures to track usage information by the one or more graph data structures. In at least one embodiment, the code is written using any suitable programming language and with respect to any suitable programming model, such as CUDA, HIP, oneAPI, and / or variations thereof.

[0041] In at least one embodiment, the system performing at least a portion of process 700 includes, at 704, executable code for implementing an API to cause at least a usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of information. In at least one embodiment, the system implements the API as part of execution of the code that represents the API. In at least one embodiment, the system implements the API by at least increasing or otherwise incrementing a value in the one or more data structures (e.g., user objects) that indicate a reference count associated with the computer program by the number of references to be held as indicated by the parameter value of the API. In at least one embodiment, the system causes at least a usage of the information by the computer program to be increased based at least in part on the one or more data structures used to monitor usage of the information by implementing the API to indicate increased usage of information by the computer program (e.g., more references to a computing resource such as the object).

[0042] FIG. 8 illustrates an example process 800 that causes information usage by a computer program to be reduced, according to at least one embodiment. In at least one embodiment, some or all of process 800 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that collectively executes on one or more processors via hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to implement process 800 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0043] In at least one embodiment, process 800 is performed by one or more systems, such as those described in this disclosure. In at least one embodiment, process 800 is performed by a system of one or more programming models. In at least one embodiment, one or more processes of process 800 are performed in any suitable order, including serially, in parallel, and / or variations thereof, and using any suitable processing unit, such as a CPU, a GPU, a PPU, and / or variations thereof.

[0044] In at least one embodiment, the system implementing at least a portion of process 800 includes, at 802, executable code for obtaining at least code indicating an API to cause information usage by a computer program to be reduced based at least in part on one or more data structures used to monitor information usage. In at least one embodiment, the API is a user object release API or a graph release user object API, such as those described with respect to FIG. 5. In at least one embodiment, the API includes parameter values, such as those described with respect to FIG. 5. In at least one embodiment, the API includes parameter values ​​indicating the one or more data structures, number of references to release, and / or variations thereof. In at least one embodiment, the API includes parameter values ​​indicating one or more graph data structures.

[0045] In at least one embodiment, the computer program is any suitable program executable by any suitable processing unit, such as one or more CPUs, GPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the computer program is associated with the one or more graph data structures. In at least one embodiment, the code is written using any suitable programming language and with respect to any suitable programming model, such as CUDA, HIP, oneAPI, and / or variations thereof.

[0046] In at least one embodiment, the system performing at least a portion of process 800 includes executable code for implementing an API to cause at least a computer program's information usage to be reduced based at least in part on one or more data structures used to monitor information usage, at 804. In at least one embodiment, the system implements the API as part of execution of the code that indicates the API. In at least one embodiment, the system implements the API by at least reducing or otherwise decrementing values ​​in the one or more data structures (e.g., user objects) that indicate reference counts associated with the computer program by the number of references to be released indicated by the parameter value of the API. In at least one embodiment, the system causes the computer program's information usage to be reduced based at least in part on the one or more data structures used to monitor information usage by implementing the API to indicate at least a reduction in the computer program's information usage (e.g., fewer references to a computing resource). In at least one embodiment, the system invokes one or more functions (e.g., destructors) to destroy or otherwise delete the information (e.g., computing resources such as the object) used by the computer program when the value indicating the count of references reaches zero.

[0047] In the preceding and following descriptions, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0048] Data Center 9 illustrates an exemplary data center 900, according to at least one embodiment. In at least one embodiment, data center 900 includes, but is not limited to, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0049] In at least one embodiment, as shown in FIG. 9 , a data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node CR”) 916(1) through 916(N), where “N” represents any positive integer. In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, cooling modules, etc. In at least one embodiment, one or more nodes CR from among nodes CR 916(1)-916(N) may be a server having one or more of the computing resources described above.

[0050] In at least one embodiment, the grouped computing resources 914 may include a distinct grouping of node CRs housed within one or more racks (not shown), or many racks housed in a data center at various geographic locations (also not shown). The distinct groupings of node CRs within the grouped computing resources 914 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0051] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or some combination thereof.

[0052] 9 , framework layer 920 includes, but is not limited to, a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, framework layer 920 may include a framework for supporting software 952 in software layer 930 and / or one or more applications 942 in application layer 940. In at least one embodiment, software 952 or application(s) 942 may include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 920 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which may utilize distributed file system 938 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 932 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 900. In at least one embodiment, configuration manager 934 may be capable of configuring different tiers, such as software tier 930 and framework tier 920, which includes Spark and distributed file system 938 to support large-scale data processing. In at least one embodiment, resource manager 936 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 938 and job scheduler 932. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 in data center infrastructure tier 910.In at least one embodiment, resource manager 936 may manage these mapped or allocated computing resources in coordination with resource orchestrator 912.

[0053] In at least one embodiment, software 952 included in software layer 930 may include software used by nodes CR 916(1)-916(N), grouped computing resources 914, and / or at least a portion of distributed file system 938 of framework layer 920. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0054] In at least one embodiment, the application(s) 942 included in the application layer 940 may include one or more types of applications used by the nodes CR 916(1)-916(N), the grouped computing resources 914, and / or at least a portion of the distributed file system 938 of the framework layer 920. At least one or more types of applications may include, but are not limited to, CUDA applications.

[0055] In at least one embodiment, any of configuration manager 934, resource manager 936, and resource orchestrator 912 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve data center operators of data center 900 from determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center.

[0056] In at least one embodiment, one or more systems illustrated in Figure 9 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 9 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 9 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 9 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0057] Computer-Based Systems The following diagram describes an exemplary computer-based system that may be used to implement at least one embodiment, but is not limited to the embodiment.

[0058] 10 illustrates a processing system 1000, according to at least one embodiment. In at least one embodiment, the processing system 1000 includes one or more processors 1002 and one or more graphics processors 1008 and may be a single-processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 1002 or processor cores 1007. In at least one embodiment, the processing system 1000 is a processing platform integrated into a system-on-a-chip ("SoC") integrated circuit for use in a mobile, handheld, or embedded device.

[0059] In at least one embodiment, processing system 1000 may include or be incorporated within a server-based gaming platform, a game console, a media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, processing system 1000 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, processing system 1000 may also include, be coupled to, or be incorporated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0060] In at least one embodiment, the one or more processors 1002 each include one or more processor cores 1007 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a particular instruction set 1009. In at least one embodiment, the instruction set 1009 may facilitate computing via Complex Instruction Set Computing ("CISC"), Reduced Instruction Set Computing ("RISC"), or Very Long Instruction Word ("VLIW"). In at least one embodiment, the processor cores 1007 may each process a different instruction set 1009, and the instruction set 1009 may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, the processor cores 1007 may also include other processing devices, such as a digital signal processor ("DSP").

[0061] In at least one embodiment, processor 1002 includes cache memory (“cache”) 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a level 3 (“L3”) cache or a last level cache (“LLC”)) (not shown), which may be shared among processor cores 1007 using known cache coherency techniques. In at least one embodiment, processor 1002 additionally includes a register file 1006, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1006 may include general-purpose registers or other registers.

[0062] In at least one embodiment, the one or more processors 1002 are coupled to one or more interface buses 1010 for transmitting communication signals, such as address, data, or control signals, between the processors 1002 and other components in the processing system 1000. In at least one embodiment, the interface bus 1010 in one embodiment may be a processor bus, such as a version of a Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 1010 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., Peripheral Component Interconnect, PCI Express ("PCIe")), a memory bus, or other types of interface buses. In at least one embodiment, the processor(s) 1002 include an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, a memory controller 1016 facilitates communication between memory devices and other components of the processing system 1000, and a platform controller hub (“PCH”) 1030 provides connectivity to I / O devices via a local input / output (“I / O”) bus.

[0063] In at least one embodiment, memory device 1020 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or any other memory device having suitable performance to serve as processor memory. In at least one embodiment, memory device 1020 may operate as system memory for processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, memory controller 1016 also couples to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 in processor 1002 to perform graphics and media operations. In at least one embodiment, display device 1011 may be connected to processor(s) 1002. In at least one embodiment, display device 1011 may include one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 1011 may include a head mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications.

[0064] In at least one embodiment, platform controller hub 1030 allows peripherals to connect to memory device 1020 and processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 1024 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, touch sensor 1025 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 1026 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution ("LTE") transceiver. In at least one embodiment, firmware interface 1028 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 1034 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples to interface bus 1010. In at least one embodiment, audio controller 1046 is a multi-channel high-definition audio controller.In at least one embodiment, processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (“PS / 2”)) devices to processing system 1000. In at least one embodiment, platform controller hub 1030 can also connect to one or more Universal Serial Bus (“USB”) controller 1042-connected input devices, such as a keyboard and mouse 1043 combination, a camera 1044, or other USB input devices.

[0065] In at least one embodiment, instances of memory controller 1016 and platform controller hub 1030 may be embedded in a discreet external graphics processor, such as external graphics processor 1012. In at least one embodiment, platform controller hub 1030 and / or memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, processing system 1000 may include external memory controller 1016 and platform controller hub 1030, which may be configured as memory controller hubs and peripheral controller hubs within a system chipset in communication with processor(s) 1002.

[0066] In at least one embodiment, one or more systems illustrated in Figure 10 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 10 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 10 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 10 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0067] FIG. 11 illustrates a computer system 1100 according to at least one embodiment. In at least one embodiment, computer system 1100 may be a system, a SOC, or some combination with interconnected devices and components. In at least one embodiment, computer system 1100 is formed with a processor 1102, which may include an execution unit for executing instructions. In at least one embodiment, computer system 1100 may include components such as, but not limited to, processor 1102, to employ an execution unit that includes logic for implementing algorithms for processing data. In at least one embodiment, computer system 1100 may include a processor such as the PENTIUM® Processor Family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may run a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0068] In at least one embodiment, computer system 1100 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), an SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of performing one or more instructions.

[0069] In at least one embodiment, computer system 1100 may include, but is not limited to, a processor 1102, which may include one or more execution units 1108 that may be configured to execute, but is not limited to, a Compute Unified Device Architecture ("CUDA") (CUDA® is developed by NVIDIA Corporation of Santa Clara, California) programs. In at least one embodiment, the CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1100 is a single-processor desktop or server system. In at least one embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 1102 may be coupled to a processor bus 1110 that may transmit data signals between the processor 1102 and other components in the computer system 1100.

[0070] In at least one embodiment, processor 1102 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1102. In at least one embodiment, processor 1102 may also include a combination of both internal and external cache. In at least one embodiment, register file 1106 may store different types of data in various registers, including, but not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0071] In at least one embodiment, an execution unit 1108, including logic for performing integer and floating-point operations, may also be present in the processor 1102. The processor 1102 may also include a microcode (“u-code”) read-only memory (“ROM”) that stores microcode for some macroinstructions. In at least one embodiment, the execution unit 1108 may include logic for dealing with a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109, along with associated circuitry for executing the instructions, in the instruction set of the general-purpose processor 1102, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1102. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0072] In at least one embodiment, the execution unit 1108 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1100 may include, but is not limited to, a memory 1120. In at least one embodiment, the memory 1120 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other memory device. The memory 1120 may store instruction(s) 1119 and / or data 1121 represented by data signals that may be executed by the processor 1102.

[0073] In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may direct data signals between the processor 1102, the memory 1120, and other components in the computer system 1100, and may bridge data signals between the processor bus 1110, the memory 1120, and the system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to memory 1120 through a high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0074] In at least one embodiment, computer system 1100 may use system I / O 1122, a proprietary hub interface bus, to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub ("flash BIOS") 1128, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1123 including a user input interface 1125 and a keyboard interface, a serial expansion port 1127 such as USB, and a network controller 1134. Data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0075] In at least one embodiment, FIG. 11 illustrates a system including interconnected hardware devices or "chips." In at least one embodiment, FIG. 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 11 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1100 are interconnected using a Compute Express Link ("CXL") interconnect.

[0076] In at least one embodiment, one or more systems illustrated in Figure 11 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 11 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 11 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 11 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0077] 12 illustrates a system 1200, according to at least one embodiment. In at least one embodiment, system 1200 is an electronic device utilizing a processor 1210. In at least one embodiment, system 1200 may be, for example, but not limited to, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premise or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0078] In at least one embodiment, system 1200 may include, without limitation, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2The devices may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, USB (versions 1, 2, and 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 12 illustrates a system including interconnected hardware devices or “chips.” In at least one embodiment, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 12 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 12 are interconnected using a CXL interconnect.

[0079] In at least one embodiment, FIG. 12 includes a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communication (NFC) unit 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset (EC) 1235, a Trusted Platform Module (TPM) 1238, a BIOS / firmware / flash memory (BIOS,FW flash) 1222, a DSP 1260, a Solid State Disk (SSD) or Hard Disk Drive (HDD) 1220, a Wireless Local Area Network (WLAN) unit 1250, a Bluetooth unit 1252, a Wireless Wide Area Network (WWAN) unit 1254, a Bluetooth module 1256, a Bluetooth-enabled device 1258 ... Network) 1256, Global Positioning System (“GPS”) 1255, a camera such as a USB 3.0 camera (“USB 3.0 Camera”) 1254, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0080] In at least one embodiment, other components may be communicatively coupled to processor 1210 through the components described above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, headphones 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and class D amplifier”) 1262, which may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250 and Bluetooth unit 1252, and WWAN unit 1256 may be implemented in a Next Generation Form Factor ("NGFF").

[0081] In at least one embodiment, one or more systems illustrated in Figure 12 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 12 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 12 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 12 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0082] 13 illustrates an exemplary integrated circuit 1300, according to at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1300 is an SoC that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPU, DPU), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1300 includes a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I / O controller 1340. 2 S / I 2The integrated circuit 1300 may include peripheral or bus logic including a C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a high-definition multimedia interface ("HDMI") controller 1350 and a mobile industry processor interface ("MIPI") display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for access to an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1370.

[0083] In at least one embodiment, one or more systems illustrated in Figure 13 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 13 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 13 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 13 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0084] 14 illustrates a computing system 1400 according to at least one embodiment. In at least one embodiment, the computing system 1400 includes a processing subsystem 1401 having one or more processors 1402 and system memory 1404 that communicate via an interconnection path that may include a memory hub 1405. In at least one embodiment, the memory hub 1405 may be a separate component within a chipset component or may be incorporated within the one or more processors 1402. In at least one embodiment, the memory hub 1405 couples to an I / O subsystem 1411 via a communication link 1406. In at least one embodiment, the I / O subsystem 1411 includes an I / O hub 1407 that may enable the computing system 1400 to receive input from one or more input devices 1408. In at least one embodiment, I / O hub 1407 can enable a display controller, which may be included in one or more processors 1402, to provide output to one or more display devices 1410A. In at least one embodiment, the one or more display devices 1410A coupled with I / O hub 1407 can include local, internal, or embedded display devices.

[0085] In at least one embodiment, processing subsystem 1401 includes one or more parallel processors 1412 coupled to memory hub 1405 via a bus or other communication link 1413. In at least one embodiment, communication link 1413 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1412 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many-integrated-core processor. In at least one embodiment, one or more parallel processors 1412 form a graphics processing subsystem that can output pixels to one of one or more display devices 1410A coupled via I / O hub 1407. In at least one embodiment, the one or more parallel processors 1412 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1410B.

[0086] In at least one embodiment, system storage unit 1414 may connect to I / O hub 1407 to provide storage for computing system 1400. In at least one embodiment, I / O switch 1416 may be used to provide an interface mechanism to enable connections between I / O hub 1407 and other components, such as network adapter 1418 and / or wireless network adapter 1419, which may be embedded in the platform, as well as various other devices, which may be added via one or more add-in devices 1420. In at least one embodiment, network adapter 1418 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1419 may include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more wireless radios.

[0087] In at least one embodiment, computing system 1400 may include other components not expressly shown that may also be connected to I / O hub 1407, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in FIG. 14 may be implemented using any suitable protocol, such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interface and / or protocol(s), such as an NVLink high-speed interconnect, or interconnect protocol.

[0088] In at least one embodiment, one or more parallel processors 1412 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, to form a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 1412 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1400 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1412, memory hub 1405, processor(s) 1402, and I / O hub 1407 may be integrated into an SoC integrated circuit. In at least one embodiment, components of computing system 1400 may be integrated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of computing system 1400 may be incorporated into a multi-chip module ("MCM"), which may be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 1411 and display device 1410B are omitted from computing system 1400.

[0089] In at least one embodiment, one or more systems illustrated in FIG. 14 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 14 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 14 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 14 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0090] Processing System The following figures describe exemplary processing systems that may be used to implement, but are not limited to, at least one embodiment.

[0091] FIG. 15 illustrates an accelerated processing unit ("APU") 1500 according to at least one embodiment. In at least one embodiment, the APU 1500 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 1500 may be configured to execute application programs, such as CUDA programs. In at least one embodiment, the APU 1500 includes, but is not limited to, a core complex 1510, a graphics complex 1540, a fabric 1560, an I / O interface 1570, a memory controller 1580, a display controller 1592, and a multimedia engine 1594. In at least one embodiment, the APU 1500 may include, but is not limited to, any number of core complexes 1510, any number of graphics complexes 1550, any number of display controllers 1592, and any number of multimedia engines 1594 in any combination. For purposes of explanation, multiple instances of similar objects are referred to herein with a reference number that identifies the object and, where necessary, a parenthetical number that identifies the instance.

[0092] In at least one embodiment, core complex 1510 is a CPU, graphics complex 1540 is a GPU, and APU 1500 is a processing unit incorporating 1510 and 1540 on a single chip, without limitation. In at least one embodiment, some tasks may be assigned to core complex 1510 and other tasks may be assigned to graphics complex 1540. In at least one embodiment, core complex 1510 is configured to execute main control software associated with APU 1500, such as an operating system. In at least one embodiment, core complex 1510 is the master processor of APU 1500, controlling and coordinating the operation of the other processors. In at least one embodiment, core complex 1510 issues commands that control the operation of graphics complex 1540. In at least one embodiment, core complex 1510 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1540 may be configured to execute device executable code derived from CUDA source code.

[0093] In at least one embodiment, core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and an L3 cache 1530. In at least one embodiment, core complex 1510 may include, but is not limited to, any number of cores 1520 and any number and type of caches in any combination. In at least one embodiment, cores 1520 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1520 is a CPU core.

[0094] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 can simultaneously dispatch one micro-instruction to the integer execution engine 1524 and another micro-instruction to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1526 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1522 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1524 and the floating-point execution engine 1526 .

[0095] In at least one embodiment, each core 1520(i), where i is an integer representing a particular instance of core 1520, may access an L2 cache 1528(i) included in core 1520(i). In at least one embodiment, each core 1520 included in a core complex 1510(j), where j is an integer representing a particular instance of core complex 1510, is connected to the other cores 1520 included in core complex 1510(j) via an L3 cache 1530(j) included in core complex 1510(j). In at least one embodiment, a core 1520 included in a core complex 1510(j), where j is an integer representing a particular instance of core complex 1510, may access all of the L3 caches 1530(j) included in core complex 1510(j). In at least one embodiment, L3 cache 1530 may include, without limitation, any number of slices.

[0096] In at least one embodiment, the graphics complex 1540 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the graphics complex 1540 is configured to execute graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the graphics complex 1540 is configured to execute non-graphics related operations. In at least one embodiment, the graphics complex 1540 is configured to execute both graphics related and non-graphics related operations.

[0097] In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of compute units 1550 and an L2 cache 1542. In at least one embodiment, the compute units 1550 share the L2 cache 1542. In at least one embodiment, the L2 cache 1542 is partitioned. In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of compute units 1550 and any number and type of cache (including zero). In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any amount of dedicated graphics hardware.

[0098] In at least one embodiment, each compute unit 1550 includes, but is not limited to, any number of SIMD units 1552 and shared memory 1554. In at least one embodiment, each SIMD unit 1552 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 1550 may execute any number of thread blocks, with each thread block executing on a single compute unit 1550. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1552 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1554.

[0099] In at least one embodiment, fabric 1560 is a system interconnect that facilitates data and control transmission across core complex 1510, graphics complex 1540, I / O interface 1570, memory controller 1580, display controller 1592, and multimedia engine 1594. In at least one embodiment, APU 1500 may include any quantity and type of system interconnect in addition to or instead of fabric 1560, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to APU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc. In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, peripheral devices coupled to I / O interface 1570 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0100] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display ("LCD") devices. In at least one embodiment, multimedia engine 1594 includes any quantity and type of circuitry related to multimedia, such as, but not limited to, a video decoder, a video encoder, and an image signal processor. In at least one embodiment, memory controller 1580 facilitates data transfer between APU 1500 and unified system memory 1590. In at least one embodiment, core complex 1510 and graphics complex 1540 share unified system memory 1590.

[0101] In at least one embodiment, the APU 1500 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1580 and memory devices (e.g., shared memory 1554) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1500 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1628, L3 cache 1530, and L2 cache 1542), each of which may be private to any number of components (e.g., core 1520, core complex 1510, SIMD unit 1552, compute unit 1550, and graphics complex 1540) or shared among any number of components.

[0102] In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0103] FIG. 16 illustrates a CPU 1600 according to at least one embodiment. In at least one embodiment, the CPU 1600 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the CPU 1600 may be configured to execute application programs. In at least one embodiment, the CPU 1600 may be configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 1600 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1600 may be configured to execute host executable code derived from CUDA source code, and the external GPU may be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1600 includes, but is not limited to, any number of core complexes 1610, a fabric 1660, an I / O interface 1670, and a memory controller 1680.

[0104] In at least one embodiment, core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and an L3 cache 1630. In at least one embodiment, core complex 1610 may include, but is not limited to, any number of cores 1620 and any number and type of caches in any combination. In at least one embodiment, cores 1620 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1620 is a CPU core.

[0105] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating-point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes such instructions, generates micro-ops, and dispatches separate micro-instructions to the integer execution engine 1624 and the floating-point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 can simultaneously dispatch one micro-instruction to the integer execution engine 1624 and another micro-instruction to the floating-point execution engine 1626. In at least one embodiment, the integer execution engine 1624 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1626 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch decode unit 1622 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1624 and the floating-point execution engine 1626 .

[0106] In at least one embodiment, each core 1620(i), where i is an integer representing a particular instance of core 1620, may access an L2 cache 1628(i) included in core 1620(i). In at least one embodiment, each core 1620 included in a core complex 1610(j), where j is an integer representing a particular instance of core complex 1610, is connected to the other cores 1620 in core complex 1610(j) via an L3 cache 1630(j) included in core complex 1610(j). In at least one embodiment, a core 1620 included in a core complex 1610(j), where j is an integer representing a particular instance of core complex 1610, may access all of the L3 caches 1630(j) included in core complex 1610(j). In at least one embodiment, L3 cache 1630 may include, without limitation, any number of slices.

[0107] In at least one embodiment, fabric 1660 is a system interconnect that facilitates data and control transmission across core complexes 1610(1) through 1610(N), where N is an integer greater than 0, I / O interface 1670, and memory controller 1680. In at least one embodiment, CPU 1600 may include any quantity and type of system interconnect in addition to or instead of fabric 1660, which facilitates data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to CPU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interface (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0108] In at least one embodiment, memory controller 1680 facilitates data transfer between CPU 1600 and system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share system memory 1690. In at least one embodiment, CPU 1600 implements a memory subsystem including, but not limited to, any quantity and type of memory controller 1680 and memory devices, which may be dedicated to one component or shared among multiple components. In at least one embodiment, CPU 1600 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1628 and L3 cache 1630), each of which may be private to any number of components (e.g., core 1620 and core complex 1610) or shared among any number of components.

[0109] In at least one embodiment, one or more systems illustrated in Figure 16 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 16 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 16 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 16 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0110] FIG. 17 illustrates an exemplary accelerator integrated slice 1790 according to at least one embodiment. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines included in the graphics acceleration module. The graphics processing engines may each comprise a separate GPU. Alternatively, the graphics processing engine may comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0111] Application effective address space 1782 in system memory 1714 stores process elements 1783. In one embodiment, process elements 1783 are stored in response to GPU calls 1781 from applications 1780 executing on processor 1707. Process elements 1783 contain the process state of the corresponding applications 1780. Work descriptors (“WD”) 1784 contained in process elements 1783 may be single jobs requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1784 is a pointer to a job request queue in application effective address space 1782.

[0112] The graphics acceleration module 1746 and / or individual graphics processing engines may be shared by all or a subset of the processes in the system. In at least one embodiment, infrastructure may be included for setting process state and submitting a WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0113] In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine. Because the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integration circuitry for the owning partition, and the operating system initializes the accelerator integration circuitry for the owning process when the graphics acceleration module 1746 is allocated.

[0114] In operation, WD fetch unit 1791 in accelerator integrated slice 1790 fetches the next WD 1784, which contains instructions for work to be performed by one or more graphics processing engines of graphics acceleration module 1746. As shown, data from WD 1784 is stored in register 1745 and may be used by memory management unit (“MMU”) 1739, interrupt management circuitry 1747, and / or context management circuitry 1748. For example, one embodiment of MMU 1739 includes segment / page walk circuitry for accessing segment / page table 1786 within OS virtual address space 1785. Interrupt management circuit 1747 may process interrupt events (“INT”) 1792 received from graphics acceleration module 1746. When performing graphics operations, effective addresses 1793 generated by the graphics processing engines are translated into real addresses by MMU 1739.

[0115] In one embodiment, the same set of registers 1745 may be replicated for each graphics processing engine and / or graphics acceleration module 1746 and initialized by the hypervisor or operating system. Each of these replicated registers may be included in the accelerator integration slice 1790. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0116] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0117] In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or a particular graphics processing engine. The WD 1784 may contain all the information needed by the graphics processing engine to perform work, or the WD 1784 may be a pointer to a memory location where the application has set up a command queue for work to be completed.

[0118] In at least one embodiment, one or more systems illustrated in Figure 17 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 17 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 17 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 17 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0119] 18A-18B illustrate exemplary graphics processors, according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within an SoC.

[0120] FIG. 18A illustrates an exemplary graphics processor 1810 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 18B illustrates an additional exemplary graphics processor 1840 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1810 of FIG. 18A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1840 of FIG. 18B is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1810, 1840 may be a variation of the graphics processor 1310 of FIG. 13.

[0121] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D-1815N-1, and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs through separate logic, whereby the vertex processor 1805 is optimized to perform operations for vertex shader programs, and one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processor(s) 1815A-1815N use the primitive and vertex data generated by the vertex processor 1805 to create a frame buffer that is displayed on a display device. In at least one embodiment, the fragment processor(s) 1815A-1815N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0122] In at least one embodiment, the graphics processor 1810 additionally includes one or more MMUs 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, the one or more MMUs 1820A-1820B provide virtual-to-physical address mapping for the graphics processor 1810, including the vertex processor 1805 and / or fragment processor(s) 1815A-1815N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1305, image processor 1315, and / or video processor 1320 of Figure 13, thereby allowing each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable graphics processor 1810 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection.

[0123] In at least one embodiment, graphics processor 1840 includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B of graphics processor 1810 of FIG. 18A. In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F-1855N-1, and 1855N), where the one or more shader cores 1855A-1855N provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1855A-1855N, and a tiling unit 1858 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are sub-partitioned in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0124] In at least one embodiment, one or more systems illustrated in Figures 18A-18B are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figures 18A-18B are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 18A-18B are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 18A-18B are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0125] FIG. 19A illustrates a graphics core 1900 according to at least one embodiment. In at least one embodiment, graphics core 1900 may be included within graphics processor 1310 of FIG. 13. In at least one embodiment, graphics core 1900 may be unified shader cores 1855A-1855N as in FIG. 18B. In at least one embodiment, graphics core 1900 includes a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920, which are common to execution resources within graphics core 1900. In at least one embodiment, graphics core 1900 may include multiple slices 1901A-1901N, or partitions for each core, and a graphics processor may include multiple instances of graphics core 1900. The slices 1901A-1901N may include support logic including a local instruction cache 1904A-1904N, a thread scheduler 1906A-1906N, a thread dispatcher 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional function units (“AFUs”) 1912A-1912N, floating-point units (“FPUs”) 1914A-1914N, integer arithmetic logic units (“ALUs”) 1916-1916N, address computational units (“ACUs”) 1913A-1913N, double-precision floating-point units (“DPFPUs”) 1915A-1915N, and matrix processing units (“MPUs”) 1917A-1917N.

[0126] In at least one embodiment, FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, MPUs 1917A-1917N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication ("GEMM"). In at least one embodiment, AFUs 1912A-1912N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0127] FIG. 19B illustrates a general-purpose graphics processing unit (“GPGPU”) 1930, according to at least one embodiment. In at least one embodiment, the GPGPU 1930 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1930 may be configured to allow highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1930 may be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 to enable connection with a host processor. In at least one embodiment, the host interface 1932 is a PCIe interface. In at least one embodiment, the host interface 1932 may be a vendor-specific communication interface or fabric. In at least one embodiment, GPGPU 1930 receives commands from a host processor and distributes execution threads associated with those commands across a set of compute clusters 1936A-1936H using a global scheduler 1934. In at least one embodiment, compute clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, cache memory 1938 can act as a higher-level cache for cache memories within compute clusters 1936A-1936H.

[0128] In at least one embodiment, GPGPU 1930 includes memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B can include various types of memory devices, including DRAM or graphics random access memory such as synchronous graphics random access memory ("SGRAM"), including graphics double data rate ("GDDR") memory.

[0129] In at least one embodiment, compute clusters 1936A-1936H each include a set of graphics cores, such as graphics core 1900 of FIG. 19A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for computations associated with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, and a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0130] In at least one embodiment, multiple instances of GPGPU 1930 may be configured to operate as a compute cluster. Compute clusters 1936A-1936H may implement any technically feasible communication technique for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU link 1940 that enables direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs 1930 or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible via host interface 1932. In at least one embodiment, GPU link 1940 may be configured to allow connection to a host processor in addition to, or as an alternative to, host interface 1932. In at least one embodiment, GPGPU 1930 may be configured to execute CUDA programs.

[0131] In at least one embodiment, one or more systems illustrated in Figures 19A-19B are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figures 19A-19B are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 19A-19B are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 19A-19B are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0132] 20A illustrates a parallel processor 2000, according to at least one embodiment. In at least one embodiment, various components of parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit ("ASIC"), or an FPGA.

[0133] In at least one embodiment, parallel processor 2000 includes parallel processing units 2002. In at least one embodiment, parallel processing units 2002 include I / O units 2004 that enable communication with other devices, including other instances of parallel processing units 2002. In at least one embodiment, I / O units 2004 may be directly connected to other devices. In at least one embodiment, I / O units 2004 connect to other devices through the use of a hub or switch interface, such as memory hub 2005. In at least one embodiment, the connection between memory hub 2005 and I / O units 2004 forms a communication link. In at least one embodiment, I / O units 2004 connect to host interface 2006 and memory crossbar 2016, where host interface 2006 receives commands intended to perform processing operations and memory crossbar 2016 receives commands intended to perform memory operations.

[0134] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations to implement those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to distribute commands or other work items to processing array 2012. In at least one embodiment, scheduler 2010 ensures that processing array 2012 is properly configured and in a valid state before tasks are distributed to processing array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, allowing rapid preemption and context switching of threads executing on the processing array 2012. In at least one embodiment, host software can present workloads for scheduling on the processing array 2012 via one of multiple graphics processing docks. In at least one embodiment, the workloads can then be automatically distributed across the processing array 2012 by scheduler 2010 logic within the microcontroller that includes the scheduler 2010.

[0135] In at least one embodiment, processing array 2012 may include up to “N” clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N). In at least one embodiment, each cluster 2014A-2014N of processing array 2012 may execute multiple concurrent threads. In at least one embodiment, scheduler 2010 may allocate work to clusters 2014A-2014N of processing array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload occurring for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during compilation of program logic configured for execution by processing array 2012. In at least one embodiment, different clusters 2014A-2014N of processing array 2012 may be allocated to process different types of programs or perform different types of computations.

[0136] In at least one embodiment, processing array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 2012 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing array 2012 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0137] In at least one embodiment, the processing array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2012 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0138] In at least one embodiment, when parallel processing units 2002 are used to perform graphics processing, scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations to multiple clusters 2014A-2014N of processing array 2012. In at least one embodiment, portions of processing array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data produced by one or more of clusters 2014A-2014N may be stored in a buffer to allow the intermediate data to be transmitted between clusters 2014A-2014N for further processing.

[0139] In at least one embodiment, the processing array 2012 may receive processing tasks to be performed via a scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks may include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 2010 may be configured to fetch the index corresponding to the task or may receive the index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing array 2012 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0140] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via memory crossbar 2016, which may receive memory requests from processing array 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 may include multiple partition units (e.g., partition unit 2020A, partition unit 2020B through partition unit 2020N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 2022. In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory units, such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0141] In at least one embodiment, the memory units 2024A-2024N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM, including GDDR memory. In at least one embodiment, the memory units 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (“HBM”). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2022, render targets, such as frame buffers or texture maps, may be stored across the memory units 2024A-2024N, allowing the partition units 2020A-2020N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2022 may be eliminated in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.

[0142] In at least one embodiment, any one of the clusters 2014A-2014N of the processing array 2012 can process data that is to be written to any one of the memory units 2024A-2024N in the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to forward the output of each cluster 2014A-2014N to any partition unit 2020A-2020N that can perform additional processing operations on the output, or to another cluster 2014A-2014N. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has a connection to a memory interface 2018 for communicating with the I / O units 2004, as well as a connection to a local instance of parallel processor memory 2022, which allows processing units in different clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate traffic streams between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0143] In at least one embodiment, multiple instances of parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2002 may include a higher precision floating-point unit relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0144] FIG. 20B illustrates a processing cluster 2094, according to at least one embodiment. In at least one embodiment, the processing cluster 2094 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2094 is one of the processing clusters 2014A-2014N of FIG. 20. In at least one embodiment, the processing cluster 2094 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, a single instruction, multiple data ("SIMD") instruction issue technique is used to support the parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, a single instruction, multiple thread ("SIMT") technique is used to support the parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2094.

[0145] In at least one embodiment, operation of the processing cluster 2094 may be controlled via a pipeline manager 2032 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20 and manages the execution of those instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2094. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of the processed data by specifying a destination for the processed data to be distributed through the data crossbar 2040.

[0146] In at least one embodiment, each graphics multiprocessor 2034 in a processing cluster 2094 may include an identical set of function execution logic (e.g., arithmetic logic units, load / store units (“LSUs”), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, such that new instructions may be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may be present.

[0147] In at least one embodiment, instructions sent to a processing cluster 2094 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, when a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 2034.

[0148] In at least one embodiment, the graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 can forgo internal cache and use cache memory (e.g., L1 cache 2048) within the processing cluster 2094. In at least one embodiment, each graphics multiprocessor 2034 also has access to a level 2 (“L2”) cache within a partition unit (e.g., partition units 2020A-2020N in FIG. 20A ), which is shared among all processing clusters 2094 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2002 can be used as global memory. In at least one embodiment, processing cluster 2094 includes multiple instances of graphics multiprocessor 2034, and the graphics multiprocessors 2034 can share common instructions and data, which can be stored in L1 cache 2048.

[0149] In at least one embodiment, each processing cluster 2094 may include an MMU 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside in memory interface 2018 of FIG. 20. In at least one embodiment, MMU 2045 includes a set of page table entries (“PTEs”) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, MMU 2045 may include an address translation lookaside buffer (“TLB”) or cache, which may reside in graphics multiprocessor 2034, L1 cache 2048, or processing cluster 2094. In at least one embodiment, physical addresses are processed to distribute surface data access locality and enable efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0150] In at least one embodiment, the processing clusters 2094 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to the data crossbar 2040 to provide the processed tasks to another processing cluster 2094 for further processing, or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2016. In at least one embodiment, a pre-raster operation unit (“pre-ROP”) 2042 is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which may be co-located with a partition unit as described herein (e.g., partition units 2020A-2020N of FIG. 20). In at least one embodiment, the pre-ROP 2042 may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0151] FIG. 20C illustrates a graphics multiprocessor 2096, according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2096 is the graphics multiprocessor 2034 of FIG. 20B. In at least one embodiment, the graphics multiprocessor 2096 couples to the pipeline manager 2032 of the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2096 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more GPGPU cores 2062, and one or more LSUs 2066. The GPGPU cores 2062 and LSUs 2066 are coupled to the cache memory 2072 and the shared memory 2070 via the memory and cache interconnect 2068.

[0152] In at least one embodiment, instruction cache 2052 receives a stream of instructions to execute from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched for execution by instruction unit 2054. In at least one embodiment, instruction unit 2054 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying an address in the unified address space. In at least one embodiment, address mapping unit 2056 can be used to translate addresses in the unified address space into individual memory addresses that can be accessed by LSU 2066.

[0153] In at least one embodiment, register file 2058 provides a set of registers to the functional units of graphics multiprocessor 2096. In at least one embodiment, register file 2058 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2062, LSUs 2066) of graphics multiprocessor 2096. In at least one embodiment, register file 2058 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of register file 2058. In at least one embodiment, register file 2058 is divided among different thread groups being executed by graphics multiprocessor 2096.

[0154] In at least one embodiment, the GPGPU cores 2062 each include an FPU and / or integer ALU used to execute instructions for the graphics multiprocessor 2096. The GPGPU cores 2062 may be of similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and integer ALU, and a second portion of the GPGPU core 2062 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2096 may additionally include one or more fixed-function or special-function units for performing specific functions, such as rectangle copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed or special-function logic.

[0155] In at least one embodiment, GPGPU core 2062 includes SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU core 2062 may be generated at compile time by a shader compiler or automatically generated when executing a program written and compiled for a single program multiple data (“SPMD”) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0156] In at least one embodiment, memory and cache interconnect 2068 is an interconnect network connecting each functional unit of graphics multiprocessor 2096 to register file 2058 and shared memory 2070. In at least one embodiment, memory and cache interconnect 2068 is a crossbar interconnect that allows LSU 2066 to implement load and store operations between shared memory 2070 and register file 2058. In at least one embodiment, register file 2058 can operate at the same frequency as GPGPU cores 2062, and therefore data transfers between GPGPU cores 2062 and register file 2058 are very low latency. In at least one embodiment, shared memory 2070 can be used to enable communication between threads executing on functional units within graphics multiprocessor 2096. In at least one embodiment, cache memory 2072 can be used as a data cache, for example, to cache texture data communicated between functional units and texture unit 2036. In at least one embodiment, shared memory 2070 can also be used as a managed program cache. In at least one embodiment, threads executing on GPGPU cores 2062 can programmatically store data in the shared memory in addition to the automatically cached data stored in cache memory 2072.

[0157] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated in the same package or chip as the cores and communicatively coupled to the cores via a processor bus / interconnect internal to the package or chip. In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0158] In at least one embodiment, one or more systems illustrated in Figures 20A-20C are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figures 20A-20C are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 20A-20C are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 20A-20C are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0159] 21 illustrates a graphics processor 2100 according to at least one embodiment. In at least one embodiment, the graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, the ring interconnect 2102 couples the graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2100 is one of many processors incorporated within a multi-core processing system.

[0160] In at least one embodiment, graphics processor 2100 receives batches of commands via ring interconnect 2102. In at least one embodiment, the incoming commands are interpreted by command streamer 2103 in pipeline front end 2104. In at least one embodiment, graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics core(s) 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, command streamer 2103 supplies the commands to geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, command streamer 2103 supplies the commands to video front end 2134, which couples to media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine ("VQE") 2130 for video and image post-processing and a multi-format encode / decode ("MFX") engine 2133 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each spawn execution threads for thread execution resources provided by at least one graphics core 2180A.

[0161] In at least one embodiment, graphics processor 2100 includes scalable thread execution resources characterized by modular graphics cores 2180A-2180N (sometimes referred to as core slices), each having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2100 can have any number of graphics cores 2180A-2180N. In at least one embodiment, graphics processor 2100 includes graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, graphics processor 2100 is a low-power processor with a single sub-core (e.g., sub-core 2150A). In at least one embodiment, graphics processor 2100 includes multiple graphics cores 2180A-2180N, each including a first set of sub-cores 2150A-2150N and a second set of sub-cores 2160A-2160N. In at least one embodiment, each sub-core in the first sub-cores 2150A-2150N includes at least a first set of execution units ("EUs") 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each sub-core in the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources 2170 include shared cache memory and pixel operating logic.

[0162] In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0163] FIG. 22 illustrates a processor 2200 according to at least one embodiment. In at least one embodiment, the processor 2200 may include logic circuitry for implementing instructions, including, but not limited to, x86 instructions, AMR instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 2200 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled with MMX™ technology from Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as "SSEx") technology may hold such packed data operands. In at least one embodiment, the processor 2210 may execute instructions to accelerate CUDA programs.

[0164] In at least one embodiment, processor 2200 includes an in-order front end (“front end”) 2201 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and feeds the instructions to instruction decoder 2228, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes received instructions into one or more operations called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”) for execution. In at least one embodiment, instruction decoder 2228 parses instructions into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2230 may assemble decoded uops into program-order sequences, or traces, for execution in uop queue 2234. In at least one embodiment, when trace cache 2230 encounters a complex instruction, microcode ROM 2232 provides the uops necessary to complete the operation.

[0165] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to implement the instruction. In at least one embodiment, an instruction may be decoded into a fewer number of micro-ops for processing in the instruction decoder 2228. In at least one embodiment, an instruction may be stored in the microcode ROM 2232 if several micro-ops are required to accomplish the operation. In at least one embodiment, the trace cache 2230 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2232. In at least one embodiment, after the microcode ROM 2232 finishes sequencing micro-ops for an instruction, the machine front end 2201 may resume fetching micro-ops from the trace cache 2230.

[0166] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2203 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth the flow of instructions and reorder them to optimize performance as they move down the pipeline and are scheduled for execution. Out-of-order execution engine 2203 includes, but is not limited to, allocator / register renamer 2240, memory uop queue 2242, integer / floating point uop queue 2244, memory scheduler 2246, fast scheduler 2202, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2204, and simple floating point scheduler ("simple FP scheduler") 2206. In at least one embodiment, fast scheduler 2202, slow / general purpose floating point scheduler 2204, and simple floating point scheduler 2206 are also collectively referred to herein as "uop schedulers 2202, 2204, 2206." Allocator / register renamer 2240 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2240 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2240 also allocates an entry for each uop in one of two uop queues, memory uop queue 2242 for memory operations and integer / floating point uop queue 2244 for non-memory operations, before memory scheduler 2246 and uop schedulers 2202, 2204, 2206. In at least one embodiment, uop schedulers 2202, 2204, 2206 determine when uops are ready to execute based on the readiness of their dependent input register operand sources and the availability of execution resources required by the uops to complete their operations.In at least one embodiment, the fast scheduler 2202 of at least one embodiment may schedule every half of a main clock cycle, and the slow / general purpose floating point scheduler 2204 and simple floating point scheduler 2206 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2202, 2204, 2206 arbitrate for dispatch ports to schedule uops for execution.

[0167] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / bypass network 2208, floating point register file / bypass network (“FP register file / bypass network”) 2210, address generation units (“AGUs”) 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating point ALU (“FP”) 2222, and floating point move unit (“FP move”) 2224. In at least one embodiment, integer register file / bypass network 2208 and floating point register file / bypass network 2210 are also referred to herein as “register files 2208, 2210.” In at least one embodiment, AGUs 2212 and 2214, fast ALUs 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point move unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224." In at least one embodiment, an execution block may include any number and type of register files (including, but not limited to, zero), bypass networks, address generation units, and execution units, in any combination.

[0168] In at least one embodiment, register files 2208, 2210 may be located between uop schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / bypass network 2208 performs integer operations. In at least one embodiment, floating point register file / bypass network 2210 performs floating point operations. In at least one embodiment, each of register files 2208, 2210 may include, but is not limited to, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2208 may include, but is not limited to, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64 to 128 bits wide, so floating-point register file / bypass network 2210 may include, but is not limited to, 128-bit wide entries.

[0169] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 may execute instructions. In at least one embodiment, register files 2208 and 2210 store integer and floating-point data operand values ​​that microinstructions need to execute. In at least one embodiment, processor 2200 may include, but is not limited to, any number and combination of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, the floating-point ALU 2222 may include a 64-bit floating-point divider for performing, but not limited to, division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2216, 2218. In at least one embodiment, the high-speed ALUs 2216, 2218 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2220 may include integer execution hardware for long-latency type operations such as, but not limited to, multipliers, shifts, flag logic, and branching, so that most complex integer operations proceed to the low-speed ALU 2220. In at least one embodiment, memory load / store operations may be performed by the AGUs 2212, 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 may be implemented to support various operands having various bit widths.In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0170] In at least one embodiment, the uop schedulers 2202, 2204, 2206 dispatch dependent operations before the parent load finishes executing. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2200, the processor 2200 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0171] In at least one embodiment, the term “register” may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0172] In at least one embodiment, one or more systems illustrated in FIG. 22 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 22 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 22 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 22 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0173] FIG. 23 illustrates a processor 2300 according to at least one embodiment. In at least one embodiment, the processor 2300 includes, without limitation, one or more processor cores (“cores”) 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. In at least one embodiment, the processor 2300 may include additional cores, up to an additional processor core 2302N, represented by a dashed box. In at least one embodiment, each of the processor cores 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core also has access to one or more shared cache units 2306.

[0174] In at least one embodiment, the internal cache units 2304A-2304N and the shared cache unit 2306 represent a cache memory hierarchy within the processor 2300. In at least one embodiment, the cache memory units 2304A-2304N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as L2, L3, level 4 ("L4"), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherency logic maintains coherency between the various cache units 2306 and 2304A-2304N.

[0175] In at least one embodiment, processor 2300 may also include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, system agent core 2310 provides management functionality for various processor components. In at least one embodiment, system agent core 2310 includes one or more integrated memory controllers 2314 for managing access to various external memory devices (not shown).

[0176] In at least one embodiment, one or more of the processor cores 2302A-2302N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2310 includes components for coordinating and operating the processor cores 2302A-2302N during multithreaded processing. In at least one embodiment, the system agent core 2310 may additionally include a power control unit (“PCU”), which includes logic and components for adjusting the power state of one or more of the processor cores 2302A-2302N and the graphics processor 2308.

[0177] In at least one embodiment, processor 2300 additionally includes a graphics processor 2308 for performing graphics processing operations. In at least one embodiment, graphics processor 2308 couples to a system agent core 2310 that includes a shared cache unit 2306 and one or more integrated memory controllers 2314. In at least one embodiment, system agent core 2310 also includes a display controller 2311 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2311 may also be a separate module coupled to graphics processor 2308 via at least one interconnect or may be incorporated within graphics processor 2308.

[0178] In at least one embodiment, a ring-based interconnect unit 2312 is used to couple the internal components of processor 2300. In at least one embodiment, alternative interconnect units such as a point-to-point interconnect, a switched interconnect, or other techniques may be used. In at least one embodiment, graphics processor 2308 couples to ring interconnect 2312 via I / O link 2313.

[0179] In at least one embodiment, I / O link 2313 represents at least one of several types of I / O interconnect, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2318, such as an eDRAM module. In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 use embedded memory module 2318 as a shared LLC.

[0180] In at least one embodiment, processor cores 2302A-2302N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of ISA, where one or more of processor cores 2302A-2302N execute a common instruction set and one or more other of processor cores 2302A-2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, processor 2300 may be implemented on one or more chips or as an SoC integrated circuit.

[0181] In at least one embodiment, one or more systems illustrated in Figure 23 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 23 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 23 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 23 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0182] FIG. 24 illustrates a graphics processor core 2400 according to at least one described embodiment. In at least one embodiment, graphics processor core 2400 is included within a graphics core array. In at least one embodiment, graphics processor core 2400, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2400 is an example of a graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2400 may include a fixed function block 2430 coupled with multiple sub-cores 2401A-2401F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed-function logic.

[0183] In at least one embodiment, fixed function block 2430 includes a geometry / fixed function pipeline 2436 that may be shared by all sub-cores in graphics processor 2400, e.g., in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2436 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0184] In at least one embodiment, fixed function block 2430 also includes a graphics SoC interface 2437, a graphics microcontroller 2438, and a media pipeline 2439. Graphics SoC interface 2437 provides an interface between graphics core 2400 and other processor cores within the SoC integrated circuit. In at least one embodiment, graphics microcontroller 2438 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2400, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 2439 includes logic for facilitating decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2439 implements media operations via requests to compute logic or sampling logic within sub-cores 2401-2401F.

[0185] In at least one embodiment, SoC interface 2437 enables graphics core 2400 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 2437 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable and / or implement global memory atomics that may be shared between graphics core 2400 and a CPU within the SoC. In at least one embodiment, SoC interface 2437 can also implement power management controls for graphics core 2400 and enable an interface between the graphics core 2400 clock domain and other clock domains within the SoC. In at least one embodiment, SoC interface 2437 enables receipt of command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. In at least one embodiment, the commands and instructions may be dispatched to a media pipeline 2439 when a media operation is to be performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2436, geometry and fixed function pipeline 2414) when a graphics processing operation is to be performed.

[0186] In at least one embodiment, graphics microcontroller 2438 can be configured to perform various scheduling and management tasks for graphics core 2400. In at least one embodiment, graphics microcontroller 2438 can perform graphics and / or compute workload scheduling for various graphics parallel engines in execution unit (EU) arrays 2402A-2402F, 2404A-2404F within sub-cores 2401A-2401F. In at least one embodiment, host software running on a CPU core of an SoC including graphics core 2400 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, monitoring the progress of the workload, and notifying host software when the workload is complete. In at least one embodiment, graphics microcontroller 2438 can also facilitate low power or idle states for graphics core 2400, providing graphics core 2400 with the ability to save and restore registers within graphics core 2400 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0187] In at least one embodiment, graphics core 2400 may have up to N modular sub-cores, more or fewer than the illustrated sub-cores 2401A-2401F. For each set of N sub-cores, in at least one embodiment, graphics core 2400 may also include shared function logic 2410, shared and / or cache memory 2412, geometry / fixed function pipeline 2414, and additional fixed function logic 2416 for accelerating various graphics and compute processing operations. In at least one embodiment, shared function logic 2410 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics core 2400. Shared and / or cache memory 2412 may be an LLC for the N sub-cores 2401A-2401F in graphics core 2400 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2414 may be included in place of geometry / fixed function pipeline 2436 in fixed function block 2430 and may include the same or similar logical units.

[0188] In at least one embodiment, graphics core 2400 includes additional fixed function logic 2416, which can include various fixed-function acceleration logic for use by graphics core 2400. In at least one embodiment, additional fixed function logic 2416 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed function pipeline 2416, 2436, and a cull pipeline, which is an additional geometry pipeline that can be included in additional fixed function logic 2416. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of an application, each instance having a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the cull pipeline fetches and shades vertex position attributes without rasterizing and rendering pixels to the frame buffer, allowing the cull pipeline logic in the additional fixed-function logic 2416 to execute position shaders in parallel with the main application and produce critical results faster than the full pipeline. In at least one embodiment, the cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to in this instance as the replay pipeline) can consume the visibility information and shade only visible triangles, skipping over culled triangles, which are ultimately passed to the rasterization phase.

[0189] In at least one embodiment, the additional fixed function logic 2416 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, to accelerate CUDA programs.

[0190] In at least one embodiment, each graphics sub-core 2401A-2401F includes a set of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 2401A-2401F include a plurality of EU arrays 2402A-2402F, 2404A-2404F, thread dispatch and inter-thread communication (“TD / IC”) logic 2403A-2403F, 3D (e.g., texture) samplers 2405A-2405F, media samplers 2406A-2406F, shader processors 2407A-2407F, and shared local memory (“SLM”) 2408A-2408F. The EU arrays 2402A-2402F, 2404A-2404F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer / fixed-point logic operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2403A-2403F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitates communication between threads executing on the execution units of a sub-core. In at least one embodiment, the 3D samplers 2405A-2405F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. In at least one embodiment, media samplers 2406A-2406F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 2401A-2401F can alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of the sub-cores 2401A-2401F can utilize shared local memory 2408A-2408F within each sub-core to allow threads executing within a thread group to execute using a common pool of on-chip memory.

[0191] In at least one embodiment, one or more systems illustrated in FIG. 24 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 24 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 24 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 24 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0192] FIG. 25 illustrates a parallel processing unit (“PPU”) 2500 according to at least one embodiment. In at least one embodiment, the PPU 2500 comprises machine-readable code that, when executed by the PPU 2500, causes the PPU 2500 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2500 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizing multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by the PPU 2500. In at least one embodiment, the PPU 2500 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2500 is utilized to perform computations such as linear algebra operations and machine learning operations. Figure 25 depicts an exemplary parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture that may be implemented in at least one embodiment.

[0193] In at least one embodiment, one or more PPUs 2500 are configured to accelerate high performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2500 are configured to accelerate CUDA programs. In at least one embodiment, the PPUs 2500 include, but are not limited to, an I / O unit 2506, a front end unit 2510, a scheduler unit 2512, a work distribution unit 2514, a hub 2516, a crossbar ("Xbar") 2520, one or more general processing clusters ("GPC") 2518, and one or more partition units ("memory partition units") 2522. In at least one embodiment, the PPU 2500 is connected to a host processor or other PPUs 2500 via one or more high-speed GPU interconnects (“GPU interconnects”) 2508. In at least one embodiment, the PPU 2500 is connected to a host processor or other peripheral devices via a system bus or interconnect 2502. In at least one embodiment, the PPU 2500 is connected to local memory comprising one or more memory devices (“memory”) 2504. In at least one embodiment, the memory devices 2504 include, but are not limited to, one or more dynamic random access memory (DRAM) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high-bandwidth memory (“HBM”) subsystem with multiple DRAM dies stacked within each device.

[0194] In at least one embodiment, the high-speed GPU interconnect 2508 may refer to a wire-based, multi-lane communication link used by the system to scale and include one or more PPUs 2500 in combination with one or more CPUs, supporting cache coherence between the PPUs 2500 and the CPUs and CPU mastering. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2508 through a hub 2516 to and from other units of the PPU 2500, such as one or more copy engines, a video encoder, a video decoder, a power management unit, and other components that may not be explicitly shown in FIG. 25 .

[0195] In at least one embodiment, I / O unit 2506 is configured to receive and send communications (e.g., commands, data) from a host processor (not shown in FIG. 25 ) via system bus 2502. In at least one embodiment, I / O unit 2506 communicates with the host processor directly via system bus 2502 or through one or more intermediate devices, such as a memory bridge. In at least one embodiment, I / O unit 2506 may communicate with one or more other processors, such as one or more of PPUs 2500, via system bus 2502. In at least one embodiment, I / O unit 2506 implements a PCIe interface for communication over the PCIe bus. In at least one embodiment, I / O unit 2506 implements an interface for communicating with external devices.

[0196] In at least one embodiment, I / O unit 2506 decodes packets received via system bus 2502. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 2500 to perform various operations. In at least one embodiment, I / O unit 2506 transmits the decoded commands to various other units of PPU 2500 specified by the commands. In at least one embodiment, the commands are transmitted to front end unit 2510 and / or to hub 2516 or other units of PPU 2500, such as one or more copy engines, video encoders, video decoders, or power management units (not explicitly shown in FIG. 25 ). In at least one embodiment, I / O unit 2506 is configured to route communications to and between various logical units of PPU 2500.

[0197] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2500 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory accessible (e.g., readable / writable) by both the host processor and the PPU 2500, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2502 via memory requests sent by the I / O unit 2506 over the system bus 2502. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2500, whereupon the front end unit 2510 receives the pointer to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to various units of the PPU 2500.

[0198] In at least one embodiment, the front end unit 2510 is coupled to a scheduler unit 2512 that configures the various GPCs 2518 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2512 is configured to track state information related to the various tasks managed by the scheduler unit 2512, where the state information may indicate which of the GPCs 2518 the task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, the scheduler unit 2512 manages the execution of multiple tasks on one or more of the GPCs 2518.

[0199] In at least one embodiment, scheduler unit 2512 is coupled to a work distribution unit 2514 configured to dispatch tasks for execution on GPCs 2518. In at least one embodiment, work distribution unit 2514 tracks the number of scheduled tasks received from scheduler unit 2512, and work distribution unit 2514 manages a pending task pool and an active task pool for each of GPCs 2518. In at least one embodiment, the pending task pool may comprise a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2518, and the active task pool may comprise a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 2518, such that when one of the GPCs 2518 completes execution of a task, the task is removed from the active task pool for the GPC 2518 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2518. In at least one embodiment, when an active task is idle on the GPC2518, such as while waiting for a data dependency to be resolved, the active task is evicted from the GPC2518 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC2518.

[0200] In at least one embodiment, work distribution unit 2514 communicates with one or more GPCs 2518 via X-bar 2520. In at least one embodiment, X-bar 2520 is an interconnection network coupling many units of PPU 2500 to other units of PPU 2500 and may be configured to couple work distribution unit 2514 to a particular GPC 2518. In at least one embodiment, one or more other units of PPU 2500 may also be connected to X-bar 2520 via hub 2516.

[0201] In at least one embodiment, tasks are managed by scheduler unit 2512 and dispatched by work distribution unit 2514 to one of GPCs 2518. GPC 2518 is configured to process the task and produce a result. In at least one embodiment, the result may be consumed by other tasks within GPC 2518, routed to a different GPC 2518 via Xbar 2520, or stored in memory 2504. In at least one embodiment, the result may be written to memory 2504 via partition unit 2522, which implements a memory interface for reading and writing data to / from memory 2504. In at least one embodiment, the result may be sent to another PPU 2504 or a CPU via high-speed GPU interconnect 2508. In at least one embodiment, the PPU 2500 includes U partition units 2522 equal to, but not limited to, the number of distinct individual memory devices 2504 coupled to the PPU 2500 .

[0202] In at least one embodiment, the host processor executes a driver kernel, which implements an application programming interface ("API") that allows one or more applications running on the host processor to schedule operations for execution on the PPU 2500. In at least one embodiment, multiple compute applications are executed simultaneously by the PPU 2500, which provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 2500, and the driver kernel outputs the tasks to one or more streams that are processed by the PPU 2500. In at least one embodiment, each task comprises one or more groups of participating threads, which may be referred to as a warp. In at least one embodiment, a warp comprises multiple participating threads (e.g., 32 threads) that may be executed in parallel. In at least one embodiment, cooperating threads can refer to multiple threads that contain instructions to perform a task and exchange data through a shared memory.

[0203] In at least one embodiment, one or more systems illustrated in FIG. 25 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 25 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 25 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 25 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0204] Figure 26 illustrates a GPC 2600, according to at least one embodiment. In at least one embodiment, the GPC 2600 is the GPC 2518 of Figure 25. In at least one embodiment, each GPC 2600 includes several hardware units for processing tasks, including, but not limited to, a pipeline manager 2602, a pre-raster operation unit ("PROP") 2604, a raster engine 2608, a work distribution crossbar ("WDX") 2616, an MMU 2618, one or more data processing clusters ("DPC") 2606, and any suitable combination of parts.

[0205] In at least one embodiment, operation of the GPC 2600 is controlled by a pipeline manager 2602. In at least one embodiment, the pipeline manager 2602 manages the configuration of one or more DPCs 2606 to process tasks allocated to the GPC 2600. In at least one embodiment, the pipeline manager 2602 configures at least one of the one or more DPCs 2606 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2606 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2614. In at least one embodiment, pipeline manager 2602 is configured to route packets received from the work distribution unit to the appropriate logical unit within GPC 2600; in at least one embodiment, some packets may be routed to a fixed function hardware unit in PROP 2604 and / or raster engine 2608, while other packets may be routed to DPC 2606 for processing by primitive engine 2612 or SM 2614. In at least one embodiment, pipeline manager 2602 configures at least one of DPC 2606 to implement a computing pipeline. In at least one embodiment, pipeline manager 2602 configures at least one of DPC 2606 to execute at least a portion of a CUDA program.

[0206] In at least one embodiment, the PROP unit 2604 is configured to route data generated by the raster engine 2608 and the DPC 2606 to a raster operation ("ROP") unit in a partition unit, such as the memory partition unit 2522 described in more detail above in conjunction with FIG. 25. In at least one embodiment, the PROP unit 2604 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2608 includes several fixed-function hardware units configured to perform various raster operations, including, but not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are sent to a coarse raster engine to generate coverage information for the primitives (e.g., x, y coverage masks for tiles). The output of the coarse raster engine is sent to a culling engine to cull fragments associated with primitives that fail a z-test and to a clipping engine to clip fragments that are outside the view frustum. In at least one embodiment, fragments that pass clipping and culling are passed to a fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2608 includes fragments to be processed by any suitable entity, such as by a fragment shader implemented within the DPC 2606.

[0207] In at least one embodiment, each DPC 2606 included in GPC 2600 includes, but is not limited to, an M-Pipe Controller (“MPC”) 2610, a Primitive Engine 2612, one or more SMs 2614, and any suitable combination thereof. In at least one embodiment, MPC 2610 controls the operation of DPC 2606, routing packets received from pipeline manager 2602 to the appropriate units in DPC 2606. In at least one embodiment, packets related to vertices are routed to primitive engine 2612, which is configured to fetch vertex attributes associated with the vertices from memory; in contrast, packets related to shader programs may be sent to SM 2614.

[0208] In at least one embodiment, SM2614 includes a programmable streaming processor configured to process tasks represented by, but not limited to, several threads. In at least one embodiment, SM2614 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular group of threads and implements a SIMD architecture, where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instructions. In at least one embodiment, SM2614 implements a SIMT architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp to enable concurrent processing between warps and serial execution within a warp when threads within a warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to allow equal concurrency among all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread, so that threads executing the same instructions can converge and execute in parallel for better efficiency. At least one embodiment of SM2614 is described in further detail in conjunction with FIG. 27.

[0209] In at least one embodiment, MMU 2618 provides an interface between GPC 2600 and a memory partition unit (e.g., partition unit 2522 of FIG. 25), and MMU 2618 provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, MMU 2618 provides one or more translation lookaside buffers (TLBs) for performing translations from virtual addresses to physical addresses in memory.

[0210] In at least one embodiment, one or more systems illustrated in FIG. 26 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 26 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 26 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 26 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0211] Figure 27 illustrates a streaming multiprocessor ("SM") 2700, according to at least one embodiment. In at least one embodiment, the SM 2700 is the SM 2614 of Figure 26. In at least one embodiment, the SM 2700 includes, but is not limited to, an instruction cache 2702, one or more scheduler units 2704, a register file 2708, one or more processing cores ("cores") 2710, one or more special function units ("SFUs") 2712, one or more LSUs 2714, an interconnect network 2716, a shared memory / L1 cache 2718, and any suitable combination thereof. In at least one embodiment, the work distribution unit dispatches tasks for execution on the GPCs of the parallel processing unit (PPU), with each task being assigned to a particular data processing cluster (DPC) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2700. In at least one embodiment, the scheduler unit 2704 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SMs 2700. In at least one embodiment, the scheduler unit 2704 schedules the thread blocks for execution as warps of parallel threads, with each thread block being assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, scheduler unit 2704 manages multiple different thread blocks, allocates warps to the different thread blocks, and then dispatches instructions from multiple different interlocking groups to various functional units (e.g., processing cores 2710, SFUs 2712, and LSUs 2714) during each clock cycle.

[0212] In at least one embodiment, a "coordination group" may refer to a programming model for organizing groups of communicating threads, where the programming model allows developers to express the granularity at which threads are communicating, enabling richer and more efficient expression of parallel decompositions. In at least one embodiment, a coordination invocation API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, traditional programming model APIs provide a single simple construct for synchronizing coordinated threads, i.e., a barrier across all threads in a thread block (e.g., the syncthreads() function). However, in at least one embodiment, a programmer may define groups of threads at a granularity finer than a thread block and synchronize within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, coordination groups allow programmers to explicitly define groups of threads at sub-block and multi-block granularity and perform collective operations, such as synchronization, on threads in the coordination group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local context without having to make assumptions about convergence. In at least one embodiment, the interlocking group primitive enables new patterns of interlocking parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0213] In at least one embodiment, the dispatch unit 2706 is configured to send instructions to one or more of the functional units, and the scheduler unit 2704 includes, without limitation, two dispatch units 2706, allowing two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2704 includes a single dispatch unit 2706 or additional dispatch units 2706.

[0214] In at least one embodiment, each SM2700 includes, in at least one embodiment, a register file 2708 that provides a set of registers to the functional units of the SM2700. In at least one embodiment, the register file 2708 is divided among each of the functional units such that each functional unit is allocated a dedicated portion of the register file 2708. In at least one embodiment, the register file 2708 is divided among the different warps being executed by the SM2700, and the register file 2708 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2700 includes, in at least one embodiment, a plurality of, inclusive of L, processing cores 2710. In at least one embodiment, the SM2700 includes, inclusive of L, a number of individual processing cores 2710 (e.g., 128 or more). In at least one embodiment, each processing core 2710 includes, but is not limited to, fully pipelined single-precision, double-precision, and / or mixed-precision processing units, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, processing core 2710 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores.

[0215] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in processing core 2710. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0216] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and sum matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor cores operate on 16-bit floating-point input data with a 32-bit floating-point sum. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations, resulting in a full-precision product, which is then added using 32-bit floating-point addition with other intermediate products for a 4x4x4 matrix multiplication. In at least one embodiment, the tensor cores are used to perform much larger two-dimensional or even higher-dimensional matrix operations that build up from these smaller elements. In at least one embodiment, an API such as the CUDA-C++ API exposes specialized matrix load, matrix multiply-and-add, and matrix store operations to efficiently use the tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp-level interface assumes a matrix of size 16x16 that spans all 32 threads of a warp.

[0217] In at least one embodiment, each SM2700 includes M SFUs2712 that perform special functions (e.g., but not limited to, attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs2712 include, but are not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs2712 include, but are not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., 2D arrays of texels) from memory and sample texture maps to produce sampled texture values ​​for use in shader programs executed by the SM2700. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2718. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2700 includes, but is not limited to, two texture units.

[0218] In at least one embodiment, each SM 2700 includes, but is not limited to, N LSUs 2714 that implement load and store operations between shared memory / L1 cache 2718 and register file 2708. In at least one embodiment, each SM 2700 includes, but is not limited to, an interconnection network 2716 that connects each of the functional units to register file 2708 and connects LSUs 2714 to register file 2708 and shared memory / L1 cache 2718. In at least one embodiment, interconnection network 2716 is a crossbar that can be configured to connect any of the functional units to any of the registers in register file 2708 and connect LSUs 2714 to memory locations in register file 2708 and shared memory / L1 cache 2718.

[0219] In at least one embodiment, shared memory / L1 cache 2718 is an array of on-chip memory that enables data storage and communication between SM2700 and the primitive engines and between threads in SM2700. In at least one embodiment, shared memory / L1 cache 2718 has, but is not limited to, 128 KB of storage capacity and is in the path from SM2700 to the partition unit. In at least one embodiment, shared memory / L1 cache 2718 is used to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 2718, L2 cache, and memory are backing stores.

[0220] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used as a cache or available for use by programs that do not use shared memory, such as when the shared memory is configured to use half the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, the integration within the shared memory / L1 cache 2718 allows the shared memory / L1 cache 2718 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth, low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computation, a simpler configuration may be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a much simpler programming model. In at least one embodiment, and in the general-purpose parallel computation configuration, the work distribution unit directly assigns and distributes blocks of threads to the DPCs. In at least one embodiment, blocked threads execute the same program using unique thread IDs in computations to ensure each thread produces unique results, use SM2700 to execute the program and perform computations, use shared memory / L1 cache 2718 to communicate between threads, and use LSU2714 to read and write global memory through shared memory / L1 cache 2718 and memory partition unit 2714. In at least one embodiment, when configured for general-purpose parallel computation, SM2700 writes commands that scheduler unit 2704 can use to launch new work on DPCs.

[0221] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smart phone (e.g., a wireless handheld device), a PDA, a digital camera, a vehicle, a head-mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC with one or more other devices, such as additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.

[0222] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") included in the chipset of the motherboard.

[0223] In at least one embodiment, one or more systems illustrated in Figure 27 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 27 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 27 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 27 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0224] Software Constructs for General-Purpose Computing The following diagram describes an exemplary software construct for implementing at least one embodiment, but is not limited to this embodiment.

[0225] FIG. 28 illustrates a software stack for a programming platform, according to at least one embodiment. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL™ is developed by the Khronos group), SYCL, or the Intel One API.

[0226] In at least one embodiment, a programming platform's software stack 2800 provides an execution environment for an application 2801. In at least one embodiment, the application 2801 may include any computer software capable of being run on the software stack 2800. In at least one embodiment, the application 2801 may include, but is not limited to, an artificial intelligence (“AI”) / machine learning (“ML”) application, a high performance computing (“HPC”) application, a virtual desktop infrastructure (“VDI”), or a data center workload.

[0227] In at least one embodiment, application 2801 and software stack 2800 run on hardware 2807. In at least one embodiment, hardware 2807 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices supporting a programming platform. In at least one embodiment, such as in the case of CUDA, software stack 2800 may be vendor-specific and compatible only with devices from a particular vendor(s). In at least one embodiment, such as in the case of OpenCL, software stack 2800 may be used with devices from different vendors. In at least one embodiment, hardware 2807 includes a host connected to another device that may be accessed to perform computational tasks via application programming interface (“API”) calls. In at least one embodiment, in contrast to a host in hardware 2807, which may include, but is not limited to, a CPU (but may also include a compute device) and its memory, a device in hardware 2807 may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (but may also include a CPU) and its memory.

[0228] In at least one embodiment, the programming platform's software stack 2800 includes, but is not limited to, several libraries 2803, a runtime 2805, and a device kernel driver 2806. In at least one embodiment, each of the libraries 2803 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 2803 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 2803 include functionality optimized for execution on one or more types of devices. In at least one embodiment, the libraries 2803 may include, but are not limited to, functionality for performing mathematics, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 2803 are associated with corresponding APIs 2802, which may include one or more APIs that expose the functionality implemented in the libraries 2803.

[0229] In at least one embodiment, application 2801 is written as source code that is compiled into executable code, as described in more detail below in conjunction with FIGS. 33-35. In at least one embodiment, the executable code of application 2801 may run, at least in part, on an execution environment provided by software stack 2800. In at least one embodiment, during execution of application 2801, code that needs to run on the device, as opposed to the host, may be reached. In at least one embodiment, in such cases, runtime 2805 may be called to load and launch the requisite code on the device. In at least one embodiment, runtime 2805 may include any technically feasible runtime system capable of supporting the execution of application S01.

[0230] In at least one embodiment, runtime 2805 is implemented as one or more runtime libraries associated with corresponding API(s), shown as API(s) 2804. In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, as well as transferring data between host and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the functions are global functions callable from the host) and setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0231] In at least one embodiment, the runtime library and corresponding API(s) 2804 may be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functionality for fine-grained control of the device, while another (or any number of) APIs may expose a higher-level set of such functionality. In at least one embodiment, a high-level runtime API may be built on top of the low-level API. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of a language-agnostic runtime API.

[0232] In at least one embodiment, device kernel driver 2806 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2806 may provide low-level functionality upon which APIs, such as API(s) 2804 and / or other software rely. In at least one embodiment, device kernel driver 2806 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, in the case of CUDA, device kernel driver 2806 may compile non-hardware-specific Parallel Thread Execution (“PTX”) IR code into binary code for a particular target device at runtime (with caching of the compiled binary code), which may be referred to as “finalizing” the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not have been present when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline without requiring the device kernel driver 2806 to compile the IR code at run time.

[0233] In at least one embodiment, one or more systems illustrated in FIG. 28 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 28 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 28 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 28 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0234] Figure 29 illustrates a CUDA implementation of software stack 2800 of Figure 28, according to at least one embodiment. In at least one embodiment, CUDA software stack 2900, upon which application 2901 may be launched, includes CUDA library 2903, CUDA runtime 2905, CUDA driver 2907, and device kernel driver 2908. In at least one embodiment, CUDA software stack 2900 executes on hardware 2909, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation of Santa Clara, California.

[0235] In at least one embodiment, application 2901, CUDA runtime 2905, and device kernel driver 2908 may perform functionality similar to application 2801, runtime 2805, and device kernel driver 2806, respectively, described above in conjunction with FIG. 28. In at least one embodiment, CUDA driver 2907 includes a library (libcuda.so) that implements CUDA driver API 2906. In at least one embodiment, similar to CUDA runtime API 2904 implemented by the CUDA runtime library (cudart), CUDA driver API 2906 may expose functionality for, among other things, but not limited to, memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2906 differs from the CUDA runtime API 2904 in that the CUDA runtime API 2904 simplifies device code management by providing implicit initialization, context management (similar to processes), and module management (similar to dynamically loaded libraries). In at least one embodiment, in contrast to the high-level CUDA runtime API 2904, the CUDA driver API 2906 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2906 may expose functionality for context management not exposed by the CUDA runtime API 2904. In at least one embodiment, the CUDA driver API 2906 is also language-independent, e.g., supports OpenCL in addition to the CUDA runtime API 2904. Additionally, in at least one embodiment, the development libraries including the CUDA runtime 2905 may be considered separate from the driver components including the user-mode CUDA driver 2907 and the kernel-mode device driver 2908 (sometimes referred to as the "display" driver).

[0236] In at least one embodiment, CUDA libraries 2903 may include, but are not limited to, math libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries that may be utilized by parallel computing applications, such as application 2901. In at least one embodiment, CUDA libraries 2903 may include, among other things, math libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subprograms (“BLAS”) for performing linear algebra operations, the cuFFT library for computing fast Fourier transforms (“FFTs”), and the cuRAND library for generating random numbers. In at least one embodiment, CUDA libraries 2903 may include, among other deep learning libraries, such as the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0237] In at least one embodiment, one or more systems illustrated in Figure 29 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 29 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 29 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 29 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0238] Figure 30 illustrates a ROCm implementation of software stack 2800 of Figure 28, according to at least one embodiment. In at least one embodiment, ROCm software stack 3000, upon which application 3001 may be launched, includes language runtime 3003, system runtime 3005, thunk 3007, and ROCm kernel driver 3008. In at least one embodiment, ROCm software stack 3000 executes on hardware 3009, which may include a GPU, which supports ROCm and is developed by AMD Corporation of Santa Clara, California.

[0239] In at least one embodiment, application 3001 may perform functionality similar to application 2801 described above in conjunction with FIG. 28. Additionally, in at least one embodiment, language runtime 3003 and system runtime 3005 may perform functionality similar to runtime 2805 described above in conjunction with FIG. 28. In at least one embodiment, language runtime 3003 and system runtime 3005 differ in that system runtime 3005 is a language-independent runtime that implements ROCr system runtime API 3004 and utilizes the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes an interface for accessing and interacting with an AMD GPU, including functions for, among other things, memory management, execution control via kernel architected dispatch, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, the language runtime 3003, as opposed to the system runtime 3005, is an implementation of a language-specific runtime API 3002 layered on top of the ROCr system runtime API 3004. In at least one embodiment, the language runtime API may include, but is not limited to, the Heterogeneous Compute Interface for Portability (“HIP”) language runtime API, the Heterogeneous Compute Compiler (“HCC”) language runtime API, or the OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA facilities, and in at least one embodiment, the HIP language runtime API includes functionality similar to the functionality of the CUDA runtime API 2904 described above in conjunction with FIG. 29, such as functionality for memory management, execution control, device management, error handling, and synchronization, among others.

[0240] In at least one embodiment, thunk (ROCt) 3007 is an interface 3006 that can be used to interact with an underlying ROCm driver 3008. In at least one embodiment, ROCm driver 3008 is a ROCk driver that is a combination of an AMDGPU driver and an HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that implements functionality similar to device kernel driver 2806 described above in conjunction with FIG. 28. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more effectively share system resources through hardware features.

[0241] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3000 above the language runtime 3003 and may provide functionality similar to the CUDA library 2903 described above in conjunction with Figure 29. In at least one embodiment, the various libraries may include, but are not limited to, mathematics, deep learning, and / or other libraries, such as, among others, a hipBLAS library that implements functionality similar to that of CUDA cuBLAS, a rocFFT library for computing FFTs that are similar to CUDA cuFFT, and the like.

[0242] In at least one embodiment, one or more systems illustrated in Figure 30 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 30 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 30 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figure 30 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0243] Figure 31 illustrates an OpenCL implementation of software stack 2800 of Figure 28, according to at least one embodiment. In at least one embodiment, OpenCL software stack 3100, upon which application 3101 may be launched, includes OpenCL framework 3110, OpenCL runtime 3106, and driver 3107. In at least one embodiment, OpenCL software stack 3100 executes on non-vendor-specific hardware 2909. In at least one embodiment, OpenCL is supported by devices developed by different vendors, and therefore, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0244] In at least one embodiment, application 3101, OpenCL runtime 3106, device kernel driver 3107, and hardware 3108 may perform functionality similar to application 2801, runtime 2805, device kernel driver 2806, and hardware 2807, respectively, described above in conjunction with Figure 28. In at least one embodiment, application 3101 further includes an OpenCL kernel 3102 with code to be executed on the device.

[0245] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, denoted as platform API 3103 and runtime API 3105. In at least one embodiment, the runtime API 3105 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device may be associated with a respective context, and the runtime API 3105 may use each context to manage command queues, program objects, and kernel objects for that device, among other things, and share memory objects. In at least one embodiment, the platform API 3103 exposes functions that allow device contexts to be used to, among other things, select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In at least one embodiment, the OpenCL framework also provides various built-in functions (not shown), including, among other things, mathematical functions, relational functions, and image processing functions.

[0246] In at least one embodiment, a compiler 3104 is also included in the OpenCL framework 3110. In at least one embodiment, source code may be compiled offline prior to executing the application or online while the application is running. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment may be compiled online by compiler 3104, which is included to represent any number of compilers that may be used to compile source code and / or IR code into binary code, such as Standard Portable Intermediate Representation ("SPIR-V") code. Alternatively, in at least one embodiment, OpenCL applications may be compiled offline prior to executing such applications.

[0247] In at least one embodiment, one or more systems illustrated in Figure 31 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 31 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 31 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 31 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0248] 32 illustrates software supported by a programming platform, according to at least one embodiment. In at least one embodiment, programming platform 3204 is configured to support various programming models 3203, middleware and / or libraries 3202, and frameworks 3201 upon which applications 3200 may rely. In at least one embodiment, applications 3200 may be AI / ML applications implemented using deep learning frameworks such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, the NVIDIA Collective Communication Library ("NCCL"), and / or the NVIDIA Developer Data Loading Library ("DALI®") CUDA library to provide accelerated computing on the underlying hardware.

[0249] In at least one embodiment, programming platform 3204 may be one of the CUDA, ROCm, or OpenCL platforms described above in conjunction with Figures 29, 30, and 31, respectively. In at least one embodiment, programming platform 3204 supports multiple programming models 3203, which are abstractions of the underlying computing system that allow expression of algorithms and data structures. In at least one embodiment, programming model 3203 may expose features of the underlying hardware to improve performance. In at least one embodiment, programming model 3203 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute.

[0250] In at least one embodiment, libraries and / or middleware 3202 provide implementations of the abstractions in programming model 3204. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware includes software that provides services to applications beyond software available from programming platform 3204. In at least one embodiment, libraries and / or middleware 3202 may include, but are not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, libraries and / or middleware 3202 may include NCCL and ROCm Communication Collectives Library ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or Eigen libraries for linear algebra, matrix and vector operations, geometric transforms, numerical solvers, and related algorithms.

[0251] In at least one embodiment, application frameworks 3201 depend on libraries and / or middleware 3202. In at least one embodiment, each of application frameworks 3201 is a software framework used to implement a standard structure of application software. Returning to the AI / ML example described above, in at least one embodiment, the AI / ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0252] In at least one embodiment, one or more systems illustrated in FIG. 32 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 32 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 32 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 32 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0253] Figure 33 illustrates compiling code for execution on one of the programming platforms of Figures 28-31, according to at least one embodiment. In at least one embodiment, compiler 3301 receives source code 3300, which includes both host code and device code. In at least one embodiment, compiler 3301 is configured to convert source code 3300 into host executable code 3302 for execution on the host and device executable code 3303 for execution on the device. In at least one embodiment, source code 3300 may be compiled either offline prior to execution of the application or online while the application is running.

[0254] In at least one embodiment, source code 3300 may include code in any programming language supported by compiler 3301, such as C++, C, Fortran, etc. In at least one embodiment, source code 3300 may be included in a single source file having a mixture of host code and device code, with the location of the device code indicated therein. In at least one embodiment, the single source file may be a .cu file containing CUDA code or a .hip.cpp file containing HIP code. Alternatively, in at least one embodiment, source code 3300 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0255] In at least one embodiment, compiler 3301 is configured to compile source code 3300 into host executable code 3302 for execution on the host and device executable code 3303 for execution on the device. In at least one embodiment, compiler 3301 performs operations including parsing source code 3300 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which source code 3300 comprises a single source file, compiler 3301 may separate the device code from the host code in such single source file, compile the device code and host code into device executable code 3303 and host executable code 3302, respectively, and link the device executable code 3303 and host executable code 3302 together in the single file, as described in more detail below with respect to FIG.

[0256] In at least one embodiment, host executable code 3302 and device executable code 3303 may be in any suitable format, such as binary code and / or IR code. In at least one embodiment, in the case of CUDA, host executable code 3302 may include native object code and device executable code 3303 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3302 and device executable code 3303 may include target binary code.

[0257] In at least one embodiment, one or more systems illustrated in FIG. 33 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 33 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 33 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 33 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0258] FIG. 34 is a more detailed diagram of compiling code for execution on one of the programming platforms of FIGS. 28-31 , according to at least one embodiment. In at least one embodiment, compiler 3401 is configured to receive source code 3400, compile source code 3400, and output executable file 3410. In at least one embodiment, source code 3400 is a single source file, such as a .cu file, a .hip.cpp file, or another format file, that contains both host code and device code. In at least one embodiment, compiler 3401 may be, but is not limited to, the NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in a .cu file or the HIP compiler for compiling HIP code in a .hip.cpp file.

[0259] In at least one embodiment, compiler 3401 includes compiler front end 3402, host compiler 3405, device compiler 3406, and linker 3409. In at least one embodiment, compiler front end 3402 is configured to separate device code 3404 from host code 3403 in source code 3400. In at least one embodiment, device code 3404 is compiled by device compiler 3406 into device executable code 3408, which may include binary code or IR code, as described. In at least one embodiment, separately, host code 3403 is compiled by host compiler 3405 into host executable code 3407. In at least one embodiment, for NVCC, host compiler 3405 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3406 may be, but is not limited to, a Low Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both host compiler 3405 and device compiler 3406 may be, but are not limited to, LLVM-based compilers that output target binary code.

[0260] In at least one embodiment, after compiling source code 3400 into host executable code 3407 and device executable code 3408, linker 3409 links host executable code 3407 and device executable code 3408 together in executable file 3410. In at least one embodiment, the native object code for the host and the PTX or binary code for the device may be linked together in an Executable and Linkable Format (“ELF”) file, which is a container format used to store object code.

[0261] In at least one embodiment, one or more systems illustrated in FIG. 34 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 34 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 34 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 34 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0262] 35 illustrates translating source code prior to compiling the source code, according to at least one embodiment. In at least one embodiment, source code 3500 is passed through translation tool 3501, which translates source code 3500 into translated source code 3502. In at least one embodiment, compiler 3503 is used to compile translated source code 3502 into host executable code 3504 and device executable code 3505, in a process similar to the compilation of source code 3300 by compiler 3301 into host executable code 3302 and device executable code 3303, as described above in conjunction with FIG. 33.

[0263] In at least one embodiment, the translation performed by translation tool 3501 is used to port source code 3500 for execution in an environment different from the environment in which it was originally intended to run. In at least one embodiment, translation tool 3501 may include, but is not limited to, a HIP translator used to "hipify" CUDA code targeted for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the translation of source code 3500 may include parsing source code 3500 and converting calls to API(s) provided by one programming model (e.g., CUDA) into corresponding calls to API(s) provided by another programming model (e.g., HIP), as described in more detail below in conjunction with Figures 36A-37. Returning to the example of hipfifying CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries may be converted to corresponding HIP API calls. In at least one embodiment, the automatic translation performed by translation tool 3501 may sometimes be incomplete and require additional manual effort to fully port source code 3500.

[0264] In at least one embodiment, one or more systems illustrated in FIG. 35 are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 35 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 35 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in FIG. 35 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0265] Configuring GPUs for general-purpose computing The following diagram describes an exemplary architecture for compiling and executing compute source code according to at least one embodiment, but not by way of limitation.

[0266] 36A illustrates a system 36A00 configured to compile and execute CUDA source code 3610 using different types of processing units, according to at least one embodiment. In at least one embodiment, system 36A00 includes, but is not limited to, CUDA source code 3610, CUDA compiler 3650, host executable code 3670(1), host executable code 3670(2), CUDA device executable code 3684, CPU 3690, CUDA-enabled GPU 3694, GPU 3692, CUDA to HIP translation tool 3620, HIP source code 3630, HIP compiler driver 3640, HCC 3660, and HCC device executable code 3682.

[0267] In at least one embodiment, the CUDA source code 3610 is a set of human-readable code in the CUDA programming language. In at least one embodiment, the CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language, including, but not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, the device code is source code that is executable in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3690, GPU 36192, or another GPGPU. In at least one embodiment, the host code is source code that is executable on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3690.

[0268] In at least one embodiment, CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, global functions 3612, device functions 3614, host functions 3616, and host / device functions 3618 may be intermixed in CUDA source code 3610. In at least one embodiment, each of global functions 3612 is executable on a device and callable from a host. In at least one embodiment, one or more of global functions 3612 may therefore serve as entry points to a device. In at least one embodiment, each of global functions 3612 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3612 define a kernel, which is executable on a device and callable from such a device. In at least one embodiment, a kernel is executed N times in parallel by N different threads on the device during execution, where N is any positive integer.

[0269] In at least one embodiment, each of the device functions 3614 executes on a device and is callable only from such device. In at least one embodiment, each of the host functions 3616 executes on a host and is callable only from such host. In at least one embodiment, each of the host / device functions 3616 defines both a host version of the function that executes on a host and is callable only from such host, and a device version of the function that executes on a device and is callable only from such device.

[0270] In at least one embodiment, CUDA source code 3610 may include, but is not limited to, any number of calls to any number of functions defined via CUDA runtime API 3602. In at least one embodiment, CUDA runtime API 3602 may include, but is not limited to, any number of functions that execute on the host to allocate and deallocate device memory, transfer data between host memory and device memory, manage systems with multiple devices, etc. In at least one embodiment, CUDA source code 3610 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, CUDA runtime API 3602, a CUDA driver API, an API for any number of CUDA libraries, etc. In at least one embodiment, and relative to the CUDA Runtime API 3602, the CUDA Driver API is a lower level API, but provides finer grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, etc.

[0271] In at least one embodiment, CUDA compiler 3650 compiles input CUDA code (e.g., CUDA source code 3610) to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, CUDA compiler 3650 is NVCC. In at least one embodiment, host executable code 3670(1) is a compiled version of host code contained in the input source code that is executable on CPU 3690. In at least one embodiment, CPU 3690 can be any processor optimized for sequential instruction processing.

[0272] In at least one embodiment, the CUDA device executable code 3684 is a compiled version of device code included in the input source code that is executable on a CUDA-enabled GPU 3694. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes IR code, such as, but not limited to, PTX code, which is further compiled at runtime by a device driver into binary code for a particular target device (e.g., a CUDA-enabled GPU 3694). In at least one embodiment, the CUDA-enabled GPU 3694 can be any processor that is optimized for parallel instruction processing and supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3694 is developed by NVIDIA Corporation of Santa Clara, California.

[0273] In at least one embodiment, CUDA to HIP translation tool 3620 is configured to translate CUDA source code 3610 into functionally similar HIP source code 3630. In at least one embodiment, HIP source code 3630 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension to the C++ programming language that includes, but is not limited to, a functionally similar version of CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism(s) for defining global functions 3612, but such HIP programming languages ​​may lack support for dynamic parallelism, and therefore, global functions 3612 defined in the HIP code may only be callable from the host.

[0274] In at least one embodiment, HIP source code 3630 includes, but is not limited to, any number of global functions 3612 (including zero), any number of device functions 3614 (including zero), any number of host functions 3616 (including zero), and any number of host / device functions 3618 (including zero). In at least one embodiment, HIP source code 3630 may also include any number of calls to any number of functions specified in HIP runtime API 3632. In at least one embodiment, HIP runtime API 3632 includes, but is not limited to, functionally similar versions of a subset of functions included in CUDA runtime API 3602. In at least one embodiment, HIP source code 3630 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP APIs include, but are not limited to, a HIP runtime API 3632, a HIP driver API, an API for any number of HIP libraries, an API for any number of ROCm libraries, and the like.

[0275] In at least one embodiment, the CUDA to HIP translation tool 3620 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, the CUDA calls are calls to functions specified in the CUDA API and the HIP calls are calls to functions specified in the HIP API. In at least one embodiment, the CUDA to HIP translation tool 3620 converts any number of calls to functions specified in the CUDA runtime API 3602 into any number of calls to functions specified in the HIP runtime API 3632.

[0276] In at least one embodiment, the CUDA to HIP translation tool 3620 is a tool known as hipify-perl, which performs a text-based translation process. In at least one embodiment, the CUDA to HIP translation tool 3620 is a tool known as hipify-clang, which performs a more complex and robust translation process for hipify-perl that involves parsing the CUDA code using clang (a compiler front end) and then translating the resulting symbols. In at least one embodiment, properly converting the CUDA code to HIP code may require modifications (e.g., manual edits) in addition to the modifications performed by the CUDA to HIP translation tool 3620.

[0277] In at least one embodiment, HIP compiler driver 3640 is a front end that determines a target device 3646 and then configures a compiler compatible with target device 3646 to compile HIP source code 3630. In at least one embodiment, target device 3646 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3640 may determine target device 3646 in any technically feasible manner.

[0278] In at least one embodiment, if target device 3646 is compatible with CUDA (e.g., CUDA-enabled GPU 3694), HIP compiler driver 3640 generates HIP / NVCC compile commands 3642. In at least one embodiment, and as described in more detail in conjunction with FIG. 36B, HIP / NVCC compile commands 3642 configure CUDA compiler 3650 to compile HIP source code 3630 using, without limitation, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile commands 3642, CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684.

[0279] In at least one embodiment, if target device 3646 is not CUDA compatible, HIP compiler driver 3640 generates HIP / HCC compile commands 3644. In at least one embodiment, and as described in more detail in conjunction with FIG. 36C , HIP / HCC compile commands 3644 configure HCC 3660 to compile HIP source code 3630 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile commands 3644, HCC 3660 generates host executable code 3670(2) and HCC device executable code 3682. In at least one embodiment, HCC device executable code 3682 is a compiled version of device code included in HIP source code 3630 that is executable on GPU 3692. In at least one embodiment, the GPU 3692 may be any processor that is optimized for parallel instruction processing, is not CUDA compatible, and is HCC compatible. In at least one embodiment, the GPU 3692 is developed by AMD Corporation of Santa Clara, Calif. In at least one embodiment, the GPU 3692 is a non-CUDA GPU 3692.

[0280] For illustrative purposes only, three different flows that may be implemented in at least one embodiment for compiling CUDA source code 3610 for execution on CPU 3690 and different devices are illustrated in Figure 36A. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3610 for execution on CPU 3690 and CUDA-enabled GPU 3694 without translating CUDA source code 3610 into HIP source code 3630. In at least one embodiment, an indirect CUDA flow translates CUDA source code 3610 into HIP source code 3630 and then compiles HIP source code 3630 for execution on CPU 3690 and CUDA-enabled GPU 3694. In at least one embodiment, the CUDA / HCC flow translates CUDA source code 3610 into HIP source code 3630 and then compiles the HIP source code 3630 for execution on the CPU 3690 and GPU 3692.

[0281] A direct CUDA flow that may be implemented in at least one embodiment is illustrated via dashed lines and a series of bubbles annotated A1-A3. In at least one embodiment, and as illustrated by the bubble annotated A1, a CUDA compiler 3650 receives CUDA source code 3610 and a CUDA compile command 3648 that configures the CUDA compiler 3650 to compile the CUDA source code 3610. In at least one embodiment, the CUDA source code 3610 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3648, the CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684 (illustrated by the bubble annotated A2). In at least one embodiment, and as illustrated by the bubble annotated A3, host executable code 3670(1) and CUDA device executable code 3684 may execute on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0282] An indirect CUDA flow that may be implemented in at least one embodiment is illustrated via a dotted line and a series of bubbles annotated B1-B6. In at least one embodiment, and as illustrated by the bubble annotated B1, a CUDA to HIP translation tool 3620 receives CUDA source code 3610. In at least one embodiment, and as illustrated by the bubble annotated B2, the CUDA to HIP translation tool 3620 translates the CUDA source code 3610 into HIP source code 3630. In at least one embodiment, and as illustrated by the bubble annotated B3, a HIP compiler driver 3640 receives the HIP source code 3630 and determines that the target device 3646 is CUDA-capable.

[0283] In at least one embodiment, and as illustrated by the bubble annotated B4, HIP compiler driver 3640 generates HIP / NVCC compile command 3642 and sends both HIP / NVCC compile command 3642 and HIP source code 3630 to CUDA compiler 3650. In at least one embodiment, and as described in more detail in conjunction with FIG. 36B, HIP / NVCC compile command 3642 configures CUDA compiler 3650 to compile HIP source code 3630 using, but not limited to, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to HIP / NVCC compile command 3642, CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684 (illustrated by the bubble annotated B5). In at least one embodiment, and as illustrated by the bubble annotated B6, host executable code 3670(1) and CUDA device executable code 3684 may execute on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device.

[0284] A CUDA / HCC flow that may be implemented in at least one embodiment is illustrated via a solid line and a series of bubbles annotated C1-C6. In at least one embodiment, and as illustrated by the bubble annotated C1, a CUDA to HIP translation tool 3620 receives CUDA source code 3610. In at least one embodiment, and as illustrated by the bubble annotated C2, the CUDA to HIP translation tool 3620 translates the CUDA source code 3610 into HIP source code 3630. In at least one embodiment, and as illustrated by the bubble annotated C3, a HIP compiler driver 3640 receives the HIP source code 3630 and determines that the target device 3646 is not CUDA-capable.

[0285] In at least one embodiment, HIP compiler driver 3640 generates HIP / HCC compile command 3644 and sends both HIP / HCC compile command 3644 and HIP source code 3630 to HCC 3660 (illustrated by the bubble annotated C4). In at least one embodiment, and as described in more detail in conjunction with FIG. 36C, HIP / HCC compile command 3644 configures HCC 3660 to compile HIP source code 3630 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to HIP / HCC compile command 3644, HCC 3660 generates host executable code 3670(2) and HCC device executable code 3682 (illustrated by the bubble annotated C5). In at least one embodiment, and as illustrated by the bubble annotated C6, host executable code 3670(2) and HCC device executable code 3682 may execute on CPU 3690 and GPU 3692, respectively.

[0286] In at least one embodiment, after CUDA source code 3610 is translated into HIP source code 3630, HIP compiler driver 3640 can then be used to generate executable code for either CUDA-enabled GPU 3694 or GPU 3692 without re-running CUDA to HIP translation tool 3620. In at least one embodiment, CUDA to HIP translation tool 3620 translates CUDA source code 3610 into HIP source code 3630, which is then stored in memory. In at least one embodiment, HIP compiler driver 3640 then configures HCC 3660 to generate host executable code 3670(2) and HCC device executable code 3682 based on HIP source code 3630. In at least one embodiment, HIP compiler driver 3640 then configures CUDA compiler 3650 to generate host executable code 3670(1) and CUDA device executable code 3684 based on the stored HIP source code 3630.

[0287] Figure 36B illustrates a system 3604 configured to compile and execute the CUDA source code 3610 of Figure 36A using a CPU 3690 and a CUDA-enabled GPU 3694, according to at least one embodiment. In at least one embodiment, system 3604 includes, but is not limited to, CUDA source code 3610, a CUDA to HIP translation tool 3620, HIP source code 3630, a HIP compiler driver 3640, a CUDA compiler 3650, host executable code 3670(1), CUDA device executable code 3684, a CPU 3690, and a CUDA-enabled GPU 3694.

[0288] 36A , CUDA source code 3610 includes, but is not limited to, any number of global functions 3612 (including zero), any number of device functions 3614 (including zero), any number of host functions 3616 (including zero), and any number of host / device functions 3618. In at least one embodiment, CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0289] In at least one embodiment, CUDA to HIP translation tool 3620 translates CUDA source code 3610 into HIP source code 3630. In at least one embodiment, CUDA to HIP translation tool 3620 converts each kernel call in CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA source code 3610 into any number of other functionally similar HIP calls.

[0290] In at least one embodiment, HIP compiler driver 3640 determines that target device 3646 is CUDA-enabled and generates HIP / NVCC compile commands 3642. In at least one embodiment, HIP compiler driver 3640 then configures CUDA compiler 3650 via HIP / NVCC compile commands 3642 to compile HIP source code 3630. In at least one embodiment, HIP compiler driver 3640, as part of configuring CUDA compiler 3650, provides access to HIP-to-CUDA translation header 3652. In at least one embodiment, HIP-to-CUDA translation header 3652 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs into any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, CUDA compiler 3650 uses HIP to CUDA translation header 3652 in conjunction with CUDA runtime library 3654 corresponding to CUDA runtime API 3602 to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, host executable code 3670(1) and CUDA device executable code 3684 may then be executed on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, PTX code and is further compiled at runtime into binary code for a particular target device.

[0291] Figure 36C illustrates a system 3606 configured to compile and execute the CUDA source code 3610 of Figure 36A using a CPU 3690 and a non-CUDA GPU 3692, according to at least one embodiment. In at least one embodiment, system 3606 includes, but is not limited to, CUDA source code 3610, a CUDA to HIP translation tool 3620, HIP source code 3630, a HIP compiler driver 3640, an HCC 3660, host executable code 3670(2), an HCC device executable code 3682, a CPU 3690, and a GPU 3692.

[0292] 36A , CUDA source code 3610 includes, but is not limited to, any number of global functions 3612 (including zero), any number of device functions 3614 (including zero), any number of host functions 3616 (including zero), and any number of host / device functions 3618. In at least one embodiment, CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0293] In at least one embodiment, CUDA to HIP translation tool 3620 translates CUDA source code 3610 into HIP source code 3630. In at least one embodiment, CUDA to HIP translation tool 3620 converts each kernel call in CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in source code 3610 into any number of other functionally similar HIP calls.

[0294] In at least one embodiment, HIP compiler driver 3640 then determines that target device 3646 is not CUDA-enabled and generates HIP / HCC compile commands 3644. In at least one embodiment, HIP compiler driver 3640 then configures HCC 3660 to execute HIP / HCC compile commands 3644 to compile HIP source code 3630. In at least one embodiment, HIP / HCC compile commands 3644 configure HCC 3660 to use, without limitation, HIP / HCC runtime library 3658 and HCC headers 3656 to generate host executable code 3670(2) and HCC device executable code 3682. In at least one embodiment, HIP / HCC runtime library 3658 corresponds to HIP runtime API 3632. In at least one embodiment, HCC header 3656 includes, without limitation, any number and type of interoperability mechanisms for the HIP and HCC. In at least one embodiment, host executable code 3670(2) and HCC device executable code 3682 may execute on CPU 3690 and GPU 3692, respectively.

[0295] In at least one embodiment, one or more systems illustrated in Figures 36A-36C are utilized to implement an API to generate one or more data structures to be used to monitor usage of information by a computer program. In at least one embodiment, one or more systems illustrated in Figures 36A-36C are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 36A-36C are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor usage of the information. In at least one embodiment, one or more systems illustrated in Figures 36A-36C are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0296] FIG. 37 illustrates an exemplary kernel translated by the CUDA to HIP translation tool 3620 of FIG. 36C , according to at least one embodiment. In at least one embodiment, the CUDA source code 3610 partitions the overall problem that a given kernel is designed to solve into relatively coarse-grained subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, without limitation, any number of threads. In at least one embodiment, each subproblem is partitioned into relatively finer pieces that can be solved in parallel and in concert by threads within a thread block. In at least one embodiment, threads within a thread block can coordinate by sharing data through shared memory and by synchronizing execution to coordinate memory accesses.

[0297] In at least one embodiment, CUDA source code 3610 organizes thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks, where in at least one embodiment each thread block includes, but is not limited to, any number of threads, and a grid includes, but is not limited to, any number of thread blocks.

[0298] In at least one embodiment, a kernel is a function in device code that is defined using the "__global__" declaration specifier. In at least one embodiment, the dimensions of the grid in which the kernel will execute for a given kernel call and associated stream are specified using CUDA kernel invocation syntax 3710. In at least one embodiment, CUDA kernel invocation syntax 3710 includes the following syntax: "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> >>(KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<<...>>>" construct inserted between the kernel name ("KernelName") and the parenthesized list of kernel arguments ("KernelArguments"). In at least one embodiment, CUDA kernel launch syntax 3710 includes, but is not limited to, CUDA launch function syntax instead of execution configuration syntax.

[0299] In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure including, but not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing a kernel is given a unique thread ID that is accessible within the kernel through a built-in variable (e.g., "threadIdx").

[0300] In at least one embodiment, and with respect to CUDA kernel invocation syntax 3710, "SharedMemorySize" is an optional argument that specifies the number of bytes in shared memory that will be dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3710, SharedMemorySize defaults to 0. In at least one embodiment, and with respect to CUDA kernel invocation syntax 3710, "Stream" is an optional argument that specifies the associated stream and defaults to 0 to specify the default stream. In at least one embodiment, a stream is a sequence of commands (possibly issued by different host threads) that execute in order. In at least one embodiment, different streams may execute commands out of order or concurrently with respect to each other.

[0301] In at least one embodiment, CUDA source code 3610 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd." In at least one embodiment, the main function is host code that executes on the host and includes, but is not limited to, a kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines a threadsPerBlock variable as 16×16 and a numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then defines the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);." In at least one embodiment, and in accordance with CUDA kernel invocation syntax 3710, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16 x N / 16, where each thread block has dimensions 16 x 16. In at least one embodiment, each thread block includes 256 threads, and the grid is created with enough blocks to have one thread per matrix element, and each thread in such grid executes the kernel MatAdd to perform one pairwise addition.

[0302] In at least one embodiment, while translating CUDA source code 3610 into HIP source code 3630, CUDA to HIP translation tool 3620 translates each kernel call in CUDA source code 3610 from CUDA kernel launch syntax 3710 to HIP kernel launch syntax 3720 and converts any number of other CUDA calls in source code 3610 into any number of other functionally similar HIP calls. In at least one embodiment, HIP kernel launch syntax 3720 is specified as "hipLaunchKernelGGL(KernelName, GridSize, BlockSize, SharedMemorySize, Stream, KernelArguments);" In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments have the same meaning in HIP kernel invocation syntax 3720 as in CUDA kernel invocation syntax 3710 (described earlier herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in HIP kernel invocation syntax 3720 and optional in CUDA kernel invocation syntax 3710.

[0303] In at least one embodiment, the portion of HIP source code 3630 illustrated in FIG. 37 is identical to the portion of CUDA source code 3610 illustrated in FIG. 37, except for the kernel call that causes kernel MatAdd to execute on the device. In at least one embodiment, kernel MatAdd is defined in HIP source code 3630 with the same "__global__" declaration specifier that kernel MatAdd is defined in CUDA source code 3610. In at least one embodiment, the kernel call in HIP source code 3630 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in CUDA source code 3610 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);".

[0304] In at least one embodiment, one or more systems illustrated in FIG. 37 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 37 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 37 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 37 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0305] FIG. 38 illustrates the non-CUDA GPU 3692 of FIG. 36C in more detail, according to at least one embodiment. In at least one embodiment, the GPU 3692 is developed by AMD Corporation of Santa Clara. In at least one embodiment, the GPU 3692 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3692 is configured to execute graphics pipeline operations such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the GPU 3692 is configured to execute non-graphics related operations. In at least one embodiment, the GPU 3692 is configured to execute both graphics related and non-graphics related operations. In at least one embodiment, the GPU 3692 may be configured to execute device code included in the HIP source code 3630.

[0306] In at least one embodiment, GPU 3692 includes, but is not limited to, a number of programmable processing units 3820, a command processor 3810, an L2 cache 3822, a memory controller 3870, a DMA engine 3880(1), a system memory controller 3882, a DMA engine 3880(2), and a GPU controller 3884. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, a workload manager 3830 and a number of compute units 3840. In at least one embodiment, command processor 3810 reads commands from one or more command queues (not shown) and distributes the commands to workload manager 3830. In at least one embodiment, for each programmable processing unit 3820, the associated workload manager 3830 distributes work to the compute units 3840 included in the programmable processing unit 3820. In at least one embodiment, each compute unit 3840 may execute any number of thread blocks, but each thread block executes on a single compute unit 3840. In at least one embodiment, a workgroup is a thread block.

[0307] In at least one embodiment, each compute unit 3840 includes, but is not limited to, a number of SIMD units 3850 and a shared memory 3860. In at least one embodiment, each SIMD unit 3850 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3850 includes, but is not limited to, a vector ALU 3852 and a vector register file 3854. In at least one embodiment, each SIMD unit 3850 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3860.

[0308] In at least one embodiment, the programmable processing units 3820 are referred to as "shader engines." In at least one embodiment, each programmable processing unit 3820 includes any amount of dedicated graphics hardware in addition to, but not limited to, compute units 3840. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, any number of geometry processors (including zero), any number of rasterizers (including zero), any number of render back ends (including zero), a workload manager 3830, and any number of compute units 3840.

[0309] In at least one embodiment, the compute units 3840 share an L2 cache 3822. In at least one embodiment, the L2 cache 3822 is partitioned. In at least one embodiment, the GPU memory 3890 is accessible by all of the compute units 3840 in the GPU 3692. In at least one embodiment, the memory controller 3870 and the system memory controller 3882 facilitate data transfers between the GPU 3692 and a host, and the DMA engine 3880(1) enables asynchronous memory transfers between the GPU 3692 and such a host. In at least one embodiment, the memory controller 3870 and the GPU controller 3884 facilitate data transfers between the GPU 3692 and other GPUs 3692, and the DMA engine 3880(2) enables asynchronous memory transfers between the GPU 3692 and other GPUs 3692.

[0310] In at least one embodiment, GPU 3692 includes any quantity and type of system interconnects facilitating data and control transmission across any number and type of directly or indirectly linked components, which may be internal or external to GPU 3692, without limitation. In at least one embodiment, GPU 3692 includes any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices, without limitation. In at least one embodiment, GPU 3692 may include any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3692 implements a memory subsystem, including any quantity and type of memory controllers (e.g., memory controller 3870 and system memory controller 3882) and memory devices (e.g., shared memory 3860), which may be dedicated to one component or shared among multiple components. In at least one embodiment, GPU 3692 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3822), each of which may be private to or shared among any number of components (e.g., SIMD unit 3850, compute unit 3840, and programmable processing unit 3820).

[0311] In at least one embodiment, one or more systems illustrated in FIG. 38 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in FIG. 38 are utilized to implement an API to cause usage of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 38 are utilized to implement an API to cause usage of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in FIG. 38 are utilized to implement one or more systems and / or processes, such as those described with respect to FIGS. 1-8.

[0312] FIG. 39 illustrates how threads of an exemplary CUDA grid 3920 are mapped to different compute units 3840 of FIG. 38, according to at least one embodiment. In at least one embodiment, and for illustrative purposes only, the grid 3920 has a GridSize of BX×BY×1 and a BlockSize of TX×TY×1. In at least one embodiment, the grid 3920 therefore includes, but is not limited to, (BX*BY) thread blocks 3930, and each thread block 3930 includes, but is not limited to, (TX*TY) threads 3940. The threads 3940 are illustrated in FIG. 39 as squiggly arrows.

[0313] In at least one embodiment, grid 3920 is mapped to programmable processing unit 3820(1), which may include, but is not limited to, compute units 3840(1) through 3840(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3930 are mapped to compute unit 3840(1), and the remaining thread blocks 3930 are mapped to compute unit 3840(2). In at least one embodiment, each thread block 3930 may include, but is not limited to, any number of warps, with each warp mapped to a different SIMD unit 3850 in FIG. 38.

[0314] In at least one embodiment, warps in a given thread block 3930 may synchronize with each other and communicate through shared memory 3860 included in the associated compute unit 3840. For example, and in at least one embodiment, warps in thread block 3930(BJ,1) may synchronize with each other and communicate through shared memory 3860(1). For example, and in at least one embodiment, warps in thread block 3930(BJ+1,1) may synchronize with each other and communicate through shared memory 3860(2).

[0315] In at least one embodiment, one or more systems illustrated in Figure 39 are utilized to implement an API to generate one or more data structures to be used to monitor use of information by a computer program. In at least one embodiment, one or more systems illustrated in Figure 39 are utilized to implement an API to cause use of information by a computer program to be increased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 39 are utilized to implement an API to cause use of information by a computer program to be decreased based at least in part on one or more data structures used to monitor use of the information. In at least one embodiment, one or more systems illustrated in Figure 39 are utilized to implement one or more systems and / or processes, such as those described with respect to Figures 1-8.

[0316] FIG. 40 illustrates how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. Data Parallel C++ (DPC++) may refer to an open, standards-based alternative to single-architecture, proprietary languages, allowing developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and to perform custom tuning for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that conform to ISO C++, with which developers may be familiar. DPC++ incorporates the SYCL standard from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the underlying concepts, portability, and efficiency of OpenCL, allowing code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL can enable single-source development, where C++ template functions contain both host and device code, allowing developers to build complex algorithms using OpenCL acceleration and then reuse them across their source code for different types of data.

[0317] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across a variety of hardware targets. In at least one embodiment, a DPC++ compiler is used to generate DPC++ applications that can be deployed across a variety of hardware targets, and DPC++ compatibility tools can be used to migrate CUDA applications to DPC++ multi-platform programs. In at least one embodiment, a DPC++ base toolkit includes a DPC++ compiler for deploying applications across a variety of hardware targets, a DPC++ library for increasing productivity and performance across CPUs, GPUs, and FPGAs, a DPC++ compatibility tool for migrating CUDA applications to multi-platform applications, or any suitable combination thereof.

[0318] In at least one embodiment, the DPC++ programming model is utilized solely for one or more aspects related to programming the CPU and accelerator by using modern C++ features to express parallelism using a programming language called Data Parallel C++. The DPC++ programming language is utilized for code reuse for the host (e.g., CPU) and accelerator (e.g., GPU or FPGA), using a single source language, and execution and memory dependencies can be clearly communicated. Mapping within the DPC++ code can be used to migrate applications to run on the hardware or set of hardware devices that best accelerate the workload. Even on platforms that do not have available accelerators, a host may be available to simplify development and debugging of device code.

[0319] In at least one embodiment, CUDA source code 4000 is provided as input to a DPC++ compatibility tool 4002 to generate a human-readable DPC++ 4004. In at least one embodiment, the human-readable DPC++ 4004 includes inline comments generated by the DPC++ compatibility tool 4002 that guide the developer as to how and / or where to modify the DPC++ code to complete 4006 the coding and tuning for desired performance, thereby generating DPC++ source code 4008.

[0320] In at least one embodiment, CUDA source code 4000 is or includes a set of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 4000 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension to the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may run on one or more processor cores of the device or may include a more parallelizable workflow. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may execute in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 4000 described with respect to FIG. 40 may follow CUDA source code described elsewhere herein.

[0321] In at least one embodiment, DPC++ compatibility tool 4002 refers to an executable tool, program, application, or any other suitable type of tool used to facilitate the migration of CUDA source code 4000 to DPC++ source code 4008. In at least one embodiment, DPC++ compatibility tool 4002 is a command-line based code migration tool available as part of the DPC++ tool kit used to port existing CUDA source to DPC++. In at least one embodiment, DPC++ compatibility tool 4002 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file written at least partially in DPC++, called a human-readable DPC++4004. In at least one embodiment, the human-readable DPC++4004 includes comments generated by DPC++ compatibility tool 4002 to indicate where user intervention may be required. In at least one embodiment, user intervention is required when CUDA source code 4000 calls a CUDA API that does not have a similar DPC++ API; other instances where user intervention is required are described in more detail below.

[0322] In at least one embodiment, a workflow for migrating CUDA source code 4000 (e.g., an application or portions thereof) includes creating one or more compilation database files, migrating CUDA to DPC++ using a DPC++ compatibility tool 4002, completing and validating the migration, thereby generating DPC++ source code 4008, and compiling the DPC++ source code 4008 with a DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used when a Makefile executes and stores them in a compilation database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, an intercept-built command converts Makefile commands into DPC-compatible commands.

[0323] In at least one embodiment, intercept-build is a utility script that intercepts the build process, captures compilation options, macro definitions, and include paths, and writes this data to a compilation database file. In at least one embodiment, the compilation database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 4002 parses the compilation database and applies options when migrating input sources. In at least one embodiment, use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where the commands may include required compilation flags, the directories may include paths to header files, and the files may include paths to CUDA files.

[0324] In at least one embodiment, the DPC++ compatibility tool 4002 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ compatibility tool 4002 is available as part of a tool kit. In at least one embodiment, the DPC++ tool kit includes an intercept-build tool. In at least one embodiment, the intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the intercept-built tool is used by the DPC++ compatibility tool 4002 to migrate the CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, DPC++ compatibility tool 4002 generates a human-readable DPC++ 4004, which, when generated by DPC++ compatibility tool 4002, may not compile with a DPC++ compiler and may be DPC++ code that requires additional plumbing to identify portions of code that were not correctly migrated, which may involve manual intervention, such as by a developer. In at least one embodiment, DPC++ compatibility tool 4002 provides hints or tools embedded in the code to help a developer manually migrate additional code that may not be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application.

[0325] In at least one embodiment, DPC++ compatibility tool 40002 may successfully migrate all portions of CUDA code to DPC++, with only an optional step to manually review and tune the performance of the generated DPC++ source code. In at least one embodiment, DPC++ compatibility tool 4002 directly generates DPC++ source code 4008 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by DPC++ compatibility tool 4002. In at least one embodiment, DPC++ compatibility tool generates compilable DPC++ code that may be optionally tuned by a developer for performance, readability, maintainability, various other considerations, or any combination thereof.

[0326] In at least one embodiment, one or more CUDA source files are at least partially migrated to DPC++ source files using DPC++ compatibility tool 4002. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include:<cuda.h> Header files can be used to print text<stdio.h> In at least one embodiment, a portion of a vector addition kernel CUDA source file may be written as follows or related to the following:

number

number

[0327] In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 4002 parses the CUDA source code and replaces header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is the concept of a thread ID; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0328] In at least one embodiment, and with respect to the CUDA source file presented above, there are two vectors A and B that are initialized, and the vector addition result is placed into vector C as part of VectorAddKernel(). In at least one embodiment, DPC++ compatibilit...

Claims

1. One or more circuits that implement an application programming interface (API) to generate one or more data structures to be used to monitor the use of information by computer programs. Equipped with A processor, wherein the computer program is executable by one or more graphics processing units (GPUs).

2. 2. The processor of claim 1, wherein the one or more data structures indicate at least a number of references associated with the computer program.

3. The processor of claim 1 , wherein the information includes at least a region of memory.

4. The processor of claim 1 , wherein the one or more circuits implement the API based at least in part on parameter values ​​indicating locations corresponding to the one or more data structures.

5. The processor of claim 1 , wherein the one or more circuits further perform one or more functions based at least in part on the use of the information by the computer program.

6. One or more computers having one or more processors that implement an application programming interface (API) to generate one or more data structures to be used to monitor use of information by computer programs. Equipped with The system wherein the information includes at least input data to the computer program.

7. the one or more processors further comprising: Obtaining code that indicates at least the API; Implementing the API by executing at least the code; The system of claim 6.

8. The system of claim 6 , wherein the one or more data structures encode a count of one or more references associated with the information.

9. The system of claim 6 , wherein the one or more data structures point to one or more destructor functions.

10. The system of claim 6 , wherein the computer program is executable by at least one or more parallel processing units (PPUs).

11. When implemented by one or more processors, the one or more processors are configured to perform at least: Implementing an application programming interface (API) to generate one or more data structures to be used to monitor the use of information by computer programs. memorize a set of instructions, A machine-readable medium, wherein the computer program is executable by one or more general purpose graphics processing units (GPGPUs).

12. 12. The machine-readable medium of claim 11, wherein the set of instructions, when executed by the one or more processors, further comprises instructions that cause the one or more processors to implement the API based at least in part on a parameter value indicating a number of references.

13. 12. The machine-readable medium of claim 11, wherein the use of the information is indicated by one or more references used by the computer program.

14. 12. The machine-readable medium of claim 11, wherein the set of instructions, when executed by the one or more processors, further comprises instructions that cause the one or more processors to modify the one or more data structures based on the use of the information by the computer program.

15. 12. The machine-readable medium of claim 11, wherein the set of instructions, when executed by the one or more processors, further comprises instructions that cause the one or more processors to associate the one or more data structures with one or more graph data structures.

16. Implementing an application programming interface (API) to generate one or more data structures to be used to monitor use of the information by a computer program; implementing the API based at least in part on one or more parameter values ​​indicative of one or more functions; A method comprising:

17. 17. The method of claim 16, further comprising: performing one or more functions based at least in part on the number of references indicated by the one or more data structures.

18. The method of claim 16 , wherein the API is a runtime API.

19. 17. The method of claim 16, wherein the computer program is executable by one or more central processing units (CPUs).

20. The method of claim 16 , further comprising obtaining one or more status indications as a result of implementing the API.

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