Integrated Circuit I / O Integrity and Degradation Monitoring

Abstract

To provide a device, a system, and a method for detecting input / output (I / O) integrity and / or degradation monitoring and / or optimizing bump array power / performance.SOLUTION: An input / output (I / O) block for a semiconductor integrated circuit (IC) includes: at least one I / O buffer, configured to define at least one signal path in respect of a connection to a remote I / O block via a communication channel, each signal path causing a respective signal edge slope; and an I / O sensor 200, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of (a) a timing difference between a signal edge for a first signal path and a signal edge for a second signal path, and (b) one or more eye pattern parameters for the at least one signal path.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 786,460, entitled "INTEGRATED CIRCUIT PAD FAILURE DETECTION," filed December 30, 2018, the entire contents of which are incorporated herein by reference in their entirety.

[0002] The present invention relates to the field of integrated circuits. [Background technology]

[0003] Integrated circuits (ICs) can include analog and digital electronic circuits on flat semiconductor substrates such as silicon wafers. Photolithography techniques are used to print tiny transistors onto the substrate, creating complex circuits of billions of transistors in a very small area, enabling modern electronic circuit designs to achieve both low cost and high performance. ICs are produced on assembly lines in factories called foundries, which commoditize the production of ICs such as complementary metal-oxide semiconductor (CMOS) ICs. Digital ICs contain billions of transistors arranged in functional and / or logical units on wafers and packaged in metal, plastic, glass, or ceramic casings. The casing, or package, is connected to a circuit board, for example, using solder. Package types can include lead frames (through-hole, surface-mount, chip carrier, etc.), pin grid arrays, chip-scale packages, ball grid arrays, etc., for connecting IC pads to the circuit board. As used herein, the term IC refers to an integrated circuit including its package.

[0004] Hofmeister et al., "Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST," in IEEE Aerospace Conference, 2008, discusses a sensing method for detecting failures in the solder joint networks belonging to the input / output (I / O) blocks of field programmable gate arrays (FPGAs), particularly those in ball grid array packages. This involves attaching small capacitors to two unused I / O ports as close as possible to the corners of the package. This approach may be suitable for monitoring special bumps to detect intermittent failures, but may not be suitable for monitoring functional bumps.

[0005] The foregoing examples of the related art and limitations associated therewith are intended to be illustrative and not exhaustive. Other limitations of the related art will become apparent to those skilled in the art upon reading the specification and studying the drawings. Summary of the Invention

[0006] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools, and methods that are intended to be exemplary and illustrative, not limiting in scope.

[0007] According to one embodiment, an input / output (I / O) block for a semiconductor integrated circuit (IC) is provided, the I / O block including: at least one I / O buffer configured to define at least one signal path for connection to a remote I / O block via a communication channel, each signal path causing a respective signal edge slope (or edge shape); and an I / O sensor coupled to the at least one signal path and configured to generate an output signal indicative of one or both of (a) a timing difference between a signal edge for a first signal path and a signal edge for a second signal path, and (b) one or more eye pattern parameters of the at least one signal path.

[0008] In an embodiment, the at least one I / O buffer includes a transmit buffer, and the at least one signal path includes a first signal path coupled to an output of the transmit buffer that is coupled to the communication channel.

[0009] In an embodiment, the first signal path is further coupled to a remote I / O block via at least one connection bump, and the output signal of the I / O sensor further indicates a quality of the at least one connection bump.

[0010] In an embodiment, the at least one signal path comprises a third signal path coupled to the remote I / O block via the second connection bump and a fourth signal path, and the I / O sensor is coupled to the third and / or fourth signal paths and configured to generate an output signal where the output signal of the I / O sensor further indicates one or both of a timing difference between a signal edge of the third signal path and a signal edge of the fourth signal path, and eye pattern parameters for the third signal path and / or the fourth signal path, indicative of the quality of the first connection bump and the second connection bump.

[0011] In an embodiment, the at least one signal path includes a signal path coupled to an input of a transmit buffer and / or a signal path coupled to a remote I / O block via an interconnect (such as an interposer or bridge), and a connection bump between the transmit buffer and the interconnect, and the output signal of the I / O sensor further indicates the quality of the connection bump.

[0012] In an embodiment, the I / O block further comprises a differential buffer configured to output a difference between a differential buffer input signal received on a path coupled to the communication channel and a fixed level signal, the signal path of at least one signal path being coupled to the output of the differential buffer.

[0013] In an embodiment, the fixed level signal is a voltage fixed at a predetermined percentage of the DC power supply voltage to the IC, optionally, the predetermined percentage is dynamically adjusted and / or the predetermined percentage is 75%.

[0014] In an embodiment, the at least one I / O buffer includes a receive buffer having an input coupled to the communication channel, and one signal path of the at least one signal path is coupled to an output of the receive buffer.

[0015] In an embodiment, the input to the receive buffer is coupled to the remote I / O block via an interconnect (e.g., an interposer or bridge) and a connection bump between the interconnect and the remote I / O block, and the output signal of the I / O sensor further indicates the quality of the connection bump.

[0016] In an embodiment, the communication channel is configured to transmit differential signals over two signal lines, a first signal path of the at least one signal path coupled to the first signal line and a second signal path of the at least one signal path coupled to the second signal line.

[0017] In an embodiment, at least one I / O buffer comprises a transmit buffer configured to provide a differential output over two signal lines, a first signal path coupled to a first output of the transmit buffer that is coupled to the first signal line, and a second signal path coupled to a second output of the transmit buffer that is coupled to a second signal line.

[0018] In an embodiment, the first signal line comprises a first interconnect (such as an interposer or bridge) coupled to the transmit buffer via a first near-end connection bump, the second signal line comprises a second interconnect (such as an interposer or bridge) coupled to the transmit buffer via a second near-end connection bump, and the output signal of the I / O sensor further indicates the quality of the first and second near-end connection bumps.

[0019] In an embodiment, the first signal line comprises a first interconnect (e.g., an interposer or bridge) coupled to the remote I / O block via a first far-end connection bump, the second signal line comprises a second interconnect (e.g., an interposer or bridge) coupled to the remote I / O block via a second far-end connection bump, and the output signal of the I / O sensor further indicates the quality of the first and second far-end connection bumps.

[0020] In an embodiment, the I / O sensor comprises a first input port coupled to a first option of the first signal path, a second input port coupled to a second option for the first signal path, a third input port coupled to the second signal path, and a selector configured to select the first or second input port in response to a received selection signal such that an output signal of the I / O sensor selectively indicates a timing difference between a signal edge of the second signal path and a signal edge of either the first option of the first signal path or the second option of the first signal path.

[0021] In an embodiment, the I / O block further comprises a differential buffer configured to output a difference between a first signal received on a signal path coupled to the communication channel and a second fixed level signal, and the third input port is coupled to the output of the differential buffer.

[0022] In an embodiment, the at least one I / O buffer may include one or both of a transmit buffer, where a first input port is coupled to an output of the transmit buffer that is coupled to the communication channel, and a receive buffer, where the receive buffer has an input coupled to the communication channel and a second input port is coupled to an output of the receive buffer.

[0023] In an embodiment, the eye pattern parameters include one or more of eye height, eye width jitter, and eye height variation.

[0024] In an embodiment, the output signal includes pulses having widths indicative of either a timing difference between a signal edge of the first signal path and a signal edge of the second signal path, or an eye pattern parameter.

[0025] In an embodiment, the I / O block further comprises a performance optimizer configured to adjust parameters of at least one I / O buffer based on the output signal of the I / O sensor, and / or a repair controller configured to adjust a configuration of the I / O buffer based on the output signal of the I / O sensor.

[0026] In an embodiment, the repair controller is configured to disable part or all of the IC in response to the output signal of the I / O sensor, and / or cause lane remapping of at least part of the IC in response to the output signal of the I / O sensor, and / or adjust transmit buffer strength within the IC in response to the output signal of the I / O sensor.

[0027] In an embodiment, the repair controller is configured to operate during initial operation of the IC and / or during normal operation of the IC, and / or further adjusts based on the instantaneous temperature of the IC and / or the voltage of the IC.

[0028] In an embodiment, the I / O block further comprises a time-to-digital converter configured to receive a timing signal derived from the output signal of the I / O sensor and to provide a digital time signal based on the timing signal.

[0029] A semiconductor integrated circuit (IC) may be provided that includes the I / O blocks described herein.

[0030] In an embodiment, the I / O sensor is configured to communicate an output signal external to the IC.

[0031] In an embodiment, the semiconductor IC further comprises a filtered counter block configured to receive a time signal based on the output signal of the I / O sensor, compare the received time signal with a threshold, and identify exceptional or outlier readings from the I / O sensor based on the comparison.

[0032] In an embodiment, the filtered counter block is further configured to count the number of normal reads from the I / O sensors and / or the number of exceptional or outlier reads from the I / O sensors.

[0033] A semiconductor IC system may be provided that includes the semiconductor IC described herein. The semiconductor IC may further include an I / O profiling unit configured to generate an I / O profile and / or a classification based on output signals of the I / O sensors, and / or an embedded virtual field of view (EVS) unit further configured to determine and / or characterize signal amplitudes and / or signal slew rates for pins of the semiconductor IC based on the output signals of the I / O sensors.

[0034] In an embodiment, one or more of the at least one signal path is further coupled to a remote I / O block via at least one connection bump, and the I / O profile and / or classification is based on monitoring the output signal of the I / O sensor over time.

[0035] In an embodiment, the I / O profile unit is further configured to perform one or more of: comparing the I / O profile and / or classification with family data of the semiconductor IC; detecting systematic shifts based on the I / O profile and / or classification; and detecting outliers based on tester data.

[0036] According to one embodiment, a method is provided for monitoring an input / output (I / O) block of a semiconductor integrated circuit (IC), the I / O block comprising an I / O buffer defining at least one signal path for connection to a remote I / O block via a communication channel, each signal path causing a respective signal edge slope (or edge shape), the method including generating, at an I / O sensor, an output signal indicative of one or both of a timing difference between a signal edge of a first signal path and a signal edge of a second, different signal path, and one or more eye pattern parameters of the at least one signal path. In such method embodiments, method steps may optionally be provided to include any of the features discussed with reference to embodiments of the I / O block.

[0037] In an embodiment, the method further includes adjusting a parameter of at least one I / O buffer based on the output signal of the I / O sensor and / or adjusting a configuration of the I / O buffer based on the output signal of the I / O sensor.

[0038] In an embodiment, the method further includes one or both of disabling part or all of the IC in response to the output signal of the I / O sensor and causing lane remapping of at least part of the IC in response to the output signal of the I / O sensor.

[0039] In an embodiment, this adjusting step is further based on the instantaneous temperature of the IC and / or the voltage of the IC.

[0040] In an embodiment, the method further includes generating an I / O profile and / or classification based on the output signal of the I / O sensor.

[0041] In an embodiment, one or more of the at least one signal path is further coupled to a remote I / O block via at least one connection bump, and the I / O profile and / or classification is based on monitoring the output signal of the I / O sensor over time.

[0042] In an embodiment, the method further includes one or more of comparing the I / O profile and / or classification to family data of the semiconductor IC, detecting systematic trends based on the I / O profile and / or classification, and detecting outliers based on tester data.

[0043] In an embodiment, the method further includes comparing a time signal based on the output signal of the I / O sensor to a threshold value and identifying an exceptional or outlier reading from the I / O sensor based on the comparison.

[0044] In an embodiment, the method further includes counting the number of normal readings from the I / O sensors and / or the number of exceptional or outlier readings from the I / O sensors.

[0045] In some embodiments, a computer-readable medium may be considered to have stored thereon instructions for performing any of the method embodiments disclosed herein when the instructions are executed by a processor.

[0046] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the figures and by study of the following detailed description. Those skilled in the art will appreciate that combinations and subcombinations of specific features disclosed herein may also be provided, even if not explicitly set forth. [Brief explanation of the drawings]

[0047] Exemplary embodiments are illustrated in the referenced figures. Dimensions of components and features shown in the figures have generally been chosen for convenience and clarity of presentation and are not necessarily shown to scale. The figures are set forth below.

[0048] [Figure 1]FIG. 1 is a schematic diagram of a computerized system for detecting the integrity of an IC pad. [Figure 2] 1 illustrates a schematic of solder bumps for an example of an advanced heterogeneous packaging solution (2.5D IC package). [Figure 3] 1 illustrates a first embodiment of an input / output (I / O) block according to the present disclosure, including an I / O sensor. [Figure 4] 4 illustrates an exemplary implementation of an I / O sensor according to FIG. 3. [Figure 5] 1 shows an electrical schematic diagram of a second embodiment of an I / O block according to the present disclosure for measuring near-end bump degradation in a bidirectional communication channel. [Figure 6] 10 shows an electrical schematic diagram of a third embodiment of an I / O block according to the present disclosure for measuring far-end bump degradation on a bidirectional communication channel. [Figure 7] 10 shows an electrical schematic diagram of a fourth embodiment of an I / O block according to the present disclosure for measuring near-end bump degradation in a differential communication channel. [Figure 8] 10 shows an electrical schematic diagram of a fifth embodiment of an I / O block according to the present disclosure for measuring far-end bump degradation on a differential communication channel. [Figure 9] 10 shows an electrical schematic diagram of a sixth embodiment of an I / O block according to the present disclosure for implementing a termination resistor to measure near-end bump degradation on a bidirectional communication channel. [Figure 10] 10 shows an electrical schematic diagram of a seventh embodiment of an I / O block according to the present disclosure for implementing a termination resistor to measure far-end bump degradation on a bidirectional communication channel. [Figure 11] 4 illustrates a further exemplary implementation of an I / O sensor according to a variation of the embodiment shown in FIG. 3. [Figure 12] 1 shows a graph of measured near-end pulse duration. [Figure 13] 10 shows a graph of measured far-end pulse duration. [Figure 14] 1 shows a graph of eye width versus buffer strength. [Figure 15] 10 shows a graph of simulated near-end pulse width versus buffer strength. [Figure 16] An example of offline analysis of near-end and far-end integrity is shown, reflecting actual Si data. [Figure 17] An example reflecting actual Si data of the sensitivity of near-end integrity offline analysis to transmitter driver strength is shown. [Figure 18] An example reflecting actual Si data of weak pin (outlier) analysis is shown. [Figure 19A] An example of receiver performance distribution reflecting actual Si data is shown. [Figure 19B] An example of receiver performance distribution reflecting actual Si data is shown. [Figure 20] An example reflecting actual Si data of far-end signal analysis using the Embedded Virtual View (EVS) function is shown. [Figure 21A] An example reflecting real Si data of offline analysis and far-end correlation of eye opening is shown. [Figure 21B] An example reflecting real Si data of offline analysis and far-end correlation of eye opening is shown. [Figure 22] 1 shows a schematic block diagram of a firmware-based filter. DETAILED DESCRIPTION OF THE INVENTION

[0049] Disclosed herein are devices, systems, and methods for detecting input / output (I / O) integrity and / or degradation monitoring and / or optimizing the power / performance of bump arrays. Integrity and / or degradation can be identified by measuring the timing difference between a signal on a first path to or from an I / O buffer and a signal on a second path to or from the I / O buffer. For example, this can be achieved by comparing the measured timing or slope difference to an expected value based on calibration data, reference data, or historical data for the IC or I / O block. This allows for monitoring one or more of the following: bump resistor or micro-bump resistor integrity or degradation; near-end and / or far-end I / O buffer degradation; interconnect / interposer grading and integrity or degradation; bidirectional pin or bidirectional signal integrity or degradation; unidirectional pin or unidirectional signal integrity or degradation; differential pin or differential signal integrity or degradation; intermittent fault detection; and different degradation rate scenarios.

[0050] Additionally or alternatively, this may further enable I / O profiling and / or classification. Classification or profiling can be understood as the process of binning die into Si profiles. Each bin (profile) contains a cluster of IC design parameters, resulting in device-level parameters such as high-coverage parameters. During Pre-Si, IC design parameters and device processing parameters can be used as inputs for the profiling process. During Post-Si, sensor values ​​and / or specific high-coverage measurements can be used as inputs for the profiling process. In that context, a profile can be considered as a specific cluster of signature (data) values ​​and distributions that can be applied to field performance (specifications, defects, etc.). For example, a specific cluster of manufacturing space (data) values ​​and distributions that can be applied to field performance (specifications, defects, etc.).

[0051] I / O profiling and / or classification can be combined with IC family data, which can enable systematic shift detection and / or outlier detection based on tester data. For this purpose, on-chip I / O sensors can be provided. A family in this context can refer to a group of ICs classified as having common parameters with similar values. For example, a family can be a group of physical dies with the same Si profile / classification. Additionally, a family can include a group of Monte Carlo (MC) samples whose simulated IC design simulation values ​​and device processing simulation values ​​have the same Si profile / classification as the physical family members. Details of IC family classification are described in pending PCT Patent Application Publication No. WO2019 / 202595, filed April 16, 2019, entitled "Integrated Circuit Profiling and Anomaly Detection," the contents of which are incorporated herein by reference in their entirety.

[0052] In embodiments, this may allow for I / O power and / or performance optimization. For example, the power of each transmit (Tx) buffer may be adjusted based on desired or required performance, thereby optimizing power for the entire array.

[0053] In embodiments, I / O repair functionality may be provided. For example, this may include disabling a portion of all ICs. In another embodiment, it may include lane remapping. A further example includes adjusting transmit buffer strength (e.g., increasing transmit buffer strength if lane remapping or repair is not possible). Such repair functionality may be provided on the tester or in the field. Repair functionality may be based on I / O profiling and / or outlier detection processing. Further embodiments may provide I / O mission generation.

[0054] In embodiments, this may allow for optimization of I / O buffer (Tx) slew rates to control the amplitude of the current consumption rate per buffer (dI / dT) and optimization of the entire array due to EMI / RFI (electromagnetic or radio frequency interference), if desired and necessary.

[0055] The combination of on-chip I / O sensors and auxiliary hardware and / or software may be referred to as agents, and the effect of such agents may be one or more of power and / or frequency optimization and binning, in-field repair operations (such as lane repair or remapping as discussed above), I / O characterization, verification, and / or debug, and improved quality and reliability.

[0056] Examples according to the present disclosure may be applied to memory ICs, such as other memories based on high bandwidth memory (HBM) or dynamic random access memory (DRAM). Applications to other types of memories or other types of ICs are also possible.

[0057] Reference is now made to FIG. 1 , which schematically illustrates a computerized system 100 for detecting the integrity of an IC pad. The computerized system 100 includes an IC 150 with I / O sensors, such as 131, 132, and 133, each electrically connected to at least one I / O buffer (e.g., 141, 142, and 143) that measure timing delays between signals defined by at least one I / O buffer (e.g., 151, 152, and 153) connected to the IC pad. In the near-end case (the I / O buffer operates in Tx mode), the timing delays indicate I / O buffer loading and / or I / O buffer strength. In the far-end case (the I / O buffer operates in Rx mode), the timing delays indicate channel degradation and / or Tx buffer strength at the FE. In the NE case, the output of the I / O sensor may include a pulse, the duration of which may indicate a change in I / O buffer loading and / or a change in I / O buffer strength. In the case of the FE, the output of the I / O sensor may include a pulse, the length of which may indicate a change in channel performance and / or a change in the strength of the Tx buffer at the FE. The I / O sensor may provide an input to a time-to-digital converter (TDC, which may optionally form part of the I / O sensor) so that the output may include a digital time measurement.

[0058] The I / O sensor outputs may be communicated between the data interface 111 of the IC 150 and the data interface 110 of the computer 101A via a data network 140. The computer 101A includes one or more hardware processors 101B, a user interface 120, and a non-transitory computer-readable storage medium 102. Program code modules (102A, 102B, 102C, etc.) are encoded on the storage medium 102 and, when executed on the hardware processor 101B, perform operations of methods for measuring and / or controlling an IC as disclosed herein. Optionally, the I / O output signals are received by a processing component (not shown) on the IC that performs operations of the method. For example, the data receiver 102A receives the I / O output signal values. For example, the IC analyzer 102B analyzes the I / O output signal values ​​to, for example, determine the baseline operation of the IC during operation, detect bump failures, pad failures, significant failures, future failures, and similar anomalies, profile and classify the I / O buffer or IC, or tune the performance of the IC. The IC analyzer 102B may further provide platform-based analysis and warnings, for example, based on machine learning and / or data analysis. The IC repair function 102C can then mitigate predicted or actual failures by, for example, disabling portions of all ICs, remapping lanes within the IC, and adjusting transmit buffer strength within the IC. The optimizer 102D can perform parameter optimization to improve performance and / or adjust power.

[0059] Reference is now made to Figure 2, which illustrates the solder bumps of an example advanced heterogeneous packaging solution. Several different levels of solder joints are shown within the IC package and between the IC package, interposer, and circuit board. For example, an I / O buffer may drive pads soldered to microbumps that connect the IC to the interposer die. Thus, the interposer die is an example of 2.5D / 3D packaging technology.

[0060] For example, the I / O buffers can drive I / Os on flip-chip pads, such as controlled collapse chip connection (C4) bumps, connected to the pads. C4 bumps are an example of a generic packaging technology; in the general case, the present invention is applicable to any packaging technology, or any chip-to-chip packaging technology. In this example (Figure 2), two dies are connected to each other via microbumps and an interposer chip. This is a bidirectional I / O link between the transmitter (Tx) and receiver (Rx) at each end. Flip-chip C4 bumps are used to connect the package to the interposer die. A BGA connects the package to the board. As mentioned above, the I / O buffers can drive flip-chip bumps, but this is not shown in the example of Figure 2.

[0061] Optionally, the integrity of the electrical connection is detected through one or more solder connections of the electronic package and / or through circuitry (e.g., microbumps, through-silicon via bumps, C4 bumps, package bumps (e.g., BGA balls), and the like).

[0062] Reference is now made to FIG. 3 , which illustrates a first embodiment of an input / output (I / O) block according to the present disclosure, including an I / O sensor 200. The I / O sensor 200 is coupled in an I / O buffer configuration including a transmitter (Tx) buffer 210, a pseudo-differential receive (Rx) buffer 220, and a receiver (Rx) buffer 230. A transmit input 201 is provided as an input to the Tx buffer 210 and as a first input (via a first port) to the I / O sensor 220. The Tx buffer 210 then provides an output 215 to a communication channel. The communication channel also provides an input 225 to the differential Rx buffer 220 and the Rx buffer 230. The Rx buffer 230 provides an output 235 (via a second port) as a second input to the I / O sensor 200. The second input to the differential Rx buffer 220 is a reference voltage 223. The reference voltage 223 is set as a percentage of the IC supply voltage (Vcc), which in this case is 75% (although this value may be adjustable). The differential Rx buffer 220 then provides an output 228 based on the difference between the input 225 and the reference voltage 223. The output 228 of the differential Rx buffer 220 is provided as a third input to the I / O sensor 200 (via a third port). A differential Rx buffer enable signal 225 is provided to the differential Rx buffer 220 to enable differential Rx buffer operation, and an Rx buffer enable signal 235 is provided to the Rx buffer 230 to enable Rx buffer operation.

[0063] An I / O sensor control signal 205 is also provided to the I / O sensor. Based on the I / O sensor control signal 205 (which can assume one of two logic states), the output of the I / O sensor is based on either the first input (transmit input 201) and the third input (output 228 of the differential Rx buffer 220), or the second input (output 235 of the Rx buffer 230) and the third input (output 228 of the differential Rx buffer 220). In other words, the I / O sensor generates an output based on the third input and either the first input or the second input. The I / O sensor then generates an output Po 240, which depends on the timing difference between the signal edges (typically rising edges), although it is also possible to operate on the falling edge or both the falling and rising edges of the respective signals for each of the two inputs being used. As discussed further below, the timing difference between the two signals advantageously corresponds to the I / O buffer loading. In certain embodiments, the output Po 240 is generated as a pulse having a width indicative of the timing (e.g., slope) difference. The output Po 240 may be provided to a TDC (as discussed above) to provide a digital output indicative of the pulse width.

[0064] As discussed further below, this output may enable monitoring of bump degradation, or more generally, monitoring of one or more bump arrays. I / O sensor 200 may be embedded (or integrated) specifically within an I / O block, allowing this measurement to be controlled on-die. Furthermore, data may be collected during functional operation. This data may be uploaded to an analysis platform (e.g., operable on computer 101A of FIG. 1). Using this monitoring data, analysis may be performed (either online or offline). This may be performed without interfering with the functional operation of the IC or system, and without the need for special test modes or stopping IC operation.

[0065] Reference is now made to Figure 4, which shows an exemplary implementation of an I / O sensor according to Figure 3. Here, the effect of the I / O sensor control signal in selecting either the transmit input 201 or the output 235 of the Rx buffer 230 can be seen. An exemplary digital circuit is shown for generating a pulse with a width that depends on the timing difference between the rising edges of the signals being compared. However, those skilled in the art will understand that this can be implemented in other ways.

[0066] Generally, an input / output (I / O) block of a semiconductor integrated circuit (IC) may be considered, which may include at least one I / O buffer configured to define at least one signal path (particularly first and second different signal paths) for connection to a remote I / O block via a communication channel, each signal path causing a respective signal edge slope, and an I / O sensor coupled to the at least one signal path (particularly the first and second signal paths) and configured to generate an output signal indicative of a timing difference between a signal edge (slope) of the first signal path and a signal edge (slope) of the second signal path.

[0067] A semiconductor IC including an I / O block is also contemplated. The I / O sensor may then be configured to communicate its output signal externally to the IC, for example, using a communication interface or a network port. An I / O profiling unit configured to generate an I / O profile and / or classification based on the output signal of the I / O sensor may also be provided. While some or all of the post-processing may be performed on the IC, in other embodiments, all of the post-processing may be performed on a separate platform. In embodiments, at least one signal path (e.g., a first signal path) is coupled to a remote I / O block via at least one connection bump, and the I / O profile and / or classification may be based on monitoring the output signal of the I / O sensor over time. Preferably, multiple bumps (a bump array) may be monitored in this manner. The I / O profile and / or classification may be compared to family data for the semiconductor IC, used to detect systematic shifts based on the I / O profile and / or classification, and / or used to detect outliers based on tester data.

[0068] In an embodiment, the I / O sensor comprises a first input port coupled to a first option of the first signal path, a second input port coupled to a second option for the first signal path, a third input port coupled to the second signal path, and a selector configured to select the first or second input port in response to a received selection signal such that the output signal of the I / O sensor selectively indicates a timing difference between a signal edge slope of the second signal path and a signal edge slope of either the first option of the first signal path or the second option of the first signal path. For example, the I / O block may further include a differential buffer configured to output a difference between a first signal (differential buffer input signal) received on a signal path coupled to the communication channel and a second fixed-level signal. The third input port is then preferably coupled to the output of the pseudo-differential buffer. The second fixed-level signal may be preset or dynamically adjustable and / or advantageously be a fixed voltage at a predetermined percentage of the DC power supply voltage of the IC. For example, the predetermined percentage may be greater than 50% and / or less than 100%, more preferably greater than 60% and less than 90%, and most preferably approximately 75%. The at least one I / O buffer may include one or both of a transmit buffer, having a first input port coupled to an output of the transmit buffer that is coupled to the communication channel, and a receive buffer, having an input coupled to the communication channel, and a second input port coupled to an output of the receive buffer.

[0069] Reference is now made to Figure 5, which shows the electronic circuitry of a second embodiment of an I / O block according to the present disclosure for measuring near-end (NE) bump degradation in a bidirectional communication channel. In other words, this is for sensing the integrity of the NE signal. The communication channel is represented by the pad capacitance (Cpad), μ-bump resistance (Rubump), and the interposer.

[0070] As shown, the I / O sensor control signal 205 is set to logic "1" (e.g., according to the embodiment of FIG. 4). Doing so causes the I / O sensor 200 to generate a pulse at the output Po 240 with a width that is directly proportional to the differential delay between the transmit input 201 (Tx_in) and the output 228 (Rx-diff_in) of the pseudo-differential Rx buffer 220. The differential delay from Tx_in to Rx-diff_in represents the delay between the signal edge at the transmit input 201 and the signal edge at the output 228 of the pseudo-differential Rx buffer 220 (the sum of the delay of the Tx buffer 210 and the delay of the Tx buffer 210 relative to the pseudo-differential Rx buffer 220). This delay is directly proportional to the effective buffer load. A change in the effective buffer load changes the slope of the Tx buffer output signal 215, affecting the pulse width at the output Po 240. For example, if the NEμ bump resistance increases, the effective buffer loading decreases, reducing the slope of the Tx buffer output signal 215 and therefore the width of the pulse at output Po 240. The pulse width of the signal at output Po 240 is measured by the TDC. The TDC generates a digital readout representing the pulse width. If there is a change in the pulse width, the TDC readout changes, indicating a change in the measured NEμ performance.

[0071] This approach can be useful for sensing receive and / or transmit delays over the lifetime of an IC, thereby detecting aging of the μ-bump resistor and / or detecting intermittent μ-bump disconnection.

[0072] Additionally or alternatively, this approach may be useful for scanning the reference voltage (VREF) of the Rx buffer 230, for example, to characterize or measure the slew rate at the pad (Tx buffer output). This may be used to detect and limit EMI / RFI phenomena caused by the amplitude dI / dT of the buffer's current consumption rate, as discussed further below.

[0073] In an embodiment, the second signal may be generated by a CMOS-based receive buffer having an input coupled to the communication channel. In doing so, the I / O sensor 200 generates a pulse at output Po 240 having a width that is directly proportional to the delay difference between the transmit input 201 (Tx_in) and the output of the CMOS-based Rx buffer. The Tx_in to Rx out delay difference in this case represents the loop delay (the sum of the delay of the Tx buffer 210 and the delay of the CMOS-based Rx buffer) between the signal edge at the transmit input 201 and the signal edge at the output of the CMOS-based Rx buffer. This delay is also directly proportional to the effective buffer load.

[0074] Reference is now made to FIG. 6, which illustrates the electronic circuitry of a third embodiment of an I / O block according to the present disclosure for measuring far-end (FE) bump degradation in a bidirectional communication channel. Here, the I / O sensor control signal 205 is set to logic “0” (e.g., according to the embodiment of FIG. 4). In this manner, the I / O sensor 200 generates a pulse at output Po 240 with a width that is directly proportional to the delay difference between the output 235 (Rx_in) of the Rx buffer 230 and the output 228 (Rx-diff_in) of the pseudo-differential Rx buffer 220. The delay from Rx_in to Rx-diff_in represents the timing difference (delay) between the signal edge at output 235 of the Rx buffer 230 and the signal edge at output 228 of the differential Rx buffer 220. This delay difference is directly proportional to the input slope (pad signal) of the Rx buffer 230. Any change in the input slope of the Rx buffer 230 affects the pulse width at output Po 240. For example, as the FEµ bump resistance increases, the slope of Rx_in increases, and the width of the pulse at output Po 240 also increases. The pulse width of the signal at output Po 240 is measured by the TDC. The TDC generates a digital readout representing the pulse width. If there is a change in the pulse width, the TDC readout changes, indicating a change in the measured FEµ performance.

[0075] The above discusses an embodiment in which the I / O buffer is configured for a bidirectional interface on the communication channel. However, measurements of unidirectional communication are also possible. Unidirectional signals are NE-only or FE-only signals. The same I / O sensor 220 is used with a fixed configuration of the I / O sensor control signal 205. According to the embodiment of FIG. 4, sensing only the integrity of the near-end (NE) signal is implemented by setting the I / O sensor control signal 205 to logic "1." Sensing only the integrity of the far-end (FE) signal is implemented by setting the I / O sensor control signal 205 to logic "0."

[0076] Returning to the general terms discussed above, further optional features and / or details of generalized implementations may be considered. For example, the at least one I / O buffer may include a transmit buffer. Then, at least one signal path (e.g., a first signal path) may be coupled to an output of the transmit buffer coupled to the communication channel. Optionally, the at least one signal path (e.g., the first signal path) is further coupled to a remote I / O block via at least one connection bump. Then, the output signal of the I / O sensor may further indicate the quality of the at least one connection bump. In an embodiment, the at least one signal path (e.g., a second signal path) is coupled to an input of the transmit buffer. Then, the first signal path is coupled to the remote I / O block via an interconnect and a connection bump between the transmit buffer and the interconnect. In this case, the output signal of the I / O sensor may further indicate the quality of the connection bump.

[0077] Preferably, the I / O block further includes a pseudo-differential buffer configured to output a difference between a differential buffer input signal received on a signal path coupled to the communication channel and a fixed level signal, and at least one signal path (e.g., a second signal path) is coupled to the output of the differential buffer. The pseudo-differential buffer may be considered as described above. In this manner, the I / O sensor output may represent a time difference between the first signal path and the output of the differential buffer.

[0078] In such an embodiment (where at least one signal path, such as the second signal path, is coupled to the output of the differential buffer), two options may be considered. In the first option (as discussed above), another signal path of the at least one signal path (such as the first signal path) is coupled to an input of a transmit buffer, which is coupled to a communication channel (and thus typically coupled to a remote I / O block via at least one connection bump). In the second option, the at least one I / O buffer includes a receive buffer having an input coupled to the communication channel. Then, another signal path of the at least one signal path (such as the first signal path) is coupled to an output of the receive buffer. The input to the receive buffer is optionally coupled to the remote I / O block via an interconnect and a connection bump between the interconnect and the remote I / O block. The output signal of the I / O sensor may then further indicate the quality of the connection bump.

[0079] In an embodiment, the I / O buffer can use differential signals across the communication channel. Reference is now made to FIG. 7, which shows the electronic circuitry of a fourth embodiment of an I / O block according to the present disclosure for measuring near-end bump degradation in a differential communication channel. The transmit buffer 301 generates two differential outputs: a first output 310 (outp) and a second output 320 (outn). In this case, sensing the integrity of the near-end (NE) differential signal is performed by setting the I / O sensor control signal 205 to a logic "1." The I / O sensor 220 generates a pulse at output Po 240 with a width that is directly proportional to the delay difference between the first output 310 via the first receive buffer (Rx_CMOS) 315 (provided at Tx_in, or the cp port of the I / O sensor 220) and the second output 320 via the second receive buffer (Rx_CMOS) 325 (provided at Rx-diff_in, or the cn port of the I / O sensor 220). The delay difference from Tx_in to Rx-diff_in is directly proportional to the mismatch between the effective loads of the first differential buffer output 310 (outp) and the second differential buffer output 320 (outn). Any change in the mismatch between these two effective loads affects the pulse width at output Po 240. For example, if the resistance of the NE μ-bump connected to the first output 310 (outp) increases, the effective load at the first output 310 (outp) decreases relative to the effective load at the second output 320 (outn), thereby changing the pulse width at output Po 240. The pulse width of the signal at Po is measured by a TDC. The TDC generates a digital readout representing the pulse width. Any change in pulse width causes the TDC readout to change, indicating a change in the measured NE differential μ-bump performance.

[0080] Reference is now made to FIG. 8 , which illustrates the electronic circuitry of a fifth embodiment of an I / O block according to the present disclosure for measuring far-end bump degradation in a differential communication channel. Far-end (FE) differential signal integrity sensing is performed by setting the I / O sensor control signal 205 to logic “1.” Two differential inputs, a first input 311 (padp) and a second input 321 (padn), are provided from the remote end via the communication channel. The I / O sensor 200 generates a pulse at output Po 240 with a width that is directly proportional to the delay difference between the first input 311 (Tx_in or cp) and the second input 321 (Rx-diff_in or cn). The delay difference from Tx_in to Rx-diff_in is directly proportional to the mismatch between the signal slopes of the first differential buffer input 311 (padp) and the second differential buffer input 321 (padn). Any change in the mismatch between the signal slope at the first differential buffer input 311 and the signal slope at the second differential buffer input 321 will affect the pulse width at the output Po240. For example, if the resistance of the FE μ-bump connected to the first differential buffer input 311 (padp) increases, the signal slope at the first differential buffer input 311 (padp) will increase relative to the signal slope at the second differential buffer input 321 (padn). This will change the pulse width at the output Po240. The pulse width of the signal at the output Po240 is measured by a TDC. The TDC generates a digital readout representing the pulse width. If there is a change in the pulse width, the TDC readout will change, indicating a change in the measured NE differential μ-bump performance.

[0081] Referring back to the generalized terms discussed above, in an embodiment, the communication channel is configured to transmit a differential signal over two signal lines. The first signal path may then be coupled to the first signal line, and the second signal path may be coupled to the second signal line. In such a case, the at least one I / O buffer may include a transmit buffer configured to provide a differential output over the two signal lines. The first signal path may then be coupled to a first output of the transmit buffer coupled to the first signal line, and the second signal path may be coupled to a second output of the transmit buffer coupled to the second signal line. In an embodiment, the first signal line includes a first interconnect coupled to the transmit buffer via a first near-end connection bump, and the second signal line includes a second interconnect coupled to the transmit buffer via a second near-end connection bump. The output signal of the I / O sensor may then further indicate the quality of the first and second near-end connection bumps. In an embodiment, the first signal line includes a first interconnect coupled to the remote I / O block via a first far-end connection bump, and the second signal line includes a second interconnect coupled to the remote I / O block via a second far-end connection bump. The output signal of the I / O sensor may then further indicate the quality of the first and second far-end connection bumps.

[0082] Characterization and / or validation can be based on several characteristics. For NE performance, power / performance optimization (e.g., by characterizing NE driver strength) and / or neighbor pin detection for lane repair can be used. For FE performance, one or more eye pattern parameters may be considered, such as per-pin eye width opening, per-pin eye height opening, and per-pin eye width jitter (min-max). FE neighbor pin detection can also be performed by considering one or more of the following: weak pin detection for lane repair, systematic issues due to design or manufacturing, and outlier detection based on large sample data.

[0083] The implementation described above is ideal for measuring and / or analyzing memory ICs without termination, such as HBM2. However, newer memory designs, such as HBM3, include termination, using pseudo-aperture drain drivers, for example. As a result, low logic levels can be higher than 0V. Therefore, CMOS-based Rx buffers are not used in such IC designs. I / O sensors in the I / O block can take advantage of this design to perform alternative FE measurements and / or analysis.

[0084] Reference is now made to FIG. 9, which illustrates the electronic circuitry of a sixth embodiment of an I / O block according to the present disclosure implementing a termination resistor for measuring near-end bump degradation in a bidirectional communication channel. This embodiment includes a transmit input 201, a NE Tx buffer 501, a NE differential Rx buffer 515, and a FE Rx buffer 530. An additional termination resistor 535 is shown on the FE Rx buffer 530 side. The I / O agent (sensor) 500 operates similarly to the I / O agent 200 described above with reference to FIG. 5. The I / O sensor 500 generates an output Po 540 that depends on the timing difference between the signal edges of the respective signals at each of the two inputs being used (the input to the NE Tx buffer 501 and the input from the output of the NE differential Rx buffer 515). This output is provided to a TDC (not shown).

[0085] Reference is now made to FIG. 10 , which illustrates an electronic circuit of a seventh embodiment of an I / O block according to the present disclosure, implementing termination resistors for measuring far-end bump degradation in a bidirectional communication channel. In this case, the near-end of the I / O sensor 500 functions as a receiver. Additional termination resistors 525 are shown at the NE Tx buffer 501 and NE differential Rx buffer 515 sides. The I / O sensor 500 measures the eye pattern at VREF, specifically two eyes: rising-to-falling and falling-to-rising. In particular, the eye width and / or eye height of each eye pattern can be measured directly. The I / O sensor 500 generates an output Po 540 indicative of the measured eye pattern parameters (e.g., by pulse width). Again, the output 540 is provided to a TDC (not shown).

[0086] Reference is made to FIG. 11, which illustrates a further exemplary implementation of the I / O sensor 500 as shown in FIGS. 9 and 10. The I / O sensor 500 is therefore provided with two inputs: an input to a Tx buffer 501 and an output from a differential Rx buffer 515. The differential Rx buffer 515 also has an enable signal (En_Rx_Diff). The I / O sensor 500 can measure the timing difference between the signals on the two input paths (for NE performance) and / or eye pattern parameters of the input provided by the output of the differential Rx buffer (for FE performance). The eye pattern parameters can be one or more of eye width jitter and eye height. The output signal 540 illustrates the measured parameters. Performance can be characterized with respect to driver strength and / or VREF (particularly for FE performance).

[0087] In a general sense, an input / output (I / O) block of a semiconductor integrated circuit (IC) may be considered, the I / O block including at least one I / O buffer configured to define at least one signal path (each signal path incurs a respective signal edge slope) for connection to a remote I / O block via a communication channel, and an I / O sensor coupled to the at least one signal path (e.g., the first and / or second signal path) and configured to generate an output signal indicative of eye pattern parameters of the at least one signal path. The eye pattern parameters may include one or more of eye width, eye height, eye width jitter, and eye height variation. This may be combined with any other aspect, embodiment, or feature disclosed herein and may be extended to any other embodiment (e.g., an embodiment using a differential communication channel).

[0088] Reference is now made to FIG. 12, which shows a graph of measured near-end pulse duration versus NE μ-bump resistance and FE eye width (EW). In this case, the x-axis represents far-end EW, the y-axis represents changes in pulse width, and the points on the graph represent near-end μ-bump resistance from 0 to 100 ohms. Different curves show results at different Tx buffer 210 strengths. Reference is now made to FIG. 13, which shows a graph of measured far-end pulse duration, where the x-axis represents FE μ-bump resistance and the y-axis represents pulse width. As can be seen from FIGS. 12 and 13, the approach of the present disclosure enables monitoring of functional bumps coupling I / Os of ICs, thereby enabling aging degradation to be detected, analyzed, and, in embodiments, mitigated.

[0089] The output of the I / O sensors can be used for a variety of purposes, including monitoring the NE pins, where the NE pulse width measured per pin is analyzed over time; monitoring the FE pins, where the FE pulse width measured per pin is analyzed over time; monitoring and / or data processing; changing buffer drive strength; disabling part or all of the IC; and initiating lane repair functions on adjacent pins. Some of these may be considered I / O repair functions and may be implemented as part of initial on-test and / or in-field.

[0090] For example, a software-based "lane repair" or "lane remapping" mechanism may replace a faulty lane (e.g., a data path) with a spare lane. Lane remapping may be done by writing a register (soft) or cutting an eFuse (hard). Lane repair and power optimization may work together. For example, if all redundant pins are used (due to lane repair and / or remapping), Tx buffer strength can be increased to allow continued operation and increase the time until offline repair is possible.

[0091] In particular, the output of the I / O sensors may be used to monitor the bump array and / or measure (and monitor) the degradation of multiple pins during functional operation. This is beneficially performed without interfering with the functional operation of the system. The measurements may be advantageously controlled on-die. Data may be collected during functional operation and uploaded to an analysis platform (as discussed above). This may enable online and / or offline analysis of the measurement data, for example, by machine learning algorithms (or other data analysis techniques) on the analysis platform. The analysis platform may use other data, such as instantaneous temperature and / or voltage, for the analysis. In particular, no special test modes or IC shutdowns are required.

[0092] In an embodiment, the I / O block comprises a time-to-digital converter configured to receive timing signals derived from the output signals of the I / O sensors (which may optionally include the output signals of the I / O sensors themselves) and provide a digital time signal based on the timing signals.

[0093] In another embodiment, the output of the I / O sensor may be used to determine and / or characterize the signal amplitude and / or signal slew rate at the pin. This functionality may enable an Embedded Virtual View (EVS) function that may be applied per pin of the IC. The EVS functionality is discussed with reference to Figures 19-21 described below.

[0094] Reference is now made to FIG. 14, which shows a graph of eye width versus buffer strength, and FIG. 15, which shows a graph of simulated near-end pulse width versus buffer strength. Existing I / O buffer designs may use excessive drive strength. The disclosed techniques may enable optimization of drive strength. For example, it may be understood that eye width is proportional to signal quality, and pulse width correlates to eye width. Therefore, it may be possible to measure pulse width at different buffer strengths and correlate this with pin-measured bit error rates (BERs), if possible. The data may be further correlated to process corners based on family information and / or history. Channel characteristics may then be extracted and used to distinguish between good performance and poor performance (which requires repair). An optimal buffer strength may then be set. This can be monitored (and alerts provided, if necessary) throughout the lifetime of the IC.

[0095] Reference is now made to Figures 16-21, which illustrate example analyses reflecting actual Si data. The term "integrity insight" used in the descriptions of these figures refers to offline analysis of measured pulse durations, whether near-end or far-end, respectively. The presented example analyses were performed by an IC analyzer (equivalent to IC analyzer 102B in Figure 1) that provides platform-based analysis and alerts, for example, based on machine learning and / or data analysis.

[0096] Refer to FIG. 16, which shows near-end integrity insight 401 and far-end integrity insight 402 for four I / O blocks. Each block consists of 46 active pins. The plot shows the distribution of near-end and far-end integrity insights. Referring to near-end integrity insight 401, the plot shows the near-end transmit (Tx) drive map per group and per pin within a group. Weak groups (W) and strong groups (S) can be observed. By equalizing the drive map (per group or per pin), total I / O power can be optimized. In this example, equalizing the driver strength of the strong group (S) with the weak group (W) can save power. The plot also shows observations of outlier pin 403, which is a pin with near-end insight values ​​that are at the tail of the distribution. Referring to far-end integrity insight 402, the plot shows the received performance (Rx performance) map. With far-end insight, greater variation can be observed for certain blocks. This is a result of data-dependent intersymbol interference (ISI).

[0097] Referring now to Figure 17, there is shown the average sensitivity of near-end integrity insight to driver strength for Block X and Block Y. The sensitivity of near-end insight is approximately 0.5 LSB. The absolute value is also observed.

[0098] Reference is now made to Figure 18, which shows an analysis of weak pins (outliers) on an actual chip. The behavior of the weak pins is compared statistically and electrically to the behavior of normal pins, both of which identify outliers.

[0099] 19A-19B, a distribution of Rx performance insight data from an actual chip is shown. The Rx performance insight is a measurement of the slew rate (units: ps / V) of the received signal at the pin. The sensitivity of the measurement is equal to 1-LSB / 50mV, giving 1-LSB as 10ps.

[0100] Reference is now made to FIG. 20, which illustrates far-end signal analysis using the Embedded Virtual View (EVS) feature. This plot provides insight into the far-end integrity of a real chip. Aberrant values ​​caused by low-amplitude received signals at the pins may be observed. The received signal amplitude can be measured by lowering VREF to the point where the aberrant values ​​are eliminated. At this point, the received signal amplitude becomes equal to the VREF value. The resolution of VREF is determined by design. Therefore, such aberrant or exceptional values ​​may affect the analysis and VREF setting. This effect can be corrected as discussed below.

[0101] 21A-21B, the correlation between far-end insight and eye opening is shown. A linear correlation is observed.

[0102] As mentioned above, aberrant or exceptional values ​​can affect the analysis. For example, FE sensitivity can be limited by the detectability of lone bits. This effect can be particularly noticeable when looking at eye pattern measurements such as eye width and / or eye height. Removing exceptional readings caused by lone bits can allow for an increase in VREF and improved FE sensitivity. Many exceptional readings in a particular data pattern can affect average performance values ​​and shift calculated statistics, such as the average. This can impact the ability to detect aging degradation. This effect can be seen at high transfer rates, such as 3.2 GT / s. Advantageously, such exceptional readings can be filtered from the results, especially in post-TDC sums. This can reduce the impact of mean shifts and / or improve detection of mean changes over lifetime operation.

[0103] Reference is now made to Figure 22, which shows a schematic block diagram of a firmware-based filter. Such a filter may be used as part of the read summation, particularly the post-TDC summation, as discussed above. The input to the filter is provided by a TDC 400, which provides a digital output 410. The filter comprises a comparator (CMP) 420, a summation block 430, an exception read counter 450, and a normal read counter 460.

[0104] Comparator 420 has a first input that includes a threshold level 425. The digital output 410 of TDC 400 is provided as a second input to comparator 420. When the TDC output exceeds threshold level 425, a high logic level output is provided to exception read counter 450. This high logic level is also provided as an enable signal 440 to summing block 430. Summing block 430 also receives digital output 410 of TDC 400 as an input and provides its output, along with feedback, to normal read counter 460. In this manner, counts of both normal reads and exceptional (outlier) reads may be obtained.

[0105] As part of the test phase, the system can be operated at a low frequency and the average PW measured. At low frequency operation, no exceptional readings are expected. As part of the data analysis, thresholds can be determined (calculated) on the platform and then downloaded to the IC. The thresholds can be fused to the IC or downloaded with each system activation. A less preferred approach is to determine the thresholds based on simulation and hard-code them into the IC.

[0106] Multiple types of outliers may occur. For example, there may be separate outliers for CMOS VREF and for differential comparator VREF. These may be accounted for by using multiple thresholds.

[0107] In a general sense, a filtered counter block may be considered as a filtered counter block (e.g., firmware on an IC) configured to receive a time signal (e.g., via a TDC) based on an output signal of an I / O sensor, compare the received time signal to a threshold, and identify exceptional or outlier readings from the I / O sensor based on the comparison. The filtered counter block may be further configured to count the number of normal readings from the I / O sensor and / or the number of exceptional or outlier readings from the I / O sensor. The threshold may be received from a platform external to the IC and / or may be dynamically updated, for example, upon initialization of the IC. A method for monitoring an I / O block on an IC may include comparing a time signal based on the output signal of the I / O sensor to a threshold and identifying exceptional or outlier readings from the I / O sensor based on the comparison. Advantageously, the method may also include counting the number of normal readings from the I / O sensor and / or the number of exceptional or outlier readings from the I / O sensor.

[0108] Additional benefits can be gained by detecting logic path and through-silicon-via (TSV) delay degradation at Phy inputs, detecting thermal stress, measuring I / O missions per pin and correlating with pin performance degradation, generating I / O families, detecting outliers, identifying systematic shifts, and detecting or distinguishing between different degradation mechanisms. Mission profiling can be an online process using all information available on the platform and any additional information that can be collected (e.g., customer, design, version control, etc.). With appropriate analysis, a complete graph can be generated to facilitate guardbanding for different applications and thus optimize the use of material data. For example, systematic shifts can be identifiable as unexpected parametric shifts in test conditions.

[0109] Throughout this application, various embodiments of the present invention may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the present invention. Thus, the description of a range should be considered to specifically disclose not only each individual numerical value within that range, but also all possible subranges. For example, description of a range such as 1 to 6 should be considered to specifically disclose subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as each individual number within that range, e.g., 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0110] Whenever a numerical range is given herein, it is meant to include any recited number (fractional or integer) within the stated range. The phrases "ranging between" a first designator number "and" a second designator number, and "ranging from" a first designator number "to" a second designator number, are used interchangeably herein and are meant to include the first and second designator numbers and all fractional and integer numbers therebetween.

[0111] In the description and claims of this application, the words "comprise," "include," and "have," and their forms, do not necessarily limit the elements in the list with which the word may be associated. Furthermore, in the event of a conflict between this application and any document incorporated by reference, it is hereby intended that this application control.

[0112] It should be noted that the use of words such as common nouns, proper nouns, named nouns, etc. for clarity of reference in this disclosure is not intended to suggest that embodiments of the invention are limited to a single embodiment, and that while many configurations of disclosed components may be used to describe some embodiments of the invention, other configurations may be derived from these embodiments in different configurations.

[0113] In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. Of course, it should be understood that the development of any such actual implementation will require many implementation-specific decisions to be made in order to achieve the particular goals of the developer, such as compliance with application- and business-related constraints, and that these particular goals will vary from implementation to implementation and developer to developer. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

[0114] It is expected that those skilled in the art will be able to easily practice the present invention based on the teachings of the present disclosure. The description of the various embodiments provided herein is believed to provide sufficient insight and detail into the present invention to enable those skilled in the art to practice the present invention. Furthermore, it is specifically contemplated that the various features and embodiments of the present invention described above can be used alone as well as in various combinations.

[0115] Conventional and / or modern circuit design and layout tools may be used to implement the present invention. The specific embodiments described herein, particularly the various thicknesses and compositions of the various layers, are illustrative of example embodiments and should not be considered to limit the present invention to the selection of such specific implementations. Thus, multiple instances of components described herein as a single instance may be provided.

[0116] While circuits and physical structures have been generally inferred, it is well recognized in modern semiconductor design and manufacturing that physical structures and circuits may be embodied in a computer-readable descriptive form suitable for use in subsequent design, test, or manufacturing stages and the resulting manufactured semiconductor integrated circuits. Accordingly, claims directed to conventional circuits or structures may, consistent with their specific language, read computer-readable encodings (sometimes called programs) and representations thereof, whether embodied in a medium or combined with a suitable reading mechanism, to enable the manufacture, testing, or design improvement of the corresponding circuits and / or structures. Structures and functions presented as separate components in exemplary configurations may be implemented as combined structures or components. The present invention is intended to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all of which are described herein and defined in the appended claims. As used herein, computer-readable media includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory card, ROM), or electronic media, as well as network, wired, wireless, or other communications media.

[0117] The foregoing detailed description describes only a few of the many possible implementations of the present invention. For this reason, this detailed description is intended to be illustrative rather than limiting. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope and spirit of the present invention. It is only the following claims, including all equivalents, that are intended to define the scope of the present invention. In particular, while the preferred embodiment is described in the context of a memory IC, it is believed that the teachings of the present invention may be advantageously used with other types of semiconductor ICs that employ I / O circuitry. Moreover, the techniques described herein may be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may be included within the scope of the present invention as defined by the following claims.

[0118] While one or more interposers are discussed above, it will be understood that other types of interconnects are possible, such as interconnect bridges, one such bridge being the Embedded Multi-Die Interconnect Bridge (EMIB) sold by Intel Corporation.

[0119] Embodiments of the present invention may be used to manufacture, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0120] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0121] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of an instruction, which contains executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a specific-purpose hardware and computer instruction combination.

[0122] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A computer-readable storage medium storing an encoding of an input / output (I / O) block of a semiconductor integrated circuit (IC), the encoding of the I / O block comprising: an encoding of an I / O buffer configured to define a plurality of signal paths for connection to a remote I / O block over a bidirectional communication channel, each signal path incurring a respective signal edge slope; an encoding of an I / O sensor coupled to the plurality of signal paths; and (a) a timing difference between a signal edge slope for a first signal path of the plurality of signal paths and a signal edge slope for a second signal path of the plurality of signal paths that is different from the first signal path; and / or (b) eye pattern parameters for one or more of the plurality of signal paths; an encoding of the I / O sensor configured to generate an output signal indicative of 1. A computer-readable storage medium comprising:

2. 2. The computer-readable storage medium of claim 1, wherein the I / O buffer comprises a transmit buffer, and the first signal path is coupled to an output of the transmit buffer that is coupled to the communication channel.

3. 3. The computer-readable storage medium of claim 2, wherein the first signal path is further coupled to the remote I / O block via a first connection bump, and the output signal of the I / O sensor further indicates a quality of the first connection bump.

4. 4. The computer-readable storage medium of claim 3, wherein the plurality of signal paths comprises a third signal path and a fourth signal path coupled to the remote I / O block via second connection bumps, and the I / O sensor is coupled to the third signal path and / or the fourth signal path and is configured to generate an output signal further indicative of one or both of a timing difference between a signal edge for the third signal path and a signal edge for the fourth signal path and an eye pattern parameter for the third signal path and / or the fourth signal path, the timing difference being indicative of quality of the first connection bump and the second connection bump.

5. 5. The computer-readable storage medium of claim 3, wherein the plurality of signal paths comprises a signal path coupled to an input of the transmit buffer and / or a signal path coupled to the remote I / O block via an interconnect and a connection bump between the transmit buffer and the interconnect, and the output signal of the I / O sensor further indicates a quality of the first connection bump.

6. The encoding of the I / O block comprises:

1. An encoding of a differential buffer configured to output a difference between a differential buffer input signal received on a path coupled to the communication channel and a fixed level signal, wherein a signal path of the plurality of signal paths is coupled to an output of the differential buffer. The computer-readable storage medium of any one of claims 1 to 5, further comprising:

7. 7. The computer-readable storage medium of claim 6, wherein the fixed level signal is a voltage fixed at a predetermined percentage of a DC power supply voltage to the IC, and optionally, the predetermined percentage is dynamically adjusted and / or the predetermined percentage is 75%.

8. 8. The computer-readable storage medium of claim 1, wherein the I / O buffer comprises a receive buffer having an input coupled to the communication channel, and a signal path of the plurality of signal paths is coupled to an output of the receive buffer.

9. 9. The computer-readable storage medium of claim 8, wherein an input to the receive buffer is coupled to the remote I / O block via an interconnect and a connection bump between the interconnect and the remote I / O block, and wherein the I / O sensor output signal further indicates a quality of the connection bump.

10. 10. The computer-readable storage medium of claim 1, wherein the communication channel is configured to transmit a differential signal over two signal lines, a first signal path of the plurality of signal paths being coupled to a first signal line, and a second signal path of the plurality of signal paths being coupled to a second signal line.

11. 11. The computer-readable storage medium of claim 10, wherein the I / O buffer comprises a transmit buffer configured to provide a differential output over the two signal lines, the first signal path being coupled to a first output of the transmit buffer coupled to the first signal line, and the second signal path being coupled to a second output of the transmit buffer coupled to the second signal line.

12. 12. The computer-readable storage medium of claim 11, wherein the first signal line comprises a first interconnect coupled to the transmit buffer via a first near-end connection bump, the second signal line comprises a second interconnect coupled to the transmit buffer via a second near-end connection bump, and the I / O sensor output signal further indicates quality of the first near-end connection bump and the second near-end connection bump.

13. 13. The computer-readable storage medium of claim 10, wherein the first signal line comprises a first interconnection coupled to the remote I / O block via a first far-end connection bump, the second signal line comprises a second interconnection coupled to the remote I / O block via a second far-end connection bump, and the output signal of the I / O sensor further indicates quality of the first far-end connection bump and the second far-end connection bump.

14. The I / O sensor a first input port coupled to a first option for a first signal path; a second input port coupled to a second option for the first signal path; a third input port coupled to the second signal path; and a selector configured to select the first input port or the second input port in response to a received selection signal such that an output signal of the I / O sensor selectively indicates a timing difference between a signal edge for the second signal path and a signal edge for either a first option for the first signal path or a second option for the first signal path; The computer-readable storage medium of any one of claims 1 to 13, comprising:

15. 15. The computer-readable storage medium of claim 14, wherein the I / O block further comprises a differential buffer configured to output a difference between a first signal received on a signal path coupled to the communication channel and a second fixed level signal, and wherein the third input port is coupled to an output of the differential buffer.

16. The I / O buffer a transmit buffer, the first input port coupled to an output of the transmit buffer coupled to the communication channel; a receive buffer having an input coupled to the communication channel, the second input port being coupled to an output of the receive buffer; 16. The computer-readable storage medium of claim 14 or claim 15, comprising one or both of:

17. 17. The computer-readable storage medium of claim 1, wherein the eye pattern parameters comprise one or more of eye width, eye height, eye width jitter, and eye height variation.

18. 18. The computer-readable storage medium of claim 1, wherein the output signal comprises a pulse having a width indicative of a timing difference between a signal edge on the first signal path and a signal edge on the second signal path, or the eye pattern parameter.

19. The encoding of the I / O block: a performance optimizer configured to adjust parameters of the I / O buffer based on the output signal of the I / O sensor; The computer-readable storage medium of any one of claims 1 to 18, further comprising:

20. 20. The computer-readable storage medium of claim 1, wherein the I / O block further comprises a repair controller configured to adjust a configuration of the I / O buffer based on an output signal of the I / O sensor, the repair controller configured to do one or more of: disable part or all of the IC, cause lane remapping of at least a portion of the IC, and adjust a transmit buffer strength within the IC in response to the output signal of the I / O sensor.

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