Print head and print head inspection method

Abstract

To provide a printhead which can detect whether or not both of a high-voltage signal and a low-voltage signal are normal.SOLUTION: Provided is a printhead that performs printing by supplying a drive signal inputted to a second terminal to a drive element according to print data inputted to a first terminal, the printhead including: the first terminal; the second terminal; a determination circuit configured to perform, based on different criteria, first determination to determine, in response to a first signal inputted to the first terminal, whether a potential of the second terminal is normal, and second determination to determine, in response to a second signal inputted to the first terminal, whether the potential of the second terminal is normal; and a permission circuit configured to permit printing when the potential of the second terminal is determined to be normal in the first determination and second determination and does not permit printing when the potential of the second terminal is determined to be not normal in the first determination or second determination.SELECTED DRAWING: Figure 25

Description

[Technical Field]

[0001] The present invention relates to a printhead and a method for inspecting a printhead. [Background technology]

[0002] Inkjet printers and other liquid ejection devices use piezoelectric elements in their print heads to drive them with drive signals, ejecting liquid such as ink from cavities through nozzles to form characters and images on a medium. In such liquid ejection devices, if the print head malfunctions, the accuracy of liquid ejection decreases, resulting in a decrease in the quality of the characters and images formed on the medium.

[0003] As a technique for detecting malfunctions in a print head that can cause such a decrease in ejection accuracy, Patent Document 1 discloses a technique in which the print head itself diagnoses whether or not there is an abnormality based on a control signal input to the print head. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-114020 Summary of the Invention [Problem to be solved by the invention]

[0005] One of the causes of printhead malfunctions is malfunction due to a decrease in the accuracy of the signals supplied to the printhead. In addition to low-voltage signals for controlling printhead operation, high-voltage signals for driving the drive elements to the extent that liquid is ejected are input to the printhead. Therefore, in order to reduce the risk of printhead malfunction, it is necessary to properly supply both high-voltage and low-voltage signals to the printhead. In contrast, the invention described in Patent Document 1 does not disclose any technology for detecting whether both the high-voltage and low-voltage signals supplied to the printhead are normal, with the aim of reducing the risk of printhead malfunction. Therefore, there is room for improvement in terms of reducing the risk of printhead malfunction.

[0006] In a liquid ejection device having a print head, a portion of the liquid ejected from the nozzles to form an image on a medium may become mist before landing on the medium and float as liquid mist inside the liquid ejection device. Furthermore, even after the liquid ejected from the nozzles lands on the medium, it may re-float as liquid mist inside the liquid ejection device due to air currents generated by transporting the medium. Because such liquid mist floating inside the liquid ejection device is extremely minute, it becomes charged by the Lenard effect and is attracted to conductive parts such as wiring patterns and terminals through which various signals are transmitted. The print head ejects liquid onto the medium. Therefore, a particularly large amount of liquid mist floats near the print head. As a result, a large amount of liquid mist adheres to the print head terminals to which various signals are supplied, increasing the likelihood of short-circuiting or other abnormalities caused by the liquid mist. Therefore, from the perspective of reducing the risk of malfunction in the print head, there is a strong demand for print heads that are susceptible to the effects of liquid mist to be able to accurately detect whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal. [Means for solving the problem]

[0007] One aspect of the print head according to the present invention is A print head that performs printing by supplying a drive signal input to a second terminal to a drive element in accordance with print data input to a first terminal, the first terminal; the second terminal; a determination circuit that performs a first determination of whether or not the potential of the second terminal is normal in accordance with a first signal input to the first terminal, and a second determination of whether or not the potential of the second terminal is normal in accordance with a second signal input to the first terminal, using different determination criteria; an enabling circuit that enables printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and that does not enable printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Equipped with.

[0008] One aspect of the print head inspection method according to the present invention includes: A method for inspecting a print head that performs printing by supplying a drive signal to a drive element that is input to a second terminal in response to print data that is input to a first terminal, comprising: a determination step of performing a first determination of whether or not the potential of the second terminal is normal in accordance with a first signal input to the first terminal, and a second determination of whether or not the potential of the second terminal is normal in accordance with a second signal input to the first terminal, using different determination criteria; an enabling step of enabling printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and disallowing printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Includes: [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram illustrating a functional configuration of the liquid ejection device. [Figure 2] FIG. 2 is a diagram illustrating a functional configuration of a drive circuit. [Figure 3]FIG. 2 is a diagram illustrating the functional configuration of a print head. [Figure 4] 4A and 4B are diagrams showing examples of signal waveforms of drive signals COMA and COMB. [Figure 5] FIG. 4 is a diagram showing an example of a signal waveform of a drive signal VOUT. [Figure 6] FIG. 2 is a diagram illustrating a functional configuration of a drive signal selection circuit. [Figure 7] FIG. 10 is a diagram illustrating an example of decoded content. [Figure 8] FIG. 2 is a diagram illustrating a configuration of a selection circuit. [Figure 9] 10A and 10B are diagrams for explaining the operation of a drive signal selection circuit. [Figure 10] FIG. 1 is a diagram illustrating a schematic structure of a liquid ejection device. [Figure 11] FIG. 2 is a diagram illustrating an example of the structure of a discharge control unit. [Figure 12] FIG. 2 is a diagram illustrating an example of an arrangement of print heads. [Figure 13] FIG. 1 is a diagram illustrating an example of the structure of a print head. [Figure 14] FIG. 2 is a diagram illustrating an example of a configuration of a wiring substrate. [Figure 15] FIG. 2 is a diagram showing a schematic structure of a head chip. [Figure 16] FIG. 1 is a diagram showing a schematic structure of a cable. [Figure 17] FIG. 2 is a diagram showing the schematic structure of a connector. [Figure 18] FIG. 10 is a diagram illustrating an example in which a cable is attached to a connector. [Figure 19] FIG. 2 is a diagram illustrating a functional configuration of an abnormality detection circuit. [Figure 20] FIG. 10 is a diagram illustrating an example of the operation of the abnormality detection circuit when the signal supplied to the print head is normal. [Figure 21] FIG. 10 is a diagram illustrating an example of the operation of the abnormality detection circuit when the signal supplied to the print head is normal. [Figure 22] 10A and 10B are diagrams illustrating an example of the operation of the abnormality detection circuit when a signal supplied to a print head is abnormal. [Figure 23] 10A and 10B are diagrams illustrating an example of the operation of the abnormality detection circuit when a signal supplied to a print head is abnormal. [Figure 24] 10A to 10C are diagrams illustrating a method for inspecting a print head in a liquid ejection device. [Figure 25] FIG. 10 is a diagram illustrating an example of a determination process. [Figure 26] FIG. 10 is a diagram illustrating an example of a permission process. [Figure 27] FIG. 10 is a diagram illustrating the functional configuration of a print head according to a second embodiment. [Figure 28] FIG. 10 is a diagram illustrating the functional configuration of a print head according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for the convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0011] In the following explanation, a so-called inkjet printer that forms a desired image on a medium by ejecting ink, as an example of a liquid, onto the medium will be described as an example of a liquid ejection device; however, the liquid ejection device is not limited to inkjet printers, and may be, for example, a color material ejection device used in the manufacture of color filters for liquid crystal displays and the like, an electrode material ejection device used to form electrodes for organic electroluminescence displays, surface-emitting displays, and the like, a bioorganic material ejection device used in the manufacture of biochips, etc.

[0012] Furthermore, in the following description, the inkjet printer as a liquid ejection device in this embodiment is described as a so-called line-head type inkjet printer in which print heads that eject ink are arranged in a row that is wider than the width of the medium being transported, and the desired image is formed on the medium by ejecting ink from the print heads in synchronization with the transport of the medium. However, the inkjet printer as a liquid ejection device may also be a serial-head type inkjet printer in which a carriage is equipped with a print head that ejects ink, and the carriage moves back and forth in a direction intersecting the transport direction of the medium in synchronization with the transport of the medium, thereby forming the desired image on the medium.

[0013] In describing this embodiment, the logic level of a digital signal on the high potential side is referred to as a high level or H level, and the logic level of a digital signal on the low potential side is referred to as a low level or L level.

[0014] 1. First embodiment 1.1 Functional configuration of the liquid ejection device The functional configuration of the liquid ejection device 1 will be described with reference to FIG. 1. FIG. 1 is a diagram showing the functional configuration of the liquid ejection device 1. As shown in FIG. 1, the liquid ejection device 1 includes a printhead drive circuit 2 and m printheads 100. The printhead drive circuit 2 includes a main control unit 10 to which various signals are input from outside the liquid ejection device 1, and an ejection control unit 20 that outputs various signals to the m printheads 100. The printhead drive circuit 2 drives the m printheads 100 based on signals input from outside the liquid ejection device 1. In the following description, when it is necessary to distinguish between the m printheads 100, they may be referred to as printheads 100-1 to 100-m. Here, m is an integer equal to or greater than 1 and corresponds to the number of printheads 100 included in the liquid ejection device 1.

[0015] The main control unit 10 includes a main control circuit 11 and a power supply voltage output circuit 12 .

[0016] The power supply voltage output circuit 12 receives an AC voltage, which is a commercial AC voltage, from a commercial AC power supply (not shown) provided outside the liquid ejection device 1. The power supply voltage output circuit 12 receives the AC voltage. Based on the AC voltage AC, the power supply voltage output circuit 12 generates a DC voltage VHV with a voltage value of 42 V and a DC voltage VDD with a voltage value of 3.3 V. That is, the power supply voltage output circuit 12 is an AC / DC converter that converts the AC voltage AC into the DC voltage VHV, and is configured, for example, to include an isolated flyback circuit or the like that generates the voltage VHV, and a step-down converter that generates the voltage VDD by stepping down the voltage VHV. The power supply voltage output circuit 12 then supplies the generated voltages VHV and VDD to each part of the liquid ejection device 1, including the main control unit 10, the ejection control unit 20, and the m print heads 100.

[0017] Here, the power supply voltage output circuit 12 may generate DC voltages of various voltage values ​​in addition to the voltages VHV and VDD and supply them to each part of the liquid ejection device 1, including the main control unit 10, the ejection control unit 20, and the m print heads 100. The main control unit 10, the ejection control unit 20, and the m print heads 100 operate using the voltages VHV and VDD as power supply voltages and control voltages.

[0018] The main control circuit 11 receives image data PD, including image information to be formed on a medium, from an external device such as a host computer external to the liquid ejection device 1. The main control circuit 11 generates an image information signal IP by performing predetermined image processing on the received image data PD. The main control circuit 11 then outputs the generated image information signal IP to the ejection control unit 20. The image information signal IP output from the main control circuit 11 may be, for example, an electrical signal capable of high-speed communication, such as a differential signal, or an optical signal for optical communication. Examples of image processing performed by the main control circuit 11 include color conversion processing, which converts the input image signal into red, green, and blue color information and then converts it into color information corresponding to the colors of the ink ejected from the liquid ejection device 1, and halftone processing, which binarizes the color information after color conversion processing. Note that the image processing performed by the main control circuit 11 is not limited to the color conversion processing and halftone processing described above. The main control circuit 11 may be one or more semiconductor devices equipped with multiple functions, such as an SoC (System on a Chip).

[0019] The discharge control unit 20 includes a discharge control circuit 21, differential signal restoration circuits 22-1 to 22-m, and a drive voltage output circuit 50.

[0020] The ejection control circuit 21 receives an image information signal IP output from the main control circuit 11. Based on the image information signal IP input from the main control circuit 11, the ejection control circuit 21 generates and outputs various signals for controlling the operations of each part of the ejection control unit 20 and the m print heads 100.

[0021] Specifically, the discharge control circuit 21 generates, based on the image information signal IP, differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm corresponding to control signals that control the discharge of ink from the m print heads 100. Then, the discharge control circuit 21 outputs the generated differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm to the corresponding differential signal restoration circuits 22-1 to 22-m.

[0022] Each of the differential signal restoration circuits 22-1 to 22-m restores the input differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm to generate single-ended diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, ..., SIm1 to SImn, and clock signals SCK1 to SCKm. outputs the generated diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, . . . , SIm1 to SImn, and clock signals SCK1 to SCKm to the corresponding m print heads 100.

[0023] Specifically, the discharge control circuit 21 generates a differential signal dHC1 including a pair of signals dHC1+ and dHC1−, differential signals dSI11 to dSI1n including a pair of signals dSI11+ to dSI1n+ and dSI11− to dSI1n−, and a differential signal dSCK1 including a pair of signals dSCK1+ and dSCK1− based on the image information signal IP, and outputs these signals to the differential signal restoration circuit 22-1. The differential signal restoration circuit 22-1 restores the differential signal dHC1 to generate a single-ended diagnostic control signal HC1, restores the differential signal dSCK1 to generate a single-ended clock signal SCK1, and restores the differential signals dSI11 to dSI1n to generate single-ended print data signals SI11 to SI1n. The differential signal restoration circuit 22-1 then outputs the generated diagnostic control signal HC1, clock signal SCK1, and print data signals SI11 to SI1n to the print head 100-1.

[0024] Based on the image information signal IP, the discharge control circuit 21 generates a differential signal dHCm including a pair of signals dHCm+ and dHCm−, differential signals dSIm1 to dSImn including a pair of signals dSIm1+ to dSImn+ and dSIm1 to dSImn−, and a differential signal dSCKm including a pair of signals dSCKm+ and dSCKm−, and outputs these signals to the differential signal restoration circuit 22-m. The differential signal restoration circuit 22-m restores the differential signal dHCm to generate a single-ended diagnostic control signal HCm, restores the differential signal dSCKm to generate a single-ended clock signal SCKm, and restores the differential signals dSIm1 to dSImn to generate single-ended print data signals SIm1 to SImn. The differential signal restoration circuit 22-m then outputs the generated diagnostic control signal HCm, clock signal SCKm, and print data signals SIm1 to SImn to the print head 100-m.

[0025] That is, the discharge control circuit 21 generates a differential signal dHCi including a pair of signals dHCi+ and dHCi- (where i is an integer between 1 and m), differential signals dSIi1 to dSIin including a pair of signals dSIi1+ to dSIin+ and dSIi1- to dSIin-, and a differential signal dSCKi including a pair of signals dSCKi+ and dSCKi- based on the image information signal IP, and outputs these signals to the differential signal restoration circuit 22-i. The differential signal restoration circuit 22-i restores the differential signal dHCi to generate a single-ended diagnostic control signal HCi, restores the differential signal dSCKi to generate a single-ended clock signal SCKi, and restores the differential signals dSIi1 to dSIin to generate single-ended print data signals SIi1 to SIin. The differential signal restoration circuit 22-i then outputs the generated diagnostic control signal HCi, clock signal SCKi, and print data signals SIi1 to SIin to the print head 100-i.

[0026] Here, the differential signals dHC1 to dHCm, differential signals dSI11 to dSI1n, ..., dSIm1 to dSImn, and differential signals dSCK1 to dSCKm output by the discharge control circuit 21 are differential signals conforming to a high-speed transfer method, and may be, for example, differential signals conforming to an LVDS (Low Voltage Differential Signaling) transfer method, a LVPECL (Low Voltage Positive Emitter Coupled Logic) transfer method, or a CML (Current Mode Logic) transfer method. Also, while FIG. 1 illustrates a case where the differential signal restoration circuits 22-1 to 22-m correspond one-to-one to the m print heads 100, the present invention is not limited to a case where the differential signal restoration circuits 22-1 to 22-m correspond one-to-one to the m print heads 100. For example, one differential signal restoration circuit 22-i restores differential signals corresponding to a plurality of print heads 100 and outputs the restored signals. A single-ended signal may be output to a corresponding number of printheads 100 .

[0027] Here, n is an integer equal to or greater than 1 and corresponds to the number of head chips 300 included in each of print heads 100-1 to 100-m. Of the above-mentioned print data signals SI11 to SI1n, ..., SIm1 to SImn, print data signal SIij (j is an integer from 1 to n) corresponds to print data signal SI input to head chip 300-j included in print head 100-i, and differential signal dSIij corresponds to the differential signal corresponding to print data signal SIij.

[0028] In addition, the ejection control circuit 21 generates a latch signal LAT and a change signal CH as control signals for controlling the timing of ink ejection from the m print heads 100 based on the image information signal IP input from the main control circuit 11, and outputs them to the m print heads 100.

[0029] Furthermore, the ejection control circuit 21 generates base drive signals dA and dB that serve as the basis for drive voltage signals VDR1 and VDR2 for driving the print head 100 based on the image information signal IP input from the main control circuit 11, and outputs them to the drive voltage output circuit 50.

[0030] The drive voltage output circuit 50 includes drive circuits 51a and 51b and a reference voltage output circuit 53. The drive voltage output circuit 50 generates drive voltage signals VDR1 and VDR2 based on the reference drive signals dA and dB, and outputs them to the corresponding m print heads 100.

[0031] Specifically, the reference drive signal dA is input to the drive circuit 51a. The drive circuit 51a converts the input reference drive signal dA into an analog signal, and then performs class D amplification on the converted analog signal based on the voltages VHV to generate the drive voltage signal VDR1. The drive circuit 51a then outputs the generated drive voltage signal VDR1 to each of the m print heads 100. The reference drive signal dB is input to the drive circuit 51b. The drive circuit 51b converts the input reference drive signal dB into an analog signal, and then performs class D amplification on the converted analog signal based on the voltages VHV to generate the drive voltage signal VDR2. The drive circuit 51b then outputs the generated drive voltage signal VDR2 to each of the m print heads 100. An example of a specific configuration and operation of the drive circuits 51a and 51b will be described later.

[0032] 1 illustrates an example in which the drive voltage output circuit 50 includes one drive circuit 51a that outputs the drive voltage signal VDR1 and one drive circuit 51b that outputs the drive voltage signal VDR2, but the drive voltage output circuit 50 may also include a plurality of drive circuits 51a that output the drive voltage signal VDR1 and a plurality of drive circuits 51b that output the drive voltage signal VDR2. In this case, each of the plurality of drive circuits 51a may generate a drive voltage signal VDR1 and output the generated drive voltage signal VDR1 to a corresponding print head 100, and each of the plurality of drive circuits 51b may generate a drive voltage signal VDR2 and output the generated drive voltage signal VDR2 to a corresponding print head 100.

[0033] For example, if the drive voltage output circuit 50 includes two drive circuits 51a that output a drive voltage signal VDR1 and two drive circuits 51b that output a drive voltage signal VDR2, one of the two drive circuits 51a that generate the drive voltage signal VDR1 outputs the drive voltage signal VDR1 to the print heads 100-1 to 100-i, and the other of the two drive circuits 51a that generate the drive voltage signal VDR1 outputs the drive voltage signal VDR1 to the print heads 100-i+1 to 100-m. Similarly, one of the two drive circuits 51b that generate the drive voltage signal VDR2 outputs the drive voltage signal VDR2 to the print heads 100-1 to 100-i, and the other of the two drive circuits 51b that generate the drive voltage signal VDR2 outputs the drive voltage signal VDR2 to the print heads 100-1 to 100-m. The drive voltage signal VDR2 is output to the heads 100-i+1 to 100-m.

[0034] A voltage VDD is supplied to the reference voltage output circuit 53. The reference voltage output circuit 53 generates a reference voltage signal VBS, which serves as a reference potential when ink is ejected from each of the m print heads 100, by stepping up or stepping down the supplied voltage VDD, and outputs the reference voltage signal VBS to each of the m print heads 100.

[0035] As described above, the print head drive circuit 2 generates voltages VHV, VDD, diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, ..., SIm1 to SImn, clock signals SCK1 to SCKm, latch signal LAT, change signal CH, drive voltage signals VDR1, VDR2, and reference voltage signal VBS based on the AC voltage AC supplied from a commercial AC power source and image data PD supplied from an external device, and outputs these to the m print heads 100.

[0036] The m print heads 100 use voltages VHV and VDD as power supply voltages and switch whether or not to supply drive voltage signals VDR1 and VDR2 to piezoelectric elements 60 (described later) at timings determined by diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, ..., SIm1 to SImn, clock signals SCK1 to SCKm, latch signal LAT, and change signal CH. As a result, each of the m print heads 100 ejects a predetermined amount of ink at a predetermined timing. In other words, each of the m print heads 100 is controlled by the print head drive circuit 2.

[0037] Furthermore, the print heads 100-1 to 100-m generate determination result signals ES1 to ESm indicating whether or not an abnormality has occurred in the print heads 100-1 to 100-m, and output these signals to the discharge control circuit 21 included in the discharge control unit 20 of the print head drive circuit 2. This allows the discharge control circuit 21 to drive or stop the print heads 100-1 to 100-m depending on the state of the print heads 100-1 to 100-m. An example of a specific configuration and operation of the m print heads 100 will be described later.

[0038] 1.2 Configuration and operation of the drive circuit Next, the configuration and operation of the drive circuits 51a and 51b of the drive voltage output circuit 50 will be described. The drive circuits 51a and 51b have the same configuration and operation, except for the signals they input and output. Therefore, in the following explanation, we will explain the configuration and operation of the drive circuit 51a, which outputs the drive voltage signal VDR1 based on the reference drive signal dA, and will omit explanation of the configuration and operation of the drive circuit 51b, which outputs the drive voltage signal VDR2 based on the reference drive signal dB.

[0039] Fig. 2 is a diagram showing the functional configuration of the drive circuit 51a. As shown in Fig. 2, the drive circuit 51a has an integrated circuit 500 including a modulation circuit 510, an amplifier circuit 550, a smoothing circuit 560, feedback circuits 570 and 572, and a plurality of other circuit elements.

[0040] The integrated circuit 500 is electrically connected to the outside of the integrated circuit 500 via a plurality of terminals including the terminal In, the terminal Bst, the terminal Hdr, the terminal Sw, the terminal Gvd, the terminal Ldr, the terminal Gnd, the terminal Ifb, and the terminal Vfb. The integrated circuit 500 generates and outputs a gate signal Hgd that drives the transistor M1 and a gate signal Lgd that drives the transistor M2 of the amplifier circuit 550 based on the basic drive signal dA input from the terminal In.

[0041] The integrated circuit 500 includes a digital-to-analog converter (DAC) 511, a modulation circuit 510, a gate drive circuit 520, and a power supply circuit 580.

[0042] The power supply circuit 580 generates a voltage signal DAC_HV and a voltage signal DAC_LV and outputs them to the DAC 511 .

[0043] A digital reference drive signal dA is input to the DAC 511. The DAC 511 converts the reference drive signal dA into an analog signal with a voltage value between the voltage signals DAC_HV and DAC_LV, and outputs it to the modulation circuit 510 as the reference drive signal aA. Here, the maximum value of the voltage amplitude of the reference drive signal aA is determined by the voltage signal DAC_HV, and the minimum value of the voltage amplitude of the reference drive signal aA is determined by the voltage signal DAC_LV. In other words, the voltage signal DAC_HV is the high-voltage reference voltage of the DAC 511, and the voltage signal DAC_LV is the low-voltage reference voltage of the DAC 511. A signal obtained by amplifying this reference drive signal aA by the voltage VHV becomes the drive voltage signal VDR1. In other words, the reference drive signal aA corresponds to a signal with a target waveform before amplification of the drive voltage signal VDR1, and the reference drive signal dA corresponds to a digital signal that determines the waveform of the drive voltage signal VDR1. In this embodiment, the voltage amplitude of the basic drive signal aA is, for example, 1V to 2V.

[0044] A master drive signal aA is input to the modulation circuit 510. The modulation circuit 510 generates a modulated signal Ms by modulating the input master drive signal aA and outputs the modulated signal Ms to the gate drive circuit 520. The modulation circuit 510 includes adders 512 and 513, a comparator 514, an inverter 515, an integral attenuator 516, and an attenuator 517.

[0045] The voltage at terminal Out input via terminal Vfb, i.e., the drive voltage signal VDR1, is input to integral attenuator 516. Integral attenuator 516 attenuates and integrates drive voltage signal VDR1 and supplies the result to the negative input terminal of adder 512. The basic drive signal aA is input to the positive input terminal of adder 512. Adder 512 subtracts the voltage input to the negative input terminal from the voltage input to the positive input terminal and integrates the result, and supplies the resulting voltage to the positive input terminal of adder 513.

[0046] Here, the voltage amplitude of the basic drive signal aA is about 1 V to 2 V as described above, whereas the maximum voltage value of the drive voltage signal VDR1 depends on the voltage value of the voltage VHV and may exceed 40 V. For this reason, the integral attenuator 516 attenuates the voltage of the drive voltage signal VDR1 input via the terminal Vfb in order to match the amplitude ranges of both voltages when calculating the deviation.

[0047] A voltage resulting from attenuating the high-frequency components of the drive voltage signal VDR1 is input to the attenuator 517 via the terminal Ifb. The attenuator 517 supplies the voltage resulting from attenuating the high-frequency components of the input drive voltage signal VDR1 to the negative input terminal of the adder 513. The voltage output from the adder 512 is input to the positive input terminal of the adder 513. The adder 513 outputs a voltage obtained by subtracting the voltage input to the negative input terminal from the voltage input to the positive input terminal as a voltage signal As to the comparator 514.

[0048] The voltage signal As output from this adder 513 is a voltage obtained by subtracting the voltage of the signal supplied to terminal Vfb from the voltage of the base drive signal aA, and further subtracting the voltage of the signal supplied to terminal Ifb. In other words, the voltage of the voltage signal As output from the adder 513 is a signal obtained by correcting the deviation obtained by subtracting the attenuation voltage of the drive voltage signal VDR1 from the target voltage of the base drive signal aA, using the high-frequency component of the drive voltage signal VDR1.

[0049] The comparator 514 outputs a pulse-modulated modulation signal Ms based on the voltage signal As output from the adder 513. Specifically, the comparator 514 generates a modulation signal Ms that goes to H level when the voltage signal As exceeds a predetermined threshold value during a voltage rise, and goes to L level when the voltage signal As falls below the predetermined threshold value during a voltage drop. The frequency and duty ratio of the modulation signal Ms change in accordance with the changes in the master drive signals dA and aA, and the attenuator 517 adjusts the modulation gain, which corresponds to the sensitivity, thereby adjusting the frequency and duty ratio of the modulation signal Ms.

[0050] The modulation signal Ms is input to a gate drive circuit 520. The gate drive circuit 520 includes gate drivers 521 and 522. Specifically, the modulation signal Ms output from the comparator 514 is supplied to the gate driver 521, and after its logical level is inverted by an inverter 515, is also supplied to the gate driver 522. In other words, the modulation signal Ms having mutually exclusive logical levels is input to the gate drivers 521 and 522.

[0051] Here, the mutually exclusive relationship between the logical level of the signal supplied to gate driver 521 and the logical level of the signal supplied to gate driver 522 strictly speaking includes the case where the logical level of the signal supplied to gate driver 521 and the logical level of the signal supplied to gate driver 522 are both H level at the same time. In other words, this means that the transistor M1 and the transistor M2 included in the amplifier circuit 550, which will be described later, are not turned on at the same time.

[0052] The gate driver 521 level-shifts the input modulation signal Ms and outputs it as a gate signal Hgd from the terminal Hdr. A voltage is supplied to the high side of the power supply voltage of the gate driver 521 via the terminal Bst, and a voltage is supplied to the low side of the power supply voltage via the terminal Sw. The terminal Bst is connected to one end of the capacitor C5 and the cathode of the diode D1. The terminal Sw is connected to the other end of the capacitor C5. The anode of the diode D1 is connected to the terminal Gvd. As a result, a voltage Vm is supplied to the anode of the diode D1. In other words, the capacitor C5 and the diode D1 form a bootstrap circuit. Therefore, the potential difference between the terminal Bst and the terminal Sw is approximately equal to the potential difference across the capacitor C5, i.e., the voltage Vm. Therefore, the gate driver 521 generates a gate signal Hgd that is higher by the voltage Vm than the voltage at the terminal Sw in accordance with the input modulation signal Ms, and outputs the gate signal Hgd from the integrated circuit 500 via the terminal Hdr.

[0053] The gate driver 522 level-shifts a signal obtained by inverting the logical level of the input modulation signal Ms and outputs the signal as gate signal Lgd from terminal Ldr. The gate driver 522 operates at a lower potential than the gate driver 521. A voltage Vm is supplied to the high side of the power supply voltage of the gate driver 522, and a ground potential is supplied to the low side of the power supply voltage via terminal Gnd. The gate driver 522 generates a gate signal Lgd that is higher by Vm than terminal Gnd and follows a signal obtained by inverting the logical level of the input modulation signal Ms, and outputs the gate signal Lgd from the integrated circuit 500 via terminal Ldr.

[0054] The gate signals Hgd and Lgd output from the integrated circuit 500 are input to the amplifier circuit 550. The amplifier circuit 550 includes transistors M1 and M2. A voltage VHV is supplied to the drain of the transistor M1. The gate of the transistor M1 is electrically connected to one end of a resistor R1, and the other end of the resistor R1 is electrically connected to a terminal Hdr of the integrated circuit 500. That is, the gate of the transistor M1 is supplied with the gate signal Hgd output from the terminal Hdr of the integrated circuit 500. The source of the transistor M1 is electrically connected to a terminal Sw of the integrated circuit 500.

[0055] The drain of the transistor M2 is electrically connected to the terminal Sw of the integrated circuit 500. That is, the drain of the transistor M2 and the source of the transistor M1 are electrically connected to each other. The gate of the transistor M2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to the terminal Ldr of the integrated circuit 500. That is, the gate of the transistor M2 is supplied with a gate signal Lgd output from the terminal Ldr of the integrated circuit 500. The source of the transistor M2 is supplied with the ground potential.

[0056] In the following description, when the drain and source of transistors M1 and M2 are controlled to be conductive, this may be referred to as "on," and when the drain and source of transistors M1 and M2 are controlled to be non-conductive, this may be referred to as "off."

[0057] In the amplifier circuit 550 configured as described above, when the transistor M1 is controlled to be off and the transistor M2 is controlled to be on, the potential of the node to which the terminal Sw is connected is the ground potential. Therefore, a voltage Vm is supplied to the terminal Bst. On the other hand, when the transistor M1 is controlled to be on and the transistor M2 is controlled to be off, the potential of the node to which the terminal Sw is connected is the voltage VHV. Therefore, a voltage signal having a potential of the voltage VHV+Vm is supplied to the terminal Bst. That is, the gate driver 521 that drives the transistor M1 uses the capacitor C5 as a floating power supply, and by changing the potential of the terminal Sw to 0V or the voltage VHV depending on the operation of the transistors M1 and M2, generates a gate signal Hgd whose L level is the potential of the voltage VHV or 0V and whose H level is the potential of the voltage VHV+Vm, and supplies this gate signal from the terminal Hdr to the gate of the transistor M1.

[0058] On the other hand, the gate driver 522 that drives the transistor M2 supplies a gate signal Lgd, whose L level is the ground potential and whose H level is the potential of the voltage Vm, to the gate of the transistor M2, regardless of the operation of the transistors M1 and M2.

[0059] In the amplifier circuit 550 configured as described above, the transistors M1 and M2 operate based on the modulation signal Ms obtained by modulating the basic drive signals dA and aA, and thus an amplified modulation signal AMs is generated by amplifying the modulation signal Ms based on the voltage VHV at the connection point where the source of the transistor M1 and the drain of the transistor M2 are commonly connected. The amplifier circuit 550 then outputs the generated amplified modulation signal AMs to the smoothing circuit 560. In other words, the amplified modulation signal AMs is a signal whose voltage value changes between VHV and ground potential depending on the logic level of the modulation signal Ms.

[0060] Furthermore, a capacitor C6 is electrically connected to the path that supplies the voltage VHV to the amplifier circuit 550. Specifically, the voltage VHV is supplied to one end of the capacitor C6, and the ground potential is supplied to the other end. This capacitor C6 reduces potential fluctuations in the voltage VHV that may occur due to the switching operations of the transistors M1 and M2 included in the amplifier circuit 550. It is preferable that such a capacitor C6 has a large capacitance, and for example, an electrolytic capacitor is used.

[0061] The smoothing circuit 560 smoothes the amplified modulation signal AMs input from the amplifier circuit 550 to generate the drive voltage signal VDR1, which is output from the drive circuit 51a via the terminal Out.

[0062] Specifically, the smoothing circuit 560 includes a coil L1 and a capacitor C1. One end of the coil L1 receives the amplified modulation signal AMs output from the amplifier circuit 550, and the other end of the coil L1 is connected to a terminal Out, which serves as the output of the drive circuit 51a. The other end of the coil L1 is also connected to one end of the capacitor C1. The other end of the capacitor C1 is supplied with a ground potential. That is, the coil L1 and the capacitor C1 constitutes a low pass filter, and the smoothing circuit 560 demodulates the amplified modulated signal AMs output by the amplifier circuit 550 by smoothing it using the low pass filter, and outputs the demodulated signal as the drive voltage signal VDR1.

[0063] The feedback circuit 570 includes resistors R3 and R4. One end of the resistor R3 is connected to a terminal Out from which the drive voltage signal VDR1 is output, and the other end is connected to a terminal Vfb and one end of the resistor R4. The voltage VHV is supplied to the other end of the resistor R4. As a result, the drive voltage signal VDR1 that has passed through the feedback circuit 570 from the terminal Out is fed back to the terminal Vfb in a pulled-up state.

[0064] The feedback circuit 572 includes capacitors C2, C3, and C4, and resistors R5 and R6. One end of the capacitor C2 is connected to a terminal Out from which the drive voltage signal VDR1 is output, and the other end is connected to one end of a resistor R5 and one end of a resistor R6. The other end of the resistor R5 is supplied with a ground potential. That is, the capacitors C2 and R5 function as a high-pass filter. The cutoff frequency of the high-pass filter is set to, for example, approximately 9 MHz. The other end of the resistor R6 is connected to one end of a capacitor C4 and one end of a capacitor C3. The other end of the capacitor C3 is supplied with a ground potential. That is, the resistors R6 and C3 function as a low-pass filter. The cutoff frequency of the low-pass filter is set to, for example, approximately 160 MHz.

[0065] The feedback circuit 572 configured in this manner includes a high-pass filter and a low-pass filter, and therefore functions as a band-pass filter that passes a predetermined frequency range of the drive voltage signal VDR1. The other end of the capacitor C4 is connected to the terminal Ifb of the integrated circuit 500, and a signal from which the DC component has been cut out of the high-frequency components of the drive voltage signal VDR1 that have passed through the feedback circuit 572, which functions as a band-pass filter that passes a predetermined frequency component, is fed back to the terminal Ifb.

[0066] The drive voltage signal VDR1 output from terminal Out is a signal obtained by smoothing the amplified modulation signal AMs based on the basic drive signal dA through smoothing circuit 560. The drive voltage signal VDR1 is integrated and subtracted via terminal Vfb before being fed back to adder 512. Therefore, drive circuit 51a self-oscillates at a frequency determined by the feedback delay and feedback transfer function. However, due to the large signal delay in the feedback path via terminal Vfb, feedback via terminal Vfb alone may not be able to raise the self-oscillation frequency high enough to ensure the accuracy of the drive voltage signal VDR1. Therefore, by providing a path for feeding back the high-frequency components of the drive voltage signal VDR1 via terminal Ifb, separate from the path via terminal Vfb, the delay in the entire circuit is reduced. This allows the frequency of the voltage signal As to be raised high enough to ensure the accuracy of the drive voltage signal VDR1, compared to when the path via terminal Ifb is not provided.

[0067] The drive circuit 51a configured as described above generates an amplified modulated signal AMs by amplifying the modulated signal Ms based on the reference drive signal dA with the voltage VHV, and generates a drive voltage signal VDR1 by smoothing the amplified modulated signal AMs. That is, the drive circuit 51a can output, as the drive voltage signal VDR1, a signal having a voltage value ranging from 0 V (ground potential) to the voltage VHV and having an arbitrary waveform including a DC voltage, based on the reference drive signals dA and aA. Similarly, the drive circuit 51b in this embodiment generates an amplified modulated signal AMs by amplifying the modulated signal Ms based on the reference drive signal dB with the voltage VHV, and generates a drive voltage signal VDR2 by smoothing the amplified modulated signal AMs. That is, the drive circuit 51b outputs, as the drive voltage signal VDR2, a signal having a voltage value ranging from 0 V (ground potential) to the voltage VHV and having an arbitrary waveform including a DC voltage, based on the reference drive signal dB. It is possible.

[0068] 1.3 Printhead Structure and Operation Next, the configuration and operation of the print head 100 will be described. The m print heads 100 included in the liquid ejection device 1 have the same configuration and operation, with the only difference being the signals they receive. Therefore, in the following explanation, only the configuration and operation of one print head 100 will be described, and explanations of the configurations and operations of the other print heads 100 will be omitted. In the following explanation, it is assumed that the print head 100 receives inputs of voltages VHV and VDD, a diagnostic control signal HC as diagnostic control signals HC1 to HCm, print data signals SI1 to SIn as print data signals SI11 to SI1n, ..., SIm1 to SImn, a clock signal SCK as clock signals SCK1 to SCKm, a latch signal LAT, a change signal CH, drive voltage signals VDR1 and VDR2, and a reference voltage signal VBS.

[0069] FIG. 3 is a diagram showing the functional configuration of print head 100. As shown in FIG. 3, print head 100 has an abnormality detection circuit 250, drive signal selection circuits 200-1 to 200-n, and head chips 300-1 to 300-n. Each of head chips 300-1 to 300-n includes p piezoelectric elements 60. Note that voltages VHV, VDD, and the like used as power supply voltages and control voltages are not shown in FIG. 3. Here, p is an integer equal to or greater than 1 and corresponds to the number of ejection sections 600 and piezoelectric elements 60 included in one head chip 300.

[0070] The abnormality detection circuit 250 receives the diagnostic control signal HC, print data signal SI1, clock signal SCK, latch signal LAT, change signal CH, and drive voltage signal VDR1. Based on the diagnostic control signal HC and drive voltage signal VDR1, the abnormality detection circuit 250 determines whether the signals transmitted to the print head 100 are normal. That is, the print head 100 includes the abnormality detection circuit 250 for detecting abnormalities. If the abnormality detection circuit 250 determines that the signals transmitted to the print head 100 are normal, it outputs the print data signal SI1 to the drive signal selection circuit 200-1 and the clock signal SCK, latch signal LAT, and change signal CH to the drive signal selection circuits 200-1 to 200-n. The abnormality detection circuit 250 also generates a determination result signal ES, which includes the result of determining whether the signals transmitted to the print head 100 are normal, and outputs the result to the ejection control unit 20 of the print head drive circuit 2.

[0071] Here, the abnormality detection circuit 250 may receive the print data signal SIj instead of the print data signal SI1, and may receive the drive voltage signal VDR2 instead of the drive voltage signal VDR1. In this case, the abnormality detection circuit 250 outputs the print data signal SIj to the corresponding drive signal selection circuit 200-j. The configuration and operation of the abnormality detection circuit 250 will be described in detail later.

[0072] Drive signal selection circuits 200-1 to 200-n are provided in one-to-one correspondence with head chips 300-1 to 300-n. Specifically, drive signal selection circuit 200-1 outputs various signals to head chip 300-1, drive signal selection circuit 200-n outputs various signals to head chip 300-n, and drive signal selection circuit 200-j outputs various signals to head chip 300-j.

[0073] In detail, the drive signal selection circuit 200-1 receives the print data signal SI1, the clock signal SCK, the latch signal LAT, the change signal CH, and the drive voltage signals VDR1 and VDR2. Based on the print data signal SI1, the drive signal selection circuit 200-1 selects the drive voltage signals VDR1 and VDR2 at the timing determined by the latch signal LAT and the change signal CH. By selecting or not selecting the signal waveform of 2, p drive signals VOUT corresponding to the p piezoelectric elements 60 of the head chip 300-1 are generated.

[0074] The p drive signals VOUT generated by the drive signal selection circuit 200-1 are input to the head chip 300-1. A reference voltage signal VBS is also input to the head chip 300-1. The p drive signals VOUT are individually supplied to one end of the corresponding piezoelectric elements 60. The reference voltage signal VBS is commonly supplied to the other end of the p piezoelectric elements 60. Each of the p piezoelectric elements 60 is driven in accordance with the potential difference between the drive signal VOUT supplied individually to one end and the reference voltage signal VBS supplied commonly to the other end. As a result, an amount of ink corresponding to the drive of the corresponding piezoelectric element 60 is ejected from a nozzle (not shown) corresponding to each of the p piezoelectric elements 60.

[0075] Furthermore, the drive signal selection circuit 200-1 generates a head status signal HS1 indicating the status of the head chip 300-1 based on the temperatures of the drive signal selection circuit 200-1 and the head chip 300-1, residual vibrations that occur after the drive signal VOUT is supplied to the piezoelectric element 60, and outputs this to the abnormality detection circuit 250. The abnormality detection circuit 250 determines whether or not the drive signal selection circuit 200-1 is normal based on the input head status signal HS1. The abnormality detection circuit 250 then outputs the determination result as to whether or not the drive signal selection circuit 200-1 is normal to the discharge control unit 20 as a determination result signal ES.

[0076] Furthermore, the drive signal selection circuit 200-n receives the print data signal SIn, the clock signal SCK, the latch signal LAT, the change signal CH, and the drive voltage signals VDR1 and VDR2. Based on the print data signal SIn, the drive signal selection circuit 200-n selects or deselects the signal waveforms of the drive voltage signals VDR1 and VDR2 at the timing determined by the latch signal LAT and the change signal CH, thereby generating p drive signals VOUT corresponding to the p piezoelectric elements 60 of the head chip 300-n.

[0077] The p drive signals VOUT generated by the drive signal selection circuit 200-n are input to the head chip 300-n. A reference voltage signal VBS is also input to the head chip 300-n. The p drive signals VOUT are individually supplied to one end of the corresponding piezoelectric elements 60. The reference voltage signal VBS is commonly supplied to the other end of the p piezoelectric elements 60. Each of the p piezoelectric elements 60 is driven in accordance with the potential difference between the drive signal VOUT supplied individually to one end and the reference voltage signal VBS supplied commonly to the other end. As a result, an amount of ink corresponding to the drive of the corresponding piezoelectric element 60 is ejected from a nozzle (not shown) corresponding to each of the p piezoelectric elements 60.

[0078] Furthermore, the drive signal selection circuit 200-n generates a head status signal HSn indicating the status of the head chip 300-n based on the temperatures of the drive signal selection circuit 200-n and the head chip 300-n, residual vibrations that occur after the drive signal VOUT is supplied to the piezoelectric element 60, and outputs the signal to the abnormality detection circuit 250. The abnormality detection circuit 250 determines whether the drive signal selection circuit 200-n is normal or not based on the input head status signal HSn. The abnormality detection circuit 250 then outputs the determination result as to whether the drive signal selection circuit 200-n is normal or not to the discharge control unit 20 as a determination result signal ES.

[0079] As described above, in the print head 100, the abnormality detection circuit 250 determines whether the signal transmitted to the print head 100 is normal and whether the head chip 300 and the like are normal. If the abnormality detection circuit 250 determines that the signal transmitted to the print head 100 is normal, it outputs the print data signal SI1 to the drive signal selection circuit 200-1, and outputs the clock signal SCK, the latch signal LAT, and the change signal CH to the drive signal selection circuits 200-1 to 200-n. Head chips 300-1 to 300-n generate drive signals VOUT based on input print data signals SI1 to SIn, clock signal SCK, latch signal LAT, change signal CH, and drive voltage signals VDR1 and VDR2, and output them to corresponding head chips 300-1 to 300-n. Head chips 300-1 to 300-n then eject an amount of ink according to the input drive signal VOUT.

[0080] In the following description, the process in which the abnormality detection circuit 250 determines whether the signal transmitted to the print head 100 is normal or not will be referred to as the diagnostic process, and the process in which the drive signal selection circuits 200-1 to 200-n generate drive signals VOUT based on the drive voltage signals VDR1, VDR2 and output them to the corresponding head chips 300-1 to 300-n, thereby ejecting ink from the head chips 300-1 to 300-n, will be referred to as the printing process.

[0081] Head status signals HS1 to HSn may be input to abnormality detection circuit 250 by propagating through a single wire connected in a wired-OR configuration, or may be input to abnormality detection circuit 250 by propagating through multiple individually provided wires. Head status signals HS1 to HSn may also include various information indicating the status of drive signal selection circuits 200-1 to 200-n and head chips 300-1 to 300-n, instead of or in addition to the temperature and residual vibration information.

[0082] 1.4 Configuration of the drive signal selection circuit and its operation in the printing process Next, the configuration of drive signal selection circuits 200-1 to 200-n and their operation in the printing process will be described. Here, drive signal selection circuits 200-1 to 200-n all have the same configuration, and head chips 300-1 to 300-n all have the same configuration. Therefore, in the following description, when it is not necessary to distinguish between drive signal selection circuits 200-1 to 200-n, they will simply be referred to as drive signal selection circuits 200, and when it is not necessary to distinguish between head chips 300-1 to 300-n, they will simply be referred to as head chips 300. In this case, the description will be given assuming that drive signal selection circuit 200 receives print data signal SI, clock signal SCK, latch signal LAT, change signal CH, and drive voltage signals VDR1 and VDR2.

[0083] In explaining the configuration of the drive signal selection circuit 200 and the operation of the drive signal selection circuit 200 in the printing process, we will first explain an example of the signal waveforms of the drive voltage signals VDR1 and VDR2 input to the drive signal selection circuit 200 in the printing process, and an example of the signal waveform of the drive signal VOUT output from the drive signal selection circuit 200 in the printing process. Here, in the following explanation, the signal that the ejection control unit 20 outputs as the drive voltage signal VDR1 in the printing process will be referred to as the drive signal COMA, and the signal that it outputs as the drive voltage signal VDR2 will be referred to as the drive signal COMB.

[0084] 4 is a diagram showing an example of the signal waveforms of the drive signals COMA and COMB. As shown in FIG. 4, the drive signal COMA is a signal waveform formed by successively combining a trapezoidal waveform Adp1, which is disposed during a period T1 from when the latch signal LAT rises until when the change signal CH rises, and a trapezoidal waveform Adp2, which is disposed during a period T2 from when the change signal CH rises until when the latch signal LAT rises. When the trapezoidal waveform Adp1 is supplied to the head chip 300, a predetermined amount of ink is ejected from the corresponding nozzle of the head chip 300. When the trapezoidal waveform Adp2 is supplied to the head chip 300, an amount of ink greater than the predetermined amount is ejected from the corresponding nozzle of the head chip 300. Hereinafter, the amount of ink ejected when the trapezoidal waveform Adp1 is supplied to the head chip 300 may be referred to as a small amount, and the amount of ink ejected when the trapezoidal waveform Adp2 is supplied to the head chip 300 may be referred to as a medium amount.

[0085] 4, the drive signal COMB is a signal waveform formed by successively supplying a trapezoidal waveform Bdp1 arranged in a period T1 and a trapezoidal waveform Bdp2 arranged in a period T2. When the trapezoidal waveform Bdp1 is supplied to the head chip 300, ink is not ejected from the corresponding nozzle of the head chip 300. The trapezoidal waveform Bdp1 is a waveform that vibrates the ink near the nozzle opening to a degree that prevents the ink from being ejected, thereby preventing an increase in ink viscosity. When the trapezoidal waveform Bdp2 is supplied to the head chip 300, a small amount of ink is ejected from the corresponding nozzle of the head chip 300, but is about the same amount as when the trapezoidal waveform Adp1 is supplied.

[0086] 4, the voltage values ​​at the start and end of each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 are all the same, voltage Vc. That is, each of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is a signal waveform that starts and ends at voltage Vc. The cycle Ta consisting of periods T1 and T2 corresponds to the printing cycle for forming new dots on the medium.

[0087] 4 illustrates a case where the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 are the same signal waveform, but the trapezoidal waveform Adp1 and the trapezoidal waveform Bdp2 may be different signal waveforms. Furthermore, in the following description, it is assumed that a small amount of ink is ejected from the corresponding nozzle when the trapezoidal waveform Adp1 is supplied to the head chip 300 and when the trapezoidal waveform Bdp2 is supplied to the head chip 300, but this is not limitative. In other words, the signal waveforms of the drive signals COMA and COMB are not limited to those shown in FIG. 4, and signals with a combination of signal waveforms of various shapes may be used depending on the properties of the ink ejected from the nozzles of the head chip 300, the material of the medium on which the ink lands, and the like.

[0088] Furthermore, in FIG. 4, the timing at which the trapezoidal waveforms Adp1 and Adp2 included in the drive signal COMA are switched, and the timing at which the trapezoidal waveforms Bdp1 and Bdp2 included in the drive signal COMB are switched are specified by a single change signal CH, but a change signal CH that specifies the timing at which the trapezoidal waveforms Adp1 and Adp2 included in the drive signal COMA are switched, and a change signal CH that specifies the timing at which the trapezoidal waveforms Bdp1 and Bdp2 included in the drive signal COMB are switched may be provided separately.

[0089] FIG. 5 is a diagram showing an example of the signal waveform of the drive signal VOUT when the sizes of dots formed on a medium in the printing process are large dots LD, medium dots MD, small dots SD, and non-printing dots ND.

[0090] 5, the drive signal VOUT for forming a large dot LD on the medium has a signal waveform in which a trapezoidal waveform Adp1 arranged in period T1 and a trapezoidal waveform Adp2 arranged in period T2 are successively arranged in a cycle Ta. When this drive signal VOUT is supplied to the head chip 300, a small amount of ink and a medium amount of ink are ejected from the corresponding nozzle. Therefore, in the cycle Ta, the respective ink droplets land on the medium and combine to form a large dot LD on the medium.

[0091] The drive signal VOUT for forming a medium dot MD on the medium has a signal waveform that is a series of a trapezoidal waveform Adp1 arranged in period T1 and a trapezoidal waveform Bdp2 arranged in period T2 during the cycle Ta. When this drive signal VOUT is supplied to the head chip 300, a small amount of ink is ejected twice from the corresponding nozzle. Therefore, during the cycle Ta, each ink droplet lands on the medium and combines to form a medium dot MD on the medium.

[0092] The drive signal VOUT for forming a small dot SD on the medium has a signal waveform that, during a period Ta, is a series of a trapezoidal waveform Adp1 in period T1 and a constant signal waveform at voltage Vc in period T2. When this drive signal VOUT is supplied to the head chip 300, a small amount of ink is ejected once from the corresponding nozzle. Therefore, when this ink lands on the medium during the period Ta, a small dot SD is formed on the medium.

[0093] The drive signal VOUT corresponding to the non-recording ND, which does not form dots on the medium, has a signal waveform that is a series of a trapezoidal waveform Bdp1 in period T1 and a constant signal waveform at voltage Vc in period T2 during the cycle Ta. When this drive signal VOUT is supplied to the head chip 300, the ink near the opening of the corresponding nozzle merely vibrates slightly, but the ink is not ejected. Therefore, during the cycle Ta, no ink lands on the medium, and no dots are formed on the medium.

[0094] Here, the constant signal waveform of voltage Vc in drive signal VOUT refers to a signal waveform having a voltage value that maintains the voltage Vc immediately before the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is selected as drive signal VOUT. In other words, when none of the trapezoidal waveforms Adp1, Adp2, Bdp1, and Bdp2 is selected as drive signal VOUT, the immediately preceding voltage Vc is supplied to head chip 300 as drive signal VOUT.

[0095] The drive signal selection circuit 200 generates drive signals VOUT corresponding individually to each of the p piezoelectric elements 60 by selecting or deselecting the trapezoidal waveforms Adp1, Adp2 contained in the drive signal COMA, which is the drive voltage signal VDR1 in the printing process, and the trapezoidal waveforms Bdp1, Bdp2 contained in the drive signal COMB, which is the drive voltage signal VDR2 in the printing process, and outputs the drive signals VOUT to the corresponding piezoelectric elements 60.

[0096] Fig. 6 is a diagram showing the functional configuration of the drive signal selection circuit 200. As shown in Fig. 6, the drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230. Fig. 6 also shows an example of a head chip 300 to which the drive signal VOUT output from the drive signal selection circuit 200 is supplied. The head chip 300 includes p ejection units 600 corresponding to the p piezoelectric elements 60, respectively.

[0097] A print data signal SI, a clock signal SCK, a latch signal LAT, and a change signal CH are input to the selection control circuit 210. The selection control circuit 210 is provided with a set of a register 212, a latch circuit 214, and a decoder 216 corresponding to each of the p ejection units 600 of the head chip 300. In other words, the selection control circuit 210 includes the same number of sets of registers 212, latch circuits 214, and decoders 216 as the p ejection units 600.

[0098] The print data signal SI is a signal synchronized with the clock signal SCK, and is a signal of 2p bits in total that serially includes 2-bit print data [SIH, SIL] for selecting one of large dots LD, medium dots MD, small dots SD, and non-printing ND for each of the p ejection units 600. The print data signal SI is held in the register 212 for each piece of print data [SIH, SIL] included in the print data signal SI, corresponding to the p ejection units 600.

[0099] Specifically, in the selection control circuit 210, the registers 212 are cascaded to form a p-stage shift register. The print data [SIH, SIL] input serially as the print data signal SI is sequentially transferred to the next stage in accordance with the clock signal SCK. The print data [SIH, SIL] corresponding to each of the p ejection sections 600 is transferred to the registers 212. Then, when the supply of the clock signal SCK is stopped, the print data [SIH, SIL] corresponding to each of the p ejection sections 600 is held in the registers 212 corresponding to each of the p ejection sections 600. In the following description, in order to distinguish between the p registers 212 that make up the shift register, they may be referred to as stage 1, stage 2, ..., stage p in order from the upstream side to the downstream side along which the print data signal SI is propagated.

[0100] Each of the p latch circuits 214 is provided corresponding to one of the p registers 212. Each of the latch circuits 214 simultaneously latches the print data [SIH, SIL] held in each of the p registers 212 at the rising edge of the latch signal LAT, and outputs the data to the corresponding decoder 216.

[0101] Figure 7 is a diagram showing an example of the decoded content in the decoder 216. The decoder 216 generates and outputs selection signals S1 and S2 by decoding the print data [SIH, SIL] latched by the latch circuit 214 according to the content shown in Figure 7. For example, when the input print data [SIH, SIL] is [1, 0], the decoder 216 outputs the logic level of the selection signal S1 to the selection circuit 230 as H and L levels during periods T1 and T2, and outputs the logic level of the selection signal S2 to the selection circuit 230 as L and H levels during periods T1 and T2.

[0102] A selection circuit 230 is provided corresponding to each of the p discharge sections 600. That is, the drive signal selection circuit 200 has p selection circuits 230, the same number as the p discharge sections 600. Fig. 8 is a diagram showing the configuration of a selection circuit 230 corresponding to one discharge section 600. As shown in Fig. 8, the selection circuit 230 includes inverters 232a and 232b, which are NOT circuits, and transfer gates 234a and 234b.

[0103] The selection signal S1 is input to a positive control terminal (not marked with a circle) of the transfer gate 234a, and is logically inverted by the inverter 232a before being input to a negative control terminal (marked with a circle) of the transfer gate 234a. A drive signal COMA, which is the drive voltage signal VDR1, is supplied to an input terminal of the transfer gate 234a. The selection signal S2 is input to a positive control terminal (not marked with a circle) of the transfer gate 234b, and is logically inverted by the inverter 232b before being input to a negative control terminal (marked with a circle) of the transfer gate 234b. A drive signal COMB, which is the drive voltage signal VDR2, is supplied to an input terminal of the transfer gate 234b. The output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected. A signal at a connection terminal where the output terminals of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected, is output as the drive signal VOUT.

[0104] Specifically, when the selection signal S1 is at an H level, conduction occurs between the input terminal and output terminal of the transfer gate 234a, and when the selection signal S1 is at an L level, conduction does not occur between the input terminal and output terminal of the transfer gate 234a. Furthermore, when the selection signal S2 is at an H level, conduction occurs between the input terminal and output terminal of the transfer gate 234b, and when the selection signal S2 is at an L level, conduction does not occur between the input terminal and output terminal of the transfer gate 234b. That is, the selection circuit 230 switches the conduction state between the input terminal and output terminal of the transfer gates 234a and 234b based on the selection signals S1 and S2, and selects or deselects the signal waveforms of the drive signals COMA and COMB supplied to the input terminals of the transfer gates 234a and 234b, thereby generating a drive signal VOUT at a connection terminal where the output terminal of the transfer gate 234a and the output terminal of the transfer gate 234b are commonly connected.

[0105] The operation of the drive signal selection circuit 200 will be described using FIG. 9. FIG. 9 is a diagram for explaining the operation of the drive signal selection circuit 200. The print data [SIH, SIL] included in the print data signal SI is input serially in synchronization with the clock signal SCK. The print data [SIH, SIL] is then transferred sequentially in synchronization with the clock signal SCK by the registers 212 that form a shift register corresponding to the p ejection units 600. Thereafter, the supply of the clock signal SCK is stopped, and the registers 212 hold the print data [SIH, SIL] corresponding to each of the p ejection units 600. The print data [SIH, SIL] included in the print data signal SI is input in the order corresponding to the pth, ..., 2nd, and 1st stages of the registers 212 that form the shift register.

[0106] Then, when the latch signal LAT rises, the latch circuits 214 simultaneously latch the print data [SIH, SIL] held in the registers 212. In Fig. 9, LS1, LS2, ..., LSp indicate the print data [SIH, SIL] latched by the latch circuits 214 corresponding to the first, second, ..., pth stage registers 212.

[0107] The decoder 216 outputs the logic levels of the selection signals S1 and S2 as shown in FIG. 7 during the periods T1 and T2, respectively, according to the dot size defined by the latched print data [SIH, SIL].

[0108] Specifically, when the input print data [SIH,SIL] is [1,1], the decoder 216 sets the selection signal S1 to H,H level during periods T1 and T2, and sets the selection signal S2 to L,L level during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 during period T1, and selects the trapezoidal waveform Adp2 during period T2. As a result, the drive signal VOUT corresponding to the large dot LD shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0109] Furthermore, when the input print data [SIH, SIL] is [1, 0], the decoder 216 sets the selection signal S1 to H and L levels during periods T1 and T2, and sets the selection signal S2 to L and H levels during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 during period T1, and selects the trapezoidal waveform Bdp2 during period T2. As a result, the drive signal VOUT corresponding to the medium dot MD shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0110] Furthermore, when the input print data [SIH, SIL] is [0, 1], the decoder 216 sets the selection signal S1 to H and L levels during periods T1 and T2, and sets the selection signal S2 to L and L levels during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Adp1 during period T1, and selects neither the trapezoidal waveforms Adp2 nor Bdp2 during period T2. As a result, the output terminal of the selection circuit 230 generates a drive signal VOUT corresponding to the small dot SD shown in FIG. 5.

[0111] Furthermore, when the input print data [SIH,SIL] is [0,0], the decoder 216 sets the selection signal S1 to L,L levels during periods T1 and T2, and sets the selection signal S2 to H,L levels during periods T1 and T2. In this case, the selection circuit 230 selects the trapezoidal waveform Bdp1 during period T1, and selects neither the trapezoidal waveforms Adp2 nor Bdp2 during period T2. As a result, the drive signal VOUT corresponding to the non-printing ND shown in FIG. 5 is generated at the output terminal of the selection circuit 230.

[0112] As described above, the drive signal selection circuit 200 receives the print data signal SI and the clock signal SCK Based on the latch signal LAT and the change signal CH, the drive signal VOUT is generated and output by selecting the signal waveforms of the drive signal COMA, which is the drive voltage signal VDR1 in the printing process, and the drive signal COMB, which is the drive voltage signal VDR2 in the printing process. In other words, the drive signal VOUT is an example of a drive signal. Also, considering that the drive signal VOUT is generated by selecting the waveforms of the drive signals COMA and COMB, the drive signals COMA and COMB can also be considered as examples of drive signals.

[0113] 1.5 Structure of the liquid ejection device 1.5.1 Structure of the liquid ejection device Next, an example of the structure of the liquid ejection device 1 will be described. FIG. 10 is a diagram showing a schematic structure of the liquid ejection device 1. FIG. 10 shows arrows indicating the mutually perpendicular X, Y, and Z directions. Here, the Y direction corresponds to the transport direction in which the medium P is transported, the X direction is a direction perpendicular to the Y direction and parallel to the horizontal plane, which corresponds to the main scanning direction, and the Z direction is the up-down direction of the liquid ejection device 1, which corresponds to the vertical direction. Furthermore, in the following description, when specifying the directions along the X, Y, and Z directions, the tip side of the arrow indicating the X direction will be referred to as the +X side and the starting side as the -X side, the tip side of the arrow indicating the Y direction will be referred to as the +Y side and the starting side as the -Y side, and the tip side of the arrow indicating the Z direction will be referred to as the +Z side and the starting side as the -Z side.

[0114] 10, the liquid ejection device 1 includes the above-mentioned main control unit 10, ejection control unit 20, and m print heads 100, as well as a liquid container 5, a pump 8, and a transport mechanism 40. In the following description, the liquid ejection device 1 will be described taking as an example a case where the multiple print heads 100 include six print heads 100, print heads 100-1 to 100-6.

[0115] The main control unit 10 is supplied with an AC voltage AC, which is a commercial AC voltage, from a commercial AC power source 7 provided outside the liquid ejection device 1. The liquid ejection device 1 starts operating using the AC voltage AC as its power supply voltage. Image data PD is also input to the main control unit 10 from an external device 3, such as a host computer provided outside the liquid ejection device 1, via a LAN (Local Area Network) cable or a USB (Universal Serial Bus) cable. The main control unit 10 generates an image information signal IP based on the input image data PD and outputs it to the ejection control unit 20. The main control unit 10 also controls the transport of the medium P by outputting a transport control signal TC to a transport mechanism 40 that transports the medium P, and controls the operation of the pump 8 by outputting a pump control signal AIR to the pump 8.

[0116] The liquid containers 5 store ink to be ejected onto the medium P. Specifically, the liquid containers 5 include four containers that store ink of four colors: cyan C, magenta M, yellow Y, and black K. The ink stored in the liquid containers 5 is supplied to the ejection control unit 20 via ink flow paths such as tubes. Note that the number of containers that store ink in the liquid containers 5 is not limited to four, and the colors of the stored ink are not limited to the four colors: cyan C, magenta M, yellow Y, and black K.

[0117] The ejection control unit 20 distributes ink supplied via ink flow paths such as tubes to each of the print heads 100-1 to 100-6, and generates various signals for driving each of the print heads 100-1 to 100-6 based on the image information signal IP supplied from the main control unit 10, and supplies these signals to the print heads 100-1 to 100-6.

[0118] The print heads 100-1 to 100-6 are located on the +Z side of the discharge control unit 20, and are arranged along the X direction from the -X side to the +X side, starting with print head 100-1. Print head 100-1, print head 100-2, print head 100-3, print head 100-4, print head 100-5, and print head 100-6 are arranged in this order so that their width is equal to or greater than the width of the medium P. Print heads 100-1 to 100-6 eject ink supplied via the ejection control unit 20 and ink flow paths such as tubes, based on various signals input from the ejection control unit 20. The number of print heads 100 included in the liquid ejection device 1 is not limited to six, and may be five or fewer, or seven or more.

[0119] The transport mechanism 40 transports the medium P along the Y direction based on a transport control signal TC input from the main control unit 10. Such a transport mechanism 40 is configured to include rollers (not shown) for transporting the medium P, a motor for driving the rollers to rotate, and the like.

[0120] The pump 8 controls whether or not to supply air to the discharge control unit 20 and the amount of air to be supplied, based on a pump control signal AIR input from the main control unit 10. The pump 8 is connected to the discharge control unit 20, for example, via one or more tubes. The pump 8 controls the opening and closing of valves in the discharge control unit 20 by controlling the air flowing through each tube. In the following description, the pump 8 is connected to the discharge control unit 20 via two tubes.

[0121] As described above, in the liquid ejection device 1, the main control unit 10 generates an image information signal IP based on image data PD input from an external device 3 such as a host computer, supplies the image information signal IP to the ejection control unit 20, and controls the transport of the medium P in the transport mechanism 40 using a transport control signal TC. The ejection control unit 20 also controls the ejection of ink from the print heads 100-1 to 100-6 based on the input image information signal IP. In this way, the liquid ejection device 1 controls the transport of the medium P and the timing of ink ejection, causing ink to land at desired positions on the medium P. As a result, a desired image is formed on the medium P.

[0122] 1.5.2 Structure of the discharge control unit Next, an example of the structure of the ejection control unit 20 will be described, which distributes ink supplied from the liquid container 5 via an ink flow path such as a tube to each of the print heads 100-1 to 100-6, and drives each of the print heads 100-1 to 100-6 based on an image information signal IP supplied from the main control unit 10.

[0123] Fig. 11 is a diagram showing an example of the structure of the discharge control unit 20. Fig. 11 also shows the discharge control unit 20, as well as print heads 100-1 to 100-6 located on the +Z side of the discharge control unit 20, and cables FC1 and FC2 that electrically connect the discharge control unit 20 to the print heads 100-1 to 100-6, respectively.

[0124] 11, the ejection control unit 20 has an inlet flow path portion G1 that introduces ink supplied from the liquid container 5, a supply control portion G2 that controls the supply of the introduced ink to the print heads 100-1 to 100-6, a head support portion G3 to which the print heads 100-1 to 100-6 are fixed, and an ejection control portion G4 that controls the ejection of ink from the print heads 100-1 to 100-6. The inlet flow path portion G1, supply control portion G2, head support portion G3, and ejection control portion G4 are stacked in this order along the Z direction from the -Z side to the +Z side: ejection control portion G4, inlet flow path portion G1, supply control portion G2, head support portion G3, and are fixed by fixing means such as an adhesive or screws (not shown).

[0125] The introduction flow path section G1 has a plurality of liquid inlets IS1 corresponding to the number of ink colors supplied to the discharge control unit 20, and a plurality of liquid outlets ID1 corresponding to the number of ink colors and the number of print heads 100. Each of the plurality of liquid inlets IS1 is located on the -Z side of the introduction flow path section G1. The liquid inlets IS1 are located on the +Z side of the inlet flow path section G1. Ink is supplied to the liquid container 5 via tubes (not shown) or the like. The liquid outlets ID1 are located on the +Z side of the inlet flow path section G1. The liquid outlets ID1 discharge ink supplied to the ejection control unit 20 to each of the print heads 100 included in the liquid ejection device 1. That is, the inlet flow path section G1 has a number of liquid outlets ID1 corresponding to the product of the number of print heads 100 included in the liquid ejection device 1 and the number of ink colors supplied to the ejection control unit 20. Specifically, in this embodiment, when the liquid ejection device 1 has six print heads 100 and four colors of ink are supplied to the ejection control unit 20, the inlet flow path section G1 has 24 liquid outlets ID1. Within the inlet flow path section G1, ink flow paths are formed that connect the liquid inlets IS1 to the liquid outlets ID1 for each ink color.

[0126] The introduction flow path section G1 also has a plurality of air inlets AS1 and a plurality of air outlets AD1. Each of the plurality of air inlets AS1 is provided on the -Z side surface of the introduction flow path section G1 and is connected to the pump 8 via a tube (not shown). Each of the plurality of air outlets AD1 is provided on the +Z side surface of the introduction flow path section G1. The plurality of air outlets AD1 discharge air supplied to the discharge control unit 20 in a manner corresponding to each of the plurality of print heads 100 included in the liquid ejection device 1. An air flow path is formed inside the introduction flow path section G1, connecting the single air inlet AS1 and the plurality of air outlets AD1 corresponding to the print heads 100.

[0127] The supply control unit G2 has a plurality of pressure adjustment units U corresponding to the plurality of print heads 100 of the liquid ejection device 1. Each of the plurality of pressure adjustment units U also has a plurality of liquid inlets IS2 corresponding to the number of ink colors supplied to the ejection control unit 20, and an outlet (not shown) corresponding one-to-one to the plurality of liquid inlets IS2.

[0128] Each of the multiple liquid inlets IS2 is located on the -Z side of the pressure adjustment unit U, corresponding to each of the liquid outlets ID1 of the introduction flow path portion G1, and is connected to each of the corresponding liquid outlets ID1. Also, each of the multiple outlets (not shown) is located on the -Z side of the pressure adjustment unit U. Then, inside the pressure adjustment unit U, an ink flow path is formed that connects one liquid inlet IS2 and one outlet (not shown).

[0129] Each of the multiple pressure adjustment units U has multiple air inlets AS2 corresponding to the number of tubes connected to the pump 8. Each of the multiple air inlets AS2 is located on the -Z side of the pressure adjustment unit U, corresponding to one of the air outlets AD1 of the introduction flow path section G1, and is connected to the corresponding air outlet AD1. Inside the pressure adjustment unit U, there are provided valves (not shown) that open and close the ink flow paths, and adjustment valves (not shown) that adjust the pressure of ink flowing through the ink flow paths. The pressure adjustment unit U controls the operation of these valves and adjustment valves using air supplied from the air inlet AS2, thereby controlling the amount of ink flowing through an ink flow path (not shown) that communicates with a liquid inlet IS2 and an outlet (not shown).

[0130] The head support part G3 has a support member 35 that supports the print heads 100-1 to 100-6 of the liquid ejection device 1. The support member 35 supports each of the print heads 100-1 to 100-6 on the +Z side by fixing them with fixing means such as adhesive or screws (not shown).

[0131] The support member 35 has openings 353 formed corresponding to the liquid inlets IS3 (described later) of the print heads 100-1 to 100-6. The liquid inlets IS3 (described later) of the print heads 100-1 to 100-6 are inserted through the openings 353. The print heads 100-1 to 100-6 have liquid inlets IS3 (described later) that are connected to the respective discharge ports (not shown) of the supply control unit G2.

[0132] Ink stored in the liquid container 5 is supplied to the print heads 100-1 to 100-6 via the inlet flow path G1, supply control unit G2, and head support unit G3 configured as described above. Specifically, the ink stored in the liquid container 5 is supplied to the liquid inlet port IS1 of the inlet flow path G1 via a tube or the like (not shown). The ink supplied to the liquid inlet port IS1 is distributed to the print heads 100-1 to 100-6 by ink flow paths (not shown) provided inside the inlet flow path G1, and then supplied to the liquid inlet port IS2 of the pressure adjustment unit U via the liquid outlet ID1. The ink supplied to the liquid inlet port IS2 is supplied to the liquid inlet port IS3 of each of the print heads 100-1 to 100-6 supported by the head support unit G3 via the ink flow paths provided inside the pressure adjustment unit U and an outlet (not shown). That is, ink supplied from the liquid container 5 is branched at the introduction flow path section G1, and then the amount of ink supplied is controlled by the supply control section G2, and the ink is supplied to the print heads 100-1 to 100-6 supported by the head support section G3.

[0133] The discharge control section G4 is located on the −Z side of the introduction channel section G1, and has a wiring substrate 410 and a wiring substrate 420.

[0134] The wiring substrate 410 includes a surface 411 and a surface 412 located opposite to the surface 411. The wiring substrate 410 is disposed such that the surface 412 faces the introduction flow path section G1, the supply control section G2, and the head support section G3, and the surface 411 faces the side opposite the introduction flow path section G1, the supply control section G2, and the head support section G3.

[0135] A drive voltage output circuit 50 that outputs drive voltage signals VDR1 and VDR2 is provided on a surface 411 of the wiring board 410. A connection portion 413 is provided on a surface 412 of the wiring board 410. The connection portion 413 electrically connects the wiring board 410 and the wiring board 420, and transmits the drive voltage signals VDR1 and VDR2 generated by the drive voltage output circuit 50 to the wiring board 420, and also transmits a plurality of signals to the wiring board 410, including basic drive signals dA and dB that form the basis of the drive voltage signals VDR1 and VDR2 output by the drive voltage output circuit 50.

[0136] The wiring substrate 420 includes a surface 421 and a surface 422 located opposite to the surface 421. The wiring substrate 420 is arranged such that the surface 422 faces the introduction flow path section G1, the supply control section G2, and the head support section G3, and the surface 421 faces the side opposite to the introduction flow path section G1, the supply control section G2, and the head support section G3.

[0137] A semiconductor device 428 and connection portions 423, 426, and 427 are provided on a surface 421 of the wiring board 420. The connection portion 423 is connected to a connection portion 413 provided on the wiring board 410. This electrically connects the wiring board 420 to the wiring board 410. For the connection portions 413 and 423, BtoB (Board To Board) connectors are used, which directly and electrically connect the wiring board 410 and the wiring board 420 without using a cable. The semiconductor device 428 is a circuit component that constitutes at least a part of the aforementioned discharge control circuit 21, and is formed, for example, by an SoC or the like. The semiconductor device 428 is provided in an area on the −X side of the wiring board 420 relative to the connection portion 423. The connection portion 426 receives voltages VHV and VDD, which function as power supply voltages for the discharge control unit 20. The connection portion 426 is located on the −Y side of the semiconductor device 428. The connection portion 427 receives an image information signal IP output by the main control unit 10. That is, the connection portion 427 has a plurality of terminals through which the input image information signal IP propagates. Such a connection portion 427 is located on the -Y side of the semiconductor device 428 and on the -X side of the connection portion 426. Here, the connection portions 426 and 427 may consist of one connection.

[0138] A surface 422 of the wiring substrate 420 is provided with a plurality of connection parts 424, the same number as the print heads 100 of the liquid ejection device 1, and a plurality of connection parts 425, the same number as the print heads 100 of the liquid ejection device 1. The plurality of connection parts 424 are arranged side by side along the −Y side of the wiring substrate 420, and the plurality of connection parts 425 are arranged side by side along the +Y side of the wiring substrate 420. Various control signals generated by the ejection control unit G4 are output via the connection parts 424, 425.

[0139] One end of a cable FC1 is connected to the connection part 424. The cable FC1 passes through the introduction flow path part G1, the supply control part G2, and the -Y side of the head support part G3, and is inserted through an opening part 351 provided in the head support part G3, thereby electrically connecting to each of the multiple print heads 100 located on the -Z side of the head support part G3.

[0140] One end of a cable FC2 is connected to the connection portion 425. The cable FC2 passes through the introduction channel portion G1, the supply control portion G2, and the +Y side of the head support portion G3, and is inserted through an opening 352 provided in the head support portion G3, thereby electrically connecting to each of the multiple print heads 100 located on the -Z side of the head support portion G3. That is, the cables FC1 and FC2 are provided in the same number as the print heads 100, and transmit various control signals generated by the discharge control portion G4 to the corresponding print heads 100. Such cables FC1 and FC2 are configured, for example, by a flexible flat cable (FFC) or a flexible printed circuit (FPC).

[0141] In the discharge control unit 20 configured as described above, an image information signal IP input from the main control unit 10 is supplied to the discharge control unit G4. The semiconductor device 428 and peripheral circuits (not shown) included in the discharge control unit G4 generate voltages VHV and VDD for controlling the operation of the print heads 100-1 to 100-6, diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, ..., SIm1 to SImn, clock signals SCK1 to SCKm, latch signal LAT, and change signal CH based on the image information signal IP input from the main control unit 10, as well as basic drive signals dA and dB. The basic drive signals dA and dB are supplied to a drive voltage output circuit 50 provided on a wiring board 410. The drive voltage output circuit 50 generates drive voltage signals VDR1 and VDR2 and a reference voltage signal VBS and outputs them to the wiring board 420. The discharge control unit G4 then supplies the generated diagnostic control signals HC1 to HCm, print data signals SI11 to SI1n, ..., SIm1 to SImn, clock signals SCK1 to SCKm, latch signal LAT, change signal CH, drive voltage signals VDR1, VDR2, reference voltage signal VBS, and voltages VHV, VDD to the corresponding print heads 100-1 to 100-6 via the corresponding cables FC1, FC2.

[0142] In this embodiment, the discharge control unit 20 and one print head 100 are connected by two signal cables, cable FC1 and cable FC2, but the discharge control unit 20 and one print head 100 may be electrically connected by three or more signal cables, or may be electrically connected by one signal cable. In the following description, the cables FC1 and FC2 are assumed to be flexible flat cables.

[0143] Next, an example of the arrangement of the print heads 100-1 to 100-6 supported by the head support part G3 will be described. Fig. 12 is a diagram showing an example of the arrangement of the print heads 100-1 to 100-6. As shown in Fig. 12, each of the multiple print heads 100-1 to 100-6 has six head chips 300 arranged side by side along the X direction. Head chip 300 has a plurality of nozzles 651 that eject ink and are arranged side by side along a row direction RD in a direction perpendicular to the Z direction and on a plane formed by the X and Y directions. In the following description, the plurality of nozzles 651 arranged side by side along the row direction RD may be referred to as a nozzle row.

[0144] Head chip 300 has two rows of nozzles along the row direction RD. The two rows of nozzles 651 of print head 100 include a group that ejects cyan (C) ink, a group that ejects magenta (M) ink, a group that ejects yellow (Y) ink, and a group that ejects black (K) ink. Note that the number of head chips 300 that each of print heads 100-1 to 100-6 has is not limited to six.

[0145] 1.5.3 Printhead Structure Next, the structure of print heads 100-1 to 100-6 will be described. As mentioned above, print heads 100-1 to 100-6 all have the same configuration, and in the following description, print heads 100-1 to 100-6 will be simply referred to as print heads 100.

[0146] Fig. 13 is a diagram showing an example of the structure of print head 100. As shown in Fig. 13, print head 100 includes filter section 110, sealing member 120, wiring board 130, holder 140, six head chips 300, and fixing plate 150. Print head 100 is configured by stacking filter section 110, sealing member 120, wiring board 130, holder 140, and fixing plate 150 in this order along the Z direction from the -Z side to the +Z side, and six head chips 300 are housed between holder 140 and fixing plate 150.

[0147] The filter section 110 has a generally parallelogram shape with two opposing sides extending along the X direction and two opposing sides extending along the column direction RD. The filter section 110 has four filters 113 and four liquid inlets IS3. The four liquid inlets IS3 are located on the -Z side of the filter section 110, corresponding to the four filters 113 located inside the filter section 110. Ink is supplied to the four liquid inlets IS3 from the liquid container 5 via the ejection control unit 20, and the filters 113 collect air bubbles and foreign matter contained in the ink introduced from the liquid inlets IS3.

[0148] Openings 115 and 117 are also formed in the filter unit 110. Opening 115 opens along the edge on the -Y side of the filter unit 110, and communicates with opening 351 provided in the head support unit G3 when the print head 100 is supported by the head support unit G3. Opening 117 opens along the edge on the +Y side of the filter unit 110, and communicates with opening 352 provided in the head support unit G3 when the print head 100 is supported by the head support unit G3.

[0149] The sealing member 120 is located on the +Z side of the filter section 110 and has a generally parallelogram shape with two opposing sides extending along the X direction and two opposing sides extending along the column direction RD. Through-openings 123, through which liquid flow paths 145 (described later) are inserted, are provided at the four corners of the sealing member 120. The sealing member 120 is formed of an elastic material such as rubber. Openings 125 and 127 are formed in the sealing member 120. Opening 125 opens along the −Y side of the sealing member 120 and communicates with opening 115 formed in the filter section 110. Opening 127 opens along the +Y side of the sealing member 120 and communicates with opening 117 formed in the filter section 110.

[0150] The wiring substrate 130 is located on the +Z side of the sealing member 120, and has a generally parallelogram shape with two opposing sides extending along the X direction and two opposing sides extending along the column direction RD. Fig. 14 is a diagram showing an example of the configuration of the wiring substrate 130. Note that in Fig. 14, the configuration of the wiring substrate 130 when viewed from the -Z side is shown by solid lines, and parts of the configuration that cannot be seen when viewing the wiring substrate 130 from the -Z side are shown by dashed lines.

[0151] 14, the wiring board 130 includes a substrate 400, connectors CN1 and CN2, and a semiconductor device 450. In addition to the substrate 400, connectors CN1 and CN2, and semiconductor device 450, the wiring board 130 may include electronic components (not shown) such as a resistive element, a capacitive element, an inductive element, and a semiconductor element.

[0152] Substrate 400 has a generally parallelogram shape having sides 403 and 404 facing each other, and sides 405 and 406 facing each other, and has a surface 401 and a surface 402 that is different from surface 401 and facing surface 401. Substrate 400 is provided such that side 403 extends along the X direction, side 404 is located on the +Y side of side 403 and extends along the X direction, side 405 extends along the column direction RD, and side 406 is located on the −X side of side 405 and extends along the column direction RD, with surface 401 on the −Z side and surface 402 on the +Z side. That is, substrate 400 is positioned such that sides 403 and 404 face each other in the Y direction, sides 405 and 406 face each other in the X direction, and surface 401 faces upward and surface 402 faces downward in the vertical direction. In this case, substrate 400 is preferably positioned such that surface 401 is perpendicular to the vertical direction.

[0153] Furthermore, notches 135 are formed at the four corners of substrate 400. A liquid flow path 145 provided in holder 140, which will be described later, passes through notch 135. Here, notch 135 may be configured to be able to connect liquid flow path 145 provided in holder 140 located on the +Z side of substrate 400 to liquid inlet port IS3 of filter section 110 located on the -Z side of substrate 400 so that they can communicate with each other, and may be, for example, a hole provided to penetrate surface 401 and surface 402 to allow liquid flow path 145 to pass through.

[0154] Furthermore, the substrate 400 is formed with four FPC insertion holes 136 penetrating the surfaces 401 and 402 of the substrate 400, and two FPC cutout portions 137 formed by cutting out a portion of each of the sides 405 and 406 of the substrate 400. A flexible wiring substrate 346 provided on each of the six head chips 300 (described later) passes through each of the four FPC insertion holes 136 and the FPC cutout portions 137. The flexible wiring substrates 346 that pass through each of the four FPC insertion holes 136 and the FPC cutout portions 137 are electrically connected to connection terminals 138 formed on the surface 401 of the substrate 400.

[0155] The substrate 400 may be a so-called multi-layer substrate that includes a plurality of wiring layers between a surface 401 and a surface 402 positioned opposite the surface 401 .

[0156] Connector CN1 has a plurality of terminals TM1. Connector CN1 is provided on surface 401 of substrate 400 so that the plurality of terminals TM1 are aligned along side 403. In print head 100, connector CN1 passes through opening 115 formed in filter unit 110 and opening 125 formed in seal member 120, and is exposed on the -Z side of print head 100. Connector CN2 has a plurality of terminals TM2. Connector CN2 is provided on surface 401 of substrate 400 so that the plurality of terminals TM2 are aligned along side 404. In print head 100, connector CN2 passes through opening 117 formed in filter unit 110 and opening 127 formed in seal member 120, and is exposed on the -Z side of print head 100.

[0157] Furthermore, a semiconductor device 450 is located on the surface 402 of the substrate 400. The semiconductor device 450 constitutes at least a part of the abnormality detection circuit 250 described above. Such a semiconductor device 450 is a surface-mounted component, and is electrically connected to the substrate 400 via bump electrodes, for example. Note that the semiconductor device 450 is a surface-mounted component, and may be, for example, a QFN (Quad Flat No-Leaded Package) that is electrically connected to the substrate 400 via multiple electrodes formed along the four sides of the semiconductor device 450, or may be a QFP (Quad Flat Package) that is electrically connected to the substrate 400 via multiple terminals instead of the multiple electrodes of the QFN.

[0158] If an abnormality occurs in semiconductor device 450 that constitutes at least a part of abnormality detection circuit 250, there is a risk that an operational abnormality in print head 100 cannot be properly detected. In this embodiment, semiconductor device 450 that constitutes at least a part of abnormality detection circuit 250 is provided on surface 402 located below substrate 400, thereby reducing the risk that ink mist floating inside will adhere to semiconductor device 450 and that ink leaked inside print head 100 will adhere to semiconductor device 450, thereby reducing the risk of an operational abnormality caused by adhesion of ink mist to semiconductor device 450 that constitutes at least a part of abnormality detection circuit 250.

[0159] 13, the holder 140 is located on the +Z side of the wiring substrate 130 and has a generally parallelogram shape with two opposing sides extending along the X direction and two opposing sides extending along the column direction RD. The holder 140 has holder members 141, 142, and 143. The holder members 141, 142, and 143 are stacked in this order along the Z direction from the -Z side to the +Z side: holder member 141, holder member 142, and holder member 143. The holder members 141 and 142, and the holder members 142 and 143, are bonded together with an adhesive or the like.

[0160] An accommodation space (not shown) having an opening on the +Z side is formed inside holder member 143. Head chips 300 are accommodated in the accommodation space formed inside holder member 143. Here, the accommodation space formed inside holder member 143 may be multiple spaces capable of individually accommodating each of six head chips 300, or may be one space capable of commonly accommodating six head chips 300.

[0161] Moreover, holder 140 is provided with slit holes 146 corresponding to each of six head chips 300. Flexible wiring boards 346, which will be described later, of each of six head chips 300 pass through these slit holes 146. That is, slit holes 146 formed in holder 140 are provided corresponding to four FPC insertion holes 136 and FPC cutout portions 137 of wiring board 130.

[0162] Furthermore, four liquid flow paths 145 are provided at the four corners of the -Z side surface of holder 140. Each of liquid flow paths 145 passes through cutout portion 135 of wiring substrate 130, and is inserted through through opening 123 provided in seal member 120 to be connected to filter section 110.

[0163] The fixed plate 150 is located on the +Z side of the holder 140, and seals the storage space formed inside the holder member 143 to store the six head chips 300. The fixed plate 150 has a flat portion 151 and bent portions 152, 153, and 154. The flat portion 151 has a generally parallelogram shape with two opposing sides extending along the X direction and two opposing sides extending along the row direction RD. Six openings 155 are formed in the flat portion 151 to expose the head chips 300. The head chips 300 are fixed to the fixed plate 150 so that two nozzle rows are exposed on the +Z side of the print head 100 through the openings 155 in the flat portion 151. do.

[0164] The bent portion 152 is a member that is connected to one side of the flat portion 151 extending along the X direction and is bent toward the -Z side, and is integral with the flat portion 151; the bent portion 153 is a member that is connected to one side of the flat portion 151 extending along the column direction RD and is bent toward the -Z side, and the bent portion 154 is a member that is connected to the other side of the flat portion 151 extending along the column direction RD and is bent toward the -Z side, and is integral with the flat portion 151.

[0165] Head chip 300 is located on the +Z side of holder 140 and on the -Z side of fixed plate 150. Head chip 300 is housed in a housing space formed by holder member 143 of holder 140 and fixed plate 150, and is fixed to holder member 143 and fixed plate 150.

[0166] FIG. 15 is a diagram showing a schematic structure of the head chip 300. Note that FIG. 15 shows a cross section of the head chip 300 when the head chip 300 is cut in a direction perpendicular to the column direction RD so as to include at least one nozzle 651. As shown in FIG. 15, the head chip 300 has a nozzle plate 310 provided with a plurality of nozzles 651 that eject ink, a flow path forming substrate 321 that defines a communication flow path 365, individual flow paths 363, and a reservoir 367, a pressure chamber substrate 322 that defines a pressure chamber 369, a protection substrate 323, a compliance section 330, a vibration plate 340, a piezoelectric element 60, a flexible wiring substrate 346, and a case 324 that defines the reservoir 367 and the liquid inlet 361. That is, the print head 100 has a piezoelectric element 60 as an example of a drive element.

[0167] Ink is supplied to the head chip 300 from a discharge port (not shown) provided in the holder 140 via a liquid inlet 361. The ink supplied to the head chip 300 reaches the nozzle 651 via an ink flow path 360 configured to include a reservoir 367, an individual flow path 363, a pressure chamber 369, and a communication flow path 365. The ink that has reached the nozzle 651 is then ejected as the piezoelectric element 60 is driven.

[0168] Specifically, the ink flow path 360 is configured by stacking a flow path forming substrate 321, a pressure chamber substrate 322, and a case 324 along the Z direction. Ink introduced into the case 324 from the liquid inlet 361 is stored in a reservoir 367. The reservoir 367 is a common flow path that communicates with a plurality of individual flow paths 363 corresponding to each of the plurality of nozzles 651 that make up the nozzle row. The ink stored in the reservoir 367 is supplied to the pressure chamber 369 via the individual flow paths 363.

[0169] The pressure chamber 369 applies pressure to the ink stored therein, causing the ink supplied to the pressure chamber 369 to be ejected from the nozzle 651 via the communication channel 365. A vibration plate 340 is located on the −Z side of the pressure chamber 369 so as to seal the pressure chamber 369, and a piezoelectric element 60 is located on the −Z side of the vibration plate 340. The piezoelectric element 60 is composed of a piezoelectric body and a pair of electrodes formed on both sides of the piezoelectric body. A drive signal VOUT is supplied to one of the pair of electrodes of the piezoelectric element 60 via a flexible wiring board 346, and a reference voltage signal VBS is supplied to the other of the pair of electrodes of the piezoelectric element 60 via the flexible wiring board 346. The piezoelectric body is displaced in accordance with the potential difference generated between the pair of electrodes. In other words, the piezoelectric element 60, including the piezoelectric body, is driven. As the piezoelectric element 60 is driven, the vibration plate 340 on which the piezoelectric element 60 is mounted deforms, causing the internal pressure of the pressure chamber 369 to change, and as a result, the ink stored in the pressure chamber 369 is ejected from the nozzle 651 via the communicating flow path 365.

[0170] Further, on the +Z side of the flow path forming substrate 321, a nozzle plate 310 and a compliance The nozzle plate 310 is located on the +Z side of the communication flow path 355. The nozzle plate 310 has a plurality of nozzles 651 arranged in a row in the column direction RD. That is, the nozzle plate 310 has a plurality of nozzles 651 that eject ink. The compliance section 330 is located on the +Z side of the reservoir 367 and the individual flow path 363, and includes a sealing film 331 and a support 332. The sealing film 331 is a flexible film-like member that seals the +Z side of the reservoir 367 and the individual flow path 363. The outer periphery of the sealing film 331 is supported by a frame-shaped support 332. The +Z side of the support 332 is fixed to the flat portion 151 of the fixing plate 150. The compliance section 330 configured as described above protects the head chip 300 and reduces pressure fluctuations of ink inside the reservoir 367 and the individual flow path 363.

[0171] Here, the configuration including the piezoelectric element 60 , the vibration plate 340 , the nozzle 651 , the individual flow path 363 , the pressure chamber 369 , and the communication flow path 365 corresponds to the ejection section 600 .

[0172] Furthermore, a semiconductor device 201 is mounted on the flexible wiring substrate 346 using COF (Chip On Film) technology. The semiconductor device 201 includes a drive signal selection circuit 200. The print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the change signal CH, the drive voltage signals VDR1 and VDR2, and the voltages VHV and VDD are propagated through the flexible wiring substrate 346 and supplied to the semiconductor device 201. The semiconductor device 201 generates drive signals VOUT corresponding to each of the plurality of piezoelectric elements 60 based on the supplied print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the change signal CH, the drive voltage signals VDR1 and VDR2, and the voltages VHV and VDD. The semiconductor device 201 then supplies the generated drive signals VOUT to the piezoelectric elements 60 via the flexible wiring substrate 346.

[0173] The ink distributed in the ejection control unit 20 is supplied to the print head 100 via four liquid inlets IS3. The ink supplied to the print head 100 has air bubbles and foreign matter removed by a filter 113, and is then supplied to the holder 140 via four liquid channels 145. The holder 140 branches the supplied ink corresponding to the head chips 300 and supplies it to liquid inlets 361 of the head chips 300 via outlets (not shown) provided in a storage space formed inside the holder member 143. In this way, the ink distributed in the ejection control unit 20 is supplied to the head chip 300. The ink supplied to the head chip 300 then reaches the nozzles 651 via ink channels 360 configured to include a reservoir 367, individual channels 363, pressure chambers 369, and communication channels 365.

[0174] The other end of cable FC1 passes through introduction flow path section G1, supply control section G2, and the -Y side of head support section G3, and is inserted through opening 351 provided in head support section G3, opening 115 provided in filter section 110, and opening 125 provided in seal member 120, to be electrically connected to connector CN1 provided in wiring board 130. The other end of cable FC2 passes through introduction flow path section G1, supply control section G2, and the +Y side of head support section G3, and is inserted through opening 352 provided in head support section G3, opening 117 provided in filter section 110, and opening 127 provided in seal member 120, to be electrically connected to connector CN2 provided in wiring board 130. As a result, the diagnostic control signal HC, print data signals SI1 to SIn, clock signal SCK, latch signal LAT, change signal CH, drive voltage signals VDR1, VDR2, and reference voltage signal VBS, as well as voltages VHV and VDD, output by the discharge control unit 20 are supplied to the print head 100.

[0175] The diagnostic control signal HC, print data signals SI1 to SIn, clock signal SCK, latch signal LAT, change signal CH, drive voltage signal VDR1, VDR2, reference voltage signal VBS, and voltages VHV and VDD are propagated through substrate 400 and supplied to semiconductor device 201 including drive signal selection circuit 200 via semiconductor device 450, which constitutes at least a part of abnormality detection circuit 250, connection terminal 138, and flexible wiring substrate 346. Based on the supplied signals, semiconductor device 201 generates drive signals VOUT corresponding to each piezoelectric element 60 of head chip 300 and supplies them to the corresponding piezoelectric elements 60. As a result, piezoelectric elements 60 are driven based on drive signals VOUT, and ink is ejected from nozzles 651 in response to the driving of piezoelectric elements 60.

[0176] 1.5.4 Electrical connection structure between the ejection control unit and the print head As described above, the other end of the cable FC1 of the discharge control unit 20 is electrically connected to the connector CN1 provided on the wiring board 130, and the other end of the cable FC2 is electrically connected to the connector CN2 provided on the wiring board 130. This electrically connects the discharge control unit 20 and the print head 100, and as a result, various signals output by the discharge control unit 20, including the diagnosis control signal HC, print data signals SI1 to SIn, clock signal SCK, latch signal LAT, change signal CH, drive voltage signals VDR1 and VDR2, reference voltage signal VBS, and voltages VHV and VDD, are supplied to the print head 100. Here, we will explain an example of the structure of the cables FC1 and FC2 that electrically connect the discharge control unit 20 and the print head 100, and the structure of the connectors CN1 and CN2 to which the cables FC1 and FC2 are connected, as well as an example of the electrical connection between the cables FC1 and FC2 and the connectors CN1 and CN2. In the following description, cables FC1 and FC2 are flexible flat cables with the same configuration, and will be referred to simply as cables FC unless there is a need to distinguish them. Connectors CN1 and CN2 are FFC connectors with the same configuration, and will be referred to simply as connectors CN unless there is a need to distinguish them. In other words, the following description will be given assuming that the other end of cable FC is electrically connected to connector CN.

[0177] 16 is a diagram showing a schematic structure of cable FC. Cable FC is a substantially rectangular shape having opposing short sides 191 and 192 and opposing long sides 193 and 194. Cable FC has a plurality of terminals ER1 arranged in parallel along short side 191, a plurality of terminals ER2 arranged in parallel along short side 192, and a plurality of wirings WI that electrically connect the plurality of terminals ER1 and the plurality of terminals ER2.

[0178] Specifically, q terminals ER1 are arranged side by side on the short side 191 of the cable FC, from the long side 193 toward the long side 194. Furthermore, q terminals ER2 are arranged side by side on the short side 192 of the cable FC, from the long side 193 toward the long side 194. Furthermore, q wirings WI that electrically connect each of the terminals ER1 to each of the terminals ER2 are arranged side by side on the cable FC, from the long side 193 toward the long side 194. The kth (k is any one of 1 to q) terminal ER1 from the long side 193 toward the long side 194 and the kth terminal ER2 from the long side 193 toward the long side 194 are electrically connected by the kth wiring WI from the long side 193 toward the long side 194.

[0179] Furthermore, the q wirings WI are insulated by insulators EC from one another and from the outside of the cable FC. The q terminals ER1 of the cable FC are electrically connected to the connection portions 424 and 425 of the discharge control unit 20, and the q terminals ER2 are electrically connected to the connector CN of the print head 100. Note that the configuration of the cable FC shown in FIG. 16 is merely an example and is not limited thereto. For example, the q terminals ER1 and the q terminals ER2 may be provided on different surfaces of the cable FC. The number of terminals ER1 and ER2 and wirings WI on the cable FC1 may be the same as or different from the number of terminals ER1 and ER2 and wirings WI on the cable FC2.

[0180] Here, q is an integer equal to or greater than 1, which corresponds to the number of terminals ER1, ER2 and wires WI included in the cable FC.

[0181] Next, the configuration of the connector CN will be described. FIG. 17 is a diagram showing the schematic structure of the connector CN. As shown in FIG. 17, the connector CN includes a cable attachment portion CI into which a cable FC is inserted and attached, q terminals TM electrically connected to the q terminals ER2 of the cable FC, and a housing HP that insulates the q terminals TM from one another and holds the q terminals TM, forming the cable attachment portion CI. The q terminals TM are arranged in one direction, parallel to the longitudinal direction of the cable attachment portion CI. A cable FC is attached to the cable attachment portion CI. In this case, the kth terminal ER2 of the q terminals ER2 included in the cable FC electrically contacts the kth terminal TM of the q terminals TM included in the connector CN. As a result, the cable FC and the connector CN are electrically connected. Here, the q terminals TM correspond to the terminals TM1 of the connector CN1 and the terminals TM2 of the connector CN2.

[0182] A specific example of the electrical connection between the cable FC and the connector CN will now be described with reference to FIG. 18. FIG. 18 is a diagram illustrating an example in which the cable FC is attached to the connector CN. As shown in FIG. 18, the terminal TM of the connector CN has a cable holding portion EL1, a housing insertion portion EL2, and a board attachment portion EL3. The board attachment portion EL3 is located below the connector CN and is provided between the housing HP and the board 400. The board attachment portion EL3 is electrically connected to an electrode (not shown) provided on the board 400 by, for example, soldering. The housing insertion portion EL2 passes through the interior of the housing HP. The housing insertion portion EL2 electrically connects the board attachment portion EL3 and the cable holding portion EL1. The cable holding portion EL1 has a curved shape that protrudes into the interior of the cable attachment portion CI. When the cable FC is attached to the cable attachment portion CI, the cable holding portion EL1 and the terminal ER2 are in electrical contact with each other via the contact portion Cnt. This electrically connects the cable FC and the connector CN, and as a result, the discharge control unit 20 and the print head 100 are electrically connected, and various signals are transmitted between the discharge control unit 20 and the print head 100.

[0183] 1.6 Printhead Inspection Method 1.6.1 Functional configuration of the abnormality detection circuit A method for testing whether a signal supplied to the print head 100 is normal or abnormal in the liquid ejection device 1 configured as described above will be described. In the liquid ejection device 1 of this embodiment, one test to determine whether an abnormality has occurred in the print head 100 is performed by the abnormality detection circuit 250 of the print head 100, which tests whether a signal supplied from the ejection control unit 20 to the print head 100 is normal. If the abnormality detection circuit 250 determines that the signal supplied from the ejection control unit 20 is normal, it permits the print head 100 to eject ink. If the abnormality detection circuit 250 determines that the signal supplied from the ejection control unit 20 is abnormal, it prohibits the print head 100 from ejecting ink. In other words, the abnormality detection circuit 250 permits printing if the signal supplied to the print head 100 is normal, and prohibits printing if the signal supplied to the print head 100 is abnormal. This reduces the risk of malfunction or failure of the print head 100 due to an unintended voltage signal being supplied to the print head 100.

[0184] Therefore, before explaining the method for testing whether the signal supplied to the print head 100 is normal or abnormal, we will first explain the functional configuration of the abnormality detection circuit 250, which tests whether the signal supplied to the print head 100 is normal or abnormal.

[0185] Figure 19 is a diagram showing the functional configuration of the abnormality detection circuit 250. In addition to a block diagram of the abnormality detection circuit 250 showing the functional configuration, Figure 19 also shows the discharge control unit 20 that outputs various signals to the print head 100 having the abnormality detection circuit 250, the cable FC that transmits the various signals output by the discharge control unit 20 to the print head 100, the connector CN to which the cable FC is connected, the wiring board 130 that includes the semiconductor device 450 included in the abnormality detection circuit 250, the semiconductor device 201 that includes the drive signal selection circuit 200-1 to which the output of the abnormality detection circuit 250 is supplied, and the flexible wiring board 346 on which the semiconductor device 201 is mounted. Note that Figure 19 does not show the drive signal selection circuits 200-2 to 200-6 included in the print head 100, the print data signals SI2 to SI6 input to the drive signal selection circuits 200-2 to 200-6, and the head status signals HS2 to HS6 output by the drive signal selection circuits 200-2 to 200-6.

[0186] In the following description, among the multiple wires WI included in the cable FC and the multiple terminals TM included in the connector CN, the wire WI through which the voltage VHV propagates will be referred to as wire WI-VHV, the terminal TM as terminal TM-VHV, the wire WI through which the voltage VDD propagates will be referred to as wire WI-VDD, the terminal TM as terminal TM-VDD, the wire WI through which the drive voltage signal VDR1 propagates will be referred to as wire WI-VDR1, the terminal TM as terminal TM-VDR1, the wire WI through which the drive voltage signal VDR2 propagates will be referred to as wire WI-VDR2, the terminal TM as terminal TM-VDR2, and The wiring WI through which the print data signal SI1 and the diagnosis control signal HC propagate is referred to as wiring WI-SI1 / HC, the terminal TM as terminal TM-SI1 / HC, the wiring WI through which the clock signal SCK propagates is referred to as wiring WI-SCK, the terminal TM as terminal TM-SCK, the wiring WI through which the latch signal LAT propagates is referred to as wiring WI-LAT, the terminal TM as terminal TM-LAT, the wiring WI through which the change signal CH propagates is referred to as wiring WI-CH, the terminal TM as terminal TM-CH, the wiring WI through which the judgment result signal ES propagates is referred to as wiring WI-ES, and the terminal TM as terminal TM-ES.

[0187] That is, the cable FC, which is a flexible flat cable, includes a wiring WI-VDR1 that propagates a drive voltage signal VDR1 that includes a drive signal COMA that is supplied to the piezoelectric element 60, a wiring WI-VDR2 that propagates a drive voltage signal VDR2 that includes a drive signal COMB that is supplied to the piezoelectric element 60, a wiring WI-SI1 / HC that propagates a print data signal SI1 and a diagnostic control signal HC for causing the print head 100 to print, a wiring WI-VHV that propagates a voltage VHV that is one of the power supply voltages, a wiring WI-VDD that propagates a voltage VDD that is a different power supply voltage, a wiring WI-SCK that propagates a clock signal SCK, and a wiring WI-ES that propagates a determination result signal ES that indicates whether or not there is an abnormality in the print head 100.

[0188] In addition, the connector CN to which the cable FC is attached includes a terminal TM-VDR1 that propagates a drive voltage signal VDR1 that includes a drive signal COMA that is supplied to the piezoelectric element 60, a terminal TM-VDR2 that propagates a drive voltage signal VDR2 that includes a drive signal COMB that is supplied to the piezoelectric element 60, a terminal TM-SI1 / HC that propagates a print data signal SI1 and a diagnostic control signal HC for executing printing by the print head 100, a terminal TM-VHV that propagates a voltage VHV that is one of the power supply voltages, a terminal TM-VDD that propagates a voltage VDD that is a different one of the power supply voltages, a terminal TM-SCK that propagates a clock signal SCK, and a terminal TM-ES that propagates a determination result signal ES that indicates whether or not there is an abnormality in the print head 100.

[0189] Furthermore, in the following description, of the wiring patterns formed on the flexible wiring board 346, the wiring pattern that propagates the drive voltage signal VDR1 is referred to as wiring P-VDR1, the wiring pattern that propagates the drive voltage signal VDR2 is referred to as wiring P-VDR2, the wiring pattern that propagates the clock signal SCK is referred to as wiring P-SCK, the wiring pattern that propagates the latch signal LAT is referred to as wiring P-LAT, the wiring pattern that propagates the change signal CH is referred to as wiring P-CH, the wiring pattern that propagates the print data signal SI1 is referred to as wiring P-SI1, and The wiring pattern that propagates the mode-state signal HS1 is referred to as wiring P-HS1.

[0190] 19, the abnormality detection circuit 250 has a semiconductor device 450 and a voltage input switching circuit 251. The semiconductor device 450 also includes a determination control circuit 451, a voltage determination circuit 452, an output switching circuit 453, and a memory circuit 454.

[0191] The determination control circuit 451 is electrically connected to the terminals TM-SI1 / HC and TM-SCK. The determination control circuit 451 acquires signals input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC at the timing of the signals input from the discharge control unit 20 via the wiring WI-SCK and the terminal TM-SCK, and controls the operation of each component of the semiconductor device 450 in accordance with the acquired signals input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC.

[0192] The determination control circuit 451 reads out information stored in the memory circuit 454 in response to signals input from the discharge control unit 20 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and generates a memory circuit control signal RW for storing desired information in the memory circuit 454, and outputs it to the memory circuit 454. Such a memory circuit 454 includes a temporary storage area such as a register or RAM (Random Access Memory), and a permanent storage area such as storage or ROM (Read Only Memory).

[0193] In addition, the judgment control circuit 451 outputs a voltage switching signal SV to a voltage input switching circuit 251 provided outside the semiconductor device 450 in response to a signal input from the discharge control unit 20 via wiring WI-SI1 / HC and terminal TM-SI1 / HC.

[0194] The voltage input switching circuit 251 includes resistors R10, R11, R12, and R13, and transistors M10 and M11. In this embodiment, the transistor M10 is an n-channel field-effect transistor (FET), and the transistor M11 is a p-channel FET.

[0195] One end of resistor R10 is electrically connected to terminal TM-VDR1 through which drive voltage signal VDR1 is propagated, and the other end of resistor R10 is electrically connected to one end of resistor R11. The other end of resistor R11 is electrically connected to the drain of transistor M10. A voltage switching signal SV output by semiconductor device 450 is input to the gate of transistor M10, and ground potential is supplied to the source of transistor M10. The source of transistor M11 is electrically connected to terminal TM-VDR1 through which drive voltage signal VDR1 is propagated, and the gate of transistor M11 is electrically connected to the other end of resistor R10 and one end of resistor R11, and the drain of transistor M11 is electrically connected to one end of resistor R12. The other end of resistor R12 is electrically connected to one end of resistor R13, and ground potential is supplied to the other end of resistor R13. The voltage input switching circuit 251 then outputs a signal generated at a connection point where the other end of the resistor R12 and one end of the resistor R13 are connected as a voltage detection signal DET to the semiconductor device 450. That is, the determination control circuit 451 uses the voltage switching signal SV to control the operations of the transistors M10 and M11 included in the voltage input switching circuit 251, and the voltage input switching circuit 251 outputs a voltage detection signal DET corresponding to the potential of the terminal TM-VDR1 to the semiconductor device 450 based on the voltage switching signal SV.

[0196] Furthermore, the judgment control circuit 451 reads out information indicating the judgment conditions for the voltage judgment circuit 452, which is stored in the memory circuit 454, using the memory circuit control signal RW. Then, the judgment control circuit 451 generates a judgment condition signal JC including the read information and outputs it to the voltage judgment circuit 452. Furthermore, the voltage judgment circuit 452 receives the judgment condition signal JC output by the judgment control circuit 451 and the voltage detection signal DET output by the voltage input switching circuit 251 as inputs. Voltage The determination circuit 452 determines whether the voltage detection signal DET is normal or not based on the input determination condition signal JC and voltage detection signal DET, generates a determination result signal JR indicating the result of the determination, and outputs it to the determination control circuit 451.

[0197] The determination control circuit 451 generates a switch control signal OS based on the determination result signal JR input from the voltage determination circuit 452 , and outputs the signal to the output switching circuit 453 .

[0198] The output switching circuit 453 has a switch group SW including a plurality of switches. One of the switches included in the switch group SW has one end electrically connected to the terminal TM-SI1 / HC and the other end electrically connected to the wiring P-SI1. Another of the switches included in the switch group SW has one end electrically connected to the terminal TM-SCK and the other end electrically connected to the wiring P-SCK. Similarly, another of the switches included in the switch group SW has one end electrically connected to the terminal TM-LAT and the other end electrically connected to the wiring P-LAT, and another of the switches included in the switch group SW has one end electrically connected to the terminal TM-CH and the other end electrically connected to the wiring P-CH.

[0199] The plurality of switches included in the switch group SW included in the output switching circuit 453 are controlled to be conductive or non-conductive in accordance with a switch control signal OS input from the determination control circuit 451. That is, the output switching circuit 453 switches whether or not the signals propagating through the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH are propagated to the corresponding wirings P-SI1, P-SCK, P-LAT, and P-CH, respectively.

[0200] Here, the switch group SW may include a changeover switch having one end electrically connected to each of the terminals TM-VDR1 and TM-VDR2 and the other end electrically connected to each of the wirings P-VDR1 and P-VDR2. Furthermore, the switch group SW may not include any of the changeover switches having one end electrically connected to each of the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH and the other end electrically connected to each of the wirings P-SI1, P-SCK, P-LAT, and P-CH. That is, the output switching circuit 453 only needs to include a changeover switch capable of controlling the electrical connection between at least one of the terminals TM-SCK, TM-LAT, TM-CH, TM-VDR1, and TM-VDR2 and the wirings P-SCK, P-LAT, P-CH, P-VDR1, and P-VDR2.

[0201] The multiple switches included in such switch group SW may be configured to include transistors such as FETs. In this case, the multiple switches included in switch group SW are controlled to be conductive or non-conductive according to the logic level of a switch control signal OS output by the determination control circuit 451. Note that the configuration of the switches included in switch group SW is not limited to that shown in Fig. 19. For example, the propagation of signals between each of the terminals TM-SCK, TM-LAT, TM-CH, TM-VDR1, and TM-VDR2 and each of the wires P-SCK, P-LAT, P-CH, P-VDR1, and P-VDR2 may be controlled by switching whether or not the wires through which various signals are propagated are connected to the ground potential.

[0202] Here, the multiple changeover switches included in the switch group SW in this embodiment will be described as controlling one end and the other end to be conductive when an H-level switch control signal OS is input from the judgment control circuit 451, and controlling one end and the other end to be non-conductive when an L-level switch control signal OS is input.

[0203] Further, the head status signal HS1 indicating the status of the head chip 300-1 corresponding to the drive signal selection circuit 200-1 is input to the determination control circuit 451. 19. The determination control circuit 451 also receives head status signals HS2 to HS6 indicating the status of each of the head chips 300-2 to 300-6 corresponding to the drive signal selection circuits 200-2 to 200-6, which are not shown in Fig. 19. Based on the determination result signal JR and the head status signals HS1 to HS6, the determination control circuit 451 generates a determination result signal ES indicating whether the signals supplied to the print head 100 are normal or not, and whether the drive signal selection circuits 200-1 to 200-6 of the print head 100 are normal or not, and outputs this to the discharge control unit 20 via terminal TM-ES and wiring WI-ES.

[0204] In the abnormality detection circuit 250 configured as described above, the voltage input switching circuit 251, the determination control circuit 451, and the voltage determination circuit 452 determine whether the potential of the signal propagating through the wiring WI-VDR1 and the terminal TM-VDR1 is normal based on the signal propagating through the terminal TM-SI1 / HC, and the determination control circuit 451 and the output switching circuit 453 control a plurality of switches included in the switch group SW included in the output switching circuit 453 based on the determination result, thereby switching whether or not the signal propagating through the terminals TM-SI1 / HC, TM-SCK, TM-LAT, and TM-CH is supplied to the drive signal selection circuit 200-1 via the wiring P-SI1, P-SCK, P-LAT, and P-CH. This controls the generation of the drive signal VOUT by the drive signal selection circuits 200-1 to 200-6. In other words, if the signal supplied to the print head 100 is normal, the abnormality detection circuit 250 allows ink to be ejected from the print head 100, and if an abnormality occurs in the signal supplied to the print head 100, the abnormality detection circuit 250 does not allow ink to be ejected from the print head 100.

[0205] 11 to 14, in the liquid ejection device 1 of this embodiment, the ejection control unit 20 transmits the drive voltage signals VDR1 and VDR2, the voltages VHV and VDD, the diagnostic control signal HC, the print data signal SI1, the clock signal SCK, the latch signal LAT, the change signal CH, and the determination result signal ES via cables FC1 and FC2 as the cable FC and connectors CN1 and CN2 as the connectors CN. In this liquid ejection device 1, the drive voltage signals VDR1 and VDR2, the voltages VHV and VDD, the diagnostic control signal HC, the print data signal SI, the clock signal SCK, the latch signal LAT, the change signal CH, and the determination result signal ES supplied to the abnormality detection circuit 250 of the print head 100 are preferably transmitted via the same cable FC and connector CN. Furthermore, in the wiring board 130 shown in FIG. 14, the signals are preferably transmitted via the cable FC1 and connector CN1 provided near the semiconductor device 450 included in the abnormality detection circuit 250.

[0206] This makes it possible to shorten the length of the wiring over which the signals supplied to the abnormality detection circuit 250 are propagated, and also to reduce the difference that may occur in the length of the wiring over which various signals are propagated, thereby reducing the risk that noise or the like will be superimposed on the signals supplied to the abnormality detection circuit 250, and reducing the risk that the accuracy of the signals supplied to the abnormality detection circuit 250 will be reduced.

[0207] 1.6.2 Operation of the fault detection circuit Next, we will explain an example of the operation of the abnormality detection circuit 250 included in the print head 100. First, we will explain the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is normal. Figures 20 and 21 are diagrams showing an example of the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is normal.

[0208] As shown in Figure 20, at time t1, an AC voltage AC, for example, a commercial AC voltage of 100V, is supplied from the commercial AC power supply 7 to the power supply voltage output circuit 12 of the liquid ejection device 1. The power supply voltage output circuit 12 generates voltages VHV and VDD from the supplied AC voltage AC and supplies them to each part of the liquid ejection device 1. As a result, an abnormality in the print head 100 is detected. The detection circuit 250 and the semiconductor device 450 included in the abnormality detection circuit 250 start operating. At this time, the semiconductor device 450 executes a power-on reset (POR) when a power supply voltage is supplied. As a result, information held in temporary storage areas such as registers and RAM included in the storage circuit 454 is initialized.

[0209] At time t2, after the voltages VHV and VDD are supplied to the print head 100 and the voltage values ​​have stabilized, and after the semiconductor device 450 has executed POR, the discharge control unit 20 generates, as the drive voltage signal VDR1, a voltage signal VS1 that is a constant DC voltage at a potential V1 higher than the threshold voltage Vt. The discharge control unit 20 then supplies the generated voltage signal VS1 to the print head 100 via the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the voltage signal VS1 as the drive voltage signal VDR1 is propagated via the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the potential V1 is maintained across the wiring WI-VDR1 and the terminal TM-VDR1.

[0210] Here, in the liquid ejection device 1, whether the voltage values ​​of the voltages VHV and VDD have stabilized may be determined, for example, by the liquid ejection device 1 having a detection circuit (not shown) that detects the voltage values ​​of the voltages VHV and VDD and determining whether the fluctuation range of the voltage values ​​of the voltages VHV and VDD is within a predetermined range, or by determining whether a predetermined time has elapsed after a predetermined circuit such as the semiconductor device 450 included in the abnormality detection circuit 250 has started operating.

[0211] Furthermore, the statement that the voltage values ​​of the voltages VHV and VDD supplied to the print head 100 have stabilized does not necessarily mean that the voltage values ​​of the voltages VHV and VDD supplied to the print head 100 have become completely constant, but also includes cases where the voltages VHV and VDD can be considered to have approximately constant voltage values ​​when errors due to circuit variations and fluctuations in voltage values ​​due to temperature characteristics, noise, etc. In the following explanation, the same interpretation is used when the expression "after the voltage values ​​have stabilized" is used for various signals other than the voltages VHV and VDD.

[0212] At time t3 after the voltage value of the voltage signal VS1 serving as the drive voltage signal VDR1 output by the discharge control unit 20 has stabilized at potential V1, the discharge control unit 20 generates a first command cmd1, which is a diagnostic control signal HC synchronized with the clock signal SCK and corresponds to the voltage signal VS1 at potential V1. The discharge control unit 20 then supplies the generated first command cmd1 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and also supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The first command cmd1 and clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 of the abnormality detection circuit 250.

[0213] The determination control circuit 451 analyzes the input first command cmd1 based on the timing defined by the clock signal SCK. Then, at time t4 after the determination control circuit 451 recognizes that the first command cmd1 is a normal command, the determination control circuit 451 generates a storage circuit control signal RW for reading, from the storage circuit 454, determination information c1 corresponding to the first command cmd1, and outputs the signal to the storage circuit 454. As a result, the determination information c1 corresponding to the voltage signal VS1 at the potential V1 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c1, and outputs the signal to the voltage determination circuit 452. In this embodiment, a potential V1 higher than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the determination information c1 includes a determination condition for determining that the voltage detection signal DET is normal when the voltage value of the voltage detection signal DET corresponding to the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 exceeds a threshold voltage Vth corresponding to the threshold voltage Vt. This is the potential obtained by dividing the voltage Vt between resistors R12 and R13.

[0214] Furthermore, at time t5 after the determination control circuit 451 has determined that the first command cmd1 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes conduction between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes conduction between the source and drain of the transistor M11. As a result, the voltage input switching circuit 251 outputs a voltage detection signal DET to the voltage determination circuit 452, the voltage detection signal DET having a voltage value obtained by dividing the potential V1 of the voltage signal VS1 held in the line WI-VDR1 and the terminal TM-VDR1 by the resistors R12 and R13.

[0215] Here, in an example of the operation of the abnormality detection circuit 250 shown in FIG. 20, after the determination control circuit 451 recognizes that the first command cmd1 is a normal command, the determination control circuit 451 reads out determination information c1 stored in the memory circuit 454 based on the first command cmd1 and outputs a determination condition signal JC including the determination information c1 to the voltage determination circuit 452. Thereafter, the determination control circuit 451 outputs a voltage switch signal SV of H level to the voltage input switch circuit 251, thereby causing the voltage determination circuit 452 to output a voltage detection signal DE having a voltage value according to the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1. Although the figure shows that T is supplied, after the judgment control circuit 451 recognizes that the first command cmd1 is a normal command, the judgment control circuit 451 outputs an H-level voltage switching signal SV to the voltage input switching circuit 251, thereby supplying the voltage judgment circuit 452 with a voltage detection signal DET having a voltage value corresponding to the potential held in the wiring WI-VDR1 and the terminal TM-VDR1, and then the judgment control circuit 451 reads out judgment information c1 stored in the memory circuit 454 based on the first command cmd1, and outputs a judgment condition signal JC including the judgment information c1 to the voltage judgment circuit 452. Furthermore, after the judgment control circuit 451 recognizes that the first command cmd1 is a normal command, the judgment control circuit 451 may perform the following operations in parallel: reading out judgment information c1 stored in the memory circuit 454 based on the first command cmd1 and outputting a judgment condition signal JC including the judgment information c1 to the voltage judgment circuit 452; and outputting an H-level voltage switching signal SV to the voltage input switching circuit 251, thereby supplying the voltage judgment circuit 452 with a voltage detection signal DET having a voltage value corresponding to the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1.

[0216] That is, the operation performed at time t4 and the operation performed at time t5 shown in FIG. 20 may be performed in any order, or may be performed in parallel.

[0217] At time t6 after the voltage evaluation circuit 452 receives the determination condition signal JC including determination information c1 and the voltage detection signal DET having a voltage value corresponding to the potentials held on the wiring WI-VDR1 and the terminal TM-VDR1, the voltage evaluation circuit 452 compares the voltage detection signal DET with the determination information c1 included in the determination condition signal JC. In an example of the operation of the abnormality detection circuit 250 shown in FIG. 20 , a potential V1 higher than the threshold voltage Vt is held on the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the voltage evaluation circuit 452 receives the voltage detection signal DET having a potential higher than the threshold voltage Vth. As a result, the voltage evaluation circuit 452 determines that the potentials held on the wiring WI-VDR1 and the terminal TM-VDR1 are normal, generates a determination result signal JR indicating that the potentials held on the wiring WI-VDR1 and the terminal TM-VDR1 are normal, and outputs the determination result signal JR to the evaluation control circuit 451. In Figure 20, the judgment result signal JR indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal is shown as an H-level signal, but this is not limited to this and may also be a specific command.

[0218] Thereafter, the determination control circuit 451 determines whether the wiring WI- The determination control circuit 451 generates result information r1 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal. Then, the determination control circuit 451 outputs a memory circuit control signal RW to the memory circuit 454 to store the generated result information r1 in the memory circuit 454. As a result, the memory circuit 454 stores the result information r1 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal.

[0219] At time t7 after the result information r1 is stored in the memory circuit 454, the discharge control unit 20 generates a second command cmd2 as a diagnosis control signal HC synchronized with the clock signal SCK. The discharge control unit 20 then supplies the generated second command cmd2 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The second command cmd2 and the clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 provided in the abnormality detection circuit 250.

[0220] The determination control circuit 451 analyzes the input second command cmd2 based on the timing determined by the clock signal SCK. Then, at time t8 after the determination control circuit 451 recognizes that the second command cmd2 is a normal command, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes a non-conductive state between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes a non-conductive state between the source and drain of the transistor M11. As a result, the connection point between the resistors R12 and R13 included in the voltage input switching circuit 251 is electrically disconnected from the line WI-VDR1 and the terminal TM-VDR1, and the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0221] Furthermore, at time t8 after the determination control circuit 451 recognizes that the second command cmd2 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether or not the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1, which was executed based on the first command cmd1, are normal, and outputs the signal to the voltage determination circuit 452. Upon receiving the determination condition signal JC including the stop information st, the voltage determination circuit 452 terminates the determination process and sets the logic level of the determination result signal JR to the L level.

[0222] At time t9 after the voltage evaluation circuit 452 stops outputting the evaluation result signal JR, the discharge control unit 20 generates, as the drive voltage signal VDR1, a voltage signal VS2 that is a constant DC voltage at a potential V2 lower than the threshold voltage Vt. The discharge control unit 20 then supplies the generated voltage signal VS2 to the print head 100 via the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the voltage signal VS2 as the drive voltage signal VDR1 propagates through the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the potential V2 is maintained across the wiring WI-VDR1 and the terminal TM-VDR1.

[0223] At time t10 after the voltage value of the voltage signal VS2 serving as the drive voltage signal VDR1 output by the discharge control unit 20 has stabilized at potential V2, the discharge control unit 20 generates a third command cmd3, which is a diagnostic control signal HC synchronized with the clock signal SCK and corresponds to the voltage signal VS2 at potential V2. The discharge control unit 20 then supplies the generated third command cmd3 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and also supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The third command cmd3 and clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 of the abnormality detection circuit 250.

[0224] The determination control circuit 451 analyzes the input third command cmd3 based on the timing defined by the clock signal SCK. Then, at time t11 after the determination control circuit 451 recognizes that the third command cmd3 is a normal command, the determination control circuit 451 generates a storage circuit control signal RW for reading, from the storage circuit 454, determination information c2 corresponding to the third command cmd3, and outputs the signal to the storage circuit 454. As a result, the determination information c2 corresponding to the voltage signal VS2 at the potential V2 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c2, and outputs the signal to the voltage determination circuit 452. In this embodiment, a potential V2 lower than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c2 includes a judgment condition for judging that the potential of the voltage detection signal DET is normal when the voltage value of the voltage detection signal DET corresponding to the potential held in the wiring WI-VDR1 and the terminal TM-VDR1 is lower than the threshold voltage Vth corresponding to the threshold voltage Vt.

[0225] Furthermore, at time t12 after the determination control circuit 451 has determined that the third command cmd3 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes conduction between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes conduction between the source and drain of the transistor M11. As a result, the voltage input switching circuit 251 outputs a voltage detection signal DET to the voltage determination circuit 452, the voltage detection signal DET having a voltage value obtained by dividing the potential V2 of the voltage signal VS2 held in the line WI-VDR1 and the terminal TM-VDR1 by the resistors R12 and R13.

[0226] Here, the operation performed at time t11 shown in FIG. 20 and the operation performed at time t12 may be performed in either order, or may be performed in parallel, similar to the operations performed at time t4 and time t5 described above.

[0227] At time t13 after the voltage evaluation circuit 452 receives the determination condition signal JC including determination information c2 and the voltage detection signal DET having a voltage value corresponding to the potentials held on the line WI-VDR1 and the terminal TM-VDR1, the voltage evaluation circuit 452 compares the voltage detection signal DET with the determination information c2 included in the determination condition signal JC. In an example of the operation of the abnormality detection circuit 250 shown in FIG. 20 , a potential V2 lower than the threshold voltage Vt is held on the line WI-VDR1 and the terminal TM-VDR1. Therefore, the voltage evaluation circuit 452 receives the voltage detection signal DET having a potential lower than the threshold voltage Vth. As a result, the voltage evaluation circuit 452 determines that the potentials held on the line WI-VDR1 and the terminal TM-VDR1 are normal, generates an H-level determination result signal JR indicating that the potentials held on the line WI-VDR1 and the terminal TM-VDR1 are normal, and outputs the H-level determination result signal JR to the evaluation control circuit 451.

[0228] Thereafter, the determination control circuit 451 generates result information r2 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal, based on the input determination result signal JR. Then, the determination control circuit 451 outputs a memory circuit control signal RW to the memory circuit 454 to store the generated result information r2 in the memory circuit 454. As a result, the memory circuit 454 stores the result information r2 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal.

[0229] At time t14 after the result information r2 is stored in the memory circuit 454, the discharge control unit 20 generates a fourth command cmd4 as a diagnostic control signal HC synchronized with the clock signal SCK. Then, the discharge control unit 20 supplies the generated fourth command cmd4 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and also supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The fourth command cmd4 and clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 that the abnormality detection circuit 250 has.

[0230] The determination control circuit 451 analyzes the input fourth command cmd4 based on the timing determined by the clock signal SCK. Then, at time t15 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes a non-conductive state between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes a non-conductive state between the source and drain of the transistor M11. As a result, the connection point between the resistors R12 and R13 included in the voltage input switching circuit 251 is electrically disconnected from the line WI-VDR1 and the terminal TM-VDR1, and the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0231] Furthermore, at time t15 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether or not the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1, which was executed based on the third command cmd3, are normal, and outputs the signal to the voltage determination circuit 452. Upon receiving the determination condition signal JC including the stop information st, the voltage determination circuit 452 sets the logic level of the determination result signal JR to the L level.

[0232] At time t16 after the voltage evaluation circuit 452 stops outputting the evaluation result signal JR, the discharge control unit 20 stops generating the constant voltage signal VS2 at potential V2 as the drive voltage signal VDR1, thereby maintaining the ground potential at the wire WI-VDR1 and the terminal TM-VDR1.

[0233] Then, as shown in FIG. 21, at time t17 after the discharge control unit 20 stops generating the drive voltage signal VDR1, the judgment control circuit 451 generates a memory circuit control signal RW for reading out the result information r1 and r2 stored in the memory circuit 454, and outputs it to the memory circuit 454.

[0234] 20 and 21, the memory circuit 454 stores result information r1 indicating that the signal input to the print head 100 at time t6 is normal, and result information r2 indicating that the signal input to the print head 100 at time t13 is normal. That is, both pieces of result information r1 and r2 read from the memory circuit 454 by the determination control circuit 451 include information indicating that the signal input to the print head 100 is normal. At time t18, after determining that both pieces of result information r1 and r2 read at time t17 are normal, the determination control circuit 451 outputs an H-level switch control signal OS. This causes the multiple switches included in the switch group SW of the output switching circuit 453 to be controlled to be conductive. Therefore, wiring WI-SI1 / SC and terminal TM-SI1 / HC are electrically connected to wiring P-SI1, wiring WI-SCK and terminal TM-SCK are electrically connected to wiring P-SCK, wiring WI-LAT and terminal TM-LAT are electrically connected to wiring P-LAT, and wiring WI-CH and terminal TM-CH are electrically connected to wiring P-CH.

[0235] At time t19 after the determination control circuit 451 outputs the H-level switch control signal OS, the discharge control unit 20 generates a drive voltage signal VDR1 having a constant voltage value of Vc and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive voltage signal VDR2 having a constant voltage value of Vc and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. At time t20 when image data PD is input to the liquid ejection device 1, the ejection control unit 20 generates a drive signal COMA including trapezoidal waveforms Adp1 and Adp2 as the drive voltage signal VDR1 and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive signal COMB including trapezoidal waveforms Bdp1 and Bdp2 as the drive voltage signal VDR2 and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. As a result, the drive signal COMA propagates through the wiring WI-VDR1 and the terminal TM-VDR1 and is supplied to the drive signal selection circuit 200-1, and the drive signal COMB propagates through the wiring WI-VDR2 and the terminal TM-VDR2 and is supplied to the drive signal selection circuit 200-1.

[0236] At time t21 after the supply of drive signals COMA and COMB begins, the discharge control unit 20 generates a print data signal SI1, a clock signal SCK, a latch signal LAT, and a change signal CH for forming an image based on image data PD on the medium P. The discharge control unit 20 then outputs the generated print data signal SI1, clock signal SCK, latch signal LAT, and change signal CH to the corresponding wiring WI-SI1 / HC and terminal TM-SI1 / HC, wiring WI-SCK and terminal TM-SCK, wiring WI-LAT and terminal TM-LAT, and wiring WI-CH and terminal TM-CH. That is, the wiring WI-SI1 / HC and terminal TM-SI1 / HC transmit a diagnostic control signal HC1 including a first command cmd1, a second command cmd2, a third command cmd3, and a fourth command cmd4, and then transmit a print data signal SI for causing the print head 100 to perform printing.

[0237] In this case, since the multiple changeover switches included in the switch group SW of the output switching circuit 453 are controlled to be conductive by the switch control signal OS, the print data signal SI1 propagating through the wiring WI-SI1 / HC and terminal TM-SI1 / HC is supplied to the drive signal selection circuit 200-1 via the wiring P-SI1, the clock signal SCK propagating through the wiring WI-SCK and terminal TM-SCK is supplied to the drive signal selection circuit 200-1 via the wiring P-SCK, the latch signal LAT propagating through the wiring WI-LAT and terminal TM-LAT is supplied to the drive signal selection circuit 200-1 via the wiring P-LAT, and the change signal CH propagating through the wiring WI-CH and terminal TM-CH is supplied to the drive signal selection circuit 200-1 via the wiring P-CH.

[0238] The drive signal selection circuit 200-1 generates a drive signal VOUT based on the input print data signal SI1, clock signal SCK, latch signal LAT, change signal CH, drive signal COMA as drive voltage signal VDR1, and drive signal COMB as drive voltage signal VDR2, and supplies the generated drive signal VOUT to the piezoelectric element 60.

[0239] 19 to 21, the drive signal selection circuits 200-2 to 200-6 are also supplied with the clock signal SCK, latch signal LAT, and change signal CH output by the abnormality detection circuit 250, and the corresponding print data signals SI2 to SI6, drive signal COMA as drive voltage signal VDR1, and drive signal COMB as drive voltage signal VDR2 output by the discharge control unit 20. As a result, the drive signal selection circuits 200-2 to 200-6 similarly generate drive signals VOUT and supply the generated drive signals VOUT to the corresponding piezoelectric elements 60.

[0240] As a result, ink is ejected from the nozzles 651 corresponding to the piezoelectric elements 60 of the print head 100, and a desired image is formed on the medium P.

[0241] Next, the operation of the abnormality detection circuit 250 when an abnormality occurs in the signal supplied to the print head 100, such as when a short circuit occurs between the wires WI of the cable FC that transmits various signals to the print head 100, or between the terminals TM of the connector CN, will be described. 22 and 23 are diagrams showing an example of the operation of the abnormality detection circuit 250 when the signal supplied to the print head 100 is abnormal. Note that the example of the operation of the abnormality detection circuit 250 shown in Figures 22 and 23 illustrates a case where the wiring WI-VDR1 or the terminal TM-VDR1 that propagates the drive voltage signal VDR1 is short-circuited with the wiring WI or the terminal TM that propagates the ground potential.

[0242] As shown in FIG. 22, at time t31, an AC voltage AC, for example, a 100V commercial AC voltage, is supplied from the commercial AC power supply 7 to the power supply voltage output circuit 12 of the liquid ejection device 1. The power supply voltage output circuit 12 generates voltages VHV and VDD from the supplied AC voltage AC and supplies them to various components of the liquid ejection device 1. This causes the abnormality detection circuit 250 of the print head 100 and the semiconductor device 450 included in the abnormality detection circuit 250 to start operating. At this time, the semiconductor device 450 executes POR. As a result, information held in temporary storage areas such as registers and RAM included in the storage circuit 454 is initialized.

[0243] At time t32, after the voltages VHV and VDD are supplied to the print head 100 and the voltage values ​​have stabilized, and after the semiconductor device 450 has executed POR, the discharge control unit 20 generates, as the drive voltage signal VDR1, a voltage signal VS1 that is a constant DC voltage with a potential V1 higher than the threshold voltage Vt. The discharge control unit 20 then supplies the generated voltage signal VS1 to the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited with the wiring WI or the terminal TM, through which the ground potential propagates. Therefore, the wiring WI-VDR1 and the terminal TM-VDR1 are held at ground potential.

[0244] At time t33 after the voltage value of the voltage signal VS1 serving as the drive voltage signal VDR1 output by the discharge control unit 20 has stabilized at potential V1, the discharge control unit 20 generates a first command cmd1, which is a diagnostic control signal HC synchronized with the clock signal SCK and corresponds to the voltage signal VS1 at potential V1. The discharge control unit 20 then supplies the generated first command cmd1 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and also supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The first command cmd1 and clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 of the abnormality detection circuit 250.

[0245] The determination control circuit 451 analyzes the input first command cmd1 based on the timing defined by the clock signal SCK. Then, at time t34 after the determination control circuit 451 recognizes that the first command cmd1 is a normal command, the determination control circuit 451 generates a storage circuit control signal RW for reading, from the storage circuit 454, determination information c1 corresponding to the first command cmd1, and outputs the signal to the storage circuit 454. As a result, the determination information c1 corresponding to the voltage signal VS1 at the potential V1 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c1 and outputs the signal to the voltage determination circuit 452. In this embodiment, when no short-circuit abnormality occurs between the wiring WI-VDR1 and the terminal TM-VDR1, a potential V1 higher than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c1 includes a judgment condition for determining that the voltage detection signal DET is normal when the voltage value of the voltage detection signal DET corresponding to the potential held in the wiring WI-VDR1 and the terminal TM-VDR1 exceeds the threshold voltage Vth corresponding to the threshold voltage Vt.

[0246] At time t35 after the determination control circuit 451 has determined that the first command cmd1 is a normal command, the determination control circuit 451 generates a voltage switching signal SV at H level and outputs it to the voltage input switching circuit 251. The drain-source connection of the transistor M10 is controlled to be conductive, and accordingly the source-drain connection of the transistor M11 is controlled to be conductive, so that the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential held on the wiring WI-VDR1 and the terminal TM-VDR1 to the voltage evaluation circuit 452.

[0247] Here, the operation performed at time t34 and the operation performed at time t35 may be performed in either order, or may be performed in parallel, similar to the operation performed at time t4 and the operation performed at time t5 described above.

[0248] At time t36 after the voltage evaluation circuit 452 receives the determination condition signal JC including the determination information c1 and the voltage detection signal DET at ground potential, the voltage evaluation circuit 452 compares the voltage detection signal DET with the determination information c1 included in the determination condition signal JC. In an example of the operation of the abnormality detection circuit 250 shown in FIG. 22, a ground potential lower than the threshold voltage Vt is held in the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the voltage evaluation circuit 452 receives the voltage detection signal DET at a ground potential lower than the threshold voltage Vth. As a result, the voltage evaluation circuit 452 determines that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are abnormal and does not generate an H-level determination result signal JR indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal. In other words, the voltage evaluation circuit 452 maintains the logic level of the determination result signal JR at an L level. In Figure 22, the judgment result signal JR indicating that the potential held in the wiring WI-VDR1 and the terminal TM-VDR1 is not normal is shown as an L-level signal, but this is not limited to this and may also be a specific command.

[0249] Thereafter, the determination control circuit 451 generates result information r1 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are not normal based on the input determination result signal JR. Then, the determination control circuit 451 outputs a memory circuit control signal RW to the memory circuit 454 to store the generated result information r1 in the memory circuit 454. As a result, the memory circuit 454 stores the result information r1 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are not normal.

[0250] At time t37 after the result information r1 is stored in the memory circuit 454, the discharge control unit 20 generates a second command cmd2 as a diagnosis control signal HC synchronized with the clock signal SCK. The discharge control unit 20 then supplies the generated second command cmd2 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The second command cmd2 and the clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 provided in the abnormality detection circuit 250.

[0251] The determination control circuit 451 analyzes the input second command cmd2 based on the timing determined by the clock signal SCK. Then, at time t38 after the determination control circuit 451 recognizes that the second command cmd2 is a normal command, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes a non-conductive state between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes a non-conductive state between the source and drain of the transistor M11. As a result, the connection point between the resistors R12 and R13 included in the voltage input switching circuit 251 is electrically disconnected from the line WI-VDR1 and the terminal TM-VDR1, and the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0252] Furthermore, at time t38 after the determination control circuit 451 has recognized that the second command cmd2 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether or not the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1, which was executed based on the first command cmd1, are normal, and outputs the signal to the voltage determination circuit 452. Upon receiving the determination condition signal JC including the stop information st, the voltage determination circuit 452 terminates the determination process and sets the logic level of the determination result signal JR to the L level.

[0253] At time t39 after the voltage evaluation circuit 452 stops outputting the evaluation result signal JR, the discharge control unit 20 generates, as the drive voltage signal VDR1, a voltage signal VS2 that is a constant DC voltage at a potential V2 lower than the threshold voltage Vt. The discharge control unit 20 then supplies the generated voltage signal VS2 to the wiring WI-VDR1 and the terminal TM-VDR1. At this time, the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited with the wiring WI or the terminal TM, through which the ground potential propagates. Therefore, the wiring WI-VDR1 and the terminal TM-VDR1 are held at ground potential.

[0254] At time t40 after the voltage value of the voltage signal VS2 serving as the drive voltage signal VDR1 output by the discharge control unit 20 has stabilized at potential V2, the discharge control unit 20 generates a third command cmd3, which is a diagnostic control signal HC synchronized with the clock signal SCK and corresponds to the voltage signal VS2 at potential V2. The discharge control unit 20 then supplies the generated third command cmd3 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and also supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The third command cmd3 and clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 of the abnormality detection circuit 250.

[0255] The determination control circuit 451 analyzes the input third command cmd3 based on the timing defined by the clock signal SCK. Then, at time t41 after the determination control circuit 451 recognizes that the third command cmd3 is normal, the determination control circuit 451 generates a storage circuit control signal RW for reading, from the storage circuit 454, determination information c2 corresponding to the third command cmd3, and outputs the signal to the storage circuit 454. As a result, the determination information c2 corresponding to the voltage signal VS2 at the potential V2 is read from the storage circuit 454. Then, the determination control circuit 451 generates a determination condition signal JC including the read determination information c2 and outputs the signal to the voltage determination circuit 452. In this embodiment, if no short-circuit abnormality occurs between the wiring WI-VDR1 and the terminal TM-VDR1, a potential V2 lower than the threshold voltage Vt is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. Therefore, the judgment information c2 includes a judgment condition for judging that the potential of the voltage detection signal DET, which corresponds to the potential held in the wiring WI-VDR1 and the terminal TM-VDR1, is normal when the potential of the voltage detection signal DET is lower than the threshold voltage Vth, which corresponds to the threshold voltage Vt.

[0256] Furthermore, at time t42 after the determination control circuit 451 has determined that the third command cmd3 is a normal command, the determination control circuit 451 generates an H-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes the drain-to-source connection of the transistor M10 included in the voltage input switching circuit 251 to be conductive, and accordingly, the source-to-drain connection of the transistor M11 is also controlled to be conductive. As a result, the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential held in the line WI-VDR1 and the terminal TM-VDR1 to the voltage determination circuit 452.

[0257] Here, the operation performed at time t41 and the operation performed at time t42 may be performed in either order, or may be performed in parallel, similar to the operation performed at time t11 and the operation performed at time t12 described above.

[0258] At time t43 after the voltage evaluation circuit 452 receives the determination condition signal JC including the determination information c2 and the voltage detection signal DET at ground potential, the voltage evaluation circuit 452 compares the voltage detection signal DET with the determination information c2 included in the determination condition signal JC. In an example of the operation of the abnormality detection circuit 250 shown in FIG. 22, a ground potential lower than the threshold voltage Vt is held in the line WI-VDR1 and the terminal TM-VDR1. Therefore, the voltage evaluation circuit 452 receives the voltage detection signal DET at a potential lower than the threshold voltage Vth. As a result, the voltage evaluation circuit 452 determines that the potentials held in the line WI-VDR1 and the terminal TM-VDR1 are normal, generates an H-level determination result signal JR indicating that the potentials held in the line WI-VDR1 and the terminal TM-VDR1 are normal, and outputs the signal to the evaluation control circuit 451.

[0259] Thereafter, the determination control circuit 451 generates result information r2 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal, based on the input determination result signal JR. Then, the determination control circuit 451 outputs a memory circuit control signal RW to the memory circuit 454 to store the generated result information r2 in the memory circuit 454. As a result, the memory circuit 454 stores the result information r2 indicating that the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 are normal.

[0260] At time t44 after the result information r2 is stored in the memory circuit 454, the discharge control unit 20 generates a fourth command cmd4 as a diagnosis control signal HC synchronized with the clock signal SCK. The discharge control unit 20 then supplies the generated fourth command cmd4 to the print head 100 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC, and supplies the clock signal SCK to the print head 100 via the wiring WI-SCK and the terminal TM-SCK. The fourth command cmd4 and the clock signal SCK supplied to the print head 100 are input to a determination control circuit 451 included in a semiconductor device 450 provided in the abnormality detection circuit 250.

[0261] The determination control circuit 451 analyzes the input fourth command cmd4 based on the timing determined by the clock signal SCK. Then, at time t45 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates an L-level voltage switching signal SV and outputs it to the voltage input switching circuit 251. This causes a non-conductive state between the drain and source of the transistor M10 included in the voltage input switching circuit 251, and accordingly causes a non-conductive state between the source and drain of the transistor M11. As a result, the connection point between the resistors R12 and R13 included in the voltage input switching circuit 251 is electrically disconnected from the line WI-VDR1 and the terminal TM-VDR1, and the voltage input switching circuit 251 outputs a voltage detection signal DET of the ground potential connected via the resistor R13 to the voltage determination circuit 452.

[0262] Furthermore, at time t45 after the determination control circuit 451 recognizes that the fourth command cmd4 is a normal command, the determination control circuit 451 generates a determination condition signal JC including stop information st for terminating the determination of whether or not the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1, which was executed based on the third command cmd3, are normal, and outputs the signal to the voltage determination circuit 452. Upon receiving the determination condition signal JC including the stop information st, the voltage determination circuit 452 sets the logic level of the determination result signal JR to the L level.

[0263] At time t46 after the voltage evaluation circuit 452 stops outputting the evaluation result signal JR, the discharge control unit 20 stops generating the constant voltage signal VS2 at potential V2 as the drive voltage signal VDR1, thereby maintaining the ground potential at the wire WI-VDR1 and the terminal TM-VDR1.

[0264] Then, as shown in Figure 23, at time t47 after the discharge control unit 20 stops generating the drive voltage signal VDR1, the judgment control circuit 451 generates a memory circuit control signal RW for reading out the result information r1 and r2 stored in the memory circuit 454, and outputs it to the memory circuit 454.

[0265] 22 and 23, the memory circuit 454 stores result information r1 indicating that the signal input to the print head 100 is abnormal at time t36, and result information r2 indicating that the signal input to the print head 100 is normal at time t43. That is, at least one of the result information r1 and r2 read from the memory circuit 454 by the determination control circuit 451 includes information indicating that the signal input to the print head 100 is abnormal. At time t48, after determining that at least one of the result information r1 and r2 read at time t47 is abnormal, the determination control circuit 451 determines that the signal input to the print head 100 is abnormal and continues to output an L-level switch control signal OS. As a result, the multiple switches included in the switch group SW of the output switching circuit 453 remain non-conductive. Therefore, wiring WI-SI1 / HC and terminal TM-SI1 / HC remain non-conductive with wiring P-SI1, wiring WI-SCK and terminal TM-SCK remain non-conductive with wiring P-SCK, wiring WI-LAT and terminal TM-LAT remain non-conductive with wiring P-LAT, and wiring WI-CH and terminal TM-CH remain non-conductive with wiring P-CH.

[0266] At time t49 after the determination control circuit 451 outputs the switch control signal OS at an L level, the discharge control unit 20 generates a drive voltage signal VDR1 having a constant voltage value of Vc and supplies it to the wire WI-VDR1 and terminal TM-VDR1, and generates a drive voltage signal VDR2 having a constant voltage value of Vc and supplies it to the wire WI-VDR2 and terminal TM-VDR2. At this time, the wire WI-VDR1 or terminal TM-VDR1 is short-circuited to ground potential. Therefore, the wire WI-VDR1 or terminal TM-VDR1 is held at ground potential.

[0267] Then, at time t50 when image data PD is input to the liquid ejection device 1, the ejection control unit 20 generates a drive signal COMA including trapezoidal waveforms Adp1 and Adp2 as the drive voltage signal VDR1 and supplies it to the wiring WI-VDR1 and the terminal TM-VDR1, and generates a drive signal COMB including trapezoidal waveforms Bdp1 and Bdp2 as the drive voltage signal VDR2 and supplies it to the wiring WI-VDR2 and the terminal TM-VDR2. At this time, because the wiring WI-VDR1 or the terminal TM-VDR1 is short-circuited to ground potential, the drive signal COMA is not supplied to the drive signal selection circuit 200-1, and only the drive signal COMB propagates through the wiring WI-VDR2 and the terminal TM-VDR2 and is supplied to the drive signal selection circuit 200-1.

[0268] At time t51 after the supply of the drive signals COMA and COMB starts, the discharge control unit 20 generates a print data signal SI1, a clock signal SCK, a latch signal LAT, and a change signal CH for forming an image based on the image data PD on the medium P. Then, the discharge control unit 20 outputs the generated print data signal SI1, clock signal SCK, latch signal LAT, and change signal CH to the corresponding wiring WI-SI1 / HC and terminal TM-SI1 / HC, wiring WI-SCK and terminal TM-SCK, wiring WI-LAT and terminal TM-LAT, and wiring WI-CH and terminal TM-CH.

[0269] In this case, the multiple switches included in the switch group SW of the output switching circuit 453 are controlled to be non-conductive by the switch control signal OS. Therefore, the print data signal SI1 transmitted through the wiring WI-SI1 / HC and the terminal TM-SI1 / HC is not supplied to the wiring P-SI1 and the drive signal selection circuit 200-1, but is supplied to the wiring WI-SCK and the terminal TM The clock signal SCK propagating through -SCK is not supplied to the wiring P-SCK and the drive signal selection circuit 200-1, the latch signal LAT propagating through the wiring WI-LAT and the terminal TM-LAT is not supplied to the wiring P-LAT and the drive signal selection circuit 200-1, and the change signal CH propagating through the wiring WI-CH and the terminal TM-CH is not supplied to the wiring P-CH and the drive signal selection circuit 200-1. As a result, the drive signal selection circuit 200-1 does not generate the drive signal VOUT, and the drive signal VOUT is not supplied to the piezoelectric element 60.

[0270] 19 and 22 to 23, the clock signal SCK, latch signal LAT, and change signal CH output by the abnormality detection circuit 250 are not supplied to the drive signal selection circuits 200-2 to 200-6 either, so that the drive signal selection circuits 200-2 to 200-6 do not generate the drive signal VOUT, and the drive signal VOUT is not supplied to the piezoelectric element 60.

[0271] As a result, ink is ejected from the nozzles 651 corresponding to the piezoelectric elements 60 of the print head 100, and no image is formed on the medium P.

[0272] Here, the first command cmd1 as the diagnostic control signal HC is a command for executing a test to determine whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the second command cmd2 as the diagnostic control signal HC is a command for terminating the test executed by the first command cmd1. That is, the test to determine whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is executed by the first command cmd1 and the second command cmd2. A signal including the first command cmd1 and the second command cmd2 for executing the test to determine whether the voltage signal VS1 of the potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is referred to as a first command signal HCf. That is, the first command signal HCf includes the first command cmd1 and the second command cmd2 that follows the first command cmd1.

[0273] Furthermore, the third command cmd3 as the diagnostic control signal HC is a command for executing a test to determine whether the voltage signal VS2 of potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the fourth command cmd4 as the diagnostic control signal HC is a command for terminating the test executed by the third command cmd3. That is, the test to determine whether the voltage signal VS2 of potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is executed by the third command cmd3 and the fourth command cmd4. A signal including the third command cmd3 and the fourth command cmd4 for executing the test to determine whether the voltage signal VS2 of potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1 is referred to as the second command signal HCs. That is, the second command signal HCs includes the third command cmd3 and the fourth command cmd4 that follows the third command cmd3.

[0274] Here, the first command signal HCf is a signal for executing a check as to whether the voltage signal VS1 of potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the first command cmd1 is a command for starting a check as to whether the voltage signal VS1 of potential V1 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. In contrast, the second command signal HCs is a signal for executing a check as to whether the voltage signal VS2 of potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the third command cmd3 is a command for starting a check as to whether the voltage signal VS2 of potential V2 is supplied to the wiring WI-VDR1 and the terminal TM-VDR1. When the first command cmd1 is input, the determination control circuit 451 reads out, from the memory circuit 454, determination information c1 corresponding to the voltage signal VS1 of potential V1. When the third command cmd3 is input, the determination control circuit 451 reads out, from the memory circuit 454, determination information c2 corresponding to the voltage signal VS2 of potential V2. That is, the first command cmd1 and the third command cmd3 are Although both commands are common in that they start a test to determine whether the potential supplied to the TM-VDR1 is normal, the determination information c1 read by the determination control circuit 451 in response to the first command cmd1 and the determination information c2 read by the determination control circuit 451 in response to the third command cmd3 are different. Therefore, the first command cmd1 and the third command cmd3 contain different information.

[0275] Because the first command cmd1 included in the first command signal HCf and the third command cmd3 included in the second command signal HCs contain different information, the abnormality detection circuit 250 can perform an inspection to determine whether the potentials supplied to the wiring WI-VDR1 and the terminal TM-VDR1 are normal, without being limited to the potentials supplied to the wiring WI-VDR1 and the terminal TM-VDR1. In other words, because the first command cmd1 and the third command cmd3 contain different information, the abnormality detection circuit 250 can perform an inspection to determine whether the potentials supplied to the wiring WI-VDR1 and the terminal TM-VDR1 are normal over a wide range of potentials supplied to the wiring WI-VDR1 and the terminal TM-VDR1. As a result, the versatility of the printhead 100 including the abnormality detection circuit 250 and the versatility of the printhead drive circuit 2 that outputs the diagnostic control signal HC1 and controls the printhead 100 can be improved.

[0276] Meanwhile, the second command cmd2 included in the first command signal HCf is a command for stopping the check to determine whether power is being supplied to the wiring WI-VDR1 and the terminal TM-VDR1, and the fourth command cmd4 included in the second command signal HCs is a command for stopping the check to determine whether power is being supplied to the wiring WI-VDR1 and the terminal TM-VDR1. In other words, the second command cmd2 and the fourth command cmd4 are both commands for ending the check to determine whether power is being supplied to the wiring WI-VDR1 and the terminal TM-VDR1. It is preferable that the second command cmd2 and the fourth command cmd4 contain the same information, which allows the printhead 100 and the printhead drive circuit 2 to collectively store information corresponding to the second command cmd2 and the fourth command cmd4. This reduces the risk of an increase in the number of commands that the printhead 100 and the printhead drive circuit 2 must manage, and improves the utilization efficiency of the storage areas of the printhead 100 and the printhead drive circuit 2.

[0277] Also, as shown in FIGS. 20 to 23, in this embodiment, the potential V1 of the voltage signal VS1 output by the discharge control unit 20 is different from the potential V2 of the voltage signal VS2, and the potential V1 of the voltage signal VS1 is greater than the potential V2 of the voltage signal VS2.

[0278] Specifically, the potential V1 of the voltage signal VS1 is higher than the high-level potential of the image data PD supplied from an external device 3 such as a host computer provided outside the liquid ejection device 1, and is higher than five times the high-level potential of the first command signal HCf output as the diagnostic control signal HC1, or is higher than 18.2 V. The potential V1 of the voltage signal VS1 is the second highest potential among the signals transmitted through the cable FC, after the voltage VHV, and is preferably higher than 10% of the effective value of the externally supplied alternating current voltage AC; for example, the potential V1 of the voltage signal VS1 is 70% or more of the voltage value of the voltage VHV, or 29.4 V or higher.

[0279] The voltage signal VS1 as the drive voltage signal VDR1 is supplied to the abnormality detection circuit 250 together with the diagnostic control signal HC1. Furthermore, while the voltage signal VS1 as the drive voltage signal VDR1 is a DC voltage, the first command signal HCf output as the diagnostic control signal HC1 is a digital signal that transmits information at a high frequency. Therefore, when the potential V1 of the voltage signal VS1 as the drive voltage signal VDR1 is the high level potential of the diagnostic control signal HC1, which is a potential around 3.3 V defined by the voltage VDD, the voltage signal VS1 is supplied with the diagnostic control signal HC1. As a result, the accuracy of the voltage detection signal DET based on the potential V1 of the voltage signal VS1 input to the abnormality detection circuit 250 decreases. That is, by setting the potential V1 of the voltage signal VS1, which is higher than the potential V2 of the voltage signal VS2, to a potential higher than the high level potential of the image data PD supplied from outside the liquid ejection device 1 and to a potential greater than 18.2 V or five times the potential of the high level of the first command signal HCf output as the diagnosis control signal HC1 during the period in which the voltage signal VS1 at potential V1 is output as the drive voltage signal VDR1, the risk of the accuracy of the voltage detection signal DET decreasing is reduced even when a low-potential digital signal such as the diagnosis control signal HC1 is superimposed on the potential V1 of the voltage signal VS1, and as a result, the accuracy of inspection of the potentials of the wiring WI-VDR1 and the terminal TM-VDR1 in the abnormality detection circuit 250 can be improved.

[0280] On the other hand, the potential V2 of the voltage signal VS2 is lower than five times the potential of the second command signal HCs output as the diagnosis control signal HC1 when it is at a high level, or lower than 18.2 V. Such a potential V2 of the voltage signal VS2 is 30% or less of the voltage VHV, for example, 12.6 V or less, and more preferably, is the ground potential.

[0281] This makes it possible to increase the potential difference between the potential V1 of the voltage signal VS1 as the drive voltage signal VDR1 input to the abnormality detection circuit 250 and the potential V2 of the voltage signal VS2, thereby further improving the inspection accuracy of the potentials of the wiring WI-VDR1 and the terminal TM-VDR1 in the abnormality detection circuit 250.

[0282] Furthermore, by setting the potential V2 of the voltage signal VS2, which is lower than the potential V1 of the voltage signal VS1, to a potential different from the range of potentials in which the potential V1 is determined to be normal, it is possible to reduce the risk that the abnormality detection circuit 250 will erroneously detect an abnormality in the wiring WI-VDR1 or the terminal TM-VDR1 when a short circuit abnormality occurs in the wiring WI-VDR1 or the terminal TM-VDR1 through which the drive voltage signal VDR1 propagates.

[0283] 20 to 23 illustrate a case where the potential V1 of the voltage signal VS1 and the potential V2 of the voltage signal VS2 output by the discharge control unit 20 are different potentials, with the potential V1 of the voltage signal VS1 being greater than the potential V2 of the voltage signal VS2. However, the potential V2 of the voltage signal VS2 may also be greater than the potential V1 of the voltage signal VS1. In this case, the potential V2 of the voltage signal VS2 may be higher than the high-level potential of the image data PD supplied from an external device 3, such as a host computer, external to the liquid ejection device 1, or may be higher than five times the high-level potential of the second command signal HCs output as the diagnostic control signal HC1, or may be higher than 18.2 V. Furthermore, the potential V2 of the voltage signal VS2 is the second highest potential among the signals transmitted through the cable FC, after the voltage VHV, and is preferably greater than 10% of the effective value of the externally supplied alternating current voltage AC. For example, the potential V2 of the voltage signal VS2 is greater than 70% of the voltage value of the voltage VHV, i.e., 29.4 V or greater.

[0284] On the other hand, the potential V1 of the voltage signal VS1 is lower than five times the potential of the first command signal HCf output as the diagnosis control signal HC1 when it is at a high level, or lower than 18.2 V. The potential V1 of such a voltage signal VS1 is 30% or less of the voltage VHV, for example, 12.6 V or less, and is preferably the ground potential. Even in this case, the same advantageous effects can be achieved.

[0285] As described above, in the liquid ejection device 1 of this embodiment, the print head 100 receives the first command signal HCf including the first command cmd1 and the second command cmd2 input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at the potential V1, and the third command c The print head drive circuit 2 includes an ejection control unit 20 that outputs the first command signal HCf and the second command signal HCs, a wiring WI-VDR1 electrically connected to the terminal TM-VDR1, and a wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC. The ejection control unit 20 outputs the first command signal HCf to the wiring WI-SI1 / HC when a voltage signal VS1 of potential V1 is supplied to the wiring WI-VDR1, and after outputting the first command signal HCf, when a voltage signal VS2 of potential V2 different from potential V1 is supplied to the wiring WI-VDR1, the ejection control unit 20 outputs the second command signal HCs to the wiring WI-SI1 / HC, causing the print head 100 to perform abnormality detection in response to the first command signal HCf, the second command signal HCs, the voltage signal VS1, and the voltage signal VS2.

[0286] As a result, in the liquid ejection device 1 of this embodiment, the drive voltage signal VDR1 based on the high voltage VHV includes a voltage signal VS1 at a potential V1 and a voltage signal VS2 at a potential V2 that is different from the potential V1, and it is detected whether the potentials of both the voltage signals VS1 and VS2 are normal. This makes it possible to detect the presence or absence of an abnormality in the propagation path along which the drive voltage signal VDR1, which includes the voltage signals VS1 and VS2 at different potentials, propagates. In other words, the liquid ejection device 1 of this embodiment can accurately determine whether an abnormality has occurred in the high-voltage drive voltage signal VDR1.

[0287] Furthermore, in the liquid ejection device 1 of this embodiment, it is also possible to detect a case where at least one of the first command signal HCf and the second command signal HCs is not input to the print head 100 as a normal command due to an abnormality occurring in at least one of the wiring WI-SI1 / HC, the wiring WI-SCK, the terminal TM-SI1 / HC, and the terminal TM-SCK.

[0288] As described above, in the liquid ejection device 1 of this embodiment, the determination control circuit 451 included in the abnormality detection circuit 250 controls the operation of the voltage input switching circuit 251, the voltage determination circuit 452, and the memory circuit 454 in response to the first command signal HCf or the second command signal HCs input in synchronization with the clock signal SCK, thereby determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the drive voltage signal VDR1 held on the wiring WI-VDR1 or the terminal TM-VDR1 are normal. Therefore, if an abnormality such as a short circuit or poor connection occurs in any of the wiring WI-SI1 / HC, the terminal TM-SI1 / HC, the wiring WI-SCK, or the terminal TM-SCK, causing an abnormality in at least one of the clock signal SCK, the first command signal HCf, and the second command signal HCs input to the print head 100, the determination control circuit 451 does not determine whether the voltage values ​​of the voltage signals VS1 and VS2 included in the drive voltage signal VDR1 held on the wiring WI-VDR1 or the terminal TM-VDR1 are normal. If the first command signal HCf and the second command signal HCs for determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the drive voltage signal VDR1 are normal are not input within a predetermined period after the POR of the semiconductor device 450 is executed, the determination control circuit 451 determines that an abnormality such as a short circuit or poor connection has occurred in any of the wiring WI-SI1 / HC, the terminal TM-SI1 / HC, the wiring WI-SCK, or the terminal TM-SCK, and that as a result, an abnormality has occurred in at least one of the clock signal SCK, the first command signal HCf, and the second command signal HCs input to the print head 100.

[0289] That is, in the liquid ejection device 1 of this embodiment, it is possible to determine whether an abnormality has occurred in at least one of the low-voltage clock signal SCK, the first command signal HCf, and the second command signal HCs, depending on whether the first command signal HCf and the second command signal HCs for determining whether the voltage values ​​of the voltage signals VS1 and VS2 included in the drive voltage signal VDR1 are normal or not, are input to the abnormality detection circuit 250 within a predetermined period. do.

[0290] As described above, in the liquid ejection device 1 of this embodiment, in response to the first command signal HCf including the first command cmd1 and the second command cmd2 input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at potential V1, and the second command signal HCs including the third command cmd3 and the fourth command cmd4 input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at potential V2, the ejection control unit 20 included in the print head drive circuit 2 outputs a voltage signal VS1 of potential V1 to the wiring WI-SI when the potential of the wiring WI-VDR1 is being supplied with the voltage signal VS1 of potential V1. After the first command signal HCf is output to the wiring WI-SI1 / HC, and after the first command signal HCf is output and a voltage signal VS2 of a potential V2 different from the potential V1 is supplied to the wiring WI-VDR1, a second command signal HCs is output to the wiring WI-SI1 / HC, and the print head 100 is caused to perform abnormality detection in accordance with the first command signal HCf, the second command signal HCs, the voltage signal VS1, and the voltage signal VS2, it is possible to determine whether the high-voltage signal and the low-voltage signal supplied to the print head 100 are normal, and as a result, the risk of malfunction of the print head 100 can be reduced.

[0291] Here, the predetermined period during which the determination control circuit 451 determines whether or not an abnormality has occurred in at least one of the low-voltage clock signal SCK, the first command signal HCf, and the second command signal HCs is not limited to the period after the execution of POR of the semiconductor device 450, but may be, for example, the period from when the first command cmd1 is input until when the second command cmd2 is input, the period from when the second command cmd2 is input until when the third command cmd3 is input, and the period from when the third command cmd3 is input until when the fourth command cmd4 is input.

[0292] 1.6.3 Printhead Inspection Method As described above, the liquid ejection device 1 having the print head 100 including the abnormality detection circuit 250 in this embodiment comprises the print head 100 that performs printing by supplying the drive signal COMA as the drive voltage signal VDR1 input to the terminal TM-VDR1 in response to the print data signal SI1 input to the terminal TM-SI1 / HC to the piezoelectric element 60 as the drive element, and the print head drive circuit 2 that causes the print head 100 to print.

[0293] The print head drive circuit 2 has an ejection control unit 20 that outputs a first command signal HCf and a second command signal HCs, a wiring WI-VDR1 that is electrically connected to the terminal TM-VDR1, and a wiring WI-SI1 / HC that is electrically connected to the terminal TM-SI1 / HC, and the ejection control unit 20 outputs the first command signal HCf to the wiring WI-SI1 / HC when a voltage signal VS1 of potential V1 is supplied to the wiring WI-VDR1, and outputs the second command signal HCs to the wiring WI-SI1 / HC after outputting the first command signal HCf when a voltage signal VS2 of potential V2 different from potential V1 is supplied to the wiring WI-VDR1.

[0294] In addition, the print head 100 processes the output of a circuit including a voltage input switching circuit 251 and a voltage evaluation circuit 452 electrically connected to the terminal TM-VDR1 in response to a first command signal HCf input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at potential V1, and processes the output of a circuit including a voltage input switching circuit 251 and a voltage evaluation circuit 452 electrically connected to the terminal TM-VDR1 in response to a second command signal HCs input to the terminal TM-SI1 / HC when the potential of the terminal TM-VDR1 is at potential V2.

[0295] Specifically, the print head 100 includes a terminal TM-SI1 / HC, a terminal TM-VDR1, a voltage input switching circuit 251, a voltage determination circuit 452, and an output switching circuit 453. The voltage input switching circuit 251 and the voltage evaluation circuit 452 determine whether the potential of the terminal TM-VDR1 is normal in response to the first command signal HCf input to the terminal TM-SI1 / HC, and also determine whether the potential of the terminal TM-VDR1 is normal in response to the second command signal HCs input to the terminal TM-SI1 / HC. In this case, the voltage input switching circuit 251 and the voltage evaluation circuit 452 determine whether the potential of the terminal TM-VDR1 is normal in response to the first command signal HCf input to the terminal TM-SI1 / HC based on the criteria specified by evaluation information c1, and determine whether the potential of the terminal TM-VDR1 is normal in response to the second command signal HCs input to the terminal TM-SI1 / HC based on the criteria specified by evaluation information c2, which is different from the evaluation information c1. That is, the voltage input switching circuit 251 and the voltage judgment circuit 452 judge whether the potential of the terminal TM-VDR1 is normal or not in response to the first command signal HCf input to the terminal TM-SI1 / HC, and judge whether the potential of the terminal TM-VDR1 is normal or not in response to the second command signal HCs input to the terminal TM-SI1 / HC using different criteria.

[0296] The output switching circuit 453 permits printing when it is determined that the potential of terminal TM-VDR1 is normal in both the determination of whether or not the potential of terminal TM-VDR1 is normal in response to the first command signal HCf input to terminal TM-SI1 / HC and the determination of whether or not the potential of terminal TM-VDR1 is normal in response to the second command signal HCs input to terminal TM-SI1 / HC, and does not permit printing when it is determined that the potential of terminal TM-VDR1 is not normal in at least one of the determination of whether or not the potential of terminal TM-VDR1 is normal in response to the first command signal HCf input to terminal TM-SI1 / HC and the determination of whether or not the potential of terminal TM-VDR1 is normal in response to the second command signal HCs input to terminal TM-SI1 / HC.

[0297] In the liquid ejection device 1 of this embodiment configured as described above, it is possible to check whether the signals supplied to the print head 100 are normal using the high-voltage drive voltage signal VDR1 and the low-voltage diagnostic control signal HC1 that the ejection control unit 20 outputs to the print head 100. This makes it possible to accurately determine whether the high-voltage and low-voltage signals supplied to the print head 100 are normal, thereby reducing the risk of the print head 100 malfunctioning due to the print head 100 receiving an abnormal signal, and allowing the print head drive circuit 2 to control the print head 100 depending on whether an abnormality has occurred in the print head 100.

[0298] A detailed description will be given of a method for inspecting such a print head 100. Figure 24 is a diagram showing a method for inspecting a print head 100 in a liquid ejection device 1. As shown in Figure 24, the method for inspecting a print head 100 in a liquid ejection device 1 includes a determination step (step S100) and an enabling step (step S300) that follows the determination step (step S100).

[0299] Fig. 25 is a diagram showing an example of the determination step. As shown in Fig. 25, in the determination step (step S100), the discharge control unit 20 generates a voltage signal VS1 of a constant DC voltage at a potential V1 as the drive voltage signal VDR1. Then, the discharge control unit 20 supplies the constant voltage signal VS1 at the potential V1 to the wiring WI-VDR1 and the terminal TM-VDR1 (step S110). Furthermore, the discharge control unit 20 generates a first command signal HCf as the diagnosis control signal HC. Then, the discharge control unit 20 outputs the first command signal HCf to the wiring WI-SI1 / HC and the terminal TM-SI1 / HC (step S120).

[0300] The first command signal HCf output by the discharge control unit 20 is sent to the determination control circuit 451 of the abnormality detection circuit 250 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC. The first command signal HCf is input. The determination control circuit 451 reads out the determination information c1 stored in the memory circuit 454 based on the first command signal HCf. That is, the determination control circuit 451 reads out the determination information c1 from the memory circuit 454 (step S130). Note that in step S130, if the first command signal HCf is not input to the determination control circuit 451 for a predetermined period of time, the determination control circuit 451 determines that an abnormality has occurred in the first command signal HCf. The determination control circuit 451 then generates a determination result signal ES indicating that an abnormality has occurred in the print head 100, and outputs it to the discharge control unit 20. At this point, the determination control circuit 451 may end the inspection of the print head 100.

[0301] Thereafter, the determination control circuit 451 controls the voltage input switching circuit 251 to generate a voltage detection signal DET corresponding to the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 based on the first command signal HCf, and controls the voltage determination circuit 452 to determine whether the potential of the voltage detection signal DET is normal or not based on the voltage detection signal DET and the determination information c1. That is, the determination control circuit 451 determines whether the potential of the terminal TM-VDR1 is normal or not based on the first command signal HCf input to the terminal TM-SI1 / HC1 (step S140).

[0302] Then, the determination control circuit 451 stores result information r1 including the determination result as to whether or not the potential of the terminal TM-VDR1 is normal in accordance with the first command signal HCf input to the terminal TM-SI1 / HC in the memory circuit 454. That is, the determination control circuit 451 stores the result information r1 in the memory circuit 454 (step S150).

[0303] Thereafter, the discharge control unit 20 generates a voltage signal VS2, which is a constant DC voltage at a potential V2 different from the potential V1, as the drive voltage signal VDR1. Then, the discharge control unit 20 supplies the constant voltage signal VS2 at the potential V2 to the wiring WI-VDR1 and the terminal TM-VDR1 (step S210). The discharge control unit 20 also generates a second command signal HCs as the diagnosis control signal HC. Then, the discharge control unit 20 outputs the second command signal HCs to the wiring WI-SI1 / HC and the terminal TM-SI1 / HC (step S220).

[0304] The second command signal HCs output by the discharge control unit 20 is input to the determination control circuit 451 of the abnormality detection circuit 250 via the wiring WI-SI1 / HC and the terminal TM-SI1 / HC. The determination control circuit 451 reads the determination information c2 stored in the memory circuit 454 based on the second command signal HCs. That is, the determination control circuit 451 reads the determination information c2 from the memory circuit 454 (step S230). Note that in step S230, if the second command signal HCs is not input to the determination control circuit 451 for a predetermined period, the determination control circuit 451 determines that an abnormality has occurred in the second command signal HCs. The determination control circuit 451 then generates a determination result signal ES indicating that an abnormality has occurred in the print head 100 and outputs it to the discharge control unit 20. At this time, the determination control circuit 451 may end the inspection of the print head 100.

[0305] Thereafter, the determination control circuit 451 controls the voltage input switching circuit 251 to generate a voltage detection signal DET according to the potentials held in the wiring WI-VDR1 and the terminal TM-VDR1 based on the second command signal HCs, and controls the voltage determination circuit 452 to determine whether the potential of the voltage detection signal DET is normal or not based on the voltage detection signal DET and the determination information c2. That is, the determination control circuit 451 determines whether the potential of the terminal TM-VDR1 is normal or not based on the second command signal HCs input to the terminal TM-SI1 / HC (step S240).

[0306] Then, the determination control circuit 451 receives the second command signal input to the terminal TM-SI1 / HC. The determination control circuit 451 stores result information r2, which includes the determination result as to whether the potential of the terminal TM-VDR1 is normal or not, in the storage circuit 454 in accordance with the signal HCs. That is, the determination control circuit 451 stores the result information r2 in the storage circuit 454 (step S250), and ends the determination step (step S100).

[0307] As described above, in the judgment process (step S100), a judgment including step S140 of determining whether the potential of terminal TM-VDR1 is normal in accordance with the first command signal HCf input to terminal TM-SI1 / HC, and a judgment including step S240 of determining whether the potential of terminal TM-VDR1 is normal in accordance with the second command signal HCs input to terminal TM-SI1 / HC are performed using different judgment criteria defined by judgment information c1 and judgment information c2, respectively.

[0308] Next, an example of the permission step (step S300) will be described. FIG. 26 is a diagram showing an example of the permission step. As shown in FIG. 26, in the permission step (step S300), the determination control circuit 451 reads out result information r1 and result information r2 from the memory circuit 454 (step S310). Then, the determination control circuit 451 determines whether or not both of the read result information r1 and result information r2 indicate that the potential of the terminal TM-VDR1 is normal (step S320).

[0309] If the determination control circuit 451 determines that both the result information r1 and the result information r2 indicate that the potential of the terminal TM-VDR1 is normal (Y in step S320), the determination control circuit 451 outputs a switch control signal OS to the output switching circuit 453 to control the switch group SW to be conductive (step S330). This controls the selector switches included in the switch group SW of the output switching circuit 453 to be conductive, and as a result, the clock signal SCK, the latch signal LAT, and the change signal CH are input to the drive signal selection circuit 200. Then, by inputting the clock signal SCK, the latch signal LAT, and the change signal CH, the drive signal selection circuit 200 supplies the drive signal VOUT to the piezoelectric element 60. In other words, printing on the medium P is permitted.

[0310] On the other hand, if the determination control circuit 451 determines that at least one of the result information r1 and the result information r2 does not indicate that the potential of the terminal TM-VDR1 is normal (N in step S320), the determination control circuit 451 outputs a switch control signal OS to the output switching circuit 453 to control the switch group SW to be non-conductive (step S340). As a result, the selector switches included in the switch group SW of the output switching circuit 453 are controlled to be non-conductive, and as a result, the clock signal SCK, the latch signal LAT, and the change signal CH are not input to the drive signal selection circuit 200. Therefore, the drive signal selection circuit 200 does not supply the drive signal VOUT to the piezoelectric element 60. In other words, printing on the medium P is not permitted.

[0311] As described above, in the enabling process (step S300), printing is enabled if the determination in step S140 and the determination in step S240 determines that the potential of terminal TM-VDR1 is normal, and printing is disabled if the determination in step S140 or step S240 determines that the potential of terminal TM-VDR1 is not normal. Specifically, in the enabling process (step S300), the selector switches included in the switch group SW of the output switching circuit 453 are controlled, thereby controlling the supply of the clock signal SCK, the latch signal LAT, and the change signal CH to the drive signal selection circuit 200, and controlling the supply of the drive signal VOUT based on the drive signals COMA and COMB to the piezoelectric element 60. That is, in the enabling process (step S300), whether printing is enabled or disabled is switched depending on whether the drive signal VOUT based on the drive signals COMA and COMB is supplied to the piezoelectric element 60.

[0312] Here, when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in response to the first command signal HCf input to the terminal TM-SI1 / HC, the potential V1 is held in the terminal TM-VDR1, and when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in response to the second command signal HCs input to the terminal TM-SI1 / HC, the potential V2 is held in the terminal TM-VDR1. In this case, the potential V1 held in the terminal TM-VDR1 and the potential V2 held in the terminal TM-VDR1 are different potentials.

[0313] For example, the potential V1 of the terminal TM-VDR1 when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in accordance with the first command signal HCf input to the terminal TM-SI1 / HC may be higher than the potential V2 of the terminal TM-VDR1 when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in accordance with the second command signal HCs input to the terminal TM-SI1 / HC, or the potential V2 of the terminal TM-VDR1 when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in accordance with the second command signal HCs input to the terminal TM-SI1 / HC may be higher than the potential of the terminal TM-VDR1 when the determination control circuit 451 determines that the potential of the terminal TM-VDR1 is normal in accordance with the first command signal HCf input to the terminal TM-SI1 / HC.

[0314] 24 to 26, the determination step (step S100) and the permission step (step S300) have been described as being performed by the abnormality detection circuit 250 of the print head 100, but at least part of the determination step (step S100) and the permission step (step S300) may be performed by the print head drive circuit 2. In other words, part of the configuration of the abnormality detection circuit 250 may be provided in the print head drive circuit 2. Even in this case, the same effects can be achieved.

[0315] Here, terminal TM-SI1 / HC included in connector CN is an example of a first terminal, terminal TM-VDR1 is an example of a second terminal, at least one of terminal TM-VHV and terminal TM-VDD is an example of a third terminal, terminal TM-SCK is an example of a fourth terminal, and terminal TM-ES is an example of a fifth terminal. Also, print data signal SI1 is an example of print data, first command signal HCf is an example of a first signal, second command signal HCs is an example of a second signal, potential V1 is an example of a first potential, and potential V2 is an example of a second potential. Furthermore, the voltage input switching circuit 251, the judgment control circuit 451, and the voltage judgment circuit 452 that judge whether the potential of the terminal TM-VDR1 is normal or not based on the first command signal HCf and the second command signal HCs are an example of a judgment circuit, the judgment control circuit 451 that controls whether printing is permitted or not based on the judgment results of the voltage input switching circuit 251, the judgment control circuit 451, and the voltage judgment circuit 452, and the output switching circuit 453 are an example of an permission circuit, and the semiconductor device 450 that constitutes at least a part of the voltage input switching circuit 251, the judgment control circuit 451, and the voltage judgment circuit 452 that are examples of judgment circuits, and at least a part of the judgment control circuit 451 and the output switching circuit 453 that are permission circuits is an example of a semiconductor integrated circuit, and the output switching circuit 453 is an example of a switch circuit.

[0316] Also, in view of the fact that the drive signal selection circuit 200 generates the drive signal VOUT to be supplied to the piezoelectric element 60, a configuration in which the drive signal selection circuit 200 is added to the determination control circuit 451 and the output switching circuit 453 is another example of an enabling circuit, and in this case, the drive signal selection circuit 200 is another example of a switch circuit. The determination in step S140 in the determination process (step S100) is an example of a first determination, and the determination in step S240 is an example of a second determination.

[0317] 1.7 Effects The print head 100 included in the liquid ejection device 1 configured as described above includes a voltage input switching circuit 251 and a voltage determination circuit 452 that determine whether the potential at terminal TM-VDR1 is normal in accordance with the first command signal HCf input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and that determine whether the potential at terminal TM-VDR1 is normal in accordance with the second command signal HCs input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK. As a result, if an abnormality occurs in at least one of the low-voltage first command signal HCf, the second command signal HCs input to terminal TM-SI1 / HC, and the clock signal SCK input to terminal TM-SCK, it is not possible to determine whether the signal input to the print head 100 is normal, and based on this inability to perform this determination, it is possible to determine that an abnormality has occurred in the signal input to the print head 100. Furthermore, it is possible to determine whether the potential of terminal TM-VDR1 is normal or not in accordance with the first command signal HCf input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and to determine whether the potential of terminal TM-VDR1 is normal or not in accordance with the second command signal HCs input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and to determine whether the high-voltage signal supplied to terminal TM-VDR1 is normal or not.

[0318] That is, in the print head 100 of this embodiment, it is possible to determine whether an abnormality has occurred in both the diagnostic control signal HC, which includes the low-voltage first command signal HCf and second command signal HCs, and the high-voltage drive voltage signal VDR1. This makes it possible to determine whether the high-voltage and low-voltage signals supplied to the print head 100 are normal, thereby reducing the risk of malfunction of the print head 100.

[0319] Furthermore, by determining whether the potential at terminal TM-VDR1 is normal in accordance with the first command signal HCf input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and then determining whether the potential at terminal TM-VDR1 is normal in accordance with the second command signal HCs input to terminal TM-SI1 / HC and the clock signal SCK input to terminal TM-SCK, and then permitting printing if the potential at terminal TM-VDR1 is normal in both determining whether the potential at terminal TM-VDR1 is normal in accordance with the first command signal HCf and determining whether the potential at terminal TM-VDR1 is normal in accordance with the second command signal HCs, it is possible to improve the accuracy of determining whether the high-voltage and low-voltage signals supplied to print head 100 are normal and further reduce the risk of malfunctioning of print head 100.

[0320] Furthermore, in the liquid ejection device 1 of this embodiment, when the potential of the terminal TM-VDR1 is at potential V1, outputs from the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 are processed in response to a first command signal HCf input to the terminal TM-SI1 / HC and a clock signal SCK input to the terminal TM-SCK, and when the potential of the terminal TM-VDR1 is at potential V2, outputs from the voltage input switching circuit 251 and the voltage determination circuit 452 electrically connected to the terminal TM-VDR1 are processed in response to a second command signal HCs input to the terminal TM-SI1 / HC and a clock signal SCK input to the terminal TM-SCK. The print head drive circuit 2, which processes the output from 52 and causes the print head 100 to perform printing, outputs a first command signal HCf to the wiring WI-SI1 / HC electrically connected to the terminal TM-SI1 / HC when the discharge control unit 20 is supplying a voltage signal VS1 of potential V1 to the wiring WI-VDR1 electrically connected to the terminal TM-VDR1, and outputs a second command signal HCs to the wiring WI-SI1 / HC after outputting the first command signal HCf and when the wiring WI-VDR1 is supplying a voltage signal VS2 of potential V2 different from potential V1 to the wiring WI-SI1 / HC. Printing is performed only when the potentials V1 and V2 input to the terminal TM-VDR1, the first command signal HCf and the second command signal HCs input to the terminal TM-SI1 / HC, and the clock signal SCK input to the terminal TM-SCK are input at different timings or in different states, and printing is not performed when at least one of the potentials V1 and V2 input to the terminal TM-VDR1, the first command signal HCf and the second command signal HCs input to the terminal TM-SI1 / HC, and the clock signal SCK input to the terminal TM-SCK is input at different timings or in different states.

[0321] That is, when a voltage signal VS1 at potential V1 is supplied to wiring WI-VDR1 electrically connected to terminal TM-VDR1 of the print head 100, the print head drive circuit 2 outputs a first command signal HCf to wiring WI-SI1 / HC electrically connected to terminal TM-SI1 / HC, outputs a clock signal SCK to wiring WI-SCK electrically connected to terminal TM-SCK, and, after outputting the first command signal HCf, when a voltage signal VS2 at potential V2, different from potential V1, is supplied to wiring WI-VDR1, outputs a second command signal HCs to wiring WI-SI1 / HC, and outputs a clock signal SCK to wiring WI-SCK electrically connected to terminal TM-SCK, thereby causing the print head 100 to diagnose whether the input signals are normal. This allows the print head drive circuit 2 to control the print head 100 based on whether the high-voltage signal and low-voltage signal supplied to the print head 100 are normal, thereby reducing the risk of malfunction of the print head 100.

[0322] Furthermore, in the liquid ejection device 1 of this embodiment, the print head 100 and the print head drive circuit 2 determine whether the signals input to the print head 100 are normal based on two different potentials, V1 and V2, and the first command signal HCf and second command signal HCs corresponding to the potentials V1 and V2, respectively, thereby improving the accuracy of determining whether the high-voltage signal and low-voltage signal supplied to the print head 100 are normal, and further reducing the risk of malfunctioning of the print head 100.

[0323] 1.8 Variations In the liquid ejection device 1 of this embodiment described above, an example is given in which the diagnostic control signal HC is transmitted over a common wiring WI-SI1 / HC together with the print data signal SI1 and is supplied to a common terminal TM-SI1 / HC, but the diagnostic control signal HC and the print data signal SI1 may be transmitted over different wiring WI, or may be input from different terminals TM.

[0324] Furthermore, in the liquid ejection device 1 of this embodiment described above, an example is given in which the voltage signals VS1, VS2 and drive signal COMA are propagated as the drive voltage signal VDR1 through a common wiring WI-VDR1 and supplied to a common terminal TM-VDR1, but the voltage signals VS1, VS2 and drive signal COMA may each be propagated through different wiring WI, or may be input from different terminals TM.

[0325] Furthermore, in the liquid ejection device 1 of this embodiment described above, an example is given in which the potential V1 of the voltage signal VS1 included in the drive voltage signal VDR1 is greater than the potential V2 of the voltage signal VS2, but the potential V2 of the voltage signal VS2 included in the drive voltage signal VDR1 may also be greater than the potential V1 of the voltage signal VS1.

[0326] The liquid ejection device 1 of the above modified example can also achieve the above-mentioned advantageous effects.

[0327] 2. Second embodiment Next, a liquid ejection device 1 according to a second embodiment will be described. In describing the liquid ejection device 1 according to the second embodiment, the same configuration as that of the liquid ejection device 1 according to the first embodiment will be described. The same reference numerals are used, and their explanations may be simplified or omitted.

[0328] Fig. 27 is a diagram showing the functional configuration of the print head 100 of the liquid ejection device 1 of the second embodiment. As shown in Fig. 27, the print head 100 of the second embodiment differs from the liquid ejection device 1 of the first embodiment in that print data signals SI2 to SIn are input to the abnormality detection circuit 250 in addition to print data signal SI1.

[0329] Specifically, the abnormality detection circuit 250 receives the diagnosis control signal HC, the print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, the change signal CH, and the drive voltage signal VDR1.

[0330] As in the first embodiment, the abnormality detection circuit 250 determines whether the signals transmitted to the print head 100 are normal based on the diagnosis control signal HC and the drive voltage signal VDR1. If the abnormality detection circuit 250 determines that the signals transmitted to the print head 100 are normal, it outputs the print data signals SI1 to SIn, the clock signal SCK, the latch signal LAT, and the change signal CH to the drive signal selection circuits 200-1 to 200-n.

[0331] The liquid ejection device 1 of the second embodiment configured as above also achieves the same effects as the liquid ejection device 1 shown in the first embodiment.

[0332] Furthermore, in the liquid ejection device 1 of the second embodiment, the diagnostic control signal HC may be propagated through each of the wirings through which the print data signals SI1 to SIn propagate, and in this case, the diagnostic control signal HC may include, as first command signals HCf, a first command signal HCf1 corresponding to the print data signal SI1, a first command signal HCfn corresponding to the print data signal SIn, and a first command signal HCfj corresponding to the print data signal SIj (j is any of 1 to n). Similarly, the diagnostic control signal HC may include, as second command signals HCs, a second command signal HCs1 corresponding to the print data signal SI1, a second command signal HCsn corresponding to the print data signal SIn, and a second command signal HCsj corresponding to the print data signal SIj (j is any of 1 to n).

[0333] In the cable FC, the print data signal SI1 and the first command signal HCf1 and second command signal HCs1 included in the diagnostic control signal HC propagate through a common wiring WI and terminal TM, the print data signal SIn and the first command signal HCfn and second command signal HCsn included in the diagnostic control signal HC1 propagate through a common wiring WI and terminal TM, and the print data signal SIj and the first command signal HCfj and second command signal HCsj included in the diagnostic control signal HC1 propagate through a common wiring WI and terminal TM.

[0334] By recognizing that all of the input first command signals HCf1-HCfn are normal, the abnormality detection circuit 250 determines whether the potentials of the wiring WI-VDR1 and terminal TM-VDR1 to which the voltage signal VS1 of potential V1 is supplied are normal, and by recognizing that all of the second command signals HCs1-HCsn are normal, it determines whether the potentials of the wiring WI-VDR1 and terminal TM-VDR1 to which the voltage signal VS2 of potential V2 is supplied are normal. This makes it possible to determine whether the potentials of the wiring WI and terminal TM to which the print data signals SI2-SIn are propagated, as well as the wiring WI and terminal TM to which the print data signals SI1 are propagated, are normal. As a result, it is possible to increase the accuracy of determining whether the high-voltage and low-voltage signals supplied to the print head 100 are normal, further reducing the risk of malfunction of the print head 100.

[0335] 3. Third embodiment Next, a liquid ejection device 1 according to a third embodiment will be described. In describing the liquid ejection device 1 according to the third embodiment, the same components as those of the liquid ejection device 1 according to the first embodiment and the liquid ejection device 1 according to the second embodiment will be denoted by the same reference numerals, and their description may be simplified or omitted.

[0336] Figure 28 is a diagram showing the functional configuration of the print head 100 of the liquid ejection device 1 of the third embodiment. As shown in Figure 28, the print head 100 of the third embodiment differs from the liquid ejection devices 1 of the first and second embodiments in that it has n abnormality detection circuits 250 corresponding to the drive signal selection circuits 200-1 to 200-n, respectively. Here, the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-1 will be referred to as abnormality detection circuit 250-1, the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-n will be referred to as abnormality detection circuit 250-n, and the abnormality detection circuit 250 corresponding to the drive signal selection circuit 200-j (j is any of 1 to n) will be referred to as abnormality detection circuit 250-n.

[0337] Specifically, the abnormality detection circuit 250-1 receives the diagnostic control signal HC, print data signal SI1, clock signal SCK, latch signal LAT, change signal CH, and drive voltage signal VDR1 as inputs. Then, based on the diagnostic control signal HC and drive voltage signal VDR1, the abnormality detection circuit 250-1 determines whether the signals transmitted to the print head 100 are normal, and if it determines that the signals transmitted to the print head 100 are normal, it outputs the print data signal SI1, clock signal SCK, latch signal LAT, and change signal CH to the drive signal selection circuit 200-1.

[0338] Similarly, the abnormality detection circuit 250-n receives the diagnostic control signal HC, the print data signal SIn, the clock signal SCK, the latch signal LAT, the change signal CH, and the drive voltage signal VDR1 as inputs. The abnormality detection circuit 250-n then determines whether the signals transmitted to the print head 100 are normal based on the diagnostic control signal HC and the drive voltage signal VDR1, and if it determines that the signals transmitted to the print head 100 are normal, it outputs the print data signal SIn, the clock signal SCK, the latch signal LAT, and the change signal CH to the drive signal selection circuit 200-n.

[0339] Similarly, the abnormality detection circuit 250-j receives the diagnosis control signal HC, the print data signal SIj, the clock signal SCK, the latch signal LAT, the change signal CH, and the drive voltage signal VDR1 as inputs. The abnormality detection circuit 250-j then determines whether the signals transmitted to the print head 100 are normal based on the diagnosis control signal HC and the drive voltage signal VDR1, and if it determines that the signals transmitted to the print head 100 are normal, it outputs the print data signal SIj, the clock signal SCK, the latch signal LAT, and the change signal CH to the drive signal selection circuit 200-j.

[0340] The liquid ejection device 1 of the third embodiment configured as above also achieves the same effects as the liquid ejection device 1 shown in the first embodiment.

[0341] Furthermore, in the liquid ejection device 1 of the third embodiment, the diagnostic control signal HC is branched by the ejection control unit 20, and one of the branches of the diagnostic control signal HC propagates over the same wiring WI and terminal TM as the print data signal SI1, a different branch of the diagnostic control signal HC propagates over the same wiring WI and terminal TM as the print data signal SIn, and yet another different branch of the diagnostic control signal HC propagates over the same wiring WI and terminal TM as the diagnostic control signal HCj and the print data signal SIj. This enables the abnormality detection circuits 250-1 to 250-n to determine whether the potentials of the wiring WI and terminal TM through which the print data signals SI2 to SIn propagate, in addition to the wiring WI and terminal TM through which the print data signal SI1 propagates, are normal. As a result, This increases the accuracy of determining whether the low-voltage signal is normal, and further reduces the risk of malfunction of the print head 100.

[0342] Furthermore, the semiconductor device 450 included in each of the abnormality detection circuits 250-1 to 250-n and the semiconductor device 201 including the drive signal selection circuit 200 corresponding to each of the abnormality detection circuits 250-1 to 250-n may be configured in a single integrated circuit, which allows the print head 100 to be made smaller.

[0343] Although the embodiments and modifications have been described above, the present invention is not limited to these embodiments and can be embodied in various forms without departing from the spirit of the present invention. For example, the above embodiments can be combined as appropriate.

[0344] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0345] The following can be derived from the above-described embodiment.

[0346] One embodiment of the print head comprises: A print head that performs printing by supplying a drive signal input to a second terminal to a drive element in accordance with print data input to a first terminal, the first terminal; the second terminal; a determination circuit that performs a first determination of whether or not the potential of the second terminal is normal in accordance with a first signal input to the first terminal, and a second determination of whether or not the potential of the second terminal is normal in accordance with a second signal input to the first terminal, using different determination criteria; an enabling circuit that enables printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and that does not enable printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Equipped with.

[0347] In this printhead, the judgment circuit performs a first judgment to determine whether the potential of the second terminal through which a high-voltage signal such as a drive signal is propagated is normal, based on a first signal input to the first terminal through which a low-voltage signal such as print data is propagated, and a second judgment to determine whether the potential of the second terminal through which a high-voltage signal such as a drive signal is propagated is normal, based on a second signal input to the first terminal through which a low-voltage signal such as print data is propagated, using judgment criteria different from those for the first judgment.The permission circuit permits printing if it is determined in both the first and second judgments that the potential of the second terminal is normal, and does not permit printing if it is determined in the first or second judgment that the potential of the second terminal is not normal.In other words, printing is permitted if both signals of different potentials input to the second terminal are normal, based on the low-voltage signal input to the first terminal.

[0348] That is, the print head determines whether the signal of the first potential input to the second terminal is normal or not in response to the first signal input to the first terminal, and determines whether the signal of the second potential input to the second terminal is normal or not in response to the second signal input to the first terminal. Furthermore, in view of the fact that the print head determines whether the high potential signal is normal or not in response to the first and second signals of low potential, the print head determines whether the high potential signal is normal or not in response to the first and second signals of low potential. If the first signal and the second signal are not normal, the print head does not determine whether the high-voltage signal is normal. In other words, the print head also determines whether the low-voltage signal is normal depending on whether the print head determines whether the high-voltage signal is normal.

[0349] This allows the print head to detect whether both the high-voltage signal and the low-voltage signal supplied thereto are normal, thereby reducing the risk of malfunction of the print head.

[0350] Furthermore, by determining whether or not both of the different potentials input to the second terminal are normal using different criteria, it is possible to detect whether or not both the high-voltage signal and the low-voltage signal supplied to the print head are normal even if an abnormality occurs, such as when only a fixed output is supplied, and the risk of malfunctioning of the print head can be further reduced.

[0351] In one embodiment of the print head, The first potential, which is the potential of the second terminal when the judgment circuit judges that the first judgment is normal, may be higher than the second potential, which is the potential of the second terminal when the judgment circuit judges that the second judgment is normal, and may be higher than the potential of the signal input to the first terminal.

[0352] With this print head, even if the first potential of the second terminal when the judgment circuit judges that the print head is normal in the first judgment is greater than the second potential of the second terminal when the judgment circuit judges that the print head is normal in the second judgment and is also greater than the potential of the signal input to the first terminal, it is possible to detect whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal, thereby reducing the risk of malfunction of the print head.

[0353] In one embodiment of the print head, The first potential may be greater than five times the potential when the first signal is at a high level.

[0354] With this print head, the first potential is more than five times the potential when the first signal is at a high level, so even if the first signal is superimposed on the signal at the first potential, the influence of the first signal on the signal at the first potential can be reduced, thereby improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0355] In one embodiment of the print head, The second potential may be less than five times the potential when the second signal is at a high level.

[0356] With this print head, the first potential signal and the second potential signal can be set to different voltage values ​​based on a single threshold, and the potential difference between the first potential and the second potential can be increased, thereby improving the accuracy of detecting the first potential and the second potential in the print head and improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0357] In one embodiment of the print head, The first potential may be greater than 18.2V.

[0358] With this print head, by making the first potential greater than 18.2 V, it can be made sufficiently greater than the potential of the first signal, such as 3.3 V. As a result, even if the first signal is superimposed on the signal of the first potential, the influence of the first signal on the signal of the first potential can be reduced. This improves the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0359] In one embodiment of the print head, The second potential may be less than 18.2V.

[0360] With this print head, the first potential signal and the second potential signal can be set to different voltage values ​​based on a single threshold, and the potential difference between the first potential and the second potential can be increased, thereby improving the accuracy of detecting the first potential and the second potential in the print head and improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0361] In one embodiment of the print head, At least a part of the determination circuit and at least a part of the permission circuit may be configured in a single semiconductor integrated circuit.

[0362] This print head allows the print head to be made smaller.

[0363] In one embodiment of the print head, The first signal may include a first command and a second command following the first command.

[0364] In one embodiment of the print head, The second signal may include a third command and a fourth command following the third command.

[0365] In one embodiment of the print head, The first command and the third command may include different information.

[0366] With this print head, the criteria for the first determination made based on the first signal and the criteria for the second determination made based on the second signal can be arbitrarily defined by the first command and the third command, thereby improving the accuracy and versatility of detection for determining whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0367] In one embodiment of the print head, The second command and the fourth command may include the same information.

[0368] According to this print head, since at least some of the commands are common between the first signal and the second signal, it is possible to reduce the amount of command information that needs to be managed by the print head.

[0369] In one embodiment of the print head, The first terminal and the second terminal may be included in one connector.

[0370] This printhead reduces the risk of variations occurring between the length of the wiring through which the signal input from the first terminal propagates and the length of the wiring through which the signal input from the second terminal propagates, thereby reducing the risk of variations occurring in the propagation time of the signal. This improves the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the head are normal.

[0371] In one embodiment of the print head, The connector may include a third terminal that carries a power supply voltage.

[0372] In one embodiment of the print head, The connector may include a fourth terminal that carries a clock signal.

[0373] In one embodiment of the print head, The connector may include a fifth terminal that propagates a signal indicating the determination result of the determination circuit.

[0374] In one embodiment of the print head, The permission circuit may include a switch circuit that switches between permitting and disallowing printing.

[0375] In one embodiment of the print head, The switch circuit may switch whether or not the drive signal is supplied to the drive element.

[0376] With this print head, even when the switch circuit switches between supplying a drive signal to the drive element to permit or prohibit printing, it is possible to detect whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0377] One aspect of a method for inspecting a print head includes: A method for inspecting a print head that performs printing by supplying a drive signal to a drive element that is input to a second terminal in response to print data that is input to a first terminal, comprising: a determination step of performing a first determination of whether or not the potential of the second terminal is normal in accordance with a first signal input to the first terminal, and a second determination of whether or not the potential of the second terminal is normal in accordance with a second signal input to the first terminal, using different determination criteria; an enabling step of enabling printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and disallowing printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Includes:

[0378] According to this printhead inspection method, the determination step includes a first determination of whether the potential of the second terminal through which a high-voltage signal such as a drive signal is propagated is normal, based on a first signal input to the first terminal through which a low-voltage signal such as print data is propagated, and a second determination of whether the potential of the second terminal through which a high-voltage signal such as a drive signal is propagated is normal, based on a second signal input to the first terminal through which the low-voltage signal such as print data is propagated, using a determination criterion different from that of the first determination.The permitting step includes permitting printing if the potential of the second terminal is determined to be normal in both the first and second determinations, and disallowing printing if the potential of the second terminal is determined to be abnormal in the first or second determination.That is, printing is permitted if both signals of different potentials input to the second terminal are normal, based on the low-voltage signal input to the first terminal.

[0379] That is, according to this print head inspection method, in the determining step, it is determined whether the signal of the first potential input to the second terminal is normal or not in accordance with the first signal input to the first terminal. In the determination step, whether the signal of the second potential input to the second terminal is normal is determined based on different determination criteria depending on the second signal input to the first terminal. In consideration of the fact that the determination of whether the high-potential signal is normal is performed in accordance with the first and second low-potential signals in the determination step, if it is determined that the signals input to the first and second terminals are normal, a determination of whether the high-potential signal is normal is performed, and if it is determined that the first and second signals are not normal, a determination of whether the high-potential signal is normal is not performed. In other words, in the determination step, whether the low-voltage signal is normal is also determined depending on whether a determination of whether the high-potential signal is normal is performed.

[0380] As a result, this print head inspection method can detect whether both the high voltage signal and the low voltage signal supplied to the print head are normal, thereby reducing the risk of malfunctioning of the print head.

[0381] Furthermore, by determining whether or not both of the different potentials input to the second terminal are normal using different criteria, even if an abnormality occurs, such as only a fixed output being supplied, it is possible to detect whether or not both the high-voltage signal and the low-voltage signal supplied to the print head are normal, further reducing the risk of malfunctioning of the print head.

[0382] In one aspect of the print head inspection method, The first potential, which is the potential of the second terminal when the first judgment determines that the signal is normal, may be higher than the second potential, which is the potential of the second terminal when the second judgment determines that the signal is normal, and may also be higher than the potential of the signal input to the first terminal.

[0383] According to this print head inspection method, even if the first potential of the second terminal when the first judgment indicates that the print head is normal is greater than the second potential of the second terminal when the second judgment indicates that the print head is normal and is greater than the potential of the signal input to the first terminal, it is possible to detect whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal, thereby reducing the risk of malfunction of the print head.

[0384] In one aspect of the print head inspection method, The first potential may be greater than five times the potential when the first signal is at a high level.

[0385] According to this print head inspection method, the first potential is more than five times the potential when the first signal is at a high level, so that even if the first signal is superimposed on the signal at the first potential, the influence of the first signal on the signal at the first potential can be reduced, thereby improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0386] In one aspect of the print head inspection method, The second potential may be less than five times the potential when the second signal is at a high level.

[0387] According to this printhead inspection method, the first potential signal and the second potential signal can be set to different voltage values ​​based on a single threshold, and the potential difference between the first potential and the second potential can be increased, thereby improving the accuracy of detecting the first potential and the second potential, and improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the printhead are normal.

[0388] In one aspect of the print head inspection method, The first potential may be greater than 18.2V.

[0389] According to this print head inspection method, by setting the first potential to be greater than 18.2 V, it can be made sufficiently greater than the potential of, for example, 3.3 V used as the first signal, and as a result, even if the first signal is superimposed on the signal of the first potential, the influence of the first signal on the signal of the first potential can be reduced. This improves the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0390] In one aspect of the print head inspection method, The second potential may be less than 18.2V.

[0391] According to this printhead inspection method, the first potential signal and the second potential signal can be set to different voltage values ​​based on a single threshold, and the potential difference between the first potential and the second potential can be increased, thereby improving the accuracy of detecting the first potential and the second potential, and improving the accuracy of detecting whether both the high-voltage signal and the low-voltage signal supplied to the printhead are normal.

[0392] In one aspect of the print head inspection method, At least a part of the determining step and at least a part of the enabling step may be executed in one semiconductor integrated circuit.

[0393] In one aspect of the print head inspection method, The first signal may include a first command and a second command following the first command.

[0394] In one aspect of the print head inspection method, The second signal may include a third command and a fourth command following the third command.

[0395] In one aspect of the print head inspection method, The first command and the third command may include different information.

[0396] According to this print head inspection method, the criteria for the first judgment made based on the first signal and the criteria for the second judgment made based on the second signal can be arbitrarily defined by the first command and the third command, thereby improving the accuracy and versatility of detection as to whether both the high-voltage signal and the low-voltage signal supplied to the print head are normal.

[0397] In one aspect of the print head inspection method, The second command and the fourth command may include the same information.

[0398] According to this print head inspection method, the first signal and the second signal have at least some of the commands in common, which reduces the amount of command information that needs to be managed.

[0399] In one aspect of the print head inspection method, The first terminal and the second terminal may be included in one connector.

[0400] In one aspect of the print head inspection method, The connector may include a third terminal that carries a power supply voltage.

[0401] In one aspect of the print head inspection method, The connector may include a fourth terminal that carries a clock signal.

[0402] In one aspect of the print head inspection method, The connector may include a fifth terminal that propagates a signal indicating the determination result in the determining step.

[0403] In one aspect of the print head inspection method, The enabling step may switch between enabling and disabling printing depending on whether the drive signal is supplied to the drive element.

[0404] According to this print head inspection method, even when switching between permitting and disallowing printing by switching between supplying and disallowing a drive signal to the drive element, it is possible to detect whether both the high voltage signal and the low voltage signal supplied to the print head are normal. [Explanation of symbols]

[0405] 1...liquid ejection device, 2...print head drive circuit, 3...external device, 5...liquid container, 7...commercial AC power supply, 8...pump, 10...main control unit, 11...main control circuit, 12...power supply voltage output circuit, 20...ejection control unit, 21...ejection control circuit, 22-1 to 22-m...differential signal restoration circuit, 35...support member, 40...transport mechanism, 50...drive voltage output circuit, 51a, 51b...drive circuit, 53...reference voltage output circuit, 60...piezoelectric element, 100...print head, 110...filter section, 113...filter, 115, 117...opening, 120...seal Component, 123...through opening, 125, 127...opening, 130...wiring board, 135...notch, 136...FPC insertion hole, 137...FPC notch, 138...connection terminal, 140...holder, 141-143...holder member, 145...liquid flow path, 146...slit hole, 150...fixing plate, 151...flat portion, 152-154...bent portion, 155...opening, 191, 192...short sides, 193, 194...long sides, 200...drive signal selection circuit, 201...semiconductor device, 210...selection control circuit, 212...register, 214...latch circuit, 216...decoder, 230...selection Circuit, 232a, 232b... inverter, 234a, 234b... transfer gate, 250... abnormality detection circuit, 251... voltage input switching circuit, 300... head chip, 310... nozzle plate, 321... flow path forming substrate, 322... pressure chamber substrate, 323... protection substrate, 324... case, 330... compliance portion, 331... sealing film, 332... support, 340... diaphragm, 346... flexible wiring substrate, 351 to 353... opening, 355... communicating flow path, 360... ink flow path, 361... liquid inlet, 363... individual flow path, 365... communicating flow path, 367... Reservoir, 369... pressure chamber, 400... substrate, 401, 402... surfaces, 403 to 406... edges, 410... wiring board, 411, 412... surfaces, 413... connection portion, 420... wiring board, 421, 422... surfaces, 423 to 427... connection portion, 428, 450... semiconductor device, 451... judgment control circuit, 452... voltage judgment circuit, 453... output switching circuit, 454... memory circuit, 500... integrated circuit, 510... modulation circuit, 512, 513... adder, 514... comparator, 515... inverter, 516... integral attenuator, 517... attenuator, 520... gate drive circuit, 521,522...Gate driver, 550...Amplification circuit, 560...Smoothing circuit, 570, 572...Feedback circuit, 580...Power supply circuit, 600...Discharge part, 651...Nozzle, AD1...Air exhaust port, AS1, AS2...Air inlet port, C1 to C6...Capacitor, CI...Cable mounting part, CN, CN1, CN2...Connector, Cnt...Contact part, D1...Diode, EC...Insulator, EL1...Cable holding part, EL2...Housing insertion part, EL3...Board mounting part, ER1, ER2...Terminal, FC, FC1, FC2...Cable, G1...Inlet flow path part, G2...Supply control part, G3...Head support part, G4...Discharge control part, HP...Housing, ID, 1...liquid outlet, IS1 to IS3...liquid inlet, L1...coil, M1, M2, M10, M11...transistor, P...medium, P-CH, P-HS1, P-LAT, P-SCK, P-SI1, P-VDR1, P-VDR2...wiring, R1 to R6, R10 to R13...resistor, SW...switch group, TM, TM-CH, TM-ES, TM-LAT, TM-SCK, TM-VDD, TM-VDR1, TM-VDR2, TM-VHV...terminal, U...pressure adjustment unit, WI, WI-CH, WI-ES, WI-LAT, WI-SCK, WI-VDD, WI-VDR1, WI-VDR2, WI-VHV...wiring, c1, c2...judgment information, r1, r2...result information, st...stop information

Claims

1. A print head that performs printing by supplying a drive signal input to a second terminal to a drive element in accordance with print data input to a first terminal, the first terminal; the second terminal; a determination circuit that performs a first determination of whether or not the potential of the second terminal is normal based on first determination information corresponding to a first signal input to the first terminal, and a second determination of whether or not the potential of the second terminal is normal based on second determination information corresponding to a second signal input to the first terminal after the first determination; a permission circuit that permits printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and that does not permit printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Equipped with at least one of a first potential which is a potential of the second terminal when the determination circuit determines that the first determination is normal and a second potential which is different from the first potential and is a potential of the second terminal when the determination circuit determines that the second determination is normal is higher than a potential of a signal input to the first terminal; A print head characterized by:

2. the first potential, which is the potential of the second terminal when the determination circuit determines that the first determination is normal, is higher than the second potential, which is the potential of the second terminal when the determination circuit determines that the second determination is normal, and is higher than the potential of a signal input to the first terminal; 2. The printhead of claim 1.

3. the first potential is greater than five times the potential when the first signal is at a high level; 3. The printhead of claim 2.

4. the second potential is less than five times the potential when the second signal is at a high level; 4. The printhead of claim 3.

5. the first potential is greater than 18.2 V; 3. The printhead of claim 2.

6. the second potential is less than 18.2 V; 6. The printhead of claim 5.

7. At least a part of the determination circuit and at least a part of the permission circuit are configured in a single semiconductor integrated circuit.

7. A printhead according to claim 1.

8. the first signal includes a first command and a second command following the first command; 8. A printhead according to claim 1.

9. the second signal includes a third command and a fourth command following the third command; 9. The printhead of claim 8.

10. the first command and the third command include different information; 10. The printhead of claim 9.

11. the second command and the fourth command include the same information; 11. A print head according to claim 9 or 10.

12. The first terminal and the second terminal are included in one connector.

12. A printhead according to any preceding claim.

13. the connector includes a third terminal that carries a power supply voltage; 13. The printhead of claim 12.

14. the connector includes a fourth terminal that carries a clock signal.

14. A printhead according to claim 12 or 13.

15. the connector includes a fifth terminal that propagates a signal indicating the determination result of the determination circuit; 15. A printhead according to any one of claims 12 to 14.

16. the permission circuit includes a switch circuit that switches between permitting and disallowing printing; 16. A printhead according to any preceding claim.

17. the switch circuit switches whether or not the drive signal is supplied to the drive element; 17. The printhead of claim 16.

18. 1. A method for inspecting a print head that performs printing by supplying a drive signal to a drive element that is input to a second terminal in response to print data that is input to a first terminal, the method comprising: a first determination of whether or not the potential of the second terminal is normal based on first determination information corresponding to a first signal input to the first terminal; and after the first determination, determining whether or not the potential of the second terminal is normal based on second determination information corresponding to a second signal input to the first terminal. a second judgment step of making a judgment; an enabling step of enabling printing when it is determined in the first determination and the second determination that the potential of the second terminal is normal, and disallowing printing when it is determined in the first determination or the second determination that the potential of the second terminal is not normal; Including, at least one of a first potential which is a potential of the second terminal when it is determined that the first determination is normal and a second potential which is different from the first potential and is a potential of the second terminal when it is determined that the second determination is normal is higher than a potential of a signal input to the first terminal; A method for inspecting a print head.

19. the first potential, which is the potential of the second terminal when it is determined that the first determination is normal, is higher than the second potential, which is the potential of the second terminal when it is determined that the second determination is normal, and is higher than the potential of the signal input to the first terminal; 20. The method of claim 18, wherein the printhead is inspected.

20. the first potential is greater than five times the potential when the first signal is at a high level; 20. The method of claim 19, wherein the printhead is inspected.

21. the second potential is less than five times the potential when the second signal is at a high level; 21. The method of claim 20, wherein the printhead is inspected.

22. the first potential is greater than 18.2 V; 20. The method of claim 19, wherein the printhead is inspected.

23. the second potential is less than 18.2 V; 23. The method of claim 22, wherein the printhead is inspected.

24. at least a part of the determining step and at least a part of the enabling step are executed by a single semiconductor integrated circuit; 24. The method of inspecting a print head according to any one of claims 18 to 23.

25. the first signal includes a first command and a second command following the first command; 25. The method of inspecting a print head according to any one of claims 18 to 24.

26. the second signal includes a third command and a fourth command following the third command; 26. The method of claim 25, wherein the printhead is inspected.

27. the first command and the third command include different information; 27. The method of claim 26, wherein the printhead is inspected.

28. the second command and the fourth command include the same information; 28. The method of inspecting a print head according to claim 26 or 27.

29. The first terminal and the second terminal are included in one connector.

29. The method for inspecting a print head according to claim 18, Law.

30. the connector includes a third terminal that carries a power supply voltage; 30. The method of claim 29, wherein the printhead is inspected.

31. the connector includes a fourth terminal that carries a clock signal.

31. The method of inspecting a print head according to claim 29 or 30.

32. the connector includes a fifth terminal that propagates a signal indicating a determination result in the determining step; 32. The method of claim 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58

33. the enabling step switches between enabling and disabling printing depending on whether the drive signal is supplied to the drive element; 33. A method for inspecting a printhead according to any one of claims 18 to 32.

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