Electronic device, image forming apparatus, and power supply control method for electronic device

Abstract

To generate an appropriate voltage in a power supply generation unit without mediation of a program to be executed by a processor.SOLUTION: An electronic apparatus includes: a processor; a memory that stores a program to be executed by the processor and that operates in synchronization with a clock signal while receiving a clock enable signal of a valid level from the processor; a frequency detection unit that detects a frequency the clock enable signal is set to the valid level; a power supply generation unit that generates a voltage, and sets the voltage when the frequency detected by the frequency detection part is low to be lower than the voltage when the frequency is high; and a function unit that operates with the voltage generated by the power supply generation unit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an electronic device, an image forming apparatus, and a power supply control method for an electronic device. [Background technology]

[0002] For example, an image forming apparatus may have a main power supply unit that operates in a normal mode in which the print engine is driven, and a sub-power supply unit that operates in the normal mode and in an energy-saving mode in which the print engine is not driven. The main power supply unit is operated or stopped depending on the operating mode, thereby switching the power supply capacity to the load. Summary of the Invention [Problem to be solved by the invention]

[0003] In electronic devices such as the image forming apparatus described above, a control program executed by a processor mounted on a control board switches between generating and stopping voltage from the main power supply, thereby changing the value of the voltage supplied to the functional units. However, no method has been proposed for appropriately changing the value of the voltage supplied to the functional units in accordance with the operating state of the functional units without using a control program.

[0004] In view of the above problems, an object of the present invention is to allow a power supply generating unit to generate an appropriate voltage without the intervention of a program executed by a processor. [Means for solving the problem]

[0005] In order to solve the above technical problems, one form of electronic device of the present invention is characterized by having a processor, a memory that stores a program to be executed by the processor and operates in synchronization with a clock signal while receiving a clock enable signal of an effective level from the processor, a frequency detection unit that detects the frequency at which the clock enable signal is set to an effective level, a power generation unit that generates a voltage and sets the voltage when the frequency detected by the frequency detection unit is low to be lower than the voltage when the frequency is high, and a functional unit that operates using the voltage generated by the power generation unit. [Effects of the Invention]

[0006] The power supply generating unit can generate an appropriate voltage without the intervention of a program executed by the processor. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating an overall configuration of an example of an image forming apparatus according to a first embodiment of the present invention. [Figure 2] 2 is a state transition diagram showing an example of transition of operation modes of the image forming apparatus of FIG. 1. FIG. [Figure 3] 2 is a circuit block diagram showing an outline of a hardware configuration of a main part of the image forming apparatus of FIG. 1. FIG. [Figure 4] 4 is a circuit block diagram showing an example of a power supply generating unit in FIG. 3. [Figure 5] 4 is an explanatory diagram showing an example of the relationship between a selection signal generated by a power supply control unit in FIG. 3 and a set value of a DC voltage generated by a voltage generating unit. [Figure 6] FIG. 10 is a circuit block diagram showing an outline of the hardware configuration of the main parts of an image forming apparatus according to a second embodiment of the present invention. [Figure 7] 7 is a circuit block diagram showing an example of a power supply control unit and a power supply generating unit in FIG. 6. FIG. [Figure 8] 8 is an explanatory diagram showing an example of set values ​​for FB voltage stored in the ROM of FIG. 7. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the signal lines through which information such as signals is transmitted will be designated by the same reference numerals as the signal names. In addition, the voltage lines through which voltages are transmitted will be designated by the same reference numerals as the voltage names. In each drawing, the same components will be designated by the same reference numerals, and duplicate explanations may be omitted.

[0009] <Overall configuration of image forming apparatus> FIG. 1 is a diagram illustrating an overall configuration of an example of an image forming apparatus according to an embodiment of the present invention. The image forming apparatus 100 is a multi-function printer (MFP) that includes functions such as a copy function, a fax function, a print function, and a scanner function. The image forming apparatus 100 is an example of an electronic device. The image forming apparatus 100 may have a function for saving an input image or a function for distributing the input image. For example, the input image is a document scanned by the scanner function or an image input by the fax function.

[0010] Image forming apparatus 100 can communicate with external devices such as PCs (Personal Computers) and can operate in accordance with instructions received from the external devices. In the embodiment, the images processed by image forming apparatus 100 may include not only image data including images, but also text data that does not include images.

[0011] The image forming apparatus 100 is a so-called electrophotographic image forming apparatus. The image forming apparatus 100 forms an electrostatic latent image by selectively exposing a charged photosensitive surface, causes toner to adhere to the formed electrostatic latent image, and transfers and fixes the adhered toner onto a recording medium such as paper.

[0012] 1, image forming apparatus 100 has an operation unit 10, a start switch 20, a control board 51, a reading unit 40, an engine control unit 79, a printer unit 6, paper feed cassettes 7A and 7B, a conveying unit 8, and a power supply device 1. Note that control board 51, engine control unit 79, printer unit 6, paper feed cassettes 7A and 7B, and conveying unit 8 are provided inside image forming apparatus 100, but FIG. 1 shows a see-through state of the interior.

[0013] The operation unit 10 accepts various inputs according to user operations and displays various information on a display unit (not shown). For example, the information displayed on the operation unit 10 may be information indicating the operation for which the input was accepted, information indicating the operating status of the image forming apparatus 100, or information indicating the setting status of the image forming apparatus 100.

[0014] For example, the operation unit 10 may include a liquid crystal display (LCD) with a touch panel function. Alternatively, the operation unit 10 may include an organic electroluminescence (EL) display device with a touch panel function. Furthermore, the operation unit 10 may have at least one of an operation unit such as hardware keys and a display unit such as a lamp in addition to a display device with a touch panel function.

[0015] The start switch 20 is a switch that turns on the power to the image forming apparatus 100. When the start switch 20 is pressed while the power is off, the image forming apparatus 100 starts up, and when the start switch 20 is pressed while the image forming apparatus 100 is running, the image forming apparatus 100 turns off. Note that the power on / off of the image forming apparatus 100 is not limited to being turned on / off by the operation of the start switch 20, and may also be performed based on a start instruction or a stop instruction from an external device.

[0016] The control board 51 is equipped with a plurality of electronic components including a controller such as a CPU (Central Processing Unit) that controls the overall operation of the image forming apparatus 100. For example, the electronic components equipped on the control board 51 control drawing processing, communication processing, input from the operation unit 10, and the like. For example, the electronic components equipped on the control board 51 control the image forming apparatus 100 based on operations received by the operation unit 10, and perform a copy operation and the like.

[0017] The electronic components mounted on the control board 51 may also control the image forming apparatus 100 based on instructions received from an external device such as a PC. Furthermore, the electronic components mounted on the control board 51 may cause the image forming apparatus 100 to execute a predetermined operation when it is detected that the start switch 20 has been pressed, or when an abnormality in the image forming apparatus 100 is detected, for example.

[0018] Note that a semiconductor chip such as an SoC (System on Chip) or an FPGA (Field-Programmable Gate Array) may be mounted on the control board 51 instead of a processor such as a CPU (Central Processing Unit). Alternatively, an SoC or FPGA may be mounted on the control board 51 together with a CPU. Mounting an SoC or FPGA on the control board 51 allows the size of the control board 51 to be reduced.

[0019] The reading unit 40 includes, for example, an ADF (Auto Document Feeder) 41 and a scanner unit 42. The ADF 41 sequentially transports documents placed on the ADF 41 to the scanner unit 42, and generates image data by optically reading the documents. The scanner unit 42 generates image data by optically reading documents placed on a transparent document table.

[0020] The engine control unit 79 generates control signals for controlling the printer unit 6, the scanner unit 42, the conveying unit 8, etc., based on the image data generated by the reading unit 40. For example, the engine control unit 79 may have the form of a circuit board on which a circuit for generating control signals based on image data is mounted.

[0021] The printer unit 6 functions as an image forming unit that forms an image. The printer unit 6 has a photosensitive drum 61, a charging unit 62, a writing unit 63, a developing unit 64, a conveyor belt 65, and a fixing unit 66. The charging unit 62 charges the outer surface of the photosensitive drum 61. The writing unit 63 exposes the charged photosensitive drum 61 to light based on image data read by the reading unit 40, and writes an electrostatic latent image on the photosensitive drum 61. The developing unit 64 develops the latent image written on the photosensitive drum 61 with toner. The conveyor belt 65 transports the recording medium on which the toner image is formed. The fixing unit 66 fixes the toner on the recording medium to the recording medium, forming a toner image on the recording medium.

[0022] The paper feed cassettes 7A and 7B store recording media such as paper before a toner image is formed on them. For example, the paper feed cassettes 7A and 7B can store recording media of different sizes. While FIG. 1 shows an example in which two paper feed cassettes 7A and 7B are provided in the image forming apparatus 100, the number of paper feed cassettes may be one, three, or more.

[0023] Conveyance unit 8 has various rollers and conveys recording media stored in paper feed cassette 7A or paper feed cassette 7B to printer unit 6. Note that arrow C in Figure 1 indicates the direction in which the recording media is conveyed. Power supply device 1 generates multiple types of DC voltages based on an AC power source such as a commercial power source, and supplies the generated DC voltages to each component of image forming apparatus 100.

[0024] When a user operates a function switching key or the like on the operation unit 10 to select a document box function, copy function, printer function, facsimile function, or the like, the image forming apparatus 100 becomes operable for each function. The operation mode of the image forming apparatus 100 becomes document box mode when the document box function is selected, and copy mode when the copy function is selected. The operation mode of the image forming apparatus 100 also becomes printer mode when the printer function is selected, and facsimile mode when the facsimile function is selected.

[0025] An example of the image formation operation when the image forming apparatus 100 is set to copy mode will be described below. Note that, although an example in which the printer unit 6 forms an image by a monochrome electrophotographic method will be described below, an image may also be formed by a color electrophotographic method or an inkjet method. Furthermore, the image formation method is not limited to these.

[0026] In copy mode, image forming apparatus 100 reads image information of each document to be copied using reading unit 40 and generates image data. Image forming apparatus 100 uniformly charges the outer circumferential surface of photosensitive drum 61 in the dark using charging unit 62. Next, image forming apparatus 100 exposes the surface of photosensitive drum 61 to light emitted from writing unit 63, indicated by dotted arrow A in FIG. 1, to form an electrostatic latent image on the outer circumferential surface of photosensitive drum 61. Arrow B in FIG. 1 indicates the direction of rotation of photosensitive drum 61.

[0027] The image forming apparatus 100 operates the developing unit 64 to visualize the electrostatic latent image with toner. This forms a toner image on the photosensitive drum 61. Next, the image forming apparatus 100 transfers the toner image formed on the photosensitive drum 61 to a recording medium on the conveyor belt 65. The image forming apparatus 100 then heats and melts the toner forming the toner image on the recording medium using a heater or the like in the fixing unit 66, thereby fixing the toner image to the recording medium. The image forming apparatus 100 then ejects the recording medium with the fixed toner image.

[0028] The operation unit 10 may be controlled by the control board 51, or may be controlled by a control circuit separate from the control board 51. In this case, the control circuit of the control board 51 and the control circuit of the operation unit 10 are connected to each other so that they can communicate with each other. The control board 51 controls the entire image forming apparatus 100, including the operation unit 10.

[0029] <Example of state transition of image forming device> Fig. 2 is a state transition diagram showing an example of transition of the operation mode of the image forming apparatus 100 in Fig. 1. The transition of the operation mode of the image forming apparatus 100 is controlled, for example, by a CPU mounted on the control board 51 in Fig. 1. When the image forming apparatus 100 is started by turning on the power switch, it is set to a standby mode.

[0030] When the image forming apparatus 100 receives an instruction to copy or scan from the user via the operation unit 10 while in standby mode, the image forming apparatus 100 transitions to active mode and performs a copy operation (i.e., a print operation) or a scan operation (FIG. 4(a)). After the copy operation or the scan operation is completed, the image forming apparatus 100 returns to standby mode (FIG. 4(b)).

[0031] On the other hand, if the image forming apparatus 100 is in the standby mode and no operation is performed for a predetermined time, the image forming apparatus 100 transitions from the standby mode to the energy saving mode (FIG. 4(c)). For example, if the ADF 41 is opened during the energy saving mode, the image forming apparatus 100 transitions the operation mode from the energy saving mode to the standby mode (FIG. 4(d)).

[0032] <Example of hardware configuration of image forming device> Fig. 3 is a circuit block diagram showing an outline of the hardware configuration of the main parts of image forming apparatus 100 in Fig. 1. Image forming apparatus 100 has a control unit 110, a power supply unit 120, an engine control unit 79, and an operation unit 10.

[0033] 1, and includes a CPU (Central Processing Unit) 111, a ROM (Read Only Memory) 112, a RAM (Random Access Memory) 113, a power supply control unit 114, and a power supply generation unit 115, all of which are mounted on the control board 51. The CPU 111 includes a memory controller 111a and an internal memory 111b.

[0034] The power supply unit 120 uses an AC power supply such as a commercial power supply to generate a DC voltage DC24 (e.g., 24 V) and a DC voltage DC5 (e.g., 5 V). The DC voltage DC24 is supplied to an engine mechanism including the printer unit 6 and the scanner unit 42, and the DC voltage DC5 is supplied to a power supply generating unit 115 of the control unit 110.

[0035] The engine control unit 79 has a printer circuit unit 79a that controls the operation of printing an image on a paper medium, etc., and a scanner circuit unit 79b that controls the operation of scanning an original, etc. The CPU 111 is connected to the ROM 112, RAM 113, the printer circuit unit 79a, the scanner circuit unit 79b, the operation unit 10, etc.

[0036] During active mode and standby mode, CPU 111 executes a control program stored in RAM 113 to control the overall operation of image forming apparatus 100. During energy saving mode, CPU 111 executes a monitoring program stored in internal memory 111b to detect a trigger for returning from energy saving mode to standby mode. CPU 111 is an example of a processor. Internal memory 111b is, for example, a RAM or cache mounted in CPU 111.

[0037] For example, the CPU 111 controls the printer circuit unit 79a to perform a printing operation, and the scanner circuit unit 79b to perform a scanning operation. The CPU 111 also controls the operation unit 10 to accept user operations and display the operating status of the image forming apparatus 100 on a display unit (not shown) of the operation unit 10.

[0038] The ROM 112 is a non-volatile memory, such as an eMMC (embedded multi media card) or a flash memory, on which data can be electrically rewritten. The ROM 112 may store a boot program and various parameters used in the operation of the image forming apparatus 100. The RAM 113 is, for example, a synchronous dynamic random access memory (SDRAM) that requires periodic refresh operations, and operates in synchronization with a clock signal CLK.

[0039] The RAM 113 and the CPU 111 are connected via data signal lines DQ, address signal lines AD, various command signal lines CMD, a clock signal line CLK, and a clock enable signal line CKE. For example, the command signal line CMD includes a chip select signal line, a write enable signal line, a row address strobe signal line, a column address strobe signal line, etc. The RAM 113 is an example of a memory.

[0040] The RAM 113 operates while receiving a high-level clock enable signal CKE from the memory controller 111a of the CPU 111. The high level of the clock enable signal CKE is an example of an active level. The RAM 113 then executes a read operation, a write operation, or a refresh operation in response to the clock signal CLK, the address signal AD, and various command signals CMD received from the memory controller 111a (i.e., the CPU 111). Hereinafter, the clock enable signal CKE will also be referred to as the CKE signal.

[0041] For example, while receiving a low-level CKE signal from the memory controller 111a, the RAM 113 stops operation by stopping reception of the clock signal CLK. However, if the RAM 113 receives a command signal CMD of a predetermined logic level at the falling edge of the CKE signal, it transitions to self-refresh mode. During self-refresh mode, the RAM 113 periodically performs refresh operations to retain the stored data.

[0042] For example, during an energy-saving mode in which power consumption is reduced, the CPU 111 stops the operation of the engine mechanism by the engine control unit 79. During the energy-saving mode, the CPU 111 sets the CKE signal to a low level via the memory controller 111a, stops fetching the control program stored in the RAM 113, and executes the monitoring program stored in the internal memory 111b. During the energy-saving mode, the RAM 113 is shifted to a self-refresh mode.

[0043] For example, the monitoring program is a simple program that monitors interrupts that occur in response to operations on the operation unit 10 during the energy saving mode, and does not access external devices such as the ROM 112. When the monitoring program detects an operation on the operation unit 10, the CPU 111 changes the CKE signal from low to high via the memory controller 111a. Then, the CPU 111 starts fetching the control program stored in the RAM 113, and transitions the operating mode from the energy saving mode to the standby mode.

[0044] A memory access request from the CPU 111 to the RAM 113 is held in an access queue (not shown) of the memory controller 111a. The memory access request issued by the CPU 111 is a read access request for reading a control program or data from the RAM 113, and a write access request for writing data to the RAM 113.

[0045] The memory controller 111a sequentially issues the memory access requests held in the access queue to the RAM 113. If a memory access request is held in the access queue, the memory controller 111a sets the CKE signal to a high level and sequentially issues the memory access requests held in the access queue to the RAM 113. If no memory access request is held in the access queue, the memory controller 111a sets the CKE signal to a low level and causes the RAM 113 to transition to self-refresh mode.

[0046] As described above, in this embodiment, the memory controller 111a automatically transitions to and cancels from the self-refresh mode without being controlled by the CPU 111 (auto self-refresh function). In other words, the CKE signal can be automatically output by the memory controller 111a in accordance with the operation frequency of the CPU 111 without intervention of a control program executed by the CPU 111. Note that the memory controller 111a periodically issues refresh commands to the RAM 113 while the CKE signal is set to a high level. Also, the circuit that controls the output of the CKE signal may be other than the memory controller 111a.

[0047] The power supply control unit 114 includes a frequency detection unit 1140 that detects how often the memory controller 111a sets the CKE signal to high level. The frequency with which the CKE signal is set to high level indicates how often the RAM 113 is accessed, and how often the CPU 111 operates.

[0048] When the CKE signal is frequently at high level, the CPU 111 operates frequently and consumes a lot of power. In addition, the CPU 111 accesses the ROM 112 and RAM 113 more frequently, which increases the power consumption of the ROM 112 and RAM 113.

[0049] On the other hand, when the CKE signal is at a high level infrequently, the CPU 111 operates less frequently, resulting in less power consumption by the CPU 111. Furthermore, the CPU 111 accesses the ROM 112 and RAM 113 less frequently, resulting in less power consumption by the ROM 112 and RAM 113.

[0050] For example, the frequency at which the CKE signal is set to a high level can be expressed by the ratio of the high level period of the CKE signal in a predetermined period or the number of transition edges of the CKE signal in a predetermined period, where the number of transition edges is the number of rising edges or the number of falling edges.

[0051] The power supply control unit 114 sets one of the selection signals SEL3, SEL2, SEL1, and SEL0 to an active level (e.g., a high level) and sets the others to an inactive level (e.g., a low level) based on the frequency of the high level of the CKE signal detected by the frequency detection unit 1140. The selection signals SEL3 to SEL0 are output to the power supply generation unit 115. Hereinafter, when the selection signals SEL3 to SEL0 are not to be distinguished from one another, they will be referred to as selection signals SEL.

[0052] For example, the access frequencies of the RAM 113 are assumed to be, in descending order, frequency A, frequency B, frequency C, and frequency D. Note that frequency D includes a state in which the CKE signal is fixed to a low level during a predetermined period for determining the access frequency.

[0053] The frequency detection unit 1140 sets the selection signal SEL3 to an active level when the access frequency of RAM 113 is frequency A, and sets the selection signal SEL2 to an active level when the access frequency of RAM 113 is frequency B. The frequency detection unit 1140 sets the selection signal SEL1 to an active level when the access frequency of RAM 113 is frequency C, and sets the selection signal SEL0 to an active level when the access frequency of RAM 113 is frequency C.

[0054] When detecting the ratio of the high-level period of the CKE signal for each predetermined period as the frequency, the frequency detection unit 1140 may include, for example, a digital-to-analog converter (DAC), a smoothing circuit, and a comparison circuit. The DAC converts the logic level of the CKE signal into a voltage. The smoothing circuit smoothes the output voltage of the DAC to generate a voltage VCKE that indicates the average voltage of the CKE signal over the predetermined period. A higher value of the voltage VCKE indicates a higher frequency of the high-level CKE signal.

[0055] The comparator circuit compares the voltage VCKE with a plurality of threshold voltages to set one of the selection signals SEL3-SEL1 to an active level. Therefore, by generating a voltage VCKE that indicates the frequency of the high level of the CKE signal, one of the selection signals SEL3-SEL1 can be output to the power supply generator 115 according to the value of the voltage VCKE.

[0056] On the other hand, when detecting the number of transition edges of the CKE signal per predetermined period as the frequency, the frequency detection unit 1140 includes, for example, a counter and a comparison circuit. The counter counts in synchronization with the rising or falling edges of the CLK signal and is reset per predetermined period. The larger the count value CNT generated by the counter, the higher the frequency of the high level of the CKE signal. The comparison circuit compares the count value CNT immediately before being reset with multiple thresholds, thereby setting one of the selection signals SEL3-SEL1 to an active level. Therefore, by detecting the number of transition edges of the CKE signal per predetermined period as the frequency, one of the selection signals SEL3-SEL1 can be output to the power generation unit 115 according to the count value.

[0057] Power supply generation unit 115 generates a plurality of types of DC voltages DC33, DC18, DC12, and DC105 in accordance with selection signals SEL3-SEL0, using DC voltage DC5 supplied from power supply unit 120. Then, power supply control unit 114 and power supply generation unit 115 execute a power supply control method for image forming apparatus 100 (electronic device).

[0058] Hereinafter, the DC voltages DC33, DC18, DC12, and DC105 may also be simply referred to as voltages DC33, DC18, DC12, and DC105. Furthermore, the power generation unit 115 has a function of adjusting the voltage values ​​of the voltages DC33, DC18, DC12, and DC105 in accordance with the selection signal SEL.

[0059] For example, the standard value of voltage DC33 is 3.3V, and the standard value of voltage DC18 is 1.8V. For example, the standard value of voltage DC12 is 1.2V, and the standard value of voltage DC105 is 1.05V. Although not particularly limited, voltages DC33 and DC18 are, for example, power supply voltages for operating ROM 112. Voltage DC12 is, for example, a power supply voltage for operating RAM 113. Voltage DC105 is, for example, a power supply voltage for operating CPU 111. Each of CPU 111, ROM 112, and RAM 113 is an example of a functional unit that operates using voltages generated by power generation unit 115.

[0060] <Power generation circuit block> Fig. 4 is a circuit block diagram showing an example of the power supply generating unit 115 shown in Fig. 3. The power supply generating unit 115 operates by receiving a DC voltage DC5 supplied from the power supply unit 120 and selection signals SEL3-SEL0 output from the power supply control unit 114. For example, the power supply generating unit 115 has four power supply generating units 1153, 1152, 1151, and 1150 that generate voltages DC33, DC18, DC12, and DC105, respectively.

[0061] The power supply generating unit 1153 has power supply generating circuits G34, G33, and G32 that generate three voltages DC33 with different voltage values. For example, the power supply generating circuits G34, G33, and G32 are DC / DC converters. The power supply generating circuit G34 operates when it receives a high-level selection signal SEL3 and outputs a 3.4V voltage DC33.

[0062] The power supply generating circuit G33 operates when it receives a high level selection signal SEL2 and outputs a voltage DC33 of 3.3 V. The power supply generating circuit G32 operates when it receives a high level selection signal SEL1 and outputs a voltage DC33 of 3.2 V.

[0063] The power supply generating unit 1152 has power supply generating circuits G19, G18, and G17 that generate three voltages DC18 with different voltage values. For example, the power supply generating circuits G19, G18, and G17 are DC / DC converters. The power supply generating circuit G19 operates when it receives a high-level selection signal SEL3 and outputs a voltage DC18 of 1.9 V.

[0064] The power supply generating circuit G18 operates when it receives a high level selection signal SEL2 and outputs a voltage DC18 of 1.8 V. The power supply generating circuit G17 operates when it receives a high level selection signal SEL1 and outputs a voltage DC18 of 1.7 V.

[0065] The power supply generating unit 1151 has power supply generating circuits G13, G12a, G12b, and G11 that generate three voltages DC12 with different voltage values. For example, the power supply generating circuits G13, G12a, G12b, and G11 are DC / DC converters. The power supply generating circuit G13 operates when it receives a high-level selection signal SEL3 and outputs a voltage DC12 of 1.3 V.

[0066] The power supply generating circuit G12a operates when it receives a high-level selection signal SEL2 and outputs a voltage DC12 of 1.2V. The power supply generating circuit G12b operates when it receives a high-level selection signal SEL1 and outputs a voltage DC12 of 1.2V. That is, the power supply generating unit 1151 outputs a voltage DC12 of 1.2V when it receives the selection signals SEL2 and SEL1. The power supply generating circuit G11 operates when it receives a high-level selection signal SEL0 and outputs a power supply voltage DC12 of 1.1V.

[0067] The power supply generating unit 1150 has power supply generating circuits G125, G115, G105, and G10, which generate four voltages DC105 having different voltage values. For example, the power supply generating circuits G125, G115, G105, and G10 are DC / DC converters. The power supply generating circuit G125 operates when it receives a high-level selection signal SEL3 and outputs a voltage DC105 of 1.25V.

[0068] The power supply generation circuit G115 operates when it receives a high level selection signal SEL2 and outputs a voltage DC105 of 1.15 V. The power supply generation circuit G105 operates when it receives a high level selection signal SEL1 and outputs a voltage DC105 of 1.05 V. The power supply generation circuit G10 operates when it receives a high level selection signal SEL0 and outputs a voltage DC105 of 1.0 V.

[0069] As a result, while power supply generating unit 115 is receiving high-level selection signal SEL3, it outputs voltage DC33 of 3.4 V, voltage DC18 of 1.9 V, voltage DC12 of 1.3 V, and voltage DC105 of 1.25 V. While power supply generating unit 115 is receiving high-level selection signal SEL2, it outputs voltage DC33 of 3.3 V, voltage DC18 of 1.8 V, voltage DC12 of 1.2 V, and voltage DC105 of 1.15 V.

[0070] While receiving a high-level selection signal SEL1, the power supply generating unit 115 outputs a voltage DC33 of 3.2 V, a voltage DC18 of 1.7 V, a voltage DC12 of 1.2 V, and a voltage DC105 of 1.05 V. While receiving a high-level selection signal SEL0, the power supply generating unit 115 outputs a voltage DC12 of 1.1 V and a voltage DC105 of 1.0 V, and stops outputting voltage DC33 and voltage DC18. Hereinafter, when the direct current voltage DC is not to be distinguished from other voltages, it will also be simply referred to as voltage DC.

[0071] In this way, when the operation frequency of CPU 111 is high, the frequency of the high level of the CKE signal increases, and the power consumption of CPU 111 increases, the voltage DC supplied to CPU 111 is set high. When the operation frequency of CPU 111 is high, the operation frequency of ROM 112 and RAM 113 also increases, and the power consumption of ROM 112 and RAM 113 increases. When the power consumption of ROM 112 and RAM 113 increases, the voltage DC supplied to ROM 112 and RAM 113 is set high. This makes it possible to suppress a drop in voltage DC due to increased power consumption of CPU 111, ROM 112, and RAM 113.

[0072] Furthermore, when the operation frequency of CPU 111 is low, the frequency with which the CKE signal goes high decreases, and the power consumption of CPU 111 decreases, the voltage DC supplied to CPU 111 is set low. When the operation frequency of CPU 111 is low, the operation frequency of ROM 112 and RAM 113 also decreases, and the power consumption of ROM 112 and RAM 113 decreases. When the power consumption of ROM 112 and RAM 113 decreases, the voltage DC supplied to ROM 112 and RAM 113 is set low. This makes it possible to prevent unnecessary voltage DC from being supplied to CPU 111, ROM 112, and RAM 113.

[0073] The control of adjusting the direct current voltage DC by the power supply control unit 114 can be performed without intervention of a control program executed by the CPU 111. Then, appropriate voltages DC (i.e., power) can be supplied to the CPU 111, the ROM 112, and the RAM 113 according to the operation frequency of the CPU 111 without intervention of a control program executed by the CPU 111.

[0074] Fig. 5 is an explanatory diagram showing an example of the relationship between the selection signal SEL generated by the power supply control unit 114 in Fig. 3 and the set value of the DC voltage generated by the power supply generation unit 115. Fig. 5 shows an example in which the frequency detection unit 1140 generates a voltage VCKE (average voltage of the CKE signal) indicating the frequency of the high level of the CKE signal.

[0075] The power supply control unit 114 outputs a selection signal SEL0 when the voltage VCKE is 0V, and outputs a selection signal SEL1 when the voltage VCKE is greater than 0V and equal to or less than 0.6V. The power supply control unit 114 outputs a selection signal SEL2 when the voltage VCKE is greater than 0.6V and equal to or less than 1.2V, and outputs a selection signal SEL3 when the voltage VCKE is greater than 1.2V. 0V, 0.6V, and 1.2V are examples of threshold voltages compared with the voltage VCKE. Then, a predetermined power supply generation circuit (G34, G33, etc.) shown in FIG. 4 is selected in response to the selection signals SEL3-SEL0, and the values ​​of the voltages DC33, DC18, DC12, and DC1.05 are set, respectively.

[0076] When the frequency detection unit 1140 detects the number of transition edges of the CKE signal, the number of transition edges counted by the counter is used instead of the average voltage VCKE of Fig. 5. Then, the comparator compares the number of transition edges counted by the counter with each of three thresholds to output one of the selection signals SEL3-SEL1.

[0077] As described above, in this embodiment, the power supply generating unit 1150 adjusts the value of the DC voltage DC105 to be supplied to the CPU 111 in accordance with the frequency of high level of the CKE signal output to the RAM 113 by the CPU 111 executing the control program stored in the RAM 113. This allows the power supply generating unit 1150 to generate an appropriate DC voltage DC105 (i.e., power) to be supplied to the CPU 111 in accordance with the operation frequency of the CPU 111, without intervention of the control program executed by the CPU 111.

[0078] In this embodiment, for example, one of the power supply generating circuits G125, G115, G105, and G10, which generate 1.25V, 1.15V, 1.05V, and 1.0V, respectively, is operated in response to the selection signals SEL3-SEL0. This allows the value of the DC voltage DC105 output by the power supply generating unit 1150 to be adjusted using the selection signal SEL, which is a logic signal. Similarly, the other power supply generating units 1153, 1152, and 1151 can adjust the values ​​of the DC voltages DC33, DC18, and DC12, respectively, using the selection signal SEL, which is a logic signal.

[0079] As a result, it is possible to supply an appropriate direct current voltage DC to CPU 111, ROM 112, and RAM 113 according to their operation frequencies. That is, it is possible to prevent excessive power from being supplied to CPU 111, ROM 112, and RAM 113. It is also possible to prevent a shortage of power supplied to CPU 111, ROM 112, and RAM 113. As a result, it is possible to stably operate CPU 111, ROM 112, and RAM 113, and it is possible to prevent a decrease in the reliability of image forming apparatus 100.

[0080] Furthermore, frequency detection unit 1140 always detects the frequency at which the CKE signal is set to a high level, regardless of the operation mode of image forming apparatus 100. Therefore, for example, when the operation mode transitions from energy saving mode to standby mode to active mode, each DC voltage DC generated by power supply generation unit 115 can be increased. In other words, each DC voltage DC generated by power supply generation unit 115 can be adjusted across operation modes. As a result, it is possible to optimize power consumption of image forming apparatus 100 while maintaining stable operation.

[0081] For example, the power supply control unit 114 can generate a voltage VCKE indicating the frequency of the high level of the CKE signal using the frequency detection unit 1140, and output one of the selection signals SEL3-SEL1 to the power supply generation unit 115 according to the value of the voltage VCKE. Alternatively, the power supply control unit 114 can count the number of transition edges of the CKE signal as the frequency of the high level of the CKE signal using the frequency detection unit 1140, and output one of the selection signals SEL3-SEL1 to the power supply generation unit 115 according to the count value.

[0082] Furthermore, power supply generating units 1153 and 1152 generate DC voltages DC33 and DC18 to be supplied to ROM 112, respectively, in accordance with the frequency of the high level of the CKE signal. Power supply generating unit 1151 generates DC voltage DC12 to be supplied to RAM 113 in accordance with the frequency of the high level of the CKE signal. This allows power supply generating unit 115 to generate appropriate DC voltages DC to be supplied to ROM 112 and RAM 113, respectively, in accordance with the operation frequency of CPU 111, without the intervention of a control program executed by CPU 111.

[0083] Furthermore, in this embodiment, the CPU 111 is provided with a memory controller 111a that sets the CKE signal to high level when a memory access request is held in the access queue. This allows the memory controller 111a to automatically output the CKE signal in accordance with the operation frequency of the CPU 111, without intervention of a control program executed by the CPU 111.

[0084] <Hardware configuration of main parts of image forming apparatus according to the second embodiment> 6 is a circuit block diagram showing an outline of the hardware configuration of the main parts of an image forming apparatus according to a second embodiment of the present invention. Elements similar to those in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted. The image forming apparatus 100A shown in FIG. 6 has a power supply control unit 124 and a power supply generation unit 125 instead of the power supply control unit 114 and the power supply generation unit 115 in FIG. 3. The other configuration of the image forming apparatus 100A is the same as the configuration of the image forming apparatus 100 in FIG. 3.

[0085] The power supply control unit 124 has a frequency detection unit 1240, a ROM 1243, and four FB setting units 1244. For example, the ROM 1243 may be an electrically rewritable flash memory or the like. The frequency detection unit 1240 generates a voltage VCKE indicating the average voltage of the CKE signal in a predetermined period as frequency information indicating how often the CKE signal is at a high level. An example of the frequency detection unit 1240 is shown in FIG. 7.

[0086] The ROM 1243 stores correspondence information indicating the correspondence between the voltage VCKE and the regulated voltages FB3, FB2, FB1, and FB0 output by the four FB setting units 1244. Hereinafter, when the regulated voltages FB3, FB2, FB1, and FB0 are not distinguished from one another, they will be referred to as the regulated voltages FB. The ROM 1243 is an example of a storage unit. An example of the correspondence information stored in the ROM 1243 indicating the correspondence between the voltage VCKE and the regulated voltages FB is shown in FIG. 8.

[0087] The four FB setting units 1244 refer to correspondence information that indicates the correspondence relationship between the voltage VCKE and the adjustment voltage FB, which is held in the ROM 1243, and determine the values ​​of the adjustment voltages FB3-FB0 that correspond to the voltage VCKE received from the frequency detection unit 1240. Then, the four FB setting units 1244 generate the adjustment voltages FB3-FB0 of the determined values, for example, by stepping down the DC voltage DC5, and output the generated adjustment voltages FB3-FB0 to the power generation unit 125.

[0088] For example, the four FB setting units 1244 change the resistance division ratio of the division circuit that generates the regulated voltages FB3-FB0 from the DC voltage DC5 in accordance with the determined values ​​of the regulated voltages FB3-FB0. The FB setting unit 1244 is an example of an regulated voltage generating unit that generates the regulated voltages FB in accordance with the frequency of the high level of the CKE signal.

[0089] The power supply generating unit 125 generates a DC voltage DC33 in response to the regulated voltage FB3, and generates a DC voltage DC18 in response to the regulated voltage FB2. The power supply generating unit 125 also generates a DC voltage DC12 in response to the regulated voltage FB1, and generates a DC voltage DC1.05 in response to the regulated voltage FB0. The power supply control unit 124 and the power supply generating unit 125 then execute a power supply control method for the image forming apparatus 100A (electronic device). An example of the power supply generating unit 125 is shown in FIG. 7.

[0090] <Power supply control unit and power generation unit circuit blocks> 7 is a circuit block diagram showing an example of the power supply control unit 124 and the power supply generation unit 125 of FIG. 6. For example, the frequency detection unit 1240 has a DAC 1241 and a smoothing circuit 1242. The DAC 1241 converts the logic level of the CKE signal into a voltage. The smoothing circuit 1242 smoothes the output voltage of the DAC 1241 and generates a voltage VCKE that indicates the average voltage of the CKE signal over a predetermined period.

[0091] The frequency detection unit 1240 may include a counter that counts the number of transition edges of the CKE signal for each predetermined period, and a DAC that generates a voltage VCKE according to the count value counted by the counter.

[0092] Each FB setting unit 1244 generates one of the regulated voltages FB3 to FB0 based on the voltage VCKE and the corresponding information stored in the ROM 1243 for each of the regulated voltages FB3 to FB0.

[0093] The power supply generating unit 125 has four power supply generating circuits G33A, G18A, G12A, and G105A that generate DC voltages DC33, DC18, DC12, and DC105, respectively, in response to a DC voltage DC5. For example, the power supply generating circuits G33A, G18A, G12A, and G105A are DC / DC converters. The power supply generating circuit G33A can adjust the value of the DC voltage DC33 supplied to the ROM 112 in response to an adjustment voltage FB3 received at a voltage adjustment terminal FB (feedback terminal).

[0094] The power generation circuit G18A can adjust the value of the DC voltage DC18 supplied to the ROM112 according to the adjustment voltage FB2 received at the voltage adjustment terminal FB. The power generation circuit G12A can adjust the value of the DC voltage DC12 supplied to the RAM113 according to the adjustment voltage FB1 received at the voltage adjustment terminal FB. The power generation circuit G105A can adjust the value of the DC voltage DC105 supplied to the CPU111 according to the adjustment voltage FB0 received at the voltage adjustment terminal FB.

[0095] <Corresponding information held in ROM1243> FIG. 8 is an explanatory diagram showing an example of the set values for the FB voltage held in the ROM1243 of FIG. 7. In the ROM1243, the set values VSET of the adjustment voltages FB3 - FB0 are held for each predetermined range of the voltage VCKE (average voltage of the CKE signal) indicating the frequency of the high level of the CKE signal. The symbol OFF in FIG. 8 indicates that there is no corresponding set value VSET. Note that the corresponding information shown in FIG. 8 is presented in a table structure, but it may also be presented as a numerical sequence or a character string.

[0096] In the ROM1243, corresponding to when the voltage VCKE is 0V, the set values VSET11 and VSET10 of the adjustment voltages FB1 and FB0 are held. The set value VSET11 indicates the adjustment voltage FB1 for adjusting the DC voltage DC12 to 1.1V. The set value VSET10 indicates the adjustment voltage FB0 for adjusting the DC voltage DC105 to 1.0V. When the voltage VCKE is 0V, the DC voltages DC33 and DC18 are not generated, so the set values VSET for the adjustment voltages FB3 and FB2 are not held in the ROM1243.

[0097] ROM1243 holds set values ​​VSET32, VSET17, VSET12, and VSET105 of the regulated voltages FB3-FB0 corresponding to when the voltage VCKE is greater than 0V and equal to or less than 0.6V. The set value VSET32 indicates the regulated voltage FB3 that regulates the DC voltage DC33 to 3.2V. The set value VSET17 indicates the regulated voltage FB2 that regulates the DC voltage DC18 to 1.7V. The set value VSET12 indicates the regulated voltage FB1 that regulates the DC voltage DC12 to 1.2V. The set value VSET105 indicates the regulated voltage FB0 that regulates the DC voltage DC105 to 1.05V.

[0098] ROM1243 holds set values ​​VSET33, VSET18, VSET12, and VSET115 of the regulated voltages FB3-FB0 corresponding to when the voltage VCKE is greater than 0.6V and equal to or less than 1.2V. The set value VSET33 indicates the regulated voltage FB3 that regulates the DC voltage DC33 to 3.3V. The set value VSET18 indicates the regulated voltage FB2 that regulates the DC voltage DC18 to 1.8V. The set value VSET12 indicates the regulated voltage FB1 that regulates the DC voltage DC12 to 1.2V. The set value VSET115 indicates the regulated voltage FB0 that regulates the DC voltage DC105 to 1.15V.

[0099] 8, when the voltage VCKE is greater than 0V and equal to or less than 1.2V, the FB setting unit 1244 generates the regulated voltage FB1 that regulates the DC voltage DC12 supplied to the RAM 113 to 1.2V based on the set value VSET12. When the voltage VCKE is greater than 0V, the RAM 113 receives a high-level CKE signal with a certain frequency and performs an access operation. In this case, by setting the set value VSET to VSET12, even when the voltage VCKE is equal to or less than 0.6V, a sufficient DC voltage DC12 can be supplied to the RAM 113, and a reduction in the operating margin of the RAM 113 can be suppressed.

[0100] ROM1243 holds set values ​​VSET34, VSET19, VSET13, and VSET125 of the regulated voltages FB3-FB0 corresponding to when the voltage VCKE is greater than 1.2V. The set value VSET34 indicates the regulated voltage FB3 that regulates the DC voltage DC33 to 3.4V. The set value VSET19 indicates the regulated voltage FB2 that regulates the DC voltage DC18 to 1.9V. The set value VSET13 indicates the regulated voltage FB1 that regulates the DC voltage DC12 to 1.3V. The set value VSET125 indicates the regulated voltage FB0 that regulates the DC voltage DC105 to 1.25V.

[0101] By storing correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltages FB3-FB0 in the ROM 1243, each of the FB setting units 1244 can easily refer to the set value VSET of the adjustment voltages FB3-FB0 that is set for each predetermined range of the voltage VCKE. This makes it easier for each of the FB setting units 1244 to control the generation of the adjustment voltages FB3-FB0.

[0102] For example, if the minimum value of the DC voltage DC105 at which the CPU 111 can operate is known in advance, the set value VSET11 may be set to match this minimum value. If the minimum values ​​of the DC voltages DC33 and DC18 at which the ROM 1243 can operate are known in advance, the set values ​​VSET32 and VSET17 may be set to match these minimum values, respectively.

[0103] Similarly, if the minimum value of the DC voltage DC12 at which the RAM 113 can operate is known in advance, the set value VSET11 may be set to match this minimum value. Here, the minimum value of the DC voltage DC is not the minimum operating voltage set in the electrical specifications of each device, but the actual value of each device. This makes it possible to set an appropriate DC voltage DC while suppressing power consumption according to the actual value of the device.

[0104] As described above, this embodiment can also achieve the same effects as the above-described embodiment. For example, it is possible to supply an appropriate direct current voltage DC to CPU 111, ROM 112, and RAM 113 according to the operation frequency without using a control program executed by CPU 111. As a result, it is possible to stably operate CPU 111, ROM 112, and RAM 113, and it is possible to prevent a decrease in the reliability of image forming apparatus 100.

[0105] Furthermore, in this embodiment, by adjusting the value of the DC voltage DC33 using the adjustment voltage FB3 supplied to the voltage adjustment terminal FB, it is possible to generate the DC voltage DC33 according to the frequency of the high level of the CKE signal using a single power supply generation circuit G33A. By adjusting the value of the DC voltage DC18 using the adjustment voltage FB2 supplied to the voltage adjustment terminal FB, it is possible to generate the DC voltage DC18 according to the frequency of the high level of the CKE signal using a single power supply generation circuit G18A.

[0106] Similarly, by adjusting the value of DC voltage DC12 using an adjustment voltage FB1 supplied to voltage adjustment terminal FB, a single power supply generating circuit G12A can generate DC voltage DC12 corresponding to the frequency of high-level CKE signals. By adjusting the value of DC voltage DC105 using an adjustment voltage FB0 supplied to voltage adjustment terminal FB, a single power supply generating circuit G105A can generate DC voltage DC105 corresponding to the frequency of high-level CKE signals. As a result, the circuit size of power supply generating unit 125 can be reduced compared to the circuit size of power supply generating unit 115 shown in FIG. 4, and the control board 51 implementing control unit 110 can be made smaller. As a result, the cost of image forming apparatus 100A can be reduced.

[0107] By storing correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltages FB3-FB0 in the ROM 1243, it is possible to easily refer to the set values ​​VSET of the adjustment voltages FB3-FB0 that are set for each predetermined range of the voltage VCKE, which makes it easier for each FB setting unit 1244 to control the generation of the adjustment voltages FB3-FB0.

[0108] The above-described embodiment is not limited to image forming apparatuses 100 and 100A such as multifunction peripherals, but can also be applied to electronic devices such as standalone printers, scanners, facsimiles, electronic whiteboards, projectors, and drive decoders.

[0109] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0110] 1 Power supply 6 Printer section 10 Control section 20 Start switch 40 Reading unit 41 ADF 42 Scanner section 51 Control board 79 Engine control unit 79a Printer circuit section 79b Scanner circuit section 100, 100A Image forming device 110 control section 111 CPU 111a memory controller 111b Internal memory 112 ROM 113 RAM 114 Power supply control unit 115 Power generation section 120 Power Supply Unit 124 Power supply control unit 125 Power generation section 1140 Frequency detection unit 1150, 1151, 1152, 1153 Power generation section 1240 Frequency detection unit 1241 DAC 1242 Smoothing circuit 1243 ROM 1244 FB setting section AD Address signal CKE Clock enable signal CLK Clock signal CMD Command signal CNT count value DC105, DC12, DC18, DC33 DC voltage DC5, DC24 DC voltage DQ data signal G10, G105, G105A, G115, G125 power generation circuit G11, G12a, G12b, G12A, G13 Power generation circuit G17, G18, G18A, G19 power generation circuit G32, G33, G33A, G34 power generation circuit SEL (SEL1-SEL3) selection signal VCKE voltage VSET setting value [Prior art documents] [Patent documents]

[0111] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-114973

Claims

1. a processor; a memory that stores a program to be executed by the processor and operates in synchronization with a clock signal while receiving a clock enable signal of an active level from the processor; a frequency detection unit that detects a frequency at which the clock enable signal is set to an effective level; a power supply generating unit that generates a voltage and sets the voltage when the frequency detected by the frequency detecting unit is low to be lower than the voltage when the frequency is high; a functional unit that operates using the voltage generated by the power supply generating unit; An electronic device comprising:

2. The power supply generating unit has a plurality of power supply generating circuits that generate the voltages different from each other, and adjusts the value of the voltage supplied to the functional unit by operating one of the plurality of power supply generating circuits according to the frequency.

2. The electronic device according to claim 1,

3. an adjusted voltage generating unit that generates an adjusted voltage according to the frequency; The power supply generating unit adjusts the value of the voltage to be supplied to the functional unit in accordance with the adjusted voltage.

2. The electronic device according to claim 1,

4. a holding unit that holds a correspondence relationship between the frequency and the adjustment voltage; the regulated voltage generation unit determines the regulated voltage corresponding to the frequency by referring to the holding unit, and outputs the determined regulated voltage to the power generation unit.

4. The electronic device according to claim 3,

5. The frequency detection unit detects an average voltage of the clock enable signal at every predetermined period as the frequency.

5. The electronic device according to claim 1, wherein:

6. The frequency detection unit detects the number of transition edges of the clock enable signal per predetermined period as the frequency.

5. The electronic device according to claim 1, wherein:

7. a plurality of the functional units each operating with a plurality of different voltages; a plurality of the power supply generating units that generate the plurality of types of voltages based on the frequency, The processor is one of the plurality of functional units.

7. The electronic device according to claim 1, wherein:

8. the processor has a memory controller including an access queue for holding memory access requests to be issued to the memory; the memory controller sets the clock enable signal to an active level when the memory access request is held in the access queue, and sets the clock enable signal to an inactive level when the memory access request is not held in the access queue.

8. The electronic device according to claim 1, wherein:

9. an image forming unit that forms an image; a processor that executes a program that controls the operation of the image forming unit; a memory that stores the program and operates in synchronization with a clock signal while receiving a clock enable signal at an active level from the processor; a frequency detection unit that detects a frequency at which the clock enable signal is set to an effective level; a power supply generating unit that generates a voltage and sets the voltage when the frequency detected by the frequency detecting unit is low to be lower than the voltage when the frequency is high; a functional unit that operates using the voltage generated by the power supply generating unit; An image forming apparatus comprising:

10. A power supply control method for an electronic device having a processor, a memory that stores a program executed by the processor and operates in synchronization with a clock signal while receiving a clock enable signal of an active level from the processor, a frequency detection unit, a power supply generation unit that generates a voltage, and a functional unit that operates using the voltage generated by the power supply generation unit, the frequency detection unit detects the frequency at which the clock enable signal is set to an effective level; The power supply generating unit sets the voltage when the frequency detected by the frequency detecting unit is low to be lower than the voltage when the frequency is high. A power supply control method for an electronic device, comprising:

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