Silicon carbide wafer and silicon carbide semiconductor device using the same

Abstract

To suppress expansion of BPD into SF.SOLUTION: A silicon carbide wafer includes a substrate composed of SiC, and an epitaxial layer composed of SiC and placed on a substrate, and concentration of carbon vacancies decreases continuously from the substrate side to the epitaxial layer, and the substrate is configured such that the concentration of carbon vacancies is 3.0×1015 cm-3 or more.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a SiC wafer made of silicon carbide (hereinafter also referred to as SiC) and a SiC semiconductor device using the same. [Background technology]

[0002] Conventionally, SiC semiconductor devices made of SiC have been proposed, for example, SiC semiconductor devices on which MOSFETs (abbreviation of Metal Oxide Semiconductor Field Effect Transistors) are formed. + On a type substrate, an n-type substrate with a lower impurity concentration than the substrate is - A buffer layer of the type is formed, and an n-type impurity layer having a lower impurity concentration than the buffer layer is formed on the buffer layer. - A p-type drift layer is formed on the semiconductor. A p-type base layer is disposed on the drift layer. The buffer layer and drift layer are composed of epitaxial layers.

[0003] The surface of the base layer is + A source region of a silicon nitride semiconductor is formed in the semiconductor substrate. A plurality of trenches are formed through the source region and the base layer to reach the drift layer, and a gate insulating film and a gate electrode are formed in each trench in this order, thereby forming a trench gate structure.

[0004] In the SiC semiconductor device described above, a parasitic diode is formed by the pn junction between the base layer and the drift.

[0005] In such SiC semiconductor devices, basal plane dislocations (hereinafter simply referred to as BPDs) may exist in the substrate. It has been reported that in such SiC semiconductor devices, holes injected when the parasitic diode operates may reach the BPDs, causing the BPDs to expand into stacking faults (hereinafter simply referred to as SFs) (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Non-Patent Document 1] M. Skowronski and S. Ha, "Degradation of hexagonal silicon-carbide-based bipolar devices", Applied Physics Reviews 2006 Summary of the Invention [Problem to be solved by the invention]

[0007] In the SiC semiconductor device described above, BPDs are linear defects and therefore have little effect on device operation, but SFs are planar defects and act as resistance components, which have a significant effect on device operation. Therefore, in the SiC semiconductor device described above, the on-state voltage may become high.

[0008] In view of the above, an object of the present invention is to provide a SiC wafer capable of suppressing the expansion of BPD into SF, and a SiC semiconductor device using the same. [Means for solving the problem]

[0009] Claim 1 to achieve the above object 、3、5is a SiC wafer made of SiC, comprising a substrate (10) made of SiC and an epitaxial layer (20) made of SiC and disposed on the substrate, in which the concentration of carbon vacancies (VC) continuously decreases from the substrate side toward the epitaxial layer, and the substrate has a carbon vacancy concentration of 3.0 × 10 15 cm -3 That is said to be the case. Claim 1 also provides that the substrate contains impurities including at least one of boron, aluminum, titanium, vanadium, sulfur, iron, niobium, and tantalum. . Claim 3 provides that the epitaxial layer has a film thickness of 4 to 40 μm and a donor concentration of 1.0×10 15 ~1.0×10 19 cm -3 It has a part that is said to be Claim 5 states that the substrate has a resistivity of 30 mΩ·cm or less.

[0010] This makes it possible to prevent the BPD from expanding into the SF due to carbon vacancies when a MOSFET or the like is formed.

[0011] Claim 6 is a SiC semiconductor device comprising the SiC wafer of claim 1, wherein the substrate is of a first conductivity type, the epitaxial layer has at least a drift layer (22) of the first conductivity type arranged on the substrate side, and a base layer (23) arranged on the drift layer, and a source region (24) of the first conductivity type is formed in a surface layer portion of the base layer.

[0012] A seventh aspect of the present invention provides a SiC semiconductor device comprising the SiC wafer according to the first aspect, and a diode including a substrate of the first conductivity type.

[0013] As described above, by using the above-mentioned SiC wafer to configure a SiC semiconductor device, it is possible to obtain a SiC semiconductor device in which the expansion of BPD into SF is suppressed.

[0014] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2A] 1A to 1C are cross-sectional views showing manufacturing steps of a SiC semiconductor device. [Figure 2B] 2B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 2B. [Figure 3] FIG. 10 is a diagram showing the relationship between the depth and the concentration of carbon vacancies before heat treatment. [Figure 4] FIG. 10 is a diagram showing the relationship between depth and concentration of carbon vacancies after heat treatment. [Figure 5] FIG. 10 is a diagram showing the relationship between depth and concentration of carbon vacancies after heat treatment. [Figure 6] FIG. 10 is a diagram showing the relationship between depth and concentration of carbon vacancies after heat treatment. [Figure 7] FIG. 1 is a schematic diagram of a SiC semiconductor device used in a simulation. [Figure 8] FIG. 10 is a diagram showing the relationship between depth and concentration of carbon vacancies after heat treatment. [Figure 9] FIG. 10 is a graph showing the relationship between the forward current and the amount of change in forward voltage when the concentration of carbon vacancies in the substrate is 3.0×10 15 cm −3 . [Figure 10] FIG. 10 is a graph showing the relationship between the forward current and the amount of change in forward voltage when the concentration of carbon vacancies in the substrate is 1.0×10 14 cm −3 . [Figure 11] This is a photoluminescence image of a substrate with a carbon vacancy concentration of 3.0×10 15 cm −3 , in which fluorescence of 420±10 nm was captured using an optical filter. [Figure 12] This is a photoluminescence image of a substrate with a carbon vacancy concentration of 1.0×10 14 cm −3 , in which fluorescence of 420±10 nm was captured using an optical filter. [Figure 13] FIG. 10 is a graph showing the relationship between the forward current and the amount of change in forward voltage when the concentration of carbon vacancies in the substrate is 1.0×10 14 cm −3 . [Figure 14] FIG. 10 is a photoluminescence image of the second embodiment, in which the concentration of carbon vacancies in the substrate is 1.0×10 14 cm −3 , and fluorescence of 420±10 nm is captured using an optical filter. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0017] (First embodiment) A first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed will be described as an example. Although not shown, the SiC semiconductor device has a cell region and an outer peripheral region formed to surround the cell region. The MOSFET shown in FIG. 1 is formed in the cell region of the SiC semiconductor device.

[0018] SiC semiconductor devices are made of SiC. + The present embodiment is configured using a substrate 10 of a silicon carbide (SiC) type. An epitaxial layer 20 made of SiC is disposed on the surface of the substrate 10. The epitaxial layer 20 of this embodiment is an n-type - Buffer layer 21, n - A p-type drift layer 22, a p-type base layer 23, and a p-type base layer 23 are arranged in this order. In this embodiment, the SiC wafer 1 is configured to include the substrate 10 and the epitaxial layer 20. In this embodiment, the epitaxial layer 20 has a thickness of about 4 to 40 μm, where the length along the normal direction to the surface direction of the substrate 10 is the thickness.

[0019] The surface layer of the base layer 23 is made of n +An n-type source region 24 is formed in the base layer 23. The source region 24 is formed by ion implantation into the surface layer of the base layer 23, or by forming a groove in the base layer 23 and disposing an n-type epitaxial layer in the groove.

[0020] The substrate 10 has, for example, a resistivity of 30 mΩ·cm or less (for example, 20 mΩ·cm), a (0001) Si surface, and an off-angle of 0.5 to 5° relative to the (0001) Si surface. Furthermore, as will be described later, the substrate 10 has a specified concentration of carbon vacancies, so that the minority carrier lifetime τ is 2.5 ns or less. The buffer layer 21 has, for example, an n-type impurity concentration of 1.0×10 18 ~10 19 cm -3 The drift layer 22 has an n-type impurity concentration of, for example, 1.0×10 15 ~5.0×10 16 / cm 3 In this embodiment, the substrate 10 constitutes the drain layer of the MOSFET.

[0021] The base layer 23 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 3.0×10 17 cm -3 The source region 24 has a higher impurity concentration than the drift layer 22, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18 ~1.0×10 19 cm -3 The thickness is set to about 0.5 to 2 μm. The film thicknesses of the drift layer 22, the base layer 23, and the source region 24 are arbitrary and are not limited to those mentioned above.

[0022] Further, a trench 30 is formed so as to penetrate the base layer 23 and the source region 24 and reach the drift layer 22. The base layer 23 and the source region 24 are arranged so as to contact the side surfaces of the trench 30. Although only one trench 30 is shown in FIG. 1, in reality, a plurality of trenches 30 are formed in the shape of stripes that are equally spaced from one another in the left-to-right direction of the page.

[0023] A gate insulating film 31 is formed on the inner wall surface of the trench 30. A gate electrode 32 made of doped poly-Si is formed on the surface of the gate insulating film 31. The trench 30 is completely filled with the gate insulating film 31 and the gate electrode 32. In this embodiment, a trench gate structure is configured in this manner.

[0024] An upper electrode 41 is disposed on the epitaxial layer 20 as a source electrode, insulated from the gate electrode 32 and connected to the base layer 23 and the source region 24. In this embodiment, the upper electrode 41 is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 24) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the base layer 23) is made of a metal that can make ohmic contact with the p-type SiC.

[0025] A lower electrode 42 is formed on the back surface of the substrate 10 as a drain electrode electrically connected to the substrate 10. In this embodiment, this structure constitutes an n-channel inversion type trench gate MOSFET. A cell region is constituted by arranging a plurality of such MOSFETs.

[0026] The above is the basic configuration of the SiC semiconductor device in this embodiment. Although not specifically shown, the substrate 10 may include a BPD. In a SiC semiconductor device in which a MOSFET such as the one described above is formed, holes injected when the parasitic diode operates may reach the BPD, causing the BPD to expand into the SF.

[0027] Here, the substrate 10 made of SiC contains carbon vacancies which are intrinsic defects, and the carbon vacancies have Z in the forbidden band. 1 / 2 It has been reported that a defect level called a carbon vacancy V is formed, which acts as a minority carrier killer. C Concentration and Z 1 / 2 It has also been reported that the relationship between the concentrations of carbon vacancies is approximately 1:1. For this reason, the present inventors have conducted extensive research into the influence of carbon vacancies.

[0028] First, the present inventors conducted extensive research and found that heating causes carbon vacancies contained in the substrate 10 to diffuse into the epitaxial layer 20. For this reason, the SiC semiconductor device of this embodiment is manufactured as follows.

[0029] First, as shown in FIG. 2A, a substrate 10 is prepared. The substrate 10 has carbon vacancies (i.e., carbon vacancies) V C The substrate 10 is prepared by cutting a SiC ingot containing carbon vacancies V. Since the SiC ingot is generally manufactured at a high temperature of 2000° C. or more, the substrate 10 contains carbon vacancies V. C Although not specifically shown, the substrate 10 may also include a BPD.

[0030] Next, as shown in FIG. 2B, the epitaxial layer 20 is grown at about 1600 to 1700° C. to form the SiC wafer 1. At this time, since the epitaxial layer 20 is grown at about 1600 to 1700° C., the carbon vacancies V contained in the substrate 10 are C diffuses into the epitaxial layer 20.

[0031] Thereafter, as shown in FIG. 2C, a heat treatment is performed at a temperature higher than the temperature at which the epitaxial layer 20 is grown, thereby removing carbon vacancies V contained in the substrate 10. C is further diffused toward the epitaxial layer 20. Specifically, by performing the heat treatment, carbon vacancies V contained in the epitaxial layer 20 are diffused as shown in FIGS. C 3 and 4 show the results when an epitaxial layer 20 of 9 μm is grown on a substrate 10, and the surface of the epitaxial layer 20 (i.e., the surface of the epitaxial layer 20 opposite to the substrate 10) is set to 0 μm. That is, FIGS. 3 and 4 show the carbon vacancies V in the epitaxial layer 20. C 3 and 4 show the concentration of Z by DLTS (Deep Level Transient Spectroscopy) method. 1 / 2 It is based on the results of measuring the concentration distribution, and Z 1 / 2 Concentration and carbon vacancy V C The concentration of carbon vacancies V C The carbon vacancies V, which will be described later, are measured. C The concentration of is also confirmed by DLTS method. Furthermore, when performing heat treatment, a carbon cap may be placed to prevent the surface from becoming rough.

[0032] The base layer 23 and the source region 24 are formed by appropriately implanting ions into the epitaxial layer 20, and may be formed before or after the heat treatment. The temperature during the heat treatment is set to be higher than the temperature at which the epitaxial layer 20 is grown and lower than the sublimation temperature of SiC.

[0033] And thus, carbon vacancy V C As shown in Figures 5 and 6, the carbon vacancies V CThe concentration distribution of carbon vacancies V in the epitaxial layer 20 decreases continuously from the substrate 10 side toward the epitaxial layer 20 side. Figures 5 and 6 show the results when a 9 μm epitaxial layer 20 is grown on the substrate 10 while changing the thickness of the substrate 10. As shown in Figures 5 and 6, the carbon vacancies V in the epitaxial layer 20 C It is confirmed that the concentration does not depend on the thickness of the substrate 10.

[0034] 3 to 6, as shown in FIG. 7, the n-type impurity concentration on the substrate 10 is 1.0×10 15 cm -3 4 is a schematic diagram of a Schottky diode formed by disposing an epitaxial layer 20 having a Schottky electrode 50 on the epitaxial layer 20 side and a lower electrode 42 on the substrate 10 side. Note that, in order to obtain the results shown in FIG. 4 after fabricating a MOSFET, a similar evaluation can also be performed using a parasitic diode in the MOSFET.

[0035] As shown in FIG. 8, carbon vacancies V C The concentration of carbon vacancies V in the substrate 10 C It is confirmed that the higher the concentration, the higher the

[0036] The present inventors further discovered that carbon vacancies V C The relationship between the concentration of carbon vacancies V in the substrate 10 was investigated in detail, and the results shown in Fig. 9 and Fig. 10 were obtained. Fig. 9 and Fig. 10 show the results when the epitaxial layer 20 in Fig. 7 was changed to a p-type and the Schottky electrode 50 was changed to an upper electrode 41 to form a pn diode. Fig. 9 also shows the results when the carbon vacancies V in the substrate 10 were changed to a p-type and the Schottky electrode 50 was changed to an upper electrode 41 to form a pn diode. C The concentration of 15 cm -3 10 shows the change in forward voltage when the carbon vacancies V C The concentration of 14 cm -39 and 10, the forward voltage when the forward current is 40 A is set as the reference value (i.e., Initial in the figures), and the amount of change from the reference value is the amount of change in forward voltage.

[0037] As shown in FIG. 9, carbon vacancies V in the substrate 10 C The concentration of 15 cm -3 , it is confirmed that the amount of change in the forward voltage is small even if the forward current is increased. On the other hand, as shown in FIG. C The concentration of 14 cm -3 In this case, it is confirmed that the amount of change in the forward voltage increases as the forward current increases.

[0038] The inventors then obtained photoluminescence (hereinafter simply referred to as PL) images of such a semiconductor device after passing a forward current, and obtained the results shown in Figures 11 and 12. Note that Figures 11 and 12 are PL images obtained by using an optical filter to project only light of 420±10 nm onto a detector. Figure 11 also shows the PL images obtained when a forward current of 2500 A / cm 2 Figure 12 shows the results after a forward current of 2000 A / cm 2 This is a diagram after the water has been flushed.

[0039] As shown in FIG. 11, carbon vacancies V in the substrate 10 C The concentration of 15 cm -3 12, when the concentration of carbon vacancies in the substrate 10 is 1.0×10 14 cm -3 If so, then multiple SFs are confirmed to have occurred.

[0040] Therefore, in this embodiment, the carbon vacancies V in the substrate 10 C The concentration of15 cm -3 Specifically, the substrate 10 is obtained by cutting a SiC ingot, and the SiC ingot contains carbon vacancies V C The SiC ingot is obtained by high-temperature CVD, and the temperature during production causes carbon vacancies V C In detail, the higher the temperature during manufacturing of SiC ingots, the more carbon vacancies V C Therefore, in this embodiment, the high-temperature CVD method is performed at a temperature of about 2500° C. or higher, and after the heat treatment, the concentration of 3.0×10 15 cm -3 More than carbon vacancies V C That is, the substrate 10 of this embodiment is configured to contain carbon vacancies V after the heat treatment. C The concentration of 15 cm -3 It can be said that this is a substrate containing a high amount of carbon vacancies.

[0041] According to the present embodiment described above, the substrate 10 has a thickness of 3.0×10 15 cm -3 More than carbon vacancies V C Contains carbon vacancies V C is gradually decreased from the substrate 10 side toward the epitaxial layer 20 side. This makes it difficult for the BPD to expand SF. Therefore, when a MOSFET is formed, for example, an increase in the on-state voltage can be suppressed.

[0042] (Second embodiment) A second embodiment will be described. In this embodiment, unlike the first embodiment, an impurity is added to the substrate 10. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0043] In this embodiment, the substrate 10 contains at least one impurity selected from the group consisting of boron (B), aluminum (Al), titanium (Ti), vanadium (V), sulfur (S), iron (Fe), niobium (Nb), and tantalum (Ta). This also functions as a minority carrier killer, further suppressing the expansion of BPDs into SFs.

[0044] Specifically, as shown in FIG. 13, carbon vacancies V in the substrate 10 C The concentration of 14 cm -3 , comparing with Figure 10, the carbon vacancy V C Although the concentration of impurities is the same, it can be seen that the amount of change in forward voltage is reduced by adding impurities. Also, as shown in Figure 14, when compared with Figure 13, SFs are observed, but the number is reduced. Note that in Figure 13, the forward current is set to 2500 A / cm 2 10 is a binarized view of the PL image after being passed through the lens.

[0045] According to the present embodiment described above, the substrate 10 has a thickness of 3.0×10 15 cm -3 More than carbon vacancies V C Contains carbon vacancies V C is gradually decreased from the substrate 10 side toward the epitaxial layer 20 side. Therefore, the same effects as those of the first embodiment can be obtained.

[0046] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0047] In the above embodiments, the SiC semiconductor device in which a MOSFET is formed has been described. However, the SiC semiconductor device may be configured with a Schottky diode as shown in Fig. 7, or may be configured with a pn diode in which the epitaxial layer 20 in Fig. 7 is changed to a p-type and the Schottky electrode 50 is changed to an upper electrode 41.

[0048] In addition, in each of the above embodiments, a SiC semiconductor device has been described in which a MOSFET of an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type is formed. However, for example, a SiC semiconductor device may also be formed in which a MOSFET of a p-channel type trench gate structure in which the conductivity types of each component are reversed from those of the n-channel type is formed.

[0049] (Features of the present invention) [Claim 1] A silicon carbide wafer made of silicon carbide, a substrate (10) made of silicon carbide; an epitaxial layer (20) made of silicon carbide and disposed on the substrate; Carbon vacancies (V C ) concentration is continuously decreasing, The substrate has a carbon vacancy concentration of 3.0×10 15 cm -3 Silicon carbide wafers are said to be above this level. [Claim 2] 2. The silicon carbide wafer according to claim 1, wherein the substrate contains impurities including at least one of boron, aluminum, titanium, vanadium, sulfur, iron, niobium, and tantalum. [Claim 3] The epitaxial layer has a film thickness of 4 to 40 μm and a donor concentration of 1.0×10 15 ~1.0×10 19 3. The silicon carbide wafer according to claim 1, having a portion having a density of cm −3. [Claim 4] The epitaxial layer has a buffer layer (21) located on the substrate side and a drift layer (22) located on the buffer layer, The buffer layer has a thickness of 1.0×10 18 ~1.0×10 19 cm -3 It is said that, The drift layer has a capacitance of 1.0×10 15 ~5×10 16 cm -3 4. The silicon carbide wafer according to claim 3, wherein: [Claim 5] 5. The silicon carbide wafer according to claim 1, wherein the substrate has a resistivity of 30 m·Ωcm or less. [Claim 6] A silicon carbide semiconductor device, A silicon carbide wafer according to claim 1, the substrate is of a first conductivity type; the epitaxial layer has at least a drift layer (22) of a first conductivity type arranged on the substrate side and a base layer (23) arranged on the drift layer; A silicon carbide semiconductor device having a first conductivity type source region (24) formed in a surface layer portion of the base layer. [Claim 7] A silicon carbide semiconductor device, A silicon carbide wafer according to claim 1, A silicon carbide semiconductor device having a diode including the substrate of the first conductivity type. [Explanation of symbols]

[0050] 10 Substrate 20 Epitaxial layer V C carbon vacancy

Claims

1. A silicon carbide wafer made of silicon carbide, a substrate (10) made of silicon carbide; an epitaxial layer (20) made of silicon carbide and disposed on the substrate; Carbon vacancies (V Ｃ ) concentration is continuously decreasing, The substrate has a carbon vacancy concentration of 3.0×10 １５ cm －３ It is said that The substrate is a silicon carbide wafer containing impurities including at least one of boron, aluminum, titanium, vanadium, sulfur, iron, niobium, and tantalum.

2. The epitaxial layer has a film thickness of 4 to 40 μm and a donor concentration of 1.0×10 １５ ~1.0 x 10 １９ cm －３ The silicon carbide wafer according to claim 1 , having a portion having the following structure:

3. A silicon carbide wafer made of silicon carbide, a substrate (10) made of silicon carbide; an epitaxial layer (20) made of silicon carbide and disposed on the substrate; Carbon vacancies (V Ｃ ) concentration is continuously decreasing, The substrate has a carbon vacancy concentration of 3.0×10 １５ cm －３ It is said that The epitaxial layer has a thickness of 4 to 40 μm and a portion having a donor concentration of 1.0×10 15 to 1.0×10 19 cm −3 .

4. The epitaxial layer has a buffer layer (21) located on the substrate side and a drift layer (22) located on the buffer layer, The buffer layer has a donor concentration of 1.0×10 １８ ~1.0 x 10 １９ cm －３ It is said that, The drift layer has a donor concentration of 1.0×10 １５ ~5.0 x 10 １６ cm －３ 4. The silicon carbide wafer according to claim 2 or 3, wherein:

5. A silicon carbide wafer made of silicon carbide, a substrate (10) made of silicon carbide; an epitaxial layer (20) made of silicon carbide and disposed on the substrate; Carbon vacancies (V Ｃ ) concentration is continuously decreasing, The substrate has a carbon vacancy concentration of 3.0×10 １５ cm －３ It is said that The substrate is a silicon carbide wafer having a resistivity of 30 mΩ·cm or less.

6. A silicon carbide semiconductor device, A silicon carbide wafer according to claim 1, 3, or 5, the substrate is of a first conductivity type; The epitaxial layer has at least a drift layer (22) of a first conductivity type arranged on the substrate side and a base layer (23) arranged on the drift layer, A silicon carbide semiconductor device having a first conductivity type source region (24) formed in a surface layer portion of the base layer.

7. A silicon carbide semiconductor device, A silicon carbide wafer according to claim 1, 3, or 5, A silicon carbide semiconductor device comprising a diode including the substrate of the first conductivity type.

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