Bias circuit and class AB amplifier circuit

Abstract

To provide a bias circuit and a class-AB amplifier circuit capable of outputting an input bias voltage with accuracy even when a power supply voltage fluctuates in a wide range.SOLUTION: A first voltage mirror circuit 3 operates so that voltages at a first terminal T31 and a second terminal T32 are substantially equal to each other and operates so that currents at a third terminal T33 and the second terminal T32 are substantially equal to each other. A voltage V11 is input to the first terminal T31. A second voltage mirror circuit 7 operates so that voltages of a fourth terminal T71 connected with the second terminal T32 and a fifth terminal T72 are substantially equal to each other and operates so that currents of a sixth terminal T73 and the fourth terminal T71 are substantially equal to each other. A first current source circuit 4 is connected with the third terminal T33. A second current source circuit 5 is connected with the second terminal T32. A voltage control current source circuit 6 receives the voltage at the third terminal T33, and outputs a current depending on a value of the input voltage to the sixth terminal T73.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a bias circuit and a class AB amplifier circuit. [Background technology]

[0002] The output stage of an amplifier circuit is often configured as a class AB amplifier to improve power efficiency and power supply driving capacity. The class AB amplifier circuit described in Non-Patent Document 1 has been proposed as a method for stabilizing the quiescent current and input bias voltage of a class AB output circuit.

[0003] A class AB output circuit constituting a conventional class AB amplifier circuit and a bias circuit that supplies an input bias voltage to the class AB output circuit will be described with reference to Fig. 14. As shown in Fig. 14, a class AB output circuit 10 has an N-channel transistor Mn1 and a P-channel transistor Mp1 connected in series with each other.

[0004] 14 is a circuit that applies an input bias voltage to a transistor Mn1. The Nch bias circuit 100 has a current source 101 configured from a transistor M104 whose gate is supplied with a bias voltage Vb, a transistor M101 to which current is supplied from the current source 101, a transistor M102 connected to the transistor M101 as a current mirror, a current source 102 that supplies current to the transistor M102, and a diode-connected transistor M103. The source of the transistor M102 is connected to the gate of the transistor Mn1.

[0005] The above-mentioned current sources 101 and 102 supply equal currents to the transistors M101 and M102. Because equal currents flow through the transistors M101 and M102, the gate-source voltages of the transistors M101 and M102 are equal. Therefore, when the class AB output circuit 10 is in a quiescent state, the source voltage of the transistor M102 is equal to the gate-source voltage of the transistor M103. In other words, the gate-source voltage of the transistor M103 is input to the gate of the transistor Mn1 as an input bias voltage.

[0006] The above-described Nch bias circuit 100 may be required to have a high breakdown voltage so that it can operate even when the power supply voltage of the class AB amplifier circuit is as high as 40V or 60V. For this reason, the class AB output circuit 10 further includes an Nch, high-breakdown-voltage transistor Mn2 cascode-connected to the transistor Mn1, and a Pch, high-breakdown-voltage transistor Mp2 cascode-connected to the transistor Mp1. This configuration can protect the drain-sources of the transistors Mp1 and Mn1 from excessive voltage. Furthermore, the Nch bias circuit 100 uses high-breakdown-voltage transistors for the transistors M101, M102, and M104.

[0007] The drain-source voltage Vds of the transistor M104 that constitutes the current source 101 is expressed by the following equation (1). Vds=VDD-(Vgsm101+Vgsm103) …(1) VDD: Power supply voltage Vgsm101: Gate-source voltage of transistor M101 Vgsm103: Gate-source voltage of transistor M103

[0008] When the power supply voltage VDD decreases and the voltage Vds decreases, transistor M104 cannot operate in the saturation region and instead operates in the triode region, causing a decrease in the drain current of transistor M104. When the drain current of transistor M104 decreases, the current flowing through transistors M101 and M102 decreases, changing the input bias voltage of transistor Mn1. Therefore, the power supply voltage VDD must be set to a minimum operating voltage that prevents transistor M104 from operating in the triode region. However, the high-voltage transistor M101 described above has a thick gate oxide film, resulting in a high threshold voltage and a large gate-source voltage Vgsm101. As the gate-source voltage Vgsm101 increases, the minimum operating voltage of the power supply voltage VDD is limited, as is clear from equation (1) above.

[0009] The Pch bias circuit that applies an input bias voltage to the transistor Mp1 can be explained by replacing "Pch" of the Nch bias circuit 100 with "Nch" and reversing the connections of the positive and negative power supplies, so a detailed explanation will be omitted here. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] Ron Hogervorst, John P. Tero, Ruud GH Eschauzier, and Johan H. Huijsing, “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input / Output Operational Amplifier for VLSI Cell Libraries”, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 29. NO 12. DECEMBER 1994. Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a bias circuit and a class AB amplifier circuit that can output an input bias voltage with high precision even when the power supply voltage fluctuates over a wide range. [Means for solving the problem]

[0012] In order to achieve the above-mentioned object, the bias circuit and the class AB amplifier circuit according to the present invention are as follows: 11 ] is a feature of the product. [1] a first voltage mirror circuit that operates so that a voltage input to a first terminal and a voltage output to a second terminal are approximately equal, and that a current input to a third terminal and a current output from the second terminal are approximately equal; a voltage generation circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a second voltage mirror circuit that operates so that a voltage input to a fourth terminal connected to the second terminal and a voltage output from a fifth terminal are approximately equal, and that a current input to a sixth terminal and a current output from the fourth terminal are approximately equal; a first current source circuit to which the third terminal of the first voltage mirror circuit is connected; a second current source circuit to which the second terminal of the first voltage mirror circuit and the fourth terminal of the second voltage mirror circuit are connected; a voltage-controlled current source circuit, the input of which is connected to the third terminal of the first voltage mirror circuit and the output of which is connected to the sixth terminal of the second voltage mirror circuit, and which outputs a current corresponding to an input voltage value; A negative feedback path is provided from the output to the input of the voltage controlled current source circuit. R, the voltage controlled current source circuit has a first transistor whose gate or base serves as the input and whose drain or collector serves as the output; the first transistor outputs, from the drain or collector, a current obtained by subtracting a current flowing in the first current source circuit from a current flowing in the second current source circuit; the second voltage mirror circuit includes a second transistor having a drain or a collector that serves as the sixth terminal and a source or an emitter that serves as the fourth terminal, a third transistor that is current-mirror-connected to the second transistor and has a source or an emitter that serves as the fifth terminal, and a third current source circuit that is connected to the source or the emitter of the third transistor, a ratio of a current output from the voltage controlled current source circuit to a current of the third current source circuit is set equal to a size ratio or an emitter area ratio of the second transistor to the third transistor; the first voltage mirror circuit includes a fourth current source circuit, a fourth transistor having a drain or a collector connected to the fourth current source circuit and a source or an emitter serving as the first terminal, and a fifth transistor that is current mirror connected to the fourth transistor, having a source or an emitter serving as the second terminal and a drain or a collector serving as the third terminal; a ratio of a current of the fourth current source circuit to a current of the first current source circuit is set equal to a size ratio or an emitter area ratio of the fourth transistor to the fifth transistor. It is a bias circuit. [2] In the bias circuit according to [1], a phase compensation circuit, It is a bias circuit. [3] [ 1 In the bias circuit according to The second transistor and the third transistor constitute the first voltage mirror circuit and the voltage controlled current source circuit. The first It is made up of transistors with higher voltage resistance than transistors. It is a bias circuit. [4] [ 1 In the bias circuit according to the first voltage mirror circuit includes a sixth transistor cascode-connected to the fourth transistor and a seventh transistor cascode-connected to the fifth transistor; It is a bias circuit. [5] a first voltage mirror circuit that operates so that a voltage input to a first terminal and a voltage output to a second terminal are approximately equal, and that a current input to a third terminal and a current output from the second terminal are approximately equal; a voltage generation circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a second voltage mirror circuit that operates so that a voltage input to a fourth terminal connected to the second terminal and a voltage output from a fifth terminal are approximately equal, and that a current input to a sixth terminal and a current output from the fourth terminal are approximately equal; a first current source circuit to which the third terminal of the first voltage mirror circuit is connected; a second current source circuit to which the second terminal of the first voltage mirror circuit and the fourth terminal of the second voltage mirror circuit are connected; a voltage-controlled current source circuit, the input of which is connected to the third terminal of the first voltage mirror circuit and the output of which is connected to the sixth terminal of the second voltage mirror circuit, and which outputs a current corresponding to an input voltage value; a negative feedback path is provided from the output to the input of the voltage controlled current source circuit; the voltage controlled current source circuit has a first transistor whose gate or base serves as the input and whose drain or collector serves as the output; the first transistor outputs, from the drain or collector, a current obtained by subtracting a current flowing in the first current source circuit from a current flowing in the second current source circuit; the second voltage mirror circuit includes a second transistor having a drain or a collector that serves as the sixth terminal and a source or an emitter that serves as the fourth terminal, a third transistor that is current-mirror-connected to the second transistor and has a source or an emitter that serves as the fifth terminal, and a third current source circuit that is connected to the source or the emitter of the third transistor, a ratio of a current output from the voltage controlled current source circuit to a current of the third current source circuit is set equal to a size ratio or an emitter area ratio of the second transistor to the third transistor; the first voltage mirror circuit includes an eighth transistor having a source or an emitter serving as the second terminal and a drain or a collector serving as the third terminal, and a differential amplifier having an output connected to a gate or a base of the eighth transistor, an inverting input connected to the source or the emitter of the eighth transistor, and a non-inverting input serving as the first terminal; It is a bias circuit. [6] [1]~[ 5 In the bias circuit according to any one of the above items, the voltage generating circuit includes a diode-connected ninth transistor; It is a bias circuit. [7] [1]~[ 6 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit and the voltage generating circuit are N-channel transistors, The transistors constituting the voltage controlled current source circuit are composed of Pch transistors. It is a bias circuit. [8] [1]~[ 6 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit and the voltage generating circuit are Pch transistors, The transistors constituting the voltage controlled current source circuit are composed of Nch transistors. It is a bias circuit. [9] a differential input section that outputs a differential current according to an input voltage; a class AB output circuit having an Nch tenth transistor and a Pch eleventh transistor connected in series with each other, and an output terminal connected between the tenth transistor and the eleventh transistor; connected to the gate or base of the tenth transistor 7 and a bias circuit according to claim 1 connected to the gate or base of said eleventh transistor. 8 and a control circuit that controls the tenth transistor and the eleventh transistor so as to output an output voltage and an output current corresponding to the differential current output from the differential input section to the output terminal. It must be an AB class amplifier circuit.

[10] [9 In the class AB amplifier circuit described in [ 8 a first positive power supply terminal for supplying a positive first positive power supply voltage to the bias circuit according to the present invention; a second positive power supply terminal for supplying a second positive power supply voltage to the class AB output circuit; [ 8 and a negative power supply terminal for supplying a negative power supply voltage to the bias circuit according to the present invention and the class-AB output circuit, the first positive power supply voltage and the second positive power supply voltage are different voltages; It must be an AB class amplifier circuit.

[11] [ 9 In the class AB amplifier circuit described in [ 8 a first negative power supply terminal for supplying a negative first negative power supply voltage to the bias circuit according to a second negative power supply terminal for supplying a negative second negative power supply voltage to the class AB output circuit; [ 8 and a positive power supply terminal for supplying a positive power supply voltage to the bias circuit according to the present invention and the class-AB output circuit, the first negative power supply voltage and the second negative power supply voltage are different voltages; It must be an AB class amplifier circuit. [Effects of the Invention]

[0013] According to the present invention, a bias circuit and a class AB amplifier circuit are provided that can output an input bias voltage with high precision even when the power supply voltage fluctuates over a wide range.

[0014] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing an Nch bias circuit according to the first embodiment. [Figure 2]FIG. 2 is a circuit diagram of the Nch bias circuit in the first embodiment. [Figure 3] FIG. 3 is a circuit diagram of an Nch bias circuit according to the second embodiment. [Figure 4] FIG. 4 is a circuit diagram of an Nch bias circuit according to the third embodiment. [Figure 5] FIG. 5 is a circuit diagram of an Nch bias circuit according to the fourth embodiment. [Figure 6] FIG. 6 is a block diagram showing a Pch bias circuit according to the fifth embodiment. [Figure 7] FIG. 7 is a circuit diagram of a Pch bias circuit according to the fifth embodiment. [Figure 8] FIG. 8 is a circuit diagram of a Pch bias circuit according to the sixth embodiment. [Figure 9] FIG. 9 is a circuit diagram of a Pch bias circuit according to the seventh embodiment. [Figure 10] FIG. 10 is a circuit diagram of a Pch bias circuit according to the eighth embodiment. [Figure 11] FIG. 11 is a circuit diagram of a class AB amplifier circuit according to the ninth embodiment. [Figure 12] FIG. 12 is a partial circuit diagram of a class AB amplifier circuit according to the tenth embodiment. [Figure 13] FIG. 13 is a partial circuit diagram of a class AB amplifier circuit according to the eleventh embodiment. [Figure 14] FIG. 14 is a circuit diagram showing an example of a class AB output circuit and a Pch bias circuit that constitute a conventional class AB amplifier circuit. DETAILED DESCRIPTION OF THE INVENTION

[0016] (First embodiment) Fig. 1 is a circuit diagram showing one embodiment of an Nch bias circuit 1 (= bias circuit) of the present invention. The Nch bias circuit 1 shown in Fig. 1 is a circuit that generates an input bias voltage Vb1 for an Nch transistor from a positive power supply voltage VDD1 and a negative power supply voltage VSS1, and outputs it from an output terminal T1.

[0017] The Nch bias circuit 1 includes a voltage generating circuit 2, a first voltage mirror circuit 3, a first current source circuit 4, a second current source circuit 5, a voltage controlled current source circuit 6, and a second voltage mirror circuit .

[0018] The voltage generating circuit 2 has one end connected to a negative power supply terminal T22 and the other end connected to a first terminal T31 of a first voltage mirror circuit 3 (described later), and outputs a voltage V11 (=output voltage) to the first terminal T31. A negative power supply voltage VSS1 is supplied to the negative power supply terminal T22. The first voltage mirror circuit 3 operates so that the voltage V11 input to the first terminal T31 and the voltage V11 output from the second terminal T32 are approximately equal.

[0019] One end of the first current source circuit 4 is connected to the positive power supply terminal T21, and the other end is connected to the third terminal T33 of the first voltage mirror circuit 3. A positive power supply voltage VDD1 is supplied to the positive power supply terminal T21. The first voltage mirror circuit 3 operates to output from the second terminal T32 a current substantially equal to the current I4 input to the third terminal T33.

[0020] The second current source circuit 5 is connected between the second terminal T32 of the first voltage mirror circuit 3 and the negative power supply terminal T22. The second current source circuit 5 supplies a current I5. The voltage controlled current source circuit 6 has an input T61 connected between the first current source circuit 4 and the third terminal T33. The voltage controlled current source circuit 6 outputs from an output T62 a current I6 that corresponds to the voltage value input to the input T61.

[0021] The second voltage mirror circuit 7 has a fourth terminal T71 connected to the second terminal T32 of the first voltage mirror circuit 3, and receives the voltage V11 as an input. The second voltage mirror circuit 7 operates so that the voltage V11 input to the fourth terminal T71 and the voltage output from the fifth terminal T72 are approximately equal. The fifth terminal T72 is connected to the output terminal T1, and outputs an input bias voltage Vb1 that is approximately equal to the voltage V11.

[0022] The second voltage mirror circuit 7 has a sixth terminal T73 supplied with the current I6 output from the voltage controlled current source circuit 6. The second voltage mirror circuit 7 operates so that the current I6 input to the sixth terminal T73 and the current output from the fourth terminal T71 are approximately equal.

[0023] By using the above configuration, it is possible to design and control so that the voltage V11 input to the first terminal T31 of the first voltage mirror circuit 3 and the input bias voltage Vb1 output from the fifth terminal T72 of the second voltage mirror circuit 7 are equal. In addition, a negative feedback path is formed from the output T62 to the input T61 of the voltage controlled current source circuit 6. As a result, the voltage input to the input T61 is adjusted so that the current I6 output from the voltage controlled current source circuit 6 is equal to the current I5 flowing in the second current source circuit 5 minus the current I4 flowing in the first current source circuit 4. This allows design and control so that a desired current flows from the sixth terminal T73 to the fourth terminal T71 of the second voltage mirror circuit 7.

[0024] Next, the details of the Nch bias circuit 1 outlined above will be described with reference to FIG. 2. As shown in FIG. 2, the voltage generation circuit 2 includes a diode-connected transistor M21 (the ninth transistor). The transistor M21 is an Nch, low-voltage field-effect transistor and generates a gate-source voltage V11. The first voltage mirror circuit 3 includes a constant current source 31 (the fourth current source circuit) and a current-mirror-connected transistor M31 (the fourth transistor) and a transistor M32 (the fifth transistor), with a size ratio (W / L) set to 1:1. The constant current source 31 has one end connected to the positive power supply terminal T21 and supplies a current I4 equal to that of the first current source circuit 4. Note that if the size ratio of the transistors M31 and M32 is set to 1:m, the ratio of the currents supplied by the constant current source 31 and the first current source circuit 4 should also be set to 1:m. The transistors M31 and M32 are Nch, low-voltage field-effect transistors.

[0025] The drain and gate of transistor M31 are connected to the other end of constant current source 31, and the source is connected to voltage generating circuit 2. The source of transistor M31 serves as a first terminal T31 of first voltage mirror circuit 3. The gate of transistor M32 is connected to the gate and drain of transistor M31, the drain is connected to first current source circuit 4, and the source is connected to second current source circuit 5. The source of transistor M32 serves as a second terminal T32 of first voltage mirror circuit 3, and the drain is connected to third terminal T33 of first voltage mirror circuit 3.

[0026] The voltage controlled current source circuit 6 has a transistor M61 (=first transistor). The transistor M61 is composed of a Pch, low-voltage field effect transistor. The source of the transistor M61 is connected to the positive power supply terminal T21, the drain is connected to the second voltage mirror circuit 7, and the gate is connected to the connection point between the first current source circuit 4 and the drain of the transistor M32. The gate of this transistor M61 serves as the input T61, and the drain serves as the output T62.

[0027] The second voltage mirror circuit 7 has a constant current source 71 (=third current source circuit) and a current mirror-connected transistor M71 (=second transistor) and transistor M72 (=third transistor), with a size ratio (W / L) set to 1:1. One end of the constant current source 71 is connected to the negative power supply terminal T22, and it is a current source that supplies a current I6 equal to the current I6 flowing through the transistor M61. Note that when the size ratio of the transistors M71 and M72 is set to 1:m, the ratio of the current flowing through the transistor M61 to the current supplied by the constant current source 71 should also be set to 1:m. The transistors M71 and M72 are composed of N-channel, high-voltage field-effect transistors.

[0028] The drain and gate of transistor M71 are connected to the drain of transistor M61, and the source is connected to the connection point between the source of transistor M32 and the second current source circuit 5. The source of transistor M71 serves as the fourth terminal T71 of the second voltage mirror circuit 7, and the drain serves as the sixth terminal T73 of the second voltage mirror circuit 7. The gate of transistor M72 is connected to the drain and gate of transistor M71, and the source is connected to the other end of the constant current source 71. The source of transistor M72 is connected to output terminal T1. The source of transistor M72 serves as the fifth terminal T72 of the second voltage mirror circuit 7.

[0029] With the above configuration, the same current I4 flows through the transistors M31 and M32. As a result, the gate-source voltages of the transistors M31 and M32 are equal, and the source voltage of the transistor M32 (the voltage at the second terminal T32) is approximately equal to the source voltage V11 of the transistor M31.

[0030] Furthermore, a current I6, which is the current I5 minus the current I4, flows through transistor M61, which forms the negative feedback path, and this current I6 is supplied to transistor M71. The same current I6 flows through transistors M71 and M72. As a result, the gate-source voltages of transistors M71 and M72 become equal, and the source voltage (input bias voltage Vb1) of transistor M72 becomes approximately equal to the source voltage V11 of transistor M71.

[0031] According to the above-described configuration, even when the drain-source voltage of transistor M61 is small enough to cause it to operate in the triode region, the drain current of transistor M61, which constitutes the negative feedback path, is kept constant. Therefore, even when the power supply voltage (VDD1-VSS1) drops significantly, the drain current and gate-source voltage flowing through high-voltage transistor M71 can be kept constant. As a result, the source voltage of high-voltage transistor M72 (= input bias voltage Vb1) can be kept constant. In the case of the conventional Nch bias circuit 100 shown in FIG. 14 described above, the drain-source voltage at which high-voltage transistor M104 can output a constant drain current is on the order of several hundred mV. In contrast, according to the Nch bias circuit 1 of this embodiment, the drain-source voltage of transistor M61 can be kept constant even when the drain-source voltage drops to several tens of mV. This allows the Nch bias circuit 1 of this embodiment to operate at a low voltage and to expand the range of power supply voltages. In other words, the input bias voltage Vb1 can be output with high precision even when the power supply voltage fluctuates over a wide range.

[0032] (Second embodiment) Next, an Nch bias circuit 1B in the second embodiment will be described with reference to FIG. 3. In FIG. 3, parts equivalent to those in the Nch bias circuit 1 shown in FIG. 2 described in the first embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between the first and second embodiments is the configuration of the first voltage mirror circuit 3B. The first voltage mirror circuit 3B has the same constant current source 31 and transistors M31 and M32 as in the first embodiment, as well as transistors M33 and M34. The transistors M33 and M34 are composed of Nch, low-voltage field-effect transistors.

[0033] The transistor M33 (=sixth transistor) is cascode-connected to the transistor M31. The source of the transistor M33 is connected to the drain of the transistor M31, and the drain is connected to the constant current source 31 and the gate of the transistor M31. The transistor M34 (=seventh transistor) is cascode-connected to the transistor M32. The source of the transistor M34 is connected to the drain of the transistor M32, and the drain is connected to the first current source circuit 4 and the gate of the transistor M61. A bias voltage Vb3 is supplied to the gates of the transistors M33 and M34.

[0034] According to the above configuration, it is possible to reduce fluctuations in the drain-source voltages of the transistors M31 and M32, and improve the accuracy of controlling the input bias voltage Vb1 to be equal to the voltage V11.

[0035] (Third embodiment) Next, an Nch bias circuit 1C according to the third embodiment will be described with reference to FIG. 4. In FIG. 4, parts equivalent to those in the Nch bias circuit 1 shown in FIG. 2 and described in the first embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The first embodiment differs from the third embodiment in the configuration of a first voltage mirror circuit 3C. The first voltage mirror circuit 3C has a differential amplifier 32 and a transistor M32 (=eighth transistor). The differential amplifier 32 has an inverting input connected to the source of the transistor M32 and a non-inverting input connected to the voltage generating circuit 2. In this embodiment, the non-inverting input of the differential amplifier 32 corresponds to the first terminal T31 of the first voltage mirror circuit 3C.

[0036] According to the third embodiment, the source voltage of the transistor M32 is controlled by the differential amplifier 32. More specifically, due to the virtual short-circuit phenomenon of the differential amplifier 32, the source voltage of the transistor M32 is controlled to be equal to the voltage V11 output by the voltage generating circuit 2.

[0037] With the above configuration, even if the drain-source voltage of transistor M32 fluctuates, fluctuations in the gate-source voltage can be reduced, improving the accuracy of controlling input bias voltage Vb1 to be equal to voltage V11.

[0038] (Fourth embodiment) Next, an Nch bias circuit 1D according to the fourth embodiment will be described with reference to Fig. 5. In Fig. 5, parts equivalent to those in the Nch bias circuit 1 shown in Fig. 2 and described in the first embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between the first and third embodiments is that the Nch bias circuit 1D includes a phase compensation capacitance C1. One end of the phase compensation capacitance C1 is connected to the positive power supply terminal T21, and the other end is connected to the gate of the transistor M61.

[0039] In the first to third embodiments described above, the transistor M61 forms a negative feedback path, which may result in oscillation. Therefore, in the fourth embodiment, a phase compensation capacitance C1 is connected to the gate of the transistor M61 as a phase compensation circuit. This makes it possible to suppress oscillation of the Nch bias circuit 1D. Note that, although one end of the phase compensation capacitance C1 is connected to the positive power supply terminal T21 in the example shown in FIG. 5, it is sufficient that one end of the phase compensation capacitance C1 is connected to a low-impedance terminal, and it may also be connected to the negative power supply terminal T22.

[0040] (Fifth embodiment) 6 is a circuit diagram showing an embodiment of a Pch bias circuit 1E of the present invention. The Pch bias circuit 1E shown in Fig. 1 is a circuit that generates an input bias voltage Vb2 for a Pch transistor from a positive power supply voltage VDD1 and a negative power supply voltage VSS1.

[0041] The Pch bias circuit 1E of the fifth embodiment can be explained by replacing "Nch" with "Pch" in the explanation of the Nch bias circuit 1 of the first embodiment, replacing the symbols 2 to 7, T1, T31 to T33, T61, T62, and T71 to T73 with symbols 2E to 7E, T1E, T31E to T33E, T61E, T62E, and T71E to T73E, replacing the negative power supply terminal T22 and negative power supply voltage VSS1 with a positive power supply terminal T21 and a positive power supply voltage VDD1, replacing the positive power supply terminal T21 and positive power supply voltage VDD1 with a negative power supply terminal T22 and a negative power supply voltage VSS1, and replacing the voltages V11 and Vb1 with voltages V21 and Vb2, and therefore detailed explanations will be omitted here.

[0042] Next, the details of the Pch bias circuit 1E outlined above will be described with reference to Fig. 7. The Pch bias circuit 1E shown in Fig. 7 can be described by replacing the reference numerals 31, 71, M21, M31, M32, M61, M71, and M72 in the description of the Nch bias circuit 1 shown in Fig. 2 with the reference numerals 31E, 71E, M21E, M31E, M32E, M61E, M71E, and M72E, in addition to the above-mentioned replacements, and therefore a detailed description will be omitted here.

[0043] With the above configuration, the same current I4 flows through the transistors M31E and M32E. As a result, the gate-source voltages of the transistors M31E and M32E are equal, and the source voltage of the transistor M32E (the voltage at the second terminal T32E) is approximately equal to the source voltage V21 of the transistor M31E.

[0044] Furthermore, a current I6, which is the current I5 minus the current I4, flows through transistor M61E, which forms the negative feedback path, and this current I6 is supplied to transistor M71E. The same current I6 flows through transistors M71E and M72E. As a result, the gate-source voltages of transistors M71E and M72E become equal, and the source voltage (input bias voltage Vb2) of transistor M72E becomes approximately equal to the source voltage V21 of transistor M71E.

[0045] According to the above-described configuration, even when the drain-source voltage of transistor M61E is small enough to cause it to operate in the triode region, the drain current of transistor M61E, which constitutes the negative feedback path, is maintained constant. Therefore, even when the power supply voltage (VDD1-VSS1) drops significantly, the drain current and gate-source voltage of high-voltage transistor M71E can be maintained constant. As a result, the source voltage of high-voltage transistor M72E (= input bias voltage Vb2) can be maintained constant. In the case of a Pch bias circuit corresponding to the conventional Nch bias circuit 100 shown in FIG. 14, the drain-source voltage at which high-voltage transistor M104 can output a constant drain current is on the order of several hundred millivolts. In contrast, according to the Pch bias circuit 1E of this embodiment, a constant drain current can be maintained even when the drain-source voltage of transistor M61E drops to several tens of millivolts. This allows the Pch bias circuit 1E of this embodiment to operate at a low voltage and to expand the range of power supply voltages. In other words, the input bias voltage Vb2 can be output with high precision even when the power supply voltage fluctuates over a wide range.

[0046] (Sixth embodiment) Next, a Pch bias circuit 1F (= bias circuit) in the sixth embodiment will be described with reference to FIG. 8. In FIG. 8, parts equivalent to those in the Pch bias circuit 1E shown in FIG. 7 and described in the fifth embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The fifth embodiment differs from the sixth embodiment in the configuration of the first voltage mirror circuit 3F. The first voltage mirror circuit 3F has transistors M33F and M34F in addition to the constant current source 31E and transistors M31E and M32E that are the same as those in the first embodiment. The transistors M33F and M34F are configured as Pch, low-voltage field-effect transistors.

[0047] The transistor M33F is cascode-connected to the transistor M31E. The source of the transistor M33F is connected to the drain of the transistor M31E, and the drain is connected to the constant current source 31E and the gate of the transistor M31E. The transistor M34F is cascode-connected to the transistor M32E. The source of the transistor M34F is connected to the drain of the transistor M32E, and the drain is connected to the first current source circuit 4E. A bias voltage Vb4 is supplied to the gates of the transistors M33F and M34F.

[0048] According to the above configuration, fluctuations in the drain-source voltages of the transistors M31E and M32E can be reduced, improving the accuracy of controlling the input bias voltage Vb2 to be equal to the voltage V21.

[0049] (Seventh embodiment) Next, a Pch bias circuit 1G according to the seventh embodiment will be described with reference to FIG. 9. In FIG. 9, parts equivalent to those in the Pch bias circuit 1F shown in FIG. 7 and described in the fifth embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The fifth embodiment differs from the seventh embodiment in the configuration of the first voltage mirror circuit 3G. The first voltage mirror circuit 3G includes a differential amplifier 32G and a transistor M32E. The inverting input of the differential amplifier 32G is connected to the source of the transistor M32E, and the non-inverting input is connected to the voltage generating circuit 2E. In this embodiment, the non-inverting input of the differential amplifier 32G is the first terminal T31E of the first voltage mirror circuit 3G.

[0050] According to the seventh embodiment, the source voltage of the transistor M32E is controlled by the differential amplifier 32G. More specifically, due to the virtual short-circuit phenomenon of the differential amplifier 32G, the source voltage of the transistor M32E is controlled to be equal to the voltage V21 output by the voltage generating circuit 2E.

[0051] With the above configuration, even if the drain-source voltage of transistor M32E fluctuates, fluctuations in the gate-source voltage can be reduced, improving the accuracy of controlling input bias voltage Vb2 to be equal to voltage V21.

[0052] (Eighth embodiment) Next, a Pch bias circuit 1H according to the eighth embodiment will be described with reference to FIG. 10. In FIG. 10, parts equivalent to those in the Pch bias circuit 1E shown in FIG. 7 and described in the fifth embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted. The fifth embodiment differs from the eighth embodiment in the configuration of a voltage-controlled current source circuit 6H. The voltage-controlled current source circuit 6H includes a phase compensation capacitance C1H in addition to a transistor M61E. One end of the phase compensation capacitance C1H is connected to the negative power supply terminal T22, and the other end is connected to the gate of the transistor M61E.

[0053] In the fifth to seventh embodiments described above, the transistor M61E forms a negative feedback path, which may result in oscillation. Therefore, in the eighth embodiment, a phase compensation capacitance C1H is connected to the gate of the transistor M61E as a phase compensation circuit. This makes it possible to suppress oscillation of the Pch bias circuit 1H. Note that, although one end of the phase compensation capacitance C1H is connected to the negative power supply terminal T22 in the example shown in FIG. 10, one end of the phase compensation capacitance C1H may be connected to any terminal with low impedance, such as the positive power supply terminal T21.

[0054] (Ninth embodiment) Next, a class AB amplifier circuit 8 incorporating the Nch bias circuit 1 shown in the first embodiment and the Pch bias circuit 1E shown in the fifth embodiment will be described with reference to Fig. 11. To simplify the drawing, in Fig. 11, the transistor M72 and constant current source 71 that constitute the Nch bias circuit 1 are shown outside the block representing the Nch bias circuit 1, and the transistor M72E and constant current source 71E that constitute the Pch bias circuit 1E are shown outside the block representing the Pch bias circuit 1E.

[0055] As shown in the figure, the class AB amplifier circuit 8 is a circuit that amplifies an input voltage, which is the difference between an input potential INM input to an input terminal T41 and an input potential INP input to an input terminal T42, and outputs the amplified voltage as an output signal VOUT from an output terminal T4.

[0056] The class AB amplifier circuit 8 has a differential input section 9, a class AB output circuit 10, and a floating-type control circuit 11.

[0057] The differential input section 9 outputs a differential current corresponding to the input current. The differential input section 9 has differential transistors M1 and M2 whose sources are connected in common, and a constant current source 91. The differential transistors M1 and M2 are configured by Pch, high-voltage field-effect transistors. The gate of the differential transistor M1 is connected to the input terminal T41, and the gate of the differential transistor M2 is connected to the input terminal T42. The sources of the differential transistors M1 and M2 are connected in common and connected to the constant current source 91.

[0058] The constant current source 91 is connected between the positive power supply terminal T21 and the sources of the differential transistors M1 and M2, which are connected in common. The differential input section 9 divides the constant current supplied by the constant current source 91 into the differential transistors M1 and M2. The current ratio (dividing ratio) of the currents flowing through the differential transistors M1 and M2 is a value that corresponds to the input potentials INM and INP. The difference between the currents flowing through the differential transistors M1 and M2 is output as a differential current.

[0059] The class-AB output circuit 10 includes a cascode-connected transistor Mp1 (=the eleventh transistor), a transistor Mp2, a capacitor Cm1, a cascode-connected transistor Mn1 (=the tenth transistor), a transistor Mn2, and a capacitor Cm2. The transistors Mp1 and Mp2 are P-channel field-effect transistors. The transistor Mp1 is a low-voltage transistor, and the transistor Mp2 is a high-voltage transistor. The transistor Mp2, cascode-connected to the transistor Mp1, protects the transistor Mp1 from high voltages. The transistor Mp1 has a source connected to a positive power supply terminal T21, a drain connected to the source of the transistor Mp2, and a gate connected to an output terminal T1E of the P-channel bias circuit 1E. The transistor Mp2 has a drain connected to an output terminal T4, and a constant bias voltage Vb5 is supplied to its gate. The capacitor Cm1 is connected between the gate of the transistor Mp1 and the drain of the transistor Mp2.

[0060] Transistors Mn1 and Mn2 are composed of N-channel field-effect transistors. Transistor Mn1 is composed of a low-voltage transistor, and transistor Mn2 is composed of a high-voltage transistor. Transistor Mn2, cascode-connected to transistor Mn1, protects transistor Mn1 from high voltage. Transistor Mn1 has a source connected to negative power supply terminal T22, a drain connected to the source of transistor Mn2, and a gate connected to output terminal T1 of N-channel bias circuit 1. Transistor Mn2 has a drain connected to output terminal T4, and a constant bias voltage Vb6 is supplied to its gate. Capacitor Cm2 is connected between the gate of transistor Mn1 and the drain of transistor Mn2.

[0061] The control circuit 11 is a circuit for controlling the output voltage of the class-AB output circuit 10 and the output current flowing to the output terminal T4 in accordance with the current difference (differential current) flowing through the differential transistors M1 and M2. The output signal VOUT has a value according to the output voltage and output current. The control circuit 11 has an Nch bias circuit 1 and a Pch bias circuit 1E.

[0062] The Nch bias circuit 1 and the Pch bias circuit 1E are the same as those in the first embodiment, and therefore detailed description thereof will be omitted here. The transistor M72 constituting the Nch bias circuit 1 and the transistor M72E constituting the Pch bias circuit 1E are connected in parallel. Specifically, the source of the transistor M72 is connected to the drain of the transistor M72E, and the drain of the transistor M72 is connected to the source of the transistor M72E. Therefore, the constant current source 71E supplies a current I6 and divides the current I6 according to the gate-source voltages of the transistors M72 and M72E.

[0063] In this embodiment, the constant current source 71 is composed of transistors M3 to M7 and a constant current source 711. The transistors M3 to M7 are composed of Nch, low-voltage field-effect transistors. The drain of the transistor M3 is connected to the source of the transistor M5, the source is connected to the negative power supply terminal T22, and the gate is connected to the drain of the transistor M5. The drain of the transistor M4 is connected to the source of the transistor M6, the source is connected to the negative power supply terminal T22, and the gate is connected to the gate of the transistor M3.

[0064] The drain of transistor M5 is connected to the drain of transistor M7, and the gate is connected to the gate of transistor M6. The drain of transistor M6 is connected to the drain of transistor M72E and the source of transistor M72. A bias voltage Vb7 is supplied to the gates of transistors M5 and M6. The gate of transistor M7 is connected to the gates of transistors M71E and M72E, and the source is connected to a constant current source 711. The constant current source 711 is connected between the positive power supply terminal T21 and the source of transistor M7, and supplies a current I6.

[0065] The drain of the differential transistor M1 is connected to the connection point between the drain of the transistor M3 and the source of the transistor M5, and the drain of the differential transistor M2 is connected to the connection point between the drain of the transistor M4 and the source of the transistor M6.

[0066] Transistors M3 to M6 form a cascode current mirror circuit, which operates to control the current and gate voltage of transistor M4 according to the current flowing through transistor M3. When the current flowing through differential transistor M2 is smaller than the current flowing through differential transistor M1, the current flowing from differential transistor M2 to transistor M4 is smaller, reducing the voltage drop due to the drain-source resistance of transistor M4. This increases the gate-source voltage of transistor M6, and reduces the drain voltage of transistor M6. As a result, the gate-source voltage of transistor Mn1 decreases, and the current flowing through transistor Mn1 decreases. Furthermore, the decrease in the drain voltage of transistor M6 increases the gate-source voltage of transistor M72, causing a larger proportion of the current from constant current source 71E to flow through transistor M72 and a smaller proportion to flow through transistor M72E. As a result, the source voltage of transistor M72E drops so that the gate-source voltage decreases, the gate-source voltage of transistor Mp1 connected to the source of transistor M72E increases, and the current flowing through transistor Mp1 increases.

[0067] On the other hand, if the current flowing through differential transistor M1 is less than the current flowing through transistor M2, the current flowing from differential transistor M2 to transistor M4 is greater, resulting in a larger voltage drop due to the resistance between the drain and source of transistor M4. This reduces the gate-source voltage of transistor M6 and increases the drain voltage of transistor M6. As a result, the gate-source voltage of transistor Mn1 increases, and the current flowing through transistor Mn1 increases. Furthermore, as the drain voltage of transistor M6 increases, the gate-source voltage of transistor M72 decreases, and less of the current from constant current source 71E flows through transistor M72E, and more of it flows through transistor M72E. This causes the source voltage of transistor M72E to increase its gate-source voltage, reducing the gate-source voltage of transistor Mp1, which is connected to the source of transistor M72E, and reducing the current flowing through transistor Mp1.

[0068] Furthermore, when the currents flowing through the differential transistors M1 and M2 are equal (in the quiescent state), the current flowing from capacitor Cm1 to the drain of transistor M72 and the source of transistor M72E is equal to the current flowing from the source of transistor M72 and the drain of transistor M72E to capacitor Cm2, and the output current is 0. At this time, an input bias voltage Vb2 is supplied to transistor Mp1 by the Pch bias circuit 1E, and an input bias voltage Vb1 is supplied to transistor Mn1 by the Nch bias circuit 1, so both transistors Mp1 and Mn1 are turned on.

[0069] (Tenth embodiment) Next, a class AB amplifier circuit according to the tenth embodiment will be described with reference to Fig. 12. In Fig. 12, the same components as those in the Nch bias circuit 1 shown in Fig. 2 and described in the first embodiment and the class AB amplifier circuit 8 shown in Fig. 11 and described in the ninth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

[0070] In the ninth embodiment, both the class AB output circuit 10 and the Nch bias circuit 1 are connected to the same positive power supply terminal T21. In contrast, in the tenth embodiment, the class AB output circuit 10 is connected to a positive power supply terminal T23 (= second positive power supply terminal), and the Nch bias circuit 1 is connected to a positive power supply terminal T21 (= first positive power supply terminal). A positive power supply voltage VDD2 (= second positive power supply voltage) is supplied to the positive power supply terminal T23, and the positive power supply voltage VDD2 is a higher voltage than the positive power supply voltage VDD1 (= first positive power supply voltage). The positive power supply voltage VDD1 may be generated from the positive power supply voltage VDD2. As described above, by using separate power supplies for the positive power supply voltage VDD2 supplied to the class AB output circuit 10 and the positive power supply voltage VDD1 supplied to the Nch bias circuit 1, the Nch bias circuit 1 becomes less susceptible to fluctuations in the positive power supply voltage VDD2.

[0071] (Eleventh embodiment) Next, an AB class amplifier circuit according to the eleventh embodiment will be described with reference to Fig. 13. In Fig. 13, the same components as those in the Pch bias circuit 1E shown in Fig. 6 and described in the fifth embodiment and the AB class amplifier circuit 8 shown in Fig. 11 and described in the ninth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

[0072] In the ninth embodiment, both the class AB output circuit 10 and the Pch bias circuit 1E are connected to the same negative power supply terminal T22. In contrast, in the eleventh embodiment, the class AB output circuit 10 is connected to the negative power supply terminal T24 (= second negative power supply terminal), and the Pch bias circuit 1E is connected to the negative power supply terminal T22 (= first negative power supply terminal). A negative power supply voltage VSS2 (= second negative power supply voltage) is supplied to the negative power supply terminal T24, and the negative power supply voltage VSS2 is a voltage lower than the negative power supply voltage VSS1 (= first negative power supply voltage). The negative power supply voltage VSS1 may be generated from the negative power supply voltage VSS2. As described above, by using separate power supplies for the negative power supply voltage VSS2 supplied to the class AB output circuit 10 and the negative power supply voltage VSS2 supplied to the Pch bias circuit 1E, the Pch bias circuit 1E becomes less susceptible to fluctuations in the negative power supply voltage VSS2.

[0073] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0074] For example, the Nch bias circuit 1 constituting the class-AB amplifier circuit 8 shown in the ninth to eleventh embodiments may be replaced by the Nc bias circuits 1B to 1D described in the second to fourth embodiments. Similarly, the Pch bias circuit 1E may be replaced by the Pch bias circuits 1F to 1H described in the sixth to eighth embodiments.

[0075] In the first to eleventh embodiments, the transistors are field-effect transistors, but the present invention is not limited to this. The transistors may be bipolar transistors. In this case, the transistor gate can be used as the base, the source as the emitter, the drain as the collector, and the size ratio (W / L) as the emitter area ratio. [Explanation of symbols]

[0076] 1,1B~1D Nch bias circuit (bias circuit) 1E~1H Pch bias circuit (bias circuit) 2,2E Voltage generation circuit 3, 3B, 3C, 3E, 3F, 3G First voltage mirror circuit 4,4E 1st current source circuit 5,5E 2nd current source circuit 6,6E,6H Voltage controlled current source circuit 7,7E Second voltage mirror circuit 8. Class AB amplifier circuit 9 Differential input section 10 Class AB output circuit 11 Control circuit 31,31E Constant current source (4th current source circuit) 32,32G differential amplifier 71,71E Constant current source (third current source circuit) C1, C1H Phase compensation capacitance (phase compensation circuit) M21, M21E transistor (9th transistor) M31, M31E transistor (fourth transistor) M32, M32E transistors (5th transistor, 8th transistor) M33, M33F transistor (6th transistor) M34, M34F transistor (7th transistor) M61, M61E transistor (first transistor) M71, M71E transistor (second transistor) M72, M72E transistor (third transistor) Mn1 transistor (10th transistor) Mp1 transistor (11th transistor) T21 Positive power supply terminal (first positive power supply terminal) T22 Negative power supply terminal (first negative power supply terminal) T23 Positive power supply terminal (second positive power supply terminal) T24 Negative power supply terminal (second negative power supply terminal) T31, T31E 1st terminal T32, T32E 2nd terminal T33, T33E 3rd terminal T71, T71E 4th terminal T72,T72E 5th terminal T73,T73E 6th terminal V11, V21 voltage (output voltage) VDD1 Positive power supply voltage (first positive power supply voltage) VDD2 Positive power supply voltage (second positive power supply voltage) VSS1 Negative power supply voltage (first negative power supply voltage) VSS2 Negative power supply voltage (second negative power supply voltage)

Claims

1. a first voltage mirror circuit that operates so that a voltage input to a first terminal and a voltage output to a second terminal are approximately equal, and that a current input to a third terminal and a current output from the second terminal are approximately equal; a voltage generation circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a second voltage mirror circuit that operates so that a voltage input to a fourth terminal connected to the second terminal and a voltage output from a fifth terminal become substantially equal, and that a current input to a sixth terminal and a current output from the fourth terminal become substantially equal; a first current source circuit to which the third terminal of the first voltage mirror circuit is connected; a second current source circuit to which the second terminal of the first voltage mirror circuit and the fourth terminal of the second voltage mirror circuit are connected; a voltage-controlled current source circuit having an input connected to the third terminal of the first voltage mirror circuit and an output connected to the sixth terminal of the second voltage mirror circuit, and outputting a current corresponding to an input voltage value; a negative feedback path is provided from the output to the input of the voltage controlled current source circuit; the voltage controlled current source circuit has a first transistor whose gate or base serves as the input and whose drain or collector serves as the output; the first transistor outputs, from the drain or collector, a current obtained by subtracting a current flowing in the first current source circuit from a current flowing in the second current source circuit; the second voltage mirror circuit includes a second transistor having a drain or a collector that serves as the sixth terminal and a source or an emitter that serves as the fourth terminal, a third transistor that is current-mirror-connected to the second transistor and has a source or an emitter that serves as the fifth terminal, and a third current source circuit that is connected to the source or the emitter of the third transistor, a ratio of a current output from the voltage controlled current source circuit to a current of the third current source circuit is set equal to a size ratio or an emitter area ratio of the second transistor to the third transistor; the first voltage mirror circuit includes a fourth current source circuit, a fourth transistor having a drain or a collector connected to the fourth current source circuit and a source or an emitter serving as the first terminal, and a fifth transistor that is current mirror connected to the fourth transistor, having a source or an emitter serving as the second terminal and a drain or a collector serving as the third terminal; a ratio of a current of the fourth current source circuit to a current of the first current source circuit is set equal to a size ratio or an emitter area ratio of the fourth transistor to the fifth transistor; Bias circuit.

2. 2. The bias circuit according to claim 1, a phase compensation circuit, Bias circuit.

3. 2. The bias circuit according to claim 1, the second transistor and the third transistor are configured as transistors with a higher breakdown voltage than the first transistor that configures the first voltage mirror circuit and the voltage controlled current source circuit; Bias circuit.

4. 2. The bias circuit according to claim 1, the first voltage mirror circuit includes a sixth transistor cascode-connected to the fourth transistor and a seventh transistor cascode-connected to the fifth transistor; Bias circuit.

5. A first voltage mirror circuit having a function of operating so that the voltage input to a first terminal and the voltage output to a second terminal are approximately equal, and so that the current input to a third terminal and the current output from the second terminal are approximately equal; a voltage generation circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a second voltage mirror circuit that operates so that a voltage input to a fourth terminal connected to the second terminal and a voltage output from a fifth terminal become substantially equal, and that a current input to a sixth terminal and a current output from the fourth terminal become substantially equal; a first current source circuit to which the third terminal of the first voltage mirror circuit is connected; a second current source circuit to which the second terminal of the first voltage mirror circuit and the fourth terminal of the second voltage mirror circuit are connected; a voltage-controlled current source circuit having an input connected to the third terminal of the first voltage mirror circuit and an output connected to the sixth terminal of the second voltage mirror circuit, and outputting a current corresponding to an input voltage value; a negative feedback path is provided from the output to the input of the voltage controlled current source circuit; the voltage controlled current source circuit has a first transistor whose gate or base serves as the input and whose drain or collector serves as the output; the first transistor outputs, from the drain or collector, a current obtained by subtracting a current flowing in the first current source circuit from a current flowing in the second current source circuit; the second voltage mirror circuit includes a second transistor having a drain or a collector that serves as the sixth terminal and a source or an emitter that serves as the fourth terminal, a third transistor that is current-mirror-connected to the second transistor and has a source or an emitter that serves as the fifth terminal, and a third current source circuit that is connected to the source or the emitter of the third transistor, a ratio of a current output from the voltage controlled current source circuit to a current of the third current source circuit is set equal to a size ratio or an emitter area ratio of the second transistor to the third transistor; the first voltage mirror circuit includes an eighth transistor having a source or an emitter serving as the second terminal and a drain or a collector serving as the third terminal, and a differential amplifier having an output connected to a gate or a base of the eighth transistor, an inverting input connected to the source or the emitter of the eighth transistor, and a non-inverting input serving as the first terminal; Bias circuit.

6. The bias circuit according to any one of claims 1 to 5, the voltage generating circuit includes a diode-connected ninth transistor; Bias circuit.

7. The bias circuit according to any one of claims 1 to 6, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit and the voltage generating circuit are N-channel transistors, The transistors constituting the voltage controlled current source circuit are composed of Pch transistors. Bias circuit.

8. The bias circuit according to any one of claims 1 to 6, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit and the voltage generating circuit are Pch transistors, The transistors constituting the voltage controlled current source circuit are composed of N-channel transistors. Bias circuit.

9. a differential input section that outputs a differential current according to an input voltage; a class AB output circuit having an N-channel tenth transistor and a P-channel eleventh transistor connected in series with each other, and an output terminal connected between the tenth transistor and the eleventh transistor; a bias circuit connected to a gate or a base of the tenth transistor according to claim 7 and a bias circuit connected to a gate or a base of the eleventh transistor according to claim 8, and a control circuit that controls the tenth transistor and the eleventh transistor so as to output an output voltage and an output current corresponding to a differential current output from the differential input section to the output terminal. Class AB amplifier circuit.

10. 10. The class AB amplifier circuit according to claim 9, a first positive power supply terminal for supplying a first positive power supply voltage to the bias circuit of claim 7; a second positive power supply terminal for supplying a second positive power supply voltage to the class AB output circuit; a negative power supply terminal for supplying a negative power supply voltage to the bias circuit according to claim 7 and the class AB output circuit; the first positive power supply voltage and the second positive power supply voltage are different voltages; Class AB amplifier circuit.

11. 10. The class AB amplifier circuit according to claim 9, a first negative power supply terminal for supplying a negative first negative power supply voltage to the bias circuit of claim 8; a second negative power supply terminal for supplying a negative second negative power supply voltage to the class AB output circuit; a bias circuit according to claim 8 and a positive power supply terminal for supplying a positive power supply voltage to the class AB output circuit; the first negative power supply voltage and the second negative power supply voltage are different voltages; Class AB amplifier circuit.

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